Diff: targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h

Revision:

150:02e0a0aed4ec

Parent:

149:156823d33999

--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h	Fri Oct 28 11:17:30 2016 +0100
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h	Tue Nov 08 17:45:16 2016 +0000
@@ -42,100 +42,6 @@
 
 #include "architecture.h"
 
-#ifdef REVB
-/** Watch Dog Timer Control HW Structure Overlay */
-typedef struct {
-    __IO uint32_t LOAD; /**< Watchdog load value */
-    __I uint32_t VALUE; /**< Watchdog current value */
-    union {
-        struct {
-            __IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
-            __IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
-            __IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
-        } BITS;
-        __IO uint32_t WORD;
-    } CONTROL;
-    __IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear  */
-    __I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter  */
-    __I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
-    union {
-        struct {
-            __IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
-            __IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } LOCK;
-    __I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable  */
-    union {
-        struct {
-            __IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
-            __IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
-            __IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } TEST_OUT;
-    union {
-        struct {
-            __IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PID_REG0;
-    union {
-        struct {
-            __IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
-            __IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PID_REG1;
-    union {
-        struct {
-            __IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
-            __IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PID_REG2;
-    union {
-        struct {
-            __IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PID_REG3;
-    union {
-        struct {
-            __IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PCELL_ID0;
-    union {
-        struct {
-            __IO uint32_t ID :8; /**< These bits read back as 0xF0*/
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PCELL_ID1;
-    union {
-        struct {
-            __IO uint32_t ID :8; /**< These bits read back as 0x05*/
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PCELL_ID2;
-    union {
-        struct {
-            __IO uint32_t ID :8; /**< These bits read back as 0xB1*/
-            __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
-        } BITS;
-        __IO uint32_t WORD;
-    } PCELL_ID3;
-} WdtReg_t, *WdtReg_pt;
-#endif /* REVB */
-
-#ifdef REVD
 typedef struct {
     __IO uint32_t LOAD;         /**< 0x4000A000 Contains the value from which the counter is decremented.  When this register is written to the count is immediately restarted from the new value.  The minimum valid value is 1. */
     __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
@@ -157,5 +63,4 @@
         __IO uint32_t WORD;
     } STATUS;    /* 0x4000A014 */
 } WdtReg_t, *WdtReg_pt;
-#endif /* REVD */
 #endif /* WDT_MAP_H_ */