Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 * LPC43xx/LPC18xx MCU header
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Copyright(C) NXP Semiconductors, 2012
bogdanm 0:9b334a45a8ff 5 * All rights reserved.
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * Software that is described herein is for illustrative purposes only
bogdanm 0:9b334a45a8ff 8 * which provides customers with programming information regarding the
bogdanm 0:9b334a45a8ff 9 * LPC products. This software is supplied "AS IS" without any warranties of
bogdanm 0:9b334a45a8ff 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm 0:9b334a45a8ff 11 * all warranties, express or implied, including all implied warranties of
bogdanm 0:9b334a45a8ff 12 * merchantability, fitness for a particular purpose and non-infringement of
bogdanm 0:9b334a45a8ff 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm 0:9b334a45a8ff 14 * or liability for the use of the software, conveys no license or rights under any
bogdanm 0:9b334a45a8ff 15 * patent, copyright, mask work right, or any other intellectual property rights in
bogdanm 0:9b334a45a8ff 16 * or to any products. NXP Semiconductors reserves the right to make changes
bogdanm 0:9b334a45a8ff 17 * in the software without notification. NXP Semiconductors also makes no
bogdanm 0:9b334a45a8ff 18 * representation or warranty that such application will be suitable for the
bogdanm 0:9b334a45a8ff 19 * specified use without further testing or modification.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 0:9b334a45a8ff 22 * documentation is hereby granted, under NXP Semiconductors' and its
bogdanm 0:9b334a45a8ff 23 * licensor's relevant copyrights in the software, without fee, provided that it
bogdanm 0:9b334a45a8ff 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 0:9b334a45a8ff 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 0:9b334a45a8ff 26 * this code.
bogdanm 0:9b334a45a8ff 27 *
bogdanm 0:9b334a45a8ff 28 * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
bogdanm 0:9b334a45a8ff 29 * 05/15/13 Micromint USA <support@micromint.com>
bogdanm 0:9b334a45a8ff 30 */
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 #ifndef __LPC43XX_H
bogdanm 0:9b334a45a8ff 33 #define __LPC43XX_H
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 36 extern "C" {
bogdanm 0:9b334a45a8ff 37 #endif
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 /* Treat __CORE_Mx as CORE_Mx */
bogdanm 0:9b334a45a8ff 40 #if defined(__CORTEX_M0) && !defined(CORE_M0)
bogdanm 0:9b334a45a8ff 41 #define CORE_M0
bogdanm 0:9b334a45a8ff 42 #endif
bogdanm 0:9b334a45a8ff 43 #if defined(__CORTEX_M3) && !defined(CORE_M3)
bogdanm 0:9b334a45a8ff 44 #define CORE_M3
bogdanm 0:9b334a45a8ff 45 #endif
bogdanm 0:9b334a45a8ff 46 /* Default to M4 core if no core explicitly declared */
bogdanm 0:9b334a45a8ff 47 #if !defined(CORE_M0) && !defined(CORE_M3)
bogdanm 0:9b334a45a8ff 48 #define CORE_M4
bogdanm 0:9b334a45a8ff 49 #endif
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /* Define LPC18XX or LPC43XX according to core type */
bogdanm 0:9b334a45a8ff 52 #if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
bogdanm 0:9b334a45a8ff 53 #define __LPC43XX__
bogdanm 0:9b334a45a8ff 54 #endif
bogdanm 0:9b334a45a8ff 55 #if defined(CORE_M3) && !defined(__LPC18XX__)
bogdanm 0:9b334a45a8ff 56 #define __LPC18XX__
bogdanm 0:9b334a45a8ff 57 #endif
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /* Start of section using anonymous unions */
bogdanm 0:9b334a45a8ff 60 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 61 // Kill warning "#pragma push with no matching #pragma pop"
bogdanm 0:9b334a45a8ff 62 #pragma diag_suppress 2525
bogdanm 0:9b334a45a8ff 63 #pragma push
bogdanm 0:9b334a45a8ff 64 #pragma anon_unions
bogdanm 0:9b334a45a8ff 65 #elif defined(__CWCC__)
bogdanm 0:9b334a45a8ff 66 #pragma push
bogdanm 0:9b334a45a8ff 67 #pragma cpp_extensions on
bogdanm 0:9b334a45a8ff 68 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 69 //#pragma push // FIXME not usable for IAR
bogdanm 0:9b334a45a8ff 70 #pragma language=extended
bogdanm 0:9b334a45a8ff 71 #else /* defined(__GNUC__) and others */
bogdanm 0:9b334a45a8ff 72 /* Assume anonymous unions are enabled by default */
bogdanm 0:9b334a45a8ff 73 #endif
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 #if defined(CORE_M4)
bogdanm 0:9b334a45a8ff 76 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 77 * LPC43xx (M4 Core) Cortex CMSIS definitions
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 #define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
bogdanm 0:9b334a45a8ff 81 #define __MPU_PRESENT 1 /* MPU present or not */
bogdanm 0:9b334a45a8ff 82 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 83 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 84 #define __FPU_PRESENT 1 /* FPU present or not */
bogdanm 0:9b334a45a8ff 85 #define CHIP_LPC43XX /* LPCOPEN compatibility */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 88 * LPC43xx peripheral interrupt numbers
bogdanm 0:9b334a45a8ff 89 */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 typedef enum {
bogdanm 0:9b334a45a8ff 92 /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
bogdanm 0:9b334a45a8ff 93 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 0:9b334a45a8ff 94 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 0:9b334a45a8ff 95 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
bogdanm 0:9b334a45a8ff 96 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
bogdanm 0:9b334a45a8ff 97 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
bogdanm 0:9b334a45a8ff 98 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
bogdanm 0:9b334a45a8ff 99 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
bogdanm 0:9b334a45a8ff 100 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
bogdanm 0:9b334a45a8ff 101 PendSV_IRQn = -2,/* 14 Pendable request for system service */
bogdanm 0:9b334a45a8ff 102 SysTick_IRQn = -1,/* 15 System Tick Timer */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
bogdanm 0:9b334a45a8ff 105 DAC_IRQn = 0,/* 0 DAC */
bogdanm 0:9b334a45a8ff 106 M0CORE_IRQn = 1,/* 1 M0a */
bogdanm 0:9b334a45a8ff 107 DMA_IRQn = 2,/* 2 DMA */
bogdanm 0:9b334a45a8ff 108 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
bogdanm 0:9b334a45a8ff 109 RESERVED2_IRQn = 4,
bogdanm 0:9b334a45a8ff 110 ETHERNET_IRQn = 5,/* 5 ETHERNET */
bogdanm 0:9b334a45a8ff 111 SDIO_IRQn = 6,/* 6 SDIO */
bogdanm 0:9b334a45a8ff 112 LCD_IRQn = 7,/* 7 LCD */
bogdanm 0:9b334a45a8ff 113 USB0_IRQn = 8,/* 8 USB0 */
bogdanm 0:9b334a45a8ff 114 USB1_IRQn = 9,/* 9 USB1 */
bogdanm 0:9b334a45a8ff 115 SCT_IRQn = 10,/* 10 SCT */
bogdanm 0:9b334a45a8ff 116 RITIMER_IRQn = 11,/* 11 RITIMER */
bogdanm 0:9b334a45a8ff 117 TIMER0_IRQn = 12,/* 12 TIMER0 */
bogdanm 0:9b334a45a8ff 118 TIMER1_IRQn = 13,/* 13 TIMER1 */
bogdanm 0:9b334a45a8ff 119 TIMER2_IRQn = 14,/* 14 TIMER2 */
bogdanm 0:9b334a45a8ff 120 TIMER3_IRQn = 15,/* 15 TIMER3 */
bogdanm 0:9b334a45a8ff 121 MCPWM_IRQn = 16,/* 16 MCPWM */
bogdanm 0:9b334a45a8ff 122 ADC0_IRQn = 17,/* 17 ADC0 */
bogdanm 0:9b334a45a8ff 123 I2C0_IRQn = 18,/* 18 I2C0 */
bogdanm 0:9b334a45a8ff 124 I2C1_IRQn = 19,/* 19 I2C1 */
bogdanm 0:9b334a45a8ff 125 SPI_INT_IRQn = 20,/* 20 SPI_INT */
bogdanm 0:9b334a45a8ff 126 ADC1_IRQn = 21,/* 21 ADC1 */
bogdanm 0:9b334a45a8ff 127 SSP0_IRQn = 22,/* 22 SSP0 */
bogdanm 0:9b334a45a8ff 128 SSP1_IRQn = 23,/* 23 SSP1 */
bogdanm 0:9b334a45a8ff 129 USART0_IRQn = 24,/* 24 USART0 */
bogdanm 0:9b334a45a8ff 130 UART1_IRQn = 25,/* 25 UART1 */
bogdanm 0:9b334a45a8ff 131 USART2_IRQn = 26,/* 26 USART2 */
bogdanm 0:9b334a45a8ff 132 USART3_IRQn = 27,/* 27 USART3 */
bogdanm 0:9b334a45a8ff 133 I2S0_IRQn = 28,/* 28 I2S0 */
bogdanm 0:9b334a45a8ff 134 I2S1_IRQn = 29,/* 29 I2S1 */
bogdanm 0:9b334a45a8ff 135 RESERVED4_IRQn = 30,
bogdanm 0:9b334a45a8ff 136 SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
bogdanm 0:9b334a45a8ff 137 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
bogdanm 0:9b334a45a8ff 138 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
bogdanm 0:9b334a45a8ff 139 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
bogdanm 0:9b334a45a8ff 140 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
bogdanm 0:9b334a45a8ff 141 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
bogdanm 0:9b334a45a8ff 142 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
bogdanm 0:9b334a45a8ff 143 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
bogdanm 0:9b334a45a8ff 144 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
bogdanm 0:9b334a45a8ff 145 GINT0_IRQn = 40,/* 40 GINT0 */
bogdanm 0:9b334a45a8ff 146 GINT1_IRQn = 41,/* 41 GINT1 */
bogdanm 0:9b334a45a8ff 147 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
bogdanm 0:9b334a45a8ff 148 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
bogdanm 0:9b334a45a8ff 149 RESERVED6_IRQn = 44,
bogdanm 0:9b334a45a8ff 150 RESERVED7_IRQn = 45,/* 45 VADC */
bogdanm 0:9b334a45a8ff 151 ATIMER_IRQn = 46,/* 46 ATIMER */
bogdanm 0:9b334a45a8ff 152 RTC_IRQn = 47,/* 47 RTC */
bogdanm 0:9b334a45a8ff 153 RESERVED8_IRQn = 48,
bogdanm 0:9b334a45a8ff 154 WWDT_IRQn = 49,/* 49 WWDT */
bogdanm 0:9b334a45a8ff 155 RESERVED9_IRQn = 50,
bogdanm 0:9b334a45a8ff 156 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
bogdanm 0:9b334a45a8ff 157 QEI_IRQn = 52,/* 52 QEI */
bogdanm 0:9b334a45a8ff 158 } IRQn_Type;
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 #elif defined(CORE_M3)
bogdanm 0:9b334a45a8ff 163 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 164 * LPC18xx (M3 Core) Cortex CMSIS definitions
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 #define __MPU_PRESENT 1 /* MPU present or not */
bogdanm 0:9b334a45a8ff 167 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 168 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 169 #define __FPU_PRESENT 0 /* FPU present or not */
bogdanm 0:9b334a45a8ff 170 #define CHIP_LPC18XX /* LPCOPEN compatibility */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 173 * LPC18xx peripheral interrupt numbers
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 typedef enum {
bogdanm 0:9b334a45a8ff 177 /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
bogdanm 0:9b334a45a8ff 178 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 0:9b334a45a8ff 179 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 0:9b334a45a8ff 180 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
bogdanm 0:9b334a45a8ff 181 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
bogdanm 0:9b334a45a8ff 182 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
bogdanm 0:9b334a45a8ff 183 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
bogdanm 0:9b334a45a8ff 184 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
bogdanm 0:9b334a45a8ff 185 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
bogdanm 0:9b334a45a8ff 186 PendSV_IRQn = -2,/* 14 Pendable request for system service */
bogdanm 0:9b334a45a8ff 187 SysTick_IRQn = -1,/* 15 System Tick Timer */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
bogdanm 0:9b334a45a8ff 190 DAC_IRQn = 0,/* 0 DAC */
bogdanm 0:9b334a45a8ff 191 RESERVED0_IRQn = 1,
bogdanm 0:9b334a45a8ff 192 DMA_IRQn = 2,/* 2 DMA */
bogdanm 0:9b334a45a8ff 193 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
bogdanm 0:9b334a45a8ff 194 RESERVED2_IRQn = 4,
bogdanm 0:9b334a45a8ff 195 ETHERNET_IRQn = 5,/* 5 ETHERNET */
bogdanm 0:9b334a45a8ff 196 SDIO_IRQn = 6,/* 6 SDIO */
bogdanm 0:9b334a45a8ff 197 LCD_IRQn = 7,/* 7 LCD */
bogdanm 0:9b334a45a8ff 198 USB0_IRQn = 8,/* 8 USB0 */
bogdanm 0:9b334a45a8ff 199 USB1_IRQn = 9,/* 9 USB1 */
bogdanm 0:9b334a45a8ff 200 SCT_IRQn = 10,/* 10 SCT */
bogdanm 0:9b334a45a8ff 201 RITIMER_IRQn = 11,/* 11 RITIMER */
bogdanm 0:9b334a45a8ff 202 TIMER0_IRQn = 12,/* 12 TIMER0 */
bogdanm 0:9b334a45a8ff 203 TIMER1_IRQn = 13,/* 13 TIMER1 */
bogdanm 0:9b334a45a8ff 204 TIMER2_IRQn = 14,/* 14 TIMER2 */
bogdanm 0:9b334a45a8ff 205 TIMER3_IRQn = 15,/* 15 TIMER3 */
bogdanm 0:9b334a45a8ff 206 MCPWM_IRQn = 16,/* 16 MCPWM */
bogdanm 0:9b334a45a8ff 207 ADC0_IRQn = 17,/* 17 ADC0 */
bogdanm 0:9b334a45a8ff 208 I2C0_IRQn = 18,/* 18 I2C0 */
bogdanm 0:9b334a45a8ff 209 I2C1_IRQn = 19,/* 19 I2C1 */
bogdanm 0:9b334a45a8ff 210 RESERVED3_IRQn = 20,
bogdanm 0:9b334a45a8ff 211 ADC1_IRQn = 21,/* 21 ADC1 */
bogdanm 0:9b334a45a8ff 212 SSP0_IRQn = 22,/* 22 SSP0 */
bogdanm 0:9b334a45a8ff 213 SSP1_IRQn = 23,/* 23 SSP1 */
bogdanm 0:9b334a45a8ff 214 USART0_IRQn = 24,/* 24 USART0 */
bogdanm 0:9b334a45a8ff 215 UART1_IRQn = 25,/* 25 UART1 */
bogdanm 0:9b334a45a8ff 216 USART2_IRQn = 26,/* 26 USART2 */
bogdanm 0:9b334a45a8ff 217 USART3_IRQn = 27,/* 27 USART3 */
bogdanm 0:9b334a45a8ff 218 I2S0_IRQn = 28,/* 28 I2S0 */
bogdanm 0:9b334a45a8ff 219 I2S1_IRQn = 29,/* 29 I2S1 */
bogdanm 0:9b334a45a8ff 220 RESERVED4_IRQn = 30,
bogdanm 0:9b334a45a8ff 221 RESERVED5_IRQn = 31,
bogdanm 0:9b334a45a8ff 222 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
bogdanm 0:9b334a45a8ff 223 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
bogdanm 0:9b334a45a8ff 224 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
bogdanm 0:9b334a45a8ff 225 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
bogdanm 0:9b334a45a8ff 226 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
bogdanm 0:9b334a45a8ff 227 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
bogdanm 0:9b334a45a8ff 228 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
bogdanm 0:9b334a45a8ff 229 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
bogdanm 0:9b334a45a8ff 230 GINT0_IRQn = 40,/* 40 GINT0 */
bogdanm 0:9b334a45a8ff 231 GINT1_IRQn = 41,/* 41 GINT1 */
bogdanm 0:9b334a45a8ff 232 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
bogdanm 0:9b334a45a8ff 233 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
bogdanm 0:9b334a45a8ff 234 RESERVED6_IRQn = 44,
bogdanm 0:9b334a45a8ff 235 RESERVED7_IRQn = 45,/* 45 VADC */
bogdanm 0:9b334a45a8ff 236 ATIMER_IRQn = 46,/* 46 ATIMER */
bogdanm 0:9b334a45a8ff 237 RTC_IRQn = 47,/* 47 RTC */
bogdanm 0:9b334a45a8ff 238 RESERVED8_IRQn = 48,
bogdanm 0:9b334a45a8ff 239 WWDT_IRQn = 49,/* 49 WWDT */
bogdanm 0:9b334a45a8ff 240 RESERVED9_IRQn = 50,
bogdanm 0:9b334a45a8ff 241 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
bogdanm 0:9b334a45a8ff 242 QEI_IRQn = 52,/* 52 QEI */
bogdanm 0:9b334a45a8ff 243 } IRQn_Type;
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 #elif defined(CORE_M0)
bogdanm 0:9b334a45a8ff 248 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 249 * LPC43xx (M0 Core) Cortex CMSIS definitions
bogdanm 0:9b334a45a8ff 250 */
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 #define __MPU_PRESENT 0 /* MPU present or not */
bogdanm 0:9b334a45a8ff 253 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 254 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 255 #define __FPU_PRESENT 0 /* FPU present or not */
bogdanm 0:9b334a45a8ff 256 #define CHIP_LPC43XX /* LPCOPEN compatibility */
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 259 * LPC43xx (M0 Core) peripheral interrupt numbers
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 typedef enum {
bogdanm 0:9b334a45a8ff 263 /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
bogdanm 0:9b334a45a8ff 264 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 0:9b334a45a8ff 265 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 0:9b334a45a8ff 266 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
bogdanm 0:9b334a45a8ff 267 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
bogdanm 0:9b334a45a8ff 268 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
bogdanm 0:9b334a45a8ff 269 PendSV_IRQn = -2,/* 14 Pendable request for system service */
bogdanm 0:9b334a45a8ff 270 SysTick_IRQn = -1,/* 15 System Tick Timer */
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
bogdanm 0:9b334a45a8ff 273 DAC_IRQn = 0,/* 0 DAC */
bogdanm 0:9b334a45a8ff 274 M0_M4CORE_IRQn = 1,/* 1 M0a */
bogdanm 0:9b334a45a8ff 275 DMA_IRQn = 2,/* 2 DMA r */
bogdanm 0:9b334a45a8ff 276 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
bogdanm 0:9b334a45a8ff 277 FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
bogdanm 0:9b334a45a8ff 278 ETHERNET_IRQn = 5,/* 5 ETHERNET */
bogdanm 0:9b334a45a8ff 279 SDIO_IRQn = 6,/* 6 SDIO */
bogdanm 0:9b334a45a8ff 280 LCD_IRQn = 7,/* 7 LCD */
bogdanm 0:9b334a45a8ff 281 USB0_IRQn = 8,/* 8 USB0 */
bogdanm 0:9b334a45a8ff 282 USB1_IRQn = 9,/* 9 USB1 */
bogdanm 0:9b334a45a8ff 283 SCT_IRQn = 10,/* 10 SCT */
bogdanm 0:9b334a45a8ff 284 RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
bogdanm 0:9b334a45a8ff 285 TIMER0_IRQn = 12,/* 12 TIMER0 */
bogdanm 0:9b334a45a8ff 286 GINT1_IRQn = 13,/* 13 GINT1 */
bogdanm 0:9b334a45a8ff 287 PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
bogdanm 0:9b334a45a8ff 288 TIMER3_IRQn = 15,/* 15 TIMER3 */
bogdanm 0:9b334a45a8ff 289 MCPWM_IRQn = 16,/* 16 MCPWM */
bogdanm 0:9b334a45a8ff 290 ADC0_IRQn = 17,/* 17 ADC0 */
bogdanm 0:9b334a45a8ff 291 I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
bogdanm 0:9b334a45a8ff 292 SGPIO_INT_IRQn = 19,/* 19 SGPIO */
bogdanm 0:9b334a45a8ff 293 SPI_INT_IRQn = 20,/* 20 SPI_INT */
bogdanm 0:9b334a45a8ff 294 ADC1_IRQn = 21,/* 21 ADC1 */
bogdanm 0:9b334a45a8ff 295 SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
bogdanm 0:9b334a45a8ff 296 EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
bogdanm 0:9b334a45a8ff 297 USART0_IRQn = 24,/* 24 USART0 */
bogdanm 0:9b334a45a8ff 298 UART1_IRQn = 25,/* 25 UART1 */
bogdanm 0:9b334a45a8ff 299 USART2_IRQn = 26,/* 26 USART2 */
bogdanm 0:9b334a45a8ff 300 USART3_IRQn = 27,/* 27 USART3 */
bogdanm 0:9b334a45a8ff 301 I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
bogdanm 0:9b334a45a8ff 302 C_CAN0_IRQn = 29,/* 29 C_CAN0 */
bogdanm 0:9b334a45a8ff 303 I2S1_IRQn = 29,/* 29 I2S1 */
bogdanm 0:9b334a45a8ff 304 RESERVED2_IRQn = 30,
bogdanm 0:9b334a45a8ff 305 RESERVED3_IRQn = 31,
bogdanm 0:9b334a45a8ff 306 } IRQn_Type;
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
bogdanm 0:9b334a45a8ff 309 #else
bogdanm 0:9b334a45a8ff 310 #error Please #define CORE_M0, CORE_M3 or CORE_M4
bogdanm 0:9b334a45a8ff 311 #endif
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 #include "system_LPC43xx.h"
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 316 * State Configurable Timer register block structure
bogdanm 0:9b334a45a8ff 317 */
bogdanm 0:9b334a45a8ff 318 #define LPC_SCT_BASE 0x40000000
bogdanm 0:9b334a45a8ff 319 #define CONFIG_SCT_nEV (16) /* Number of events */
bogdanm 0:9b334a45a8ff 320 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
bogdanm 0:9b334a45a8ff 321 #define CONFIG_SCT_nOU (16) /* Number of outputs */
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 typedef struct {
bogdanm 0:9b334a45a8ff 324 __IO uint32_t CONFIG; /* Configuration Register */
bogdanm 0:9b334a45a8ff 325 union {
bogdanm 0:9b334a45a8ff 326 __IO uint32_t CTRL_U; /* Control Register */
bogdanm 0:9b334a45a8ff 327 struct {
bogdanm 0:9b334a45a8ff 328 __IO uint16_t CTRL_L; /* Low control register */
bogdanm 0:9b334a45a8ff 329 __IO uint16_t CTRL_H; /* High control register */
bogdanm 0:9b334a45a8ff 330 };
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 };
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 __IO uint16_t LIMIT_L; /* limit register for counter L */
bogdanm 0:9b334a45a8ff 335 __IO uint16_t LIMIT_H; /* limit register for counter H */
bogdanm 0:9b334a45a8ff 336 __IO uint16_t HALT_L; /* halt register for counter L */
bogdanm 0:9b334a45a8ff 337 __IO uint16_t HALT_H; /* halt register for counter H */
bogdanm 0:9b334a45a8ff 338 __IO uint16_t STOP_L; /* stop register for counter L */
bogdanm 0:9b334a45a8ff 339 __IO uint16_t STOP_H; /* stop register for counter H */
bogdanm 0:9b334a45a8ff 340 __IO uint16_t START_L; /* start register for counter L */
bogdanm 0:9b334a45a8ff 341 __IO uint16_t START_H; /* start register for counter H */
bogdanm 0:9b334a45a8ff 342 uint32_t RESERVED1[10]; /* 0x03C reserved */
bogdanm 0:9b334a45a8ff 343 union {
bogdanm 0:9b334a45a8ff 344 __IO uint32_t COUNT_U; /* counter register */
bogdanm 0:9b334a45a8ff 345 struct {
bogdanm 0:9b334a45a8ff 346 __IO uint16_t COUNT_L; /* counter register for counter L */
bogdanm 0:9b334a45a8ff 347 __IO uint16_t COUNT_H; /* counter register for counter H */
bogdanm 0:9b334a45a8ff 348 };
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 };
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 __IO uint16_t STATE_L; /* state register for counter L */
bogdanm 0:9b334a45a8ff 353 __IO uint16_t STATE_H; /* state register for counter H */
bogdanm 0:9b334a45a8ff 354 __I uint32_t INPUT; /* input register */
bogdanm 0:9b334a45a8ff 355 __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
bogdanm 0:9b334a45a8ff 356 __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
bogdanm 0:9b334a45a8ff 357 __IO uint32_t OUTPUT; /* output register */
bogdanm 0:9b334a45a8ff 358 __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
bogdanm 0:9b334a45a8ff 359 __IO uint32_t RES; /* conflict resolution register */
bogdanm 0:9b334a45a8ff 360 __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
bogdanm 0:9b334a45a8ff 361 __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
bogdanm 0:9b334a45a8ff 362 uint32_t RESERVED2[35];
bogdanm 0:9b334a45a8ff 363 __IO uint32_t EVEN; /* event enable register */
bogdanm 0:9b334a45a8ff 364 __IO uint32_t EVFLAG; /* event flag register */
bogdanm 0:9b334a45a8ff 365 __IO uint32_t CONEN; /* conflict enable register */
bogdanm 0:9b334a45a8ff 366 __IO uint32_t CONFLAG; /* conflict flag register */
bogdanm 0:9b334a45a8ff 367 union {
bogdanm 0:9b334a45a8ff 368 __IO union { /* ... Match / Capture value */
bogdanm 0:9b334a45a8ff 369 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 370 struct {
bogdanm 0:9b334a45a8ff 371 uint16_t L; /* SCTMATCH[i].L Access to L value */
bogdanm 0:9b334a45a8ff 372 uint16_t H; /* SCTMATCH[i].H Access to H value */
bogdanm 0:9b334a45a8ff 373 };
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375 } MATCH[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 __I union {
bogdanm 0:9b334a45a8ff 378 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 379 struct {
bogdanm 0:9b334a45a8ff 380 uint16_t L; /* SCTCAP[i].L Access to L value */
bogdanm 0:9b334a45a8ff 381 uint16_t H; /* SCTCAP[i].H Access to H value */
bogdanm 0:9b334a45a8ff 382 };
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 } CAP[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 };
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
bogdanm 0:9b334a45a8ff 389 union {
bogdanm 0:9b334a45a8ff 390 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
bogdanm 0:9b334a45a8ff 391 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
bogdanm 0:9b334a45a8ff 392 };
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
bogdanm 0:9b334a45a8ff 395 union {
bogdanm 0:9b334a45a8ff 396 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
bogdanm 0:9b334a45a8ff 397 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
bogdanm 0:9b334a45a8ff 398 };
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
bogdanm 0:9b334a45a8ff 401 union {
bogdanm 0:9b334a45a8ff 402 __IO union { /* 0x200-... Match Reload / Capture Control value */
bogdanm 0:9b334a45a8ff 403 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 404 struct {
bogdanm 0:9b334a45a8ff 405 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
bogdanm 0:9b334a45a8ff 406 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
bogdanm 0:9b334a45a8ff 407 };
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 } MATCHREL[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 __IO union {
bogdanm 0:9b334a45a8ff 412 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 413 struct {
bogdanm 0:9b334a45a8ff 414 uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
bogdanm 0:9b334a45a8ff 415 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
bogdanm 0:9b334a45a8ff 416 };
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 } CAPCTRL[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 };
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
bogdanm 0:9b334a45a8ff 423 union {
bogdanm 0:9b334a45a8ff 424 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
bogdanm 0:9b334a45a8ff 425 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
bogdanm 0:9b334a45a8ff 426 };
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
bogdanm 0:9b334a45a8ff 429 union {
bogdanm 0:9b334a45a8ff 430 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
bogdanm 0:9b334a45a8ff 431 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
bogdanm 0:9b334a45a8ff 432 };
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
bogdanm 0:9b334a45a8ff 435 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
bogdanm 0:9b334a45a8ff 436 uint32_t STATE; /* Event State Register */
bogdanm 0:9b334a45a8ff 437 uint32_t CTRL; /* Event Control Register */
bogdanm 0:9b334a45a8ff 438 } EVENT[CONFIG_SCT_nEV];
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
bogdanm 0:9b334a45a8ff 441 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
bogdanm 0:9b334a45a8ff 442 uint32_t SET; /* Output n Set Register */
bogdanm 0:9b334a45a8ff 443 uint32_t CLR; /* Output n Clear Register */
bogdanm 0:9b334a45a8ff 444 } OUT[CONFIG_SCT_nOU];
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
bogdanm 0:9b334a45a8ff 447 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
bogdanm 0:9b334a45a8ff 448 } LPC_SCT_T;
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Macro defines for SCT configuration register */
bogdanm 0:9b334a45a8ff 451 #define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
bogdanm 0:9b334a45a8ff 452 #define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
bogdanm 0:9b334a45a8ff 455 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
bogdanm 0:9b334a45a8ff 456 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
bogdanm 0:9b334a45a8ff 457 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
bogdanm 0:9b334a45a8ff 458
bogdanm 0:9b334a45a8ff 459 #define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
bogdanm 0:9b334a45a8ff 460 #define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 /* Macro defines for SCT control register */
bogdanm 0:9b334a45a8ff 463 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
bogdanm 0:9b334a45a8ff 464 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 #define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
bogdanm 0:9b334a45a8ff 467 #define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
bogdanm 0:9b334a45a8ff 468 #define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
bogdanm 0:9b334a45a8ff 469 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
bogdanm 0:9b334a45a8ff 470 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
bogdanm 0:9b334a45a8ff 473 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
bogdanm 0:9b334a45a8ff 474 #define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
bogdanm 0:9b334a45a8ff 475 #define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
bogdanm 0:9b334a45a8ff 476 #define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
bogdanm 0:9b334a45a8ff 477 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
bogdanm 0:9b334a45a8ff 478 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /* Macro defines for SCT Conflict resolution register */
bogdanm 0:9b334a45a8ff 481 #define SCT_RES_NOCHANGE (0)
bogdanm 0:9b334a45a8ff 482 #define SCT_RES_SET_OUTPUT (1)
bogdanm 0:9b334a45a8ff 483 #define SCT_RES_CLEAR_OUTPUT (2)
bogdanm 0:9b334a45a8ff 484 #define SCT_RES_TOGGLE_OUTPUT (3)
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 487 * GPDMA Channel register block structure
bogdanm 0:9b334a45a8ff 488 */
bogdanm 0:9b334a45a8ff 489 #define LPC_GPDMA_BASE 0x40002000
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 typedef struct {
bogdanm 0:9b334a45a8ff 492 __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
bogdanm 0:9b334a45a8ff 493 __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
bogdanm 0:9b334a45a8ff 494 __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
bogdanm 0:9b334a45a8ff 495 __IO uint32_t CONTROL; /* DMA Channel Control Register */
bogdanm 0:9b334a45a8ff 496 __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
bogdanm 0:9b334a45a8ff 497 __I uint32_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 498 } LPC_GPDMA_CH_T;
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 #define GPDMA_CHANNELS 8
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 503 * GPDMA register block
bogdanm 0:9b334a45a8ff 504 */
bogdanm 0:9b334a45a8ff 505 typedef struct { /* GPDMA Structure */
bogdanm 0:9b334a45a8ff 506 __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
bogdanm 0:9b334a45a8ff 507 __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
bogdanm 0:9b334a45a8ff 508 __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
bogdanm 0:9b334a45a8ff 509 __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
bogdanm 0:9b334a45a8ff 510 __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
bogdanm 0:9b334a45a8ff 511 __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
bogdanm 0:9b334a45a8ff 512 __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
bogdanm 0:9b334a45a8ff 513 __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
bogdanm 0:9b334a45a8ff 514 __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
bogdanm 0:9b334a45a8ff 515 __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
bogdanm 0:9b334a45a8ff 516 __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
bogdanm 0:9b334a45a8ff 517 __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
bogdanm 0:9b334a45a8ff 518 __IO uint32_t CONFIG; /* DMA Configuration Register */
bogdanm 0:9b334a45a8ff 519 __IO uint32_t SYNC; /* DMA Synchronization Register */
bogdanm 0:9b334a45a8ff 520 __I uint32_t RESERVED0[50];
bogdanm 0:9b334a45a8ff 521 LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
bogdanm 0:9b334a45a8ff 522 } LPC_GPDMA_T;
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 525 * SPIFI register block structure
bogdanm 0:9b334a45a8ff 526 */
bogdanm 0:9b334a45a8ff 527 #define LPC_SPIFI_BASE 0x40003000
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 typedef struct { /* SPIFI Structure */
bogdanm 0:9b334a45a8ff 530 __IO uint32_t CTRL; /* Control register */
bogdanm 0:9b334a45a8ff 531 __IO uint32_t CMD; /* Command register */
bogdanm 0:9b334a45a8ff 532 __IO uint32_t ADDR; /* Address register */
bogdanm 0:9b334a45a8ff 533 __IO uint32_t IDATA; /* Intermediate data register */
bogdanm 0:9b334a45a8ff 534 __IO uint32_t CLIMIT; /* Cache limit register */
bogdanm 0:9b334a45a8ff 535 union {
bogdanm 0:9b334a45a8ff 536 __IO uint32_t DATA;
bogdanm 0:9b334a45a8ff 537 __IO uint16_t DATA_HWORD;
bogdanm 0:9b334a45a8ff 538 __IO uint8_t DATA_BYTE;
bogdanm 0:9b334a45a8ff 539 }; /* Data register */
bogdanm 0:9b334a45a8ff 540 __IO uint32_t MCMD; /* Memory command register */
bogdanm 0:9b334a45a8ff 541 __IO uint32_t STAT; /* Status register */
bogdanm 0:9b334a45a8ff 542 } LPC_SPIFI_T;
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 545 * SD/MMC & SDIO register block structure
bogdanm 0:9b334a45a8ff 546 */
bogdanm 0:9b334a45a8ff 547 #define LPC_SDMMC_BASE 0x40004000
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 typedef struct { /* SDMMC Structure */
bogdanm 0:9b334a45a8ff 550 __IO uint32_t CTRL; /* Control Register */
bogdanm 0:9b334a45a8ff 551 __IO uint32_t PWREN; /* Power Enable Register */
bogdanm 0:9b334a45a8ff 552 __IO uint32_t CLKDIV; /* Clock Divider Register */
bogdanm 0:9b334a45a8ff 553 __IO uint32_t CLKSRC; /* SD Clock Source Register */
bogdanm 0:9b334a45a8ff 554 __IO uint32_t CLKENA; /* Clock Enable Register */
bogdanm 0:9b334a45a8ff 555 __IO uint32_t TMOUT; /* Timeout Register */
bogdanm 0:9b334a45a8ff 556 __IO uint32_t CTYPE; /* Card Type Register */
bogdanm 0:9b334a45a8ff 557 __IO uint32_t BLKSIZ; /* Block Size Register */
bogdanm 0:9b334a45a8ff 558 __IO uint32_t BYTCNT; /* Byte Count Register */
bogdanm 0:9b334a45a8ff 559 __IO uint32_t INTMASK; /* Interrupt Mask Register */
bogdanm 0:9b334a45a8ff 560 __IO uint32_t CMDARG; /* Command Argument Register */
bogdanm 0:9b334a45a8ff 561 __IO uint32_t CMD; /* Command Register */
bogdanm 0:9b334a45a8ff 562 __I uint32_t RESP0; /* Response Register 0 */
bogdanm 0:9b334a45a8ff 563 __I uint32_t RESP1; /* Response Register 1 */
bogdanm 0:9b334a45a8ff 564 __I uint32_t RESP2; /* Response Register 2 */
bogdanm 0:9b334a45a8ff 565 __I uint32_t RESP3; /* Response Register 3 */
bogdanm 0:9b334a45a8ff 566 __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
bogdanm 0:9b334a45a8ff 567 __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
bogdanm 0:9b334a45a8ff 568 __I uint32_t STATUS; /* Status Register */
bogdanm 0:9b334a45a8ff 569 __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
bogdanm 0:9b334a45a8ff 570 __I uint32_t CDETECT; /* Card Detect Register */
bogdanm 0:9b334a45a8ff 571 __I uint32_t WRTPRT; /* Write Protect Register */
bogdanm 0:9b334a45a8ff 572 __IO uint32_t GPIO; /* General Purpose Input/Output Register */
bogdanm 0:9b334a45a8ff 573 __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
bogdanm 0:9b334a45a8ff 574 __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
bogdanm 0:9b334a45a8ff 575 __IO uint32_t DEBNCE; /* Debounce Count Register */
bogdanm 0:9b334a45a8ff 576 __IO uint32_t USRID; /* User ID Register */
bogdanm 0:9b334a45a8ff 577 __I uint32_t VERID; /* Version ID Register */
bogdanm 0:9b334a45a8ff 578 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 579 __IO uint32_t UHS_REG; /* UHS-1 Register */
bogdanm 0:9b334a45a8ff 580 __IO uint32_t RST_N; /* Hardware Reset */
bogdanm 0:9b334a45a8ff 581 __I uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 582 __IO uint32_t BMOD; /* Bus Mode Register */
bogdanm 0:9b334a45a8ff 583 __O uint32_t PLDMND; /* Poll Demand Register */
bogdanm 0:9b334a45a8ff 584 __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
bogdanm 0:9b334a45a8ff 585 __IO uint32_t IDSTS; /* Internal DMAC Status Register */
bogdanm 0:9b334a45a8ff 586 __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
bogdanm 0:9b334a45a8ff 587 __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
bogdanm 0:9b334a45a8ff 588 __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
bogdanm 0:9b334a45a8ff 589 } LPC_SDMMC_T;
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 592 * External Memory Controller (EMC) register block structure
bogdanm 0:9b334a45a8ff 593 */
bogdanm 0:9b334a45a8ff 594 #define LPC_EMC_BASE 0x40005000
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 typedef struct { /* EMC Structure */
bogdanm 0:9b334a45a8ff 597 __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
bogdanm 0:9b334a45a8ff 598 __I uint32_t STATUS; /* Provides EMC status information. */
bogdanm 0:9b334a45a8ff 599 __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
bogdanm 0:9b334a45a8ff 600 __I uint32_t RESERVED0[5];
bogdanm 0:9b334a45a8ff 601 __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
bogdanm 0:9b334a45a8ff 602 __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
bogdanm 0:9b334a45a8ff 603 __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
bogdanm 0:9b334a45a8ff 604 __I uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 605 __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
bogdanm 0:9b334a45a8ff 606 __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
bogdanm 0:9b334a45a8ff 607 __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
bogdanm 0:9b334a45a8ff 608 __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
bogdanm 0:9b334a45a8ff 609 __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
bogdanm 0:9b334a45a8ff 610 __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
bogdanm 0:9b334a45a8ff 611 __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
bogdanm 0:9b334a45a8ff 612 __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
bogdanm 0:9b334a45a8ff 613 __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
bogdanm 0:9b334a45a8ff 614 __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
bogdanm 0:9b334a45a8ff 615 __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
bogdanm 0:9b334a45a8ff 616 __I uint32_t RESERVED2[9];
bogdanm 0:9b334a45a8ff 617 __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
bogdanm 0:9b334a45a8ff 618 __I uint32_t RESERVED3[31];
bogdanm 0:9b334a45a8ff 619 __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 620 __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 621 __I uint32_t RESERVED4[6];
bogdanm 0:9b334a45a8ff 622 __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 623 __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 624 __I uint32_t RESERVED5[6];
bogdanm 0:9b334a45a8ff 625 __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 626 __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 627 __I uint32_t RESERVED6[6];
bogdanm 0:9b334a45a8ff 628 __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 629 __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
bogdanm 0:9b334a45a8ff 630 __I uint32_t RESERVED7[38];
bogdanm 0:9b334a45a8ff 631 __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
bogdanm 0:9b334a45a8ff 632 __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
bogdanm 0:9b334a45a8ff 633 __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
bogdanm 0:9b334a45a8ff 634 __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
bogdanm 0:9b334a45a8ff 635 __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
bogdanm 0:9b334a45a8ff 636 __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
bogdanm 0:9b334a45a8ff 637 __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
bogdanm 0:9b334a45a8ff 638 __I uint32_t RESERVED8;
bogdanm 0:9b334a45a8ff 639 __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
bogdanm 0:9b334a45a8ff 640 __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
bogdanm 0:9b334a45a8ff 641 __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
bogdanm 0:9b334a45a8ff 642 __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
bogdanm 0:9b334a45a8ff 643 __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
bogdanm 0:9b334a45a8ff 644 __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
bogdanm 0:9b334a45a8ff 645 __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
bogdanm 0:9b334a45a8ff 646 __I uint32_t RESERVED9;
bogdanm 0:9b334a45a8ff 647 __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
bogdanm 0:9b334a45a8ff 648 __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
bogdanm 0:9b334a45a8ff 649 __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
bogdanm 0:9b334a45a8ff 650 __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
bogdanm 0:9b334a45a8ff 651 __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
bogdanm 0:9b334a45a8ff 652 __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
bogdanm 0:9b334a45a8ff 653 __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
bogdanm 0:9b334a45a8ff 654 __I uint32_t RESERVED10;
bogdanm 0:9b334a45a8ff 655 __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
bogdanm 0:9b334a45a8ff 656 __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
bogdanm 0:9b334a45a8ff 657 __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
bogdanm 0:9b334a45a8ff 658 __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
bogdanm 0:9b334a45a8ff 659 __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
bogdanm 0:9b334a45a8ff 660 __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
bogdanm 0:9b334a45a8ff 661 __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
bogdanm 0:9b334a45a8ff 662 } LPC_EMC_T;
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 665 * USB High-Speed register block structure
bogdanm 0:9b334a45a8ff 666 */
bogdanm 0:9b334a45a8ff 667 #define LPC_USB0_BASE 0x40006000
bogdanm 0:9b334a45a8ff 668 #define LPC_USB1_BASE 0x40007000
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 typedef struct { /* USB Structure */
bogdanm 0:9b334a45a8ff 671 __I uint32_t RESERVED0[64];
bogdanm 0:9b334a45a8ff 672 __I uint32_t CAPLENGTH; /* Capability register length */
bogdanm 0:9b334a45a8ff 673 __I uint32_t HCSPARAMS; /* Host controller structural parameters */
bogdanm 0:9b334a45a8ff 674 __I uint32_t HCCPARAMS; /* Host controller capability parameters */
bogdanm 0:9b334a45a8ff 675 __I uint32_t RESERVED1[5];
bogdanm 0:9b334a45a8ff 676 __I uint32_t DCIVERSION; /* Device interface version number */
bogdanm 0:9b334a45a8ff 677 __I uint32_t RESERVED2[7];
bogdanm 0:9b334a45a8ff 678 union {
bogdanm 0:9b334a45a8ff 679 __IO uint32_t USBCMD_H; /* USB command (host mode) */
bogdanm 0:9b334a45a8ff 680 __IO uint32_t USBCMD_D; /* USB command (device mode) */
bogdanm 0:9b334a45a8ff 681 };
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 union {
bogdanm 0:9b334a45a8ff 684 __IO uint32_t USBSTS_H; /* USB status (host mode) */
bogdanm 0:9b334a45a8ff 685 __IO uint32_t USBSTS_D; /* USB status (device mode) */
bogdanm 0:9b334a45a8ff 686 };
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 union {
bogdanm 0:9b334a45a8ff 689 __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
bogdanm 0:9b334a45a8ff 690 __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
bogdanm 0:9b334a45a8ff 691 };
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 union {
bogdanm 0:9b334a45a8ff 694 __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
bogdanm 0:9b334a45a8ff 695 __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
bogdanm 0:9b334a45a8ff 696 };
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 __I uint32_t RESERVED3;
bogdanm 0:9b334a45a8ff 699 union {
bogdanm 0:9b334a45a8ff 700 __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
bogdanm 0:9b334a45a8ff 701 __IO uint32_t DEVICEADDR; /* USB device address */
bogdanm 0:9b334a45a8ff 702 };
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 union {
bogdanm 0:9b334a45a8ff 705 __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
bogdanm 0:9b334a45a8ff 706 __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
bogdanm 0:9b334a45a8ff 707 };
bogdanm 0:9b334a45a8ff 708
bogdanm 0:9b334a45a8ff 709 __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
bogdanm 0:9b334a45a8ff 710 __IO uint32_t BURSTSIZE; /* Programmable burst size */
bogdanm 0:9b334a45a8ff 711 __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
bogdanm 0:9b334a45a8ff 712 __I uint32_t RESERVED4[2];
bogdanm 0:9b334a45a8ff 713 __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
bogdanm 0:9b334a45a8ff 714 __IO uint32_t BINTERVAL; /* Length of virtual frame */
bogdanm 0:9b334a45a8ff 715 __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
bogdanm 0:9b334a45a8ff 716 __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
bogdanm 0:9b334a45a8ff 717 __I uint32_t RESERVED5;
bogdanm 0:9b334a45a8ff 718 union {
bogdanm 0:9b334a45a8ff 719 __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
bogdanm 0:9b334a45a8ff 720 __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
bogdanm 0:9b334a45a8ff 721 };
bogdanm 0:9b334a45a8ff 722
bogdanm 0:9b334a45a8ff 723 __I uint32_t RESERVED6[7];
bogdanm 0:9b334a45a8ff 724 __IO uint32_t OTGSC; /* OTG status and control */
bogdanm 0:9b334a45a8ff 725 union {
bogdanm 0:9b334a45a8ff 726 __IO uint32_t USBMODE_H; /* USB mode (host mode) */
bogdanm 0:9b334a45a8ff 727 __IO uint32_t USBMODE_D; /* USB mode (device mode) */
bogdanm 0:9b334a45a8ff 728 };
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
bogdanm 0:9b334a45a8ff 731 __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
bogdanm 0:9b334a45a8ff 732 __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
bogdanm 0:9b334a45a8ff 733 __I uint32_t ENDPTSTAT; /* Endpoint status */
bogdanm 0:9b334a45a8ff 734 __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
bogdanm 0:9b334a45a8ff 735 __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
bogdanm 0:9b334a45a8ff 736 } LPC_USBHS_T;
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 739 * LCD Controller register block structure
bogdanm 0:9b334a45a8ff 740 */
bogdanm 0:9b334a45a8ff 741 #define LPC_LCD_BASE 0x40008000
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 typedef struct { /* LCD Structure */
bogdanm 0:9b334a45a8ff 744 __IO uint32_t TIMH; /* Horizontal Timing Control register */
bogdanm 0:9b334a45a8ff 745 __IO uint32_t TIMV; /* Vertical Timing Control register */
bogdanm 0:9b334a45a8ff 746 __IO uint32_t POL; /* Clock and Signal Polarity Control register */
bogdanm 0:9b334a45a8ff 747 __IO uint32_t LE; /* Line End Control register */
bogdanm 0:9b334a45a8ff 748 __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
bogdanm 0:9b334a45a8ff 749 __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
bogdanm 0:9b334a45a8ff 750 __IO uint32_t CTRL; /* LCD Control register */
bogdanm 0:9b334a45a8ff 751 __IO uint32_t INTMSK; /* Interrupt Mask register */
bogdanm 0:9b334a45a8ff 752 __I uint32_t INTRAW; /* Raw Interrupt Status register */
bogdanm 0:9b334a45a8ff 753 __I uint32_t INTSTAT; /* Masked Interrupt Status register */
bogdanm 0:9b334a45a8ff 754 __O uint32_t INTCLR; /* Interrupt Clear register */
bogdanm 0:9b334a45a8ff 755 __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
bogdanm 0:9b334a45a8ff 756 __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
bogdanm 0:9b334a45a8ff 757 __I uint32_t RESERVED0[115];
bogdanm 0:9b334a45a8ff 758 __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
bogdanm 0:9b334a45a8ff 759 __I uint32_t RESERVED1[256];
bogdanm 0:9b334a45a8ff 760 __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
bogdanm 0:9b334a45a8ff 761 __IO uint32_t CRSR_CTRL; /* Cursor Control register */
bogdanm 0:9b334a45a8ff 762 __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
bogdanm 0:9b334a45a8ff 763 __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
bogdanm 0:9b334a45a8ff 764 __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
bogdanm 0:9b334a45a8ff 765 __IO uint32_t CRSR_XY; /* Cursor XY Position register */
bogdanm 0:9b334a45a8ff 766 __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
bogdanm 0:9b334a45a8ff 767 __I uint32_t RESERVED2[2];
bogdanm 0:9b334a45a8ff 768 __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
bogdanm 0:9b334a45a8ff 769 __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
bogdanm 0:9b334a45a8ff 770 __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
bogdanm 0:9b334a45a8ff 771 __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
bogdanm 0:9b334a45a8ff 772 } LPC_LCD_T;
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 775 * EEPROM register block structure
bogdanm 0:9b334a45a8ff 776 */
bogdanm 0:9b334a45a8ff 777 #define LPC_EEPROM_BASE 0x4000E000
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 typedef struct { /* EEPROM Structure */
bogdanm 0:9b334a45a8ff 780 __IO uint32_t CMD; /* EEPROM command register */
bogdanm 0:9b334a45a8ff 781 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 782 __IO uint32_t RWSTATE; /* EEPROM read wait state register */
bogdanm 0:9b334a45a8ff 783 __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
bogdanm 0:9b334a45a8ff 784 __IO uint32_t WSTATE; /* EEPROM wait state register */
bogdanm 0:9b334a45a8ff 785 __IO uint32_t CLKDIV; /* EEPROM clock divider register */
bogdanm 0:9b334a45a8ff 786 __IO uint32_t PWRDWN; /* EEPROM power-down register */
bogdanm 0:9b334a45a8ff 787 uint32_t RESERVED2[1007];
bogdanm 0:9b334a45a8ff 788 __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
bogdanm 0:9b334a45a8ff 789 __O uint32_t INTENSET; /* EEPROM interrupt enable set */
bogdanm 0:9b334a45a8ff 790 __I uint32_t INTSTAT; /* EEPROM interrupt status */
bogdanm 0:9b334a45a8ff 791 __I uint32_t INTEN; /* EEPROM interrupt enable */
bogdanm 0:9b334a45a8ff 792 __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
bogdanm 0:9b334a45a8ff 793 __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
bogdanm 0:9b334a45a8ff 794 } LPC_EEPROM_T;
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 797 * 10/100 MII & RMII Ethernet with timestamping register block structure
bogdanm 0:9b334a45a8ff 798 */
bogdanm 0:9b334a45a8ff 799 #define LPC_ETHERNET_BASE 0x40010000
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 typedef struct { /* ETHERNET Structure */
bogdanm 0:9b334a45a8ff 802 __IO uint32_t MAC_CONFIG; /* MAC configuration register */
bogdanm 0:9b334a45a8ff 803 __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
bogdanm 0:9b334a45a8ff 804 __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
bogdanm 0:9b334a45a8ff 805 __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
bogdanm 0:9b334a45a8ff 806 __IO uint32_t MAC_MII_ADDR; /* MII address register */
bogdanm 0:9b334a45a8ff 807 __IO uint32_t MAC_MII_DATA; /* MII data register */
bogdanm 0:9b334a45a8ff 808 __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
bogdanm 0:9b334a45a8ff 809 __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
bogdanm 0:9b334a45a8ff 810 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 811 __I uint32_t MAC_DEBUG; /* Debug register */
bogdanm 0:9b334a45a8ff 812 __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
bogdanm 0:9b334a45a8ff 813 __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
bogdanm 0:9b334a45a8ff 814 __I uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 815 __I uint32_t MAC_INTR; /* Interrupt status register */
bogdanm 0:9b334a45a8ff 816 __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
bogdanm 0:9b334a45a8ff 817 __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
bogdanm 0:9b334a45a8ff 818 __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
bogdanm 0:9b334a45a8ff 819 __I uint32_t RESERVED2[430];
bogdanm 0:9b334a45a8ff 820 __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
bogdanm 0:9b334a45a8ff 821 __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
bogdanm 0:9b334a45a8ff 822 __I uint32_t SECONDS; /* System time seconds register */
bogdanm 0:9b334a45a8ff 823 __I uint32_t NANOSECONDS; /* System time nanoseconds register */
bogdanm 0:9b334a45a8ff 824 __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
bogdanm 0:9b334a45a8ff 825 __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
bogdanm 0:9b334a45a8ff 826 __IO uint32_t ADDEND; /* Time stamp addend register */
bogdanm 0:9b334a45a8ff 827 __IO uint32_t TARGETSECONDS; /* Target time seconds register */
bogdanm 0:9b334a45a8ff 828 __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
bogdanm 0:9b334a45a8ff 829 __IO uint32_t HIGHWORD; /* System time higher word seconds register */
bogdanm 0:9b334a45a8ff 830 __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
bogdanm 0:9b334a45a8ff 831 __IO uint32_t PPSCTRL; /* PPS control register */
bogdanm 0:9b334a45a8ff 832 __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
bogdanm 0:9b334a45a8ff 833 __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
bogdanm 0:9b334a45a8ff 834 __I uint32_t RESERVED3[562];
bogdanm 0:9b334a45a8ff 835 __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
bogdanm 0:9b334a45a8ff 836 __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
bogdanm 0:9b334a45a8ff 837 __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
bogdanm 0:9b334a45a8ff 838 __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
bogdanm 0:9b334a45a8ff 839 __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
bogdanm 0:9b334a45a8ff 840 __IO uint32_t DMA_STAT; /* Status register */
bogdanm 0:9b334a45a8ff 841 __IO uint32_t DMA_OP_MODE; /* Operation mode register */
bogdanm 0:9b334a45a8ff 842 __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
bogdanm 0:9b334a45a8ff 843 __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
bogdanm 0:9b334a45a8ff 844 __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
bogdanm 0:9b334a45a8ff 845 __I uint32_t RESERVED4[8];
bogdanm 0:9b334a45a8ff 846 __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
bogdanm 0:9b334a45a8ff 847 __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
bogdanm 0:9b334a45a8ff 848 __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
bogdanm 0:9b334a45a8ff 849 __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
bogdanm 0:9b334a45a8ff 850 } LPC_ENET_T;
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 853 * Alarm Timer register block structure
bogdanm 0:9b334a45a8ff 854 */
bogdanm 0:9b334a45a8ff 855 #define LPC_ATIMER_BASE 0x40040000
bogdanm 0:9b334a45a8ff 856
bogdanm 0:9b334a45a8ff 857 typedef struct { /* ATIMER Structure */
bogdanm 0:9b334a45a8ff 858 __IO uint32_t DOWNCOUNTER; /* Downcounter register */
bogdanm 0:9b334a45a8ff 859 __IO uint32_t PRESET; /* Preset value register */
bogdanm 0:9b334a45a8ff 860 __I uint32_t RESERVED0[1012];
bogdanm 0:9b334a45a8ff 861 __O uint32_t CLR_EN; /* Interrupt clear enable register */
bogdanm 0:9b334a45a8ff 862 __O uint32_t SET_EN; /* Interrupt set enable register */
bogdanm 0:9b334a45a8ff 863 __I uint32_t STATUS; /* Status register */
bogdanm 0:9b334a45a8ff 864 __I uint32_t ENABLE; /* Enable register */
bogdanm 0:9b334a45a8ff 865 __O uint32_t CLR_STAT; /* Clear register */
bogdanm 0:9b334a45a8ff 866 __O uint32_t SET_STAT; /* Set register */
bogdanm 0:9b334a45a8ff 867 } LPC_ATIMER_T;
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 870 * Register File register block structure
bogdanm 0:9b334a45a8ff 871 */
bogdanm 0:9b334a45a8ff 872 #define LPC_REGFILE_BASE 0x40041000
bogdanm 0:9b334a45a8ff 873
bogdanm 0:9b334a45a8ff 874 typedef struct {
bogdanm 0:9b334a45a8ff 875 __IO uint32_t REGFILE[64]; /* General purpose storage register */
bogdanm 0:9b334a45a8ff 876 } LPC_REGFILE_T;
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 879 * Power Management Controller register block structure
bogdanm 0:9b334a45a8ff 880 */
bogdanm 0:9b334a45a8ff 881 #define LPC_PMC_BASE 0x40042000
bogdanm 0:9b334a45a8ff 882
bogdanm 0:9b334a45a8ff 883 typedef struct { /* PMC Structure */
bogdanm 0:9b334a45a8ff 884 __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
bogdanm 0:9b334a45a8ff 885 __I uint32_t RESERVED0[6];
bogdanm 0:9b334a45a8ff 886 __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
bogdanm 0:9b334a45a8ff 887 } LPC_PMC_T;
bogdanm 0:9b334a45a8ff 888
bogdanm 0:9b334a45a8ff 889 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 890 * CREG Register Block
bogdanm 0:9b334a45a8ff 891 */
bogdanm 0:9b334a45a8ff 892 #define LPC_CREG_BASE 0x40043000
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 typedef struct { /* CREG Structure */
bogdanm 0:9b334a45a8ff 895 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 896 __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
bogdanm 0:9b334a45a8ff 897 __I uint32_t RESERVED1[62];
bogdanm 0:9b334a45a8ff 898 __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
bogdanm 0:9b334a45a8ff 899 #if defined(CHIP_LPC18XX)
bogdanm 0:9b334a45a8ff 900 __I uint32_t RESERVED2[5];
bogdanm 0:9b334a45a8ff 901 #else
bogdanm 0:9b334a45a8ff 902 __I uint32_t RESERVED2;
bogdanm 0:9b334a45a8ff 903 __I uint32_t CREG1; /* Configuration Register 1 */
bogdanm 0:9b334a45a8ff 904 __I uint32_t CREG2; /* Configuration Register 2 */
bogdanm 0:9b334a45a8ff 905 __I uint32_t CREG3; /* Configuration Register 3 */
bogdanm 0:9b334a45a8ff 906 __I uint32_t CREG4; /* Configuration Register 4 */
bogdanm 0:9b334a45a8ff 907 #endif
bogdanm 0:9b334a45a8ff 908 __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
bogdanm 0:9b334a45a8ff 909 __IO uint32_t DMAMUX; /* DMA muxing control */
bogdanm 0:9b334a45a8ff 910 __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
bogdanm 0:9b334a45a8ff 911 __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
bogdanm 0:9b334a45a8ff 912 __IO uint32_t ETBCFG; /* ETB RAM configuration */
bogdanm 0:9b334a45a8ff 913 __IO uint32_t CREG6; /* Chip configuration register 6. */
bogdanm 0:9b334a45a8ff 914 #if defined(CHIP_LPC18XX)
bogdanm 0:9b334a45a8ff 915 __I uint32_t RESERVED4[52];
bogdanm 0:9b334a45a8ff 916 #else
bogdanm 0:9b334a45a8ff 917 __IO uint32_t M4TXEVENT; /* M4 IPC event register */
bogdanm 0:9b334a45a8ff 918 __I uint32_t RESERVED4[51];
bogdanm 0:9b334a45a8ff 919 #endif
bogdanm 0:9b334a45a8ff 920 __I uint32_t CHIPID; /* Part ID */
bogdanm 0:9b334a45a8ff 921 #if defined(CHIP_LPC18XX)
bogdanm 0:9b334a45a8ff 922 __I uint32_t RESERVED5[191];
bogdanm 0:9b334a45a8ff 923 #else
bogdanm 0:9b334a45a8ff 924 __I uint32_t RESERVED5[127];
bogdanm 0:9b334a45a8ff 925 __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
bogdanm 0:9b334a45a8ff 926 __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
bogdanm 0:9b334a45a8ff 927 __I uint32_t RESERVED6[62];
bogdanm 0:9b334a45a8ff 928 #endif
bogdanm 0:9b334a45a8ff 929 __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
bogdanm 0:9b334a45a8ff 930 __I uint32_t RESERVED7[63];
bogdanm 0:9b334a45a8ff 931 __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
bogdanm 0:9b334a45a8ff 932 } LPC_CREG_T;
bogdanm 0:9b334a45a8ff 933
bogdanm 0:9b334a45a8ff 934 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 935 * Event Router register structure
bogdanm 0:9b334a45a8ff 936 */
bogdanm 0:9b334a45a8ff 937 #define LPC_EVRT_BASE 0x40044000
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 typedef struct { /* EVENTROUTER Structure */
bogdanm 0:9b334a45a8ff 940 __IO uint32_t HILO; /* Level configuration register */
bogdanm 0:9b334a45a8ff 941 __IO uint32_t EDGE; /* Edge configuration */
bogdanm 0:9b334a45a8ff 942 __I uint32_t RESERVED0[1012];
bogdanm 0:9b334a45a8ff 943 __O uint32_t CLR_EN; /* Event clear enable register */
bogdanm 0:9b334a45a8ff 944 __O uint32_t SET_EN; /* Event set enable register */
bogdanm 0:9b334a45a8ff 945 __I uint32_t STATUS; /* Status register */
bogdanm 0:9b334a45a8ff 946 __I uint32_t ENABLE; /* Enable register */
bogdanm 0:9b334a45a8ff 947 __O uint32_t CLR_STAT; /* Clear register */
bogdanm 0:9b334a45a8ff 948 __O uint32_t SET_STAT; /* Set register */
bogdanm 0:9b334a45a8ff 949 } LPC_EVRT_T;
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 952 * Real Time Clock register block structure
bogdanm 0:9b334a45a8ff 953 */
bogdanm 0:9b334a45a8ff 954 #define LPC_RTC_BASE 0x40046000
bogdanm 0:9b334a45a8ff 955 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
bogdanm 0:9b334a45a8ff 956
bogdanm 0:9b334a45a8ff 957 typedef enum RTC_TIMEINDEX {
bogdanm 0:9b334a45a8ff 958 RTC_TIMETYPE_SECOND, /* Second */
bogdanm 0:9b334a45a8ff 959 RTC_TIMETYPE_MINUTE, /* Month */
bogdanm 0:9b334a45a8ff 960 RTC_TIMETYPE_HOUR, /* Hour */
bogdanm 0:9b334a45a8ff 961 RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
bogdanm 0:9b334a45a8ff 962 RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
bogdanm 0:9b334a45a8ff 963 RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
bogdanm 0:9b334a45a8ff 964 RTC_TIMETYPE_MONTH, /* Month */
bogdanm 0:9b334a45a8ff 965 RTC_TIMETYPE_YEAR, /* Year */
bogdanm 0:9b334a45a8ff 966 RTC_TIMETYPE_LAST
bogdanm 0:9b334a45a8ff 967 } RTC_TIMEINDEX_T;
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 #if RTC_EV_SUPPORT
bogdanm 0:9b334a45a8ff 970 typedef enum LPC_RTC_EV_CHANNEL {
bogdanm 0:9b334a45a8ff 971 RTC_EV_CHANNEL_1 = 0,
bogdanm 0:9b334a45a8ff 972 RTC_EV_CHANNEL_2,
bogdanm 0:9b334a45a8ff 973 RTC_EV_CHANNEL_3,
bogdanm 0:9b334a45a8ff 974 RTC_EV_CHANNEL_NUM,
bogdanm 0:9b334a45a8ff 975 } LPC_RTC_EV_CHANNEL_T;
bogdanm 0:9b334a45a8ff 976 #endif /*RTC_EV_SUPPORT*/
bogdanm 0:9b334a45a8ff 977
bogdanm 0:9b334a45a8ff 978 typedef struct { /* RTC Structure */
bogdanm 0:9b334a45a8ff 979 __IO uint32_t ILR; /* Interrupt Location Register */
bogdanm 0:9b334a45a8ff 980 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 981 __IO uint32_t CCR; /* Clock Control Register */
bogdanm 0:9b334a45a8ff 982 __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
bogdanm 0:9b334a45a8ff 983 __IO uint32_t AMR; /* Alarm Mask Register */
bogdanm 0:9b334a45a8ff 984 __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
bogdanm 0:9b334a45a8ff 985 __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
bogdanm 0:9b334a45a8ff 986 __IO uint32_t CALIBRATION; /* Calibration Value Register */
bogdanm 0:9b334a45a8ff 987 __I uint32_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 988 __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
bogdanm 0:9b334a45a8ff 989 #if RTC_EV_SUPPORT
bogdanm 0:9b334a45a8ff 990 __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
bogdanm 0:9b334a45a8ff 991 __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
bogdanm 0:9b334a45a8ff 992 __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
bogdanm 0:9b334a45a8ff 993 __I uint32_t RESERVED2;
bogdanm 0:9b334a45a8ff 994 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
bogdanm 0:9b334a45a8ff 995 __I uint32_t RESERVED3;
bogdanm 0:9b334a45a8ff 996 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
bogdanm 0:9b334a45a8ff 997 #endif /*RTC_EV_SUPPORT*/
bogdanm 0:9b334a45a8ff 998 } LPC_RTC_T;
bogdanm 0:9b334a45a8ff 999
bogdanm 0:9b334a45a8ff 1000 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1001 * LPC18XX/43XX CGU register block structure
bogdanm 0:9b334a45a8ff 1002 */
bogdanm 0:9b334a45a8ff 1003 #define LPC_CGU_BASE 0x40050000
bogdanm 0:9b334a45a8ff 1004 #define LPC_CCU1_BASE 0x40051000
bogdanm 0:9b334a45a8ff 1005 #define LPC_CCU2_BASE 0x40052000
bogdanm 0:9b334a45a8ff 1006 /*
bogdanm 0:9b334a45a8ff 1007 * Input clocks for the CGU and can come from both external (crystal) and
bogdanm 0:9b334a45a8ff 1008 * internal (PLL) sources. Can be routed to the base clocks.
bogdanm 0:9b334a45a8ff 1009 */
bogdanm 0:9b334a45a8ff 1010 typedef enum CGU_CLKIN {
bogdanm 0:9b334a45a8ff 1011 CLKIN_32K, /* External 32KHz input */
bogdanm 0:9b334a45a8ff 1012 CLKIN_IRC, /* Internal IRC (12MHz) input */
bogdanm 0:9b334a45a8ff 1013 CLKIN_ENET_RX, /* External ENET_RX pin input */
bogdanm 0:9b334a45a8ff 1014 CLKIN_ENET_TX, /* External ENET_TX pin input */
bogdanm 0:9b334a45a8ff 1015 CLKIN_CLKIN, /* External GPCLKIN pin input */
bogdanm 0:9b334a45a8ff 1016 CLKIN_RESERVED1,
bogdanm 0:9b334a45a8ff 1017 CLKIN_CRYSTAL, /* External (main) crystal pin input */
bogdanm 0:9b334a45a8ff 1018 CLKIN_USBPLL, /* Internal USB PLL input */
bogdanm 0:9b334a45a8ff 1019 CLKIN_AUDIOPLL, /* Internal Audio PLL input */
bogdanm 0:9b334a45a8ff 1020 CLKIN_MAINPLL, /* Internal Main PLL input */
bogdanm 0:9b334a45a8ff 1021 CLKIN_RESERVED2,
bogdanm 0:9b334a45a8ff 1022 CLKIN_RESERVED3,
bogdanm 0:9b334a45a8ff 1023 CLKIN_IDIVA, /* Internal divider A input */
bogdanm 0:9b334a45a8ff 1024 CLKIN_IDIVB, /* Internal divider B input */
bogdanm 0:9b334a45a8ff 1025 CLKIN_IDIVC, /* Internal divider C input */
bogdanm 0:9b334a45a8ff 1026 CLKIN_IDIVD, /* Internal divider D input */
bogdanm 0:9b334a45a8ff 1027 CLKIN_IDIVE, /* Internal divider E input */
bogdanm 0:9b334a45a8ff 1028 CLKINPUT_PD /* External 32KHz input */
bogdanm 0:9b334a45a8ff 1029 } CGU_CLKIN_T;
bogdanm 0:9b334a45a8ff 1030
bogdanm 0:9b334a45a8ff 1031 #define CLKIN_PLL0USB CLKIN_USBPLL
bogdanm 0:9b334a45a8ff 1032 #define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
bogdanm 0:9b334a45a8ff 1033 #define CLKIN_PLL1 CLKIN_MAINPLL
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 /*
bogdanm 0:9b334a45a8ff 1036 * CGU base clocks are clocks that are associated with a single input clock
bogdanm 0:9b334a45a8ff 1037 * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
bogdanm 0:9b334a45a8ff 1038 * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
bogdanm 0:9b334a45a8ff 1039 * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
bogdanm 0:9b334a45a8ff 1040 * CLK_PERIPH_SGPIO periphral clocks.
bogdanm 0:9b334a45a8ff 1041 */
bogdanm 0:9b334a45a8ff 1042 typedef enum CGU_BASE_CLK {
bogdanm 0:9b334a45a8ff 1043 CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
bogdanm 0:9b334a45a8ff 1044 CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
bogdanm 0:9b334a45a8ff 1045 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 1046 CLK_BASE_PERIPH, /* Base clock for SGPIO */
bogdanm 0:9b334a45a8ff 1047 #else
bogdanm 0:9b334a45a8ff 1048 CLK_BASE_RESERVED1,
bogdanm 0:9b334a45a8ff 1049 #endif
bogdanm 0:9b334a45a8ff 1050 CLK_BASE_USB1, /* Base USB clock for USB1 */
bogdanm 0:9b334a45a8ff 1051 CLK_BASE_MX, /* Base clock for CPU core */
bogdanm 0:9b334a45a8ff 1052 CLK_BASE_SPIFI, /* Base clock for SPIFI */
bogdanm 0:9b334a45a8ff 1053 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 1054 CLK_BASE_SPI, /* Base clock for SPI */
bogdanm 0:9b334a45a8ff 1055 #else
bogdanm 0:9b334a45a8ff 1056 CLK_BASE_RESERVED2,
bogdanm 0:9b334a45a8ff 1057 #endif
bogdanm 0:9b334a45a8ff 1058 CLK_BASE_PHY_RX, /* Base clock for PHY RX */
bogdanm 0:9b334a45a8ff 1059 CLK_BASE_PHY_TX, /* Base clock for PHY TX */
bogdanm 0:9b334a45a8ff 1060 CLK_BASE_APB1, /* Base clock for APB1 group */
bogdanm 0:9b334a45a8ff 1061 CLK_BASE_APB3, /* Base clock for APB3 group */
bogdanm 0:9b334a45a8ff 1062 CLK_BASE_LCD, /* Base clock for LCD pixel clock */
bogdanm 0:9b334a45a8ff 1063 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 1064 CLK_BASE_VADC, /* Base clock for VADC */
bogdanm 0:9b334a45a8ff 1065 #else
bogdanm 0:9b334a45a8ff 1066 CLK_BASE_RESERVED3,
bogdanm 0:9b334a45a8ff 1067 #endif
bogdanm 0:9b334a45a8ff 1068 CLK_BASE_SDIO, /* Base clock for SDIO */
bogdanm 0:9b334a45a8ff 1069 CLK_BASE_SSP0, /* Base clock for SSP0 */
bogdanm 0:9b334a45a8ff 1070 CLK_BASE_SSP1, /* Base clock for SSP1 */
bogdanm 0:9b334a45a8ff 1071 CLK_BASE_UART0, /* Base clock for UART0 */
bogdanm 0:9b334a45a8ff 1072 CLK_BASE_UART1, /* Base clock for UART1 */
bogdanm 0:9b334a45a8ff 1073 CLK_BASE_UART2, /* Base clock for UART2 */
bogdanm 0:9b334a45a8ff 1074 CLK_BASE_UART3, /* Base clock for UART3 */
bogdanm 0:9b334a45a8ff 1075 CLK_BASE_OUT, /* Base clock for CLKOUT pin */
bogdanm 0:9b334a45a8ff 1076 CLK_BASE_RESERVED4,
bogdanm 0:9b334a45a8ff 1077 CLK_BASE_RESERVED5,
bogdanm 0:9b334a45a8ff 1078 CLK_BASE_RESERVED6,
bogdanm 0:9b334a45a8ff 1079 CLK_BASE_RESERVED7,
bogdanm 0:9b334a45a8ff 1080 CLK_BASE_APLL, /* Base clock for audio PLL */
bogdanm 0:9b334a45a8ff 1081 CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
bogdanm 0:9b334a45a8ff 1082 CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
bogdanm 0:9b334a45a8ff 1083 CLK_BASE_LAST,
bogdanm 0:9b334a45a8ff 1084 CLK_BASE_NONE = CLK_BASE_LAST
bogdanm 0:9b334a45a8ff 1085 } CGU_BASE_CLK_T;
bogdanm 0:9b334a45a8ff 1086
bogdanm 0:9b334a45a8ff 1087 /*
bogdanm 0:9b334a45a8ff 1088 * CGU dividers provide an extra clock state where a specific clock can be
bogdanm 0:9b334a45a8ff 1089 * divided before being routed to a peripheral group. A divider accepts an
bogdanm 0:9b334a45a8ff 1090 * input clock and then divides it. To use the divided clock for a base clock
bogdanm 0:9b334a45a8ff 1091 * group, use the divider as the input clock for the base clock (for example,
bogdanm 0:9b334a45a8ff 1092 * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
bogdanm 0:9b334a45a8ff 1093 */
bogdanm 0:9b334a45a8ff 1094 typedef enum CGU_IDIV {
bogdanm 0:9b334a45a8ff 1095 CLK_IDIV_A, /* CGU clock divider A */
bogdanm 0:9b334a45a8ff 1096 CLK_IDIV_B, /* CGU clock divider B */
bogdanm 0:9b334a45a8ff 1097 CLK_IDIV_C, /* CGU clock divider A */
bogdanm 0:9b334a45a8ff 1098 CLK_IDIV_D, /* CGU clock divider D */
bogdanm 0:9b334a45a8ff 1099 CLK_IDIV_E, /* CGU clock divider E */
bogdanm 0:9b334a45a8ff 1100 CLK_IDIV_LAST
bogdanm 0:9b334a45a8ff 1101 } CGU_IDIV_T;
bogdanm 0:9b334a45a8ff 1102
bogdanm 0:9b334a45a8ff 1103 /*
bogdanm 0:9b334a45a8ff 1104 * Peripheral clocks are individual clocks routed to peripherals. Although
bogdanm 0:9b334a45a8ff 1105 * multiple peripherals may share a same base clock, each peripheral's clock
bogdanm 0:9b334a45a8ff 1106 * can be enabled or disabled individually. Some peripheral clocks also have
bogdanm 0:9b334a45a8ff 1107 * additional dividers associated with them.
bogdanm 0:9b334a45a8ff 1108 */
bogdanm 0:9b334a45a8ff 1109 typedef enum CCU_CLK {
bogdanm 0:9b334a45a8ff 1110 /* CCU1 clocks */
bogdanm 0:9b334a45a8ff 1111 CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
bogdanm 0:9b334a45a8ff 1112 CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
bogdanm 0:9b334a45a8ff 1113 CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
bogdanm 0:9b334a45a8ff 1114 CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
bogdanm 0:9b334a45a8ff 1115 CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
bogdanm 0:9b334a45a8ff 1116 CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
bogdanm 0:9b334a45a8ff 1117 CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
bogdanm 0:9b334a45a8ff 1118 CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
bogdanm 0:9b334a45a8ff 1119 CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
bogdanm 0:9b334a45a8ff 1120 CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
bogdanm 0:9b334a45a8ff 1121 CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
bogdanm 0:9b334a45a8ff 1122 CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
bogdanm 0:9b334a45a8ff 1123 CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1124 CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1125 CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1126 CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1127 CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1128 CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1129 CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1130 CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1131 CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1132 CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1133 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
bogdanm 0:9b334a45a8ff 1134 CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1135 CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1136 CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1137 CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1138 CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1139 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 1140 CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1141 CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1142 #else
bogdanm 0:9b334a45a8ff 1143 CLK_RESERVED1,
bogdanm 0:9b334a45a8ff 1144 CLK_RESERVED2,
bogdanm 0:9b334a45a8ff 1145 #endif
bogdanm 0:9b334a45a8ff 1146 CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1147 CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1148 CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1149 CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1150 CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1151 CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1152 CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1153 CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1154 CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1155 CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1156 CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1157 CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1158 CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1159 CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1160 CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1161 CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
bogdanm 0:9b334a45a8ff 1162 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 1163 CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
bogdanm 0:9b334a45a8ff 1164 CLK_RESERVED3,
bogdanm 0:9b334a45a8ff 1165 CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
bogdanm 0:9b334a45a8ff 1166 CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
bogdanm 0:9b334a45a8ff 1167 #else
bogdanm 0:9b334a45a8ff 1168 CLK_RESERVED3 = 192,
bogdanm 0:9b334a45a8ff 1169 CLK_RESERVED3A,
bogdanm 0:9b334a45a8ff 1170 CLK_RESERVED4,
bogdanm 0:9b334a45a8ff 1171 CLK_RESERVED5,
bogdanm 0:9b334a45a8ff 1172 #endif
bogdanm 0:9b334a45a8ff 1173 CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
bogdanm 0:9b334a45a8ff 1174 CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
bogdanm 0:9b334a45a8ff 1175 #if defined(CHIP_LPC43XX)
bogdanm 0:9b334a45a8ff 1176 CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
bogdanm 0:9b334a45a8ff 1177 CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
bogdanm 0:9b334a45a8ff 1178 #else
bogdanm 0:9b334a45a8ff 1179 CLK_RESERVED7 = 320,
bogdanm 0:9b334a45a8ff 1180 CLK_RESERVED8,
bogdanm 0:9b334a45a8ff 1181 #endif
bogdanm 0:9b334a45a8ff 1182 CLK_CCU1_LAST,
bogdanm 0:9b334a45a8ff 1183
bogdanm 0:9b334a45a8ff 1184 /* CCU2 clocks */
bogdanm 0:9b334a45a8ff 1185 CLK_CCU2_START,
bogdanm 0:9b334a45a8ff 1186 CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
bogdanm 0:9b334a45a8ff 1187 RESERVED_ALIGNB = CLK_CCU2_START + 31,
bogdanm 0:9b334a45a8ff 1188 CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
bogdanm 0:9b334a45a8ff 1189 RESERVED_ALIGNC = CLK_CCU2_START + 63,
bogdanm 0:9b334a45a8ff 1190 CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
bogdanm 0:9b334a45a8ff 1191 RESERVED_ALIGND = CLK_CCU2_START + 95,
bogdanm 0:9b334a45a8ff 1192 CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
bogdanm 0:9b334a45a8ff 1193 RESERVED_ALIGNE = CLK_CCU2_START + 127,
bogdanm 0:9b334a45a8ff 1194 CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
bogdanm 0:9b334a45a8ff 1195 RESERVED_ALIGNF = CLK_CCU2_START + 159,
bogdanm 0:9b334a45a8ff 1196 CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
bogdanm 0:9b334a45a8ff 1197 RESERVED_ALIGNG = CLK_CCU2_START + 191,
bogdanm 0:9b334a45a8ff 1198 CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
bogdanm 0:9b334a45a8ff 1199 RESERVED_ALIGNH = CLK_CCU2_START + 223,
bogdanm 0:9b334a45a8ff 1200 CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
bogdanm 0:9b334a45a8ff 1201 CLK_CCU2_LAST
bogdanm 0:9b334a45a8ff 1202 } CCU_CLK_T;
bogdanm 0:9b334a45a8ff 1203
bogdanm 0:9b334a45a8ff 1204 /*
bogdanm 0:9b334a45a8ff 1205 * Audio or USB PLL selection
bogdanm 0:9b334a45a8ff 1206 */
bogdanm 0:9b334a45a8ff 1207 typedef enum CGU_USB_AUDIO_PLL {
bogdanm 0:9b334a45a8ff 1208 CGU_USB_PLL,
bogdanm 0:9b334a45a8ff 1209 CGU_AUDIO_PLL
bogdanm 0:9b334a45a8ff 1210 } CGU_USB_AUDIO_PLL_T;
bogdanm 0:9b334a45a8ff 1211
bogdanm 0:9b334a45a8ff 1212 /*
bogdanm 0:9b334a45a8ff 1213 * PLL register block
bogdanm 0:9b334a45a8ff 1214 */
bogdanm 0:9b334a45a8ff 1215 typedef struct {
bogdanm 0:9b334a45a8ff 1216 __I uint32_t PLL_STAT; /* PLL status register */
bogdanm 0:9b334a45a8ff 1217 __IO uint32_t PLL_CTRL; /* PLL control register */
bogdanm 0:9b334a45a8ff 1218 __IO uint32_t PLL_MDIV; /* PLL M-divider register */
bogdanm 0:9b334a45a8ff 1219 __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
bogdanm 0:9b334a45a8ff 1220 } CGU_PLL_REG_T;
bogdanm 0:9b334a45a8ff 1221
bogdanm 0:9b334a45a8ff 1222 typedef struct { /* (@ 0x40050000) CGU Structure */
bogdanm 0:9b334a45a8ff 1223 __I uint32_t RESERVED0[5];
bogdanm 0:9b334a45a8ff 1224 __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
bogdanm 0:9b334a45a8ff 1225 __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
bogdanm 0:9b334a45a8ff 1226 CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
bogdanm 0:9b334a45a8ff 1227 __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
bogdanm 0:9b334a45a8ff 1228 __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
bogdanm 0:9b334a45a8ff 1229 __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
bogdanm 0:9b334a45a8ff 1230 __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
bogdanm 0:9b334a45a8ff 1231 __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
bogdanm 0:9b334a45a8ff 1232 } LPC_CGU_T;
bogdanm 0:9b334a45a8ff 1233
bogdanm 0:9b334a45a8ff 1234 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1235 * CCU clock config/status register pair
bogdanm 0:9b334a45a8ff 1236 */
bogdanm 0:9b334a45a8ff 1237 typedef struct {
bogdanm 0:9b334a45a8ff 1238 __IO uint32_t CFG; /* CCU clock configuration register */
bogdanm 0:9b334a45a8ff 1239 __I uint32_t STAT; /* CCU clock status register */
bogdanm 0:9b334a45a8ff 1240 } CCU_CFGSTAT_T;
bogdanm 0:9b334a45a8ff 1241
bogdanm 0:9b334a45a8ff 1242 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1243 * CCU1 register block structure
bogdanm 0:9b334a45a8ff 1244 */
bogdanm 0:9b334a45a8ff 1245 typedef struct { /* (@ 0x40051000) CCU1 Structure */
bogdanm 0:9b334a45a8ff 1246 __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
bogdanm 0:9b334a45a8ff 1247 __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
bogdanm 0:9b334a45a8ff 1248 __I uint32_t RESERVED0[62];
bogdanm 0:9b334a45a8ff 1249 CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
bogdanm 0:9b334a45a8ff 1250 } LPC_CCU1_T;
bogdanm 0:9b334a45a8ff 1251
bogdanm 0:9b334a45a8ff 1252 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1253 * CCU2 register block structure
bogdanm 0:9b334a45a8ff 1254 */
bogdanm 0:9b334a45a8ff 1255 typedef struct { /* (@ 0x40052000) CCU2 Structure */
bogdanm 0:9b334a45a8ff 1256 __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
bogdanm 0:9b334a45a8ff 1257 __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
bogdanm 0:9b334a45a8ff 1258 __I uint32_t RESERVED0[62];
bogdanm 0:9b334a45a8ff 1259 CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
bogdanm 0:9b334a45a8ff 1260 } LPC_CCU2_T;
bogdanm 0:9b334a45a8ff 1261
bogdanm 0:9b334a45a8ff 1262 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1263 * RGU register structure
bogdanm 0:9b334a45a8ff 1264 */
bogdanm 0:9b334a45a8ff 1265 #define LPC_RGU_BASE 0x40053000
bogdanm 0:9b334a45a8ff 1266
bogdanm 0:9b334a45a8ff 1267 typedef enum RGU_RST {
bogdanm 0:9b334a45a8ff 1268 RGU_CORE_RST,
bogdanm 0:9b334a45a8ff 1269 RGU_PERIPH_RST,
bogdanm 0:9b334a45a8ff 1270 RGU_MASTER_RST,
bogdanm 0:9b334a45a8ff 1271 RGU_WWDT_RST = 4,
bogdanm 0:9b334a45a8ff 1272 RGU_CREG_RST,
bogdanm 0:9b334a45a8ff 1273 RGU_BUS_RST = 8,
bogdanm 0:9b334a45a8ff 1274 RGU_SCU_RST,
bogdanm 0:9b334a45a8ff 1275 RGU_M3_RST = 13,
bogdanm 0:9b334a45a8ff 1276 RGU_LCD_RST = 16,
bogdanm 0:9b334a45a8ff 1277 RGU_USB0_RST,
bogdanm 0:9b334a45a8ff 1278 RGU_USB1_RST,
bogdanm 0:9b334a45a8ff 1279 RGU_DMA_RST,
bogdanm 0:9b334a45a8ff 1280 RGU_SDIO_RST,
bogdanm 0:9b334a45a8ff 1281 RGU_EMC_RST,
bogdanm 0:9b334a45a8ff 1282 RGU_ETHERNET_RST,
bogdanm 0:9b334a45a8ff 1283 RGU_FLASHA_RST = 25,
bogdanm 0:9b334a45a8ff 1284 RGU_EEPROM_RST = 27,
bogdanm 0:9b334a45a8ff 1285 RGU_GPIO_RST,
bogdanm 0:9b334a45a8ff 1286 RGU_FLASHB_RST,
bogdanm 0:9b334a45a8ff 1287 RGU_TIMER0_RST = 32,
bogdanm 0:9b334a45a8ff 1288 RGU_TIMER1_RST,
bogdanm 0:9b334a45a8ff 1289 RGU_TIMER2_RST,
bogdanm 0:9b334a45a8ff 1290 RGU_TIMER3_RST,
bogdanm 0:9b334a45a8ff 1291 RGU_RITIMER_RST,
bogdanm 0:9b334a45a8ff 1292 RGU_SCT_RST,
bogdanm 0:9b334a45a8ff 1293 RGU_MOTOCONPWM_RST,
bogdanm 0:9b334a45a8ff 1294 RGU_QEI_RST,
bogdanm 0:9b334a45a8ff 1295 RGU_ADC0_RST,
bogdanm 0:9b334a45a8ff 1296 RGU_ADC1_RST,
bogdanm 0:9b334a45a8ff 1297 RGU_DAC_RST,
bogdanm 0:9b334a45a8ff 1298 RGU_UART0_RST = 44,
bogdanm 0:9b334a45a8ff 1299 RGU_UART1_RST,
bogdanm 0:9b334a45a8ff 1300 RGU_UART2_RST,
bogdanm 0:9b334a45a8ff 1301 RGU_UART3_RST,
bogdanm 0:9b334a45a8ff 1302 RGU_I2C0_RST,
bogdanm 0:9b334a45a8ff 1303 RGU_I2C1_RST,
bogdanm 0:9b334a45a8ff 1304 RGU_SSP0_RST,
bogdanm 0:9b334a45a8ff 1305 RGU_SSP1_RST,
bogdanm 0:9b334a45a8ff 1306 RGU_I2S_RST,
bogdanm 0:9b334a45a8ff 1307 RGU_SPIFI_RST,
bogdanm 0:9b334a45a8ff 1308 RGU_CAN1_RST,
bogdanm 0:9b334a45a8ff 1309 RGU_CAN0_RST,
bogdanm 0:9b334a45a8ff 1310 #ifdef CHIP_LPC43XX
bogdanm 0:9b334a45a8ff 1311 RGU_M0APP_RST,
bogdanm 0:9b334a45a8ff 1312 RGU_SGPIO_RST,
bogdanm 0:9b334a45a8ff 1313 RGU_SPI_RST,
bogdanm 0:9b334a45a8ff 1314 #endif
bogdanm 0:9b334a45a8ff 1315 RGU_LAST_RST = 63,
bogdanm 0:9b334a45a8ff 1316 } RGU_RST_T;
bogdanm 0:9b334a45a8ff 1317
bogdanm 0:9b334a45a8ff 1318 typedef struct { /* RGU Structure */
bogdanm 0:9b334a45a8ff 1319 __I uint32_t RESERVED0[64];
bogdanm 0:9b334a45a8ff 1320 __O uint32_t RESET_CTRL0; /* Reset control register 0 */
bogdanm 0:9b334a45a8ff 1321 __O uint32_t RESET_CTRL1; /* Reset control register 1 */
bogdanm 0:9b334a45a8ff 1322 __I uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 1323 __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
bogdanm 0:9b334a45a8ff 1324 __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
bogdanm 0:9b334a45a8ff 1325 __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
bogdanm 0:9b334a45a8ff 1326 __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
bogdanm 0:9b334a45a8ff 1327 __I uint32_t RESERVED2[12];
bogdanm 0:9b334a45a8ff 1328 __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
bogdanm 0:9b334a45a8ff 1329 __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
bogdanm 0:9b334a45a8ff 1330 __I uint32_t RESERVED3[170];
bogdanm 0:9b334a45a8ff 1331 __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
bogdanm 0:9b334a45a8ff 1332 } LPC_RGU_T;
bogdanm 0:9b334a45a8ff 1333
bogdanm 0:9b334a45a8ff 1334 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1335 * Windowed Watchdog register block structure
bogdanm 0:9b334a45a8ff 1336 */
bogdanm 0:9b334a45a8ff 1337 #define LPC_WWDT_BASE 0x40080000
bogdanm 0:9b334a45a8ff 1338
bogdanm 0:9b334a45a8ff 1339 typedef struct { /* WWDT Structure */
bogdanm 0:9b334a45a8ff 1340 __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
bogdanm 0:9b334a45a8ff 1341 __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
bogdanm 0:9b334a45a8ff 1342 __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
bogdanm 0:9b334a45a8ff 1343 __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
bogdanm 0:9b334a45a8ff 1344 #ifdef WATCHDOG_CLKSEL_SUPPORT
bogdanm 0:9b334a45a8ff 1345 __IO uint32_t CLKSEL; /* Watchdog clock select register. */
bogdanm 0:9b334a45a8ff 1346 #else
bogdanm 0:9b334a45a8ff 1347 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 1348 #endif
bogdanm 0:9b334a45a8ff 1349 #ifdef WATCHDOG_WINDOW_SUPPORT
bogdanm 0:9b334a45a8ff 1350 __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
bogdanm 0:9b334a45a8ff 1351 __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
bogdanm 0:9b334a45a8ff 1352 #endif
bogdanm 0:9b334a45a8ff 1353 } LPC_WWDT_T;
bogdanm 0:9b334a45a8ff 1354
bogdanm 0:9b334a45a8ff 1355 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1356 * USART register block structure
bogdanm 0:9b334a45a8ff 1357 */
bogdanm 0:9b334a45a8ff 1358 #define LPC_USART0_BASE 0x40081000
bogdanm 0:9b334a45a8ff 1359 #define LPC_UART1_BASE 0x40082000
bogdanm 0:9b334a45a8ff 1360 #define LPC_USART2_BASE 0x400C1000
bogdanm 0:9b334a45a8ff 1361 #define LPC_USART3_BASE 0x400C2000
bogdanm 0:9b334a45a8ff 1362
bogdanm 0:9b334a45a8ff 1363 typedef struct { /* USARTn Structure */
bogdanm 0:9b334a45a8ff 1364
bogdanm 0:9b334a45a8ff 1365 union {
bogdanm 0:9b334a45a8ff 1366 __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
bogdanm 0:9b334a45a8ff 1367 __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
bogdanm 0:9b334a45a8ff 1368 __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
bogdanm 0:9b334a45a8ff 1369 };
bogdanm 0:9b334a45a8ff 1370
bogdanm 0:9b334a45a8ff 1371 union {
bogdanm 0:9b334a45a8ff 1372 __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
bogdanm 0:9b334a45a8ff 1373 __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
bogdanm 0:9b334a45a8ff 1374 };
bogdanm 0:9b334a45a8ff 1375
bogdanm 0:9b334a45a8ff 1376 union {
bogdanm 0:9b334a45a8ff 1377 __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
bogdanm 0:9b334a45a8ff 1378 __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
bogdanm 0:9b334a45a8ff 1379 };
bogdanm 0:9b334a45a8ff 1380
bogdanm 0:9b334a45a8ff 1381 __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
bogdanm 0:9b334a45a8ff 1382 __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
bogdanm 0:9b334a45a8ff 1383 __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
bogdanm 0:9b334a45a8ff 1384 __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
bogdanm 0:9b334a45a8ff 1385 __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
bogdanm 0:9b334a45a8ff 1386 __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
bogdanm 0:9b334a45a8ff 1387 __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
bogdanm 0:9b334a45a8ff 1388 __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
bogdanm 0:9b334a45a8ff 1389 __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
bogdanm 0:9b334a45a8ff 1390 __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
bogdanm 0:9b334a45a8ff 1391 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 1392 __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
bogdanm 0:9b334a45a8ff 1393 __I uint32_t RESERVED1[1];
bogdanm 0:9b334a45a8ff 1394 __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
bogdanm 0:9b334a45a8ff 1395 __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
bogdanm 0:9b334a45a8ff 1396 __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
bogdanm 0:9b334a45a8ff 1397 __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
bogdanm 0:9b334a45a8ff 1398 union {
bogdanm 0:9b334a45a8ff 1399 __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
bogdanm 0:9b334a45a8ff 1400 __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
bogdanm 0:9b334a45a8ff 1401 };
bogdanm 0:9b334a45a8ff 1402
bogdanm 0:9b334a45a8ff 1403 __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
bogdanm 0:9b334a45a8ff 1404 } LPC_USART_T;
bogdanm 0:9b334a45a8ff 1405
bogdanm 0:9b334a45a8ff 1406 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1407 * SSP register block structure
bogdanm 0:9b334a45a8ff 1408 */
bogdanm 0:9b334a45a8ff 1409 #define LPC_SSP0_BASE 0x40083000
bogdanm 0:9b334a45a8ff 1410 #define LPC_SSP1_BASE 0x400C5000
bogdanm 0:9b334a45a8ff 1411
bogdanm 0:9b334a45a8ff 1412 typedef struct { /* SSPn Structure */
bogdanm 0:9b334a45a8ff 1413 __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
bogdanm 0:9b334a45a8ff 1414 __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
bogdanm 0:9b334a45a8ff 1415 __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
bogdanm 0:9b334a45a8ff 1416 __I uint32_t SR; /* Status Register */
bogdanm 0:9b334a45a8ff 1417 __IO uint32_t CPSR; /* Clock Prescale Register */
bogdanm 0:9b334a45a8ff 1418 __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
bogdanm 0:9b334a45a8ff 1419 __I uint32_t RIS; /* Raw Interrupt Status Register */
bogdanm 0:9b334a45a8ff 1420 __I uint32_t MIS; /* Masked Interrupt Status Register */
bogdanm 0:9b334a45a8ff 1421 __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
bogdanm 0:9b334a45a8ff 1422 __IO uint32_t DMACR; /* SSPn DMA control register */
bogdanm 0:9b334a45a8ff 1423 } LPC_SSP_T;
bogdanm 0:9b334a45a8ff 1424
bogdanm 0:9b334a45a8ff 1425 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1426 * 32-bit Standard timer register block structure
bogdanm 0:9b334a45a8ff 1427 */
bogdanm 0:9b334a45a8ff 1428 #define LPC_TIMER0_BASE 0x40084000
bogdanm 0:9b334a45a8ff 1429 #define LPC_TIMER1_BASE 0x40085000
bogdanm 0:9b334a45a8ff 1430 #define LPC_TIMER2_BASE 0x400C3000
bogdanm 0:9b334a45a8ff 1431 #define LPC_TIMER3_BASE 0x400C4000
bogdanm 0:9b334a45a8ff 1432
bogdanm 0:9b334a45a8ff 1433 typedef struct { /* TIMERn Structure */
bogdanm 0:9b334a45a8ff 1434 __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
bogdanm 0:9b334a45a8ff 1435 __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
bogdanm 0:9b334a45a8ff 1436 __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
bogdanm 0:9b334a45a8ff 1437 __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
bogdanm 0:9b334a45a8ff 1438 __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
bogdanm 0:9b334a45a8ff 1439 __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
bogdanm 0:9b334a45a8ff 1440 __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
bogdanm 0:9b334a45a8ff 1441 __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
bogdanm 0:9b334a45a8ff 1442 __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
bogdanm 0:9b334a45a8ff 1443 __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
bogdanm 0:9b334a45a8ff 1444 __I uint32_t RESERVED0[12];
bogdanm 0:9b334a45a8ff 1445 __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
bogdanm 0:9b334a45a8ff 1446 } LPC_TIMER_T;
bogdanm 0:9b334a45a8ff 1447
bogdanm 0:9b334a45a8ff 1448 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1449 * System Control Unit register block
bogdanm 0:9b334a45a8ff 1450 */
bogdanm 0:9b334a45a8ff 1451 #define LPC_SCU_BASE 0x40086000
bogdanm 0:9b334a45a8ff 1452
bogdanm 0:9b334a45a8ff 1453 typedef struct {
bogdanm 0:9b334a45a8ff 1454 __IO uint32_t SFSP[16][32];
bogdanm 0:9b334a45a8ff 1455 __I uint32_t RESERVED0[256];
bogdanm 0:9b334a45a8ff 1456 __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
bogdanm 0:9b334a45a8ff 1457 __I uint32_t RESERVED16[28];
bogdanm 0:9b334a45a8ff 1458 __IO uint32_t SFSUSB; /* Pin configuration register for USB */
bogdanm 0:9b334a45a8ff 1459 __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
bogdanm 0:9b334a45a8ff 1460 __IO uint32_t ENAIO[3]; /* Analog function select registers */
bogdanm 0:9b334a45a8ff 1461 __I uint32_t RESERVED17[27];
bogdanm 0:9b334a45a8ff 1462 __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
bogdanm 0:9b334a45a8ff 1463 __I uint32_t RESERVED18[63];
bogdanm 0:9b334a45a8ff 1464 __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
bogdanm 0:9b334a45a8ff 1465 __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
bogdanm 0:9b334a45a8ff 1466 } LPC_SCU_T;
bogdanm 0:9b334a45a8ff 1467
bogdanm 0:9b334a45a8ff 1468 /*
bogdanm 0:9b334a45a8ff 1469 * SCU function and mode selection definitions
bogdanm 0:9b334a45a8ff 1470 * See the User Manual for specific modes and functions supoprted by the
bogdanm 0:9b334a45a8ff 1471 * various LPC18xx/43xx devices. Functionality can vary per device.
bogdanm 0:9b334a45a8ff 1472 */
bogdanm 0:9b334a45a8ff 1473 #define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
bogdanm 0:9b334a45a8ff 1474 #define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
bogdanm 0:9b334a45a8ff 1475 #define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
bogdanm 0:9b334a45a8ff 1476 #define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
bogdanm 0:9b334a45a8ff 1477 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
bogdanm 0:9b334a45a8ff 1478 #define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
bogdanm 0:9b334a45a8ff 1479 #define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
bogdanm 0:9b334a45a8ff 1480 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
bogdanm 0:9b334a45a8ff 1481 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
bogdanm 0:9b334a45a8ff 1482 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
bogdanm 0:9b334a45a8ff 1483 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
bogdanm 0:9b334a45a8ff 1484
bogdanm 0:9b334a45a8ff 1485 #define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
bogdanm 0:9b334a45a8ff 1486 #define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
bogdanm 0:9b334a45a8ff 1487 #define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
bogdanm 0:9b334a45a8ff 1488 #define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
bogdanm 0:9b334a45a8ff 1489 #define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
bogdanm 0:9b334a45a8ff 1490 #define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
bogdanm 0:9b334a45a8ff 1491 #define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
bogdanm 0:9b334a45a8ff 1492 #define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
bogdanm 0:9b334a45a8ff 1493
bogdanm 0:9b334a45a8ff 1494 /* Common SCU configurations */
bogdanm 0:9b334a45a8ff 1495 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
bogdanm 0:9b334a45a8ff 1496 #define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
bogdanm 0:9b334a45a8ff 1497 #define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
bogdanm 0:9b334a45a8ff 1498 #define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
bogdanm 0:9b334a45a8ff 1499
bogdanm 0:9b334a45a8ff 1500 /* Calculate SCU offset and register address from group and pin number */
bogdanm 0:9b334a45a8ff 1501 #define SCU_OFF(group, num) ((group << 7) + (num << 2))
bogdanm 0:9b334a45a8ff 1502 #define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
bogdanm 0:9b334a45a8ff 1503
bogdanm 0:9b334a45a8ff 1504 /**
bogdanm 0:9b334a45a8ff 1505 * SCU function and mode selection definitions (old)
bogdanm 0:9b334a45a8ff 1506 * For backwards compatibility.
bogdanm 0:9b334a45a8ff 1507 */
bogdanm 0:9b334a45a8ff 1508 #define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
bogdanm 0:9b334a45a8ff 1509 #define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
bogdanm 0:9b334a45a8ff 1510 #define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
bogdanm 0:9b334a45a8ff 1511 #define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
bogdanm 0:9b334a45a8ff 1512 #define MD_EHS (0x1 << 5) /* Enable fast slew rate */
bogdanm 0:9b334a45a8ff 1513 #define MD_EZI (0x1 << 6) /* Input buffer enable */
bogdanm 0:9b334a45a8ff 1514 #define MD_ZI (0x1 << 7) /* Disable input glitch filter */
bogdanm 0:9b334a45a8ff 1515 #define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
bogdanm 0:9b334a45a8ff 1516 #define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
bogdanm 0:9b334a45a8ff 1517 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
bogdanm 0:9b334a45a8ff 1518 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
bogdanm 0:9b334a45a8ff 1519 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
bogdanm 0:9b334a45a8ff 1520
bogdanm 0:9b334a45a8ff 1521 #define FUNC0 0x0 /* Pin function 0 */
bogdanm 0:9b334a45a8ff 1522 #define FUNC1 0x1 /* Pin function 1 */
bogdanm 0:9b334a45a8ff 1523 #define FUNC2 0x2 /* Pin function 2 */
bogdanm 0:9b334a45a8ff 1524 #define FUNC3 0x3 /* Pin function 3 */
bogdanm 0:9b334a45a8ff 1525 #define FUNC4 0x4 /* Pin function 4 */
bogdanm 0:9b334a45a8ff 1526 #define FUNC5 0x5 /* Pin function 5 */
bogdanm 0:9b334a45a8ff 1527 #define FUNC6 0x6 /* Pin function 6 */
bogdanm 0:9b334a45a8ff 1528 #define FUNC7 0x7 /* Pin function 7 */
bogdanm 0:9b334a45a8ff 1529
bogdanm 0:9b334a45a8ff 1530 #define PORT_OFFSET 0x80 /* Port offset definition */
bogdanm 0:9b334a45a8ff 1531 #define PIN_OFFSET 0x04 /* Pin offset definition */
bogdanm 0:9b334a45a8ff 1532
bogdanm 0:9b334a45a8ff 1533 /* Returns the SFSP register address in the SCU for a pin and port,
bogdanm 0:9b334a45a8ff 1534 recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
bogdanm 0:9b334a45a8ff 1535 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
bogdanm 0:9b334a45a8ff 1536 (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
bogdanm 0:9b334a45a8ff 1537
bogdanm 0:9b334a45a8ff 1538 /* Returns the address in the SCU for a SFSCLK clock register,
bogdanm 0:9b334a45a8ff 1539 recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
bogdanm 0:9b334a45a8ff 1540 #define LPC_SCU_CLK(LPC_SCU_BASE, c) \
bogdanm 0:9b334a45a8ff 1541 (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
bogdanm 0:9b334a45a8ff 1542
bogdanm 0:9b334a45a8ff 1543 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1544 * GPIO pin interrupt register block structure
bogdanm 0:9b334a45a8ff 1545 */
bogdanm 0:9b334a45a8ff 1546 #define LPC_GPIO_PIN_INT_BASE 0x40087000
bogdanm 0:9b334a45a8ff 1547
bogdanm 0:9b334a45a8ff 1548 typedef struct { /* GPIO_PIN_INT Structure */
bogdanm 0:9b334a45a8ff 1549 __IO uint32_t ISEL; /* Pin Interrupt Mode register */
bogdanm 0:9b334a45a8ff 1550 __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 1551 __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 1552 __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 1553 __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 0:9b334a45a8ff 1554 __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 0:9b334a45a8ff 1555 __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
bogdanm 0:9b334a45a8ff 1556 __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
bogdanm 0:9b334a45a8ff 1557 __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
bogdanm 0:9b334a45a8ff 1558 __IO uint32_t IST; /* Pin Interrupt Status register */
bogdanm 0:9b334a45a8ff 1559 } LPC_GPIOPININT_T;
bogdanm 0:9b334a45a8ff 1560
bogdanm 0:9b334a45a8ff 1561 typedef enum LPC_GPIOPININT_MODE {
bogdanm 0:9b334a45a8ff 1562 GPIOPININT_RISING_EDGE = 0x01,
bogdanm 0:9b334a45a8ff 1563 GPIOPININT_FALLING_EDGE = 0x02,
bogdanm 0:9b334a45a8ff 1564 GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
bogdanm 0:9b334a45a8ff 1565 GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
bogdanm 0:9b334a45a8ff 1566 } LPC_GPIOPININT_MODE_T;
bogdanm 0:9b334a45a8ff 1567
bogdanm 0:9b334a45a8ff 1568 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1569 * GPIO grouped interrupt register block structure
bogdanm 0:9b334a45a8ff 1570 */
bogdanm 0:9b334a45a8ff 1571 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
bogdanm 0:9b334a45a8ff 1572 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
bogdanm 0:9b334a45a8ff 1573
bogdanm 0:9b334a45a8ff 1574 typedef struct { /* GPIO_GROUP_INTn Structure */
bogdanm 0:9b334a45a8ff 1575 __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
bogdanm 0:9b334a45a8ff 1576 __I uint32_t RESERVED0[7];
bogdanm 0:9b334a45a8ff 1577 __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
bogdanm 0:9b334a45a8ff 1578 __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
bogdanm 0:9b334a45a8ff 1579 } LPC_GPIOGROUPINT_T;
bogdanm 0:9b334a45a8ff 1580
bogdanm 0:9b334a45a8ff 1581 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1582 * Motor Control PWM register block structure
bogdanm 0:9b334a45a8ff 1583 */
bogdanm 0:9b334a45a8ff 1584 #define LPC_MCPWM_BASE 0x400A0000
bogdanm 0:9b334a45a8ff 1585
bogdanm 0:9b334a45a8ff 1586 typedef struct { /* MCPWM Structure */
bogdanm 0:9b334a45a8ff 1587 __I uint32_t CON; /* PWM Control read address */
bogdanm 0:9b334a45a8ff 1588 __O uint32_t CON_SET; /* PWM Control set address */
bogdanm 0:9b334a45a8ff 1589 __O uint32_t CON_CLR; /* PWM Control clear address */
bogdanm 0:9b334a45a8ff 1590 __I uint32_t CAPCON; /* Capture Control read address */
bogdanm 0:9b334a45a8ff 1591 __O uint32_t CAPCON_SET; /* Capture Control set address */
bogdanm 0:9b334a45a8ff 1592 __O uint32_t CAPCON_CLR; /* Event Control clear address */
bogdanm 0:9b334a45a8ff 1593 __IO uint32_t TC[3]; /* Timer Counter register */
bogdanm 0:9b334a45a8ff 1594 __IO uint32_t LIM[3]; /* Limit register */
bogdanm 0:9b334a45a8ff 1595 __IO uint32_t MAT[3]; /* Match register */
bogdanm 0:9b334a45a8ff 1596 __IO uint32_t DT; /* Dead time register */
bogdanm 0:9b334a45a8ff 1597 __IO uint32_t CCP; /* Communication Pattern register */
bogdanm 0:9b334a45a8ff 1598 __I uint32_t CAP[3]; /* Capture register */
bogdanm 0:9b334a45a8ff 1599 __I uint32_t INTEN; /* Interrupt Enable read address */
bogdanm 0:9b334a45a8ff 1600 __O uint32_t INTEN_SET; /* Interrupt Enable set address */
bogdanm 0:9b334a45a8ff 1601 __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
bogdanm 0:9b334a45a8ff 1602 __I uint32_t CNTCON; /* Count Control read address */
bogdanm 0:9b334a45a8ff 1603 __O uint32_t CNTCON_SET; /* Count Control set address */
bogdanm 0:9b334a45a8ff 1604 __O uint32_t CNTCON_CLR; /* Count Control clear address */
bogdanm 0:9b334a45a8ff 1605 __I uint32_t INTF; /* Interrupt flags read address */
bogdanm 0:9b334a45a8ff 1606 __O uint32_t INTF_SET; /* Interrupt flags set address */
bogdanm 0:9b334a45a8ff 1607 __O uint32_t INTF_CLR; /* Interrupt flags clear address */
bogdanm 0:9b334a45a8ff 1608 __O uint32_t CAP_CLR; /* Capture clear address */
bogdanm 0:9b334a45a8ff 1609 } LPC_MCPWM_T;
bogdanm 0:9b334a45a8ff 1610
bogdanm 0:9b334a45a8ff 1611 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1612 * I2C register block structure
bogdanm 0:9b334a45a8ff 1613 */
bogdanm 0:9b334a45a8ff 1614 #define LPC_I2C0_BASE 0x400A1000
bogdanm 0:9b334a45a8ff 1615 #define LPC_I2C1_BASE 0x400E0000
bogdanm 0:9b334a45a8ff 1616
bogdanm 0:9b334a45a8ff 1617 typedef struct { /* I2C0 Structure */
bogdanm 0:9b334a45a8ff 1618 __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
bogdanm 0:9b334a45a8ff 1619 __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
bogdanm 0:9b334a45a8ff 1620 __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
bogdanm 0:9b334a45a8ff 1621 __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
bogdanm 0:9b334a45a8ff 1622 __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
bogdanm 0:9b334a45a8ff 1623 __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
bogdanm 0:9b334a45a8ff 1624 __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
bogdanm 0:9b334a45a8ff 1625 __IO uint32_t MMCTRL; /* Monitor mode control register. */
bogdanm 0:9b334a45a8ff 1626 __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
bogdanm 0:9b334a45a8ff 1627 __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
bogdanm 0:9b334a45a8ff 1628 __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
bogdanm 0:9b334a45a8ff 1629 __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
bogdanm 0:9b334a45a8ff 1630 __IO uint32_t MASK[4]; /* I2C Slave address mask register */
bogdanm 0:9b334a45a8ff 1631 } LPC_I2C_T;
bogdanm 0:9b334a45a8ff 1632
bogdanm 0:9b334a45a8ff 1633 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1634 * I2S register block structure
bogdanm 0:9b334a45a8ff 1635 */
bogdanm 0:9b334a45a8ff 1636 #define LPC_I2S0_BASE 0x400A2000
bogdanm 0:9b334a45a8ff 1637 #define LPC_I2S1_BASE 0x400A3000
bogdanm 0:9b334a45a8ff 1638
bogdanm 0:9b334a45a8ff 1639 typedef struct { /* I2S Structure */
bogdanm 0:9b334a45a8ff 1640 __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
bogdanm 0:9b334a45a8ff 1641 __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
bogdanm 0:9b334a45a8ff 1642 __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
bogdanm 0:9b334a45a8ff 1643 __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
bogdanm 0:9b334a45a8ff 1644 __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
bogdanm 0:9b334a45a8ff 1645 __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
bogdanm 0:9b334a45a8ff 1646 __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
bogdanm 0:9b334a45a8ff 1647 __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
bogdanm 0:9b334a45a8ff 1648 __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
bogdanm 0:9b334a45a8ff 1649 __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
bogdanm 0:9b334a45a8ff 1650 __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
bogdanm 0:9b334a45a8ff 1651 __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
bogdanm 0:9b334a45a8ff 1652 __IO uint32_t TXMODE; /* I2S Transmit mode control */
bogdanm 0:9b334a45a8ff 1653 __IO uint32_t RXMODE; /* I2S Receive mode control */
bogdanm 0:9b334a45a8ff 1654 } LPC_I2S_T;
bogdanm 0:9b334a45a8ff 1655
bogdanm 0:9b334a45a8ff 1656 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1657 * CCAN Controller Area Network register block structure
bogdanm 0:9b334a45a8ff 1658 */
bogdanm 0:9b334a45a8ff 1659 #define LPC_C_CAN1_BASE 0x400A4000
bogdanm 0:9b334a45a8ff 1660 #define LPC_C_CAN0_BASE 0x400E2000
bogdanm 0:9b334a45a8ff 1661
bogdanm 0:9b334a45a8ff 1662 typedef struct { /* C_CAN message interface Structure */
bogdanm 0:9b334a45a8ff 1663 __IO uint32_t IF_CMDREQ; /* Message interface command request */
bogdanm 0:9b334a45a8ff 1664 union {
bogdanm 0:9b334a45a8ff 1665 __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
bogdanm 0:9b334a45a8ff 1666 __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
bogdanm 0:9b334a45a8ff 1667 };
bogdanm 0:9b334a45a8ff 1668
bogdanm 0:9b334a45a8ff 1669 __IO uint32_t IF_MSK1; /* Message interface mask 1 */
bogdanm 0:9b334a45a8ff 1670 __IO uint32_t IF_MSK2; /* Message interface mask 2 */
bogdanm 0:9b334a45a8ff 1671 __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
bogdanm 0:9b334a45a8ff 1672 __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
bogdanm 0:9b334a45a8ff 1673 __IO uint32_t IF_MCTRL; /* Message interface message control */
bogdanm 0:9b334a45a8ff 1674 __IO uint32_t IF_DA1; /* Message interface data A1 */
bogdanm 0:9b334a45a8ff 1675 __IO uint32_t IF_DA2; /* Message interface data A2 */
bogdanm 0:9b334a45a8ff 1676 __IO uint32_t IF_DB1; /* Message interface data B1 */
bogdanm 0:9b334a45a8ff 1677 __IO uint32_t IF_DB2; /* Message interface data B2 */
bogdanm 0:9b334a45a8ff 1678 __I uint32_t RESERVED[13];
bogdanm 0:9b334a45a8ff 1679 } LPC_CCAN_IF_T;
bogdanm 0:9b334a45a8ff 1680
bogdanm 0:9b334a45a8ff 1681 typedef struct { /* C_CAN Structure */
bogdanm 0:9b334a45a8ff 1682 __IO uint32_t CNTL; /* CAN control */
bogdanm 0:9b334a45a8ff 1683 __IO uint32_t STAT; /* Status register */
bogdanm 0:9b334a45a8ff 1684 __I uint32_t EC; /* Error counter */
bogdanm 0:9b334a45a8ff 1685 __IO uint32_t BT; /* Bit timing register */
bogdanm 0:9b334a45a8ff 1686 __I uint32_t INT; /* Interrupt register */
bogdanm 0:9b334a45a8ff 1687 __IO uint32_t TEST; /* Test register */
bogdanm 0:9b334a45a8ff 1688 __IO uint32_t BRPE; /* Baud rate prescaler extension register */
bogdanm 0:9b334a45a8ff 1689 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 1690 LPC_CCAN_IF_T IF[2];
bogdanm 0:9b334a45a8ff 1691 __I uint32_t RESERVED2[8];
bogdanm 0:9b334a45a8ff 1692 __I uint32_t TXREQ1; /* Transmission request 1 */
bogdanm 0:9b334a45a8ff 1693 __I uint32_t TXREQ2; /* Transmission request 2 */
bogdanm 0:9b334a45a8ff 1694 __I uint32_t RESERVED3[6];
bogdanm 0:9b334a45a8ff 1695 __I uint32_t ND1; /* New data 1 */
bogdanm 0:9b334a45a8ff 1696 __I uint32_t ND2; /* New data 2 */
bogdanm 0:9b334a45a8ff 1697 __I uint32_t RESERVED4[6];
bogdanm 0:9b334a45a8ff 1698 __I uint32_t IR1; /* Interrupt pending 1 */
bogdanm 0:9b334a45a8ff 1699 __I uint32_t IR2; /* Interrupt pending 2 */
bogdanm 0:9b334a45a8ff 1700 __I uint32_t RESERVED5[6];
bogdanm 0:9b334a45a8ff 1701 __I uint32_t MSGV1; /* Message valid 1 */
bogdanm 0:9b334a45a8ff 1702 __I uint32_t MSGV2; /* Message valid 2 */
bogdanm 0:9b334a45a8ff 1703 __I uint32_t RESERVED6[6];
bogdanm 0:9b334a45a8ff 1704 __IO uint32_t CLKDIV; /* CAN clock divider register */
bogdanm 0:9b334a45a8ff 1705 } LPC_CCAN_T;
bogdanm 0:9b334a45a8ff 1706
bogdanm 0:9b334a45a8ff 1707 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1708 * Repetitive Interrupt Timer register block structure
bogdanm 0:9b334a45a8ff 1709 */
bogdanm 0:9b334a45a8ff 1710 #define LPC_RITIMER_BASE 0x400C0000
bogdanm 0:9b334a45a8ff 1711
bogdanm 0:9b334a45a8ff 1712 typedef struct { /* RITIMER Structure */
bogdanm 0:9b334a45a8ff 1713 __IO uint32_t COMPVAL; /* Compare register */
bogdanm 0:9b334a45a8ff 1714 __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
bogdanm 0:9b334a45a8ff 1715 __IO uint32_t CTRL; /* Control register. */
bogdanm 0:9b334a45a8ff 1716 __IO uint32_t COUNTER; /* 32-bit counter */
bogdanm 0:9b334a45a8ff 1717 } LPC_RITIMER_T;
bogdanm 0:9b334a45a8ff 1718
bogdanm 0:9b334a45a8ff 1719 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1720 * Quadrature Encoder Interface register block structure
bogdanm 0:9b334a45a8ff 1721 */
bogdanm 0:9b334a45a8ff 1722 #define LPC_QEI_BASE 0x400C6000
bogdanm 0:9b334a45a8ff 1723
bogdanm 0:9b334a45a8ff 1724 typedef struct { /* QEI Structure */
bogdanm 0:9b334a45a8ff 1725 __O uint32_t CON; /* Control register */
bogdanm 0:9b334a45a8ff 1726 __I uint32_t STAT; /* Encoder status register */
bogdanm 0:9b334a45a8ff 1727 __IO uint32_t CONF; /* Configuration register */
bogdanm 0:9b334a45a8ff 1728 __I uint32_t POS; /* Position register */
bogdanm 0:9b334a45a8ff 1729 __IO uint32_t MAXPOS; /* Maximum position register */
bogdanm 0:9b334a45a8ff 1730 __IO uint32_t CMPOS0; /* position compare register 0 */
bogdanm 0:9b334a45a8ff 1731 __IO uint32_t CMPOS1; /* position compare register 1 */
bogdanm 0:9b334a45a8ff 1732 __IO uint32_t CMPOS2; /* position compare register 2 */
bogdanm 0:9b334a45a8ff 1733 __I uint32_t INXCNT; /* Index count register */
bogdanm 0:9b334a45a8ff 1734 __IO uint32_t INXCMP0; /* Index compare register 0 */
bogdanm 0:9b334a45a8ff 1735 __IO uint32_t LOAD; /* Velocity timer reload register */
bogdanm 0:9b334a45a8ff 1736 __I uint32_t TIME; /* Velocity timer register */
bogdanm 0:9b334a45a8ff 1737 __I uint32_t VEL; /* Velocity counter register */
bogdanm 0:9b334a45a8ff 1738 __I uint32_t CAP; /* Velocity capture register */
bogdanm 0:9b334a45a8ff 1739 __IO uint32_t VELCOMP; /* Velocity compare register */
bogdanm 0:9b334a45a8ff 1740 __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
bogdanm 0:9b334a45a8ff 1741 __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
bogdanm 0:9b334a45a8ff 1742 __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
bogdanm 0:9b334a45a8ff 1743 __IO uint32_t WINDOW; /* Index acceptance window register */
bogdanm 0:9b334a45a8ff 1744 __IO uint32_t INXCMP1; /* Index compare register 1 */
bogdanm 0:9b334a45a8ff 1745 __IO uint32_t INXCMP2; /* Index compare register 2 */
bogdanm 0:9b334a45a8ff 1746 __I uint32_t RESERVED0[993];
bogdanm 0:9b334a45a8ff 1747 __O uint32_t IEC; /* Interrupt enable clear register */
bogdanm 0:9b334a45a8ff 1748 __O uint32_t IES; /* Interrupt enable set register */
bogdanm 0:9b334a45a8ff 1749 __I uint32_t INTSTAT; /* Interrupt status register */
bogdanm 0:9b334a45a8ff 1750 __I uint32_t IE; /* Interrupt enable register */
bogdanm 0:9b334a45a8ff 1751 __O uint32_t CLR; /* Interrupt status clear register */
bogdanm 0:9b334a45a8ff 1752 __O uint32_t SET; /* Interrupt status set register */
bogdanm 0:9b334a45a8ff 1753 } LPC_QEI_T;
bogdanm 0:9b334a45a8ff 1754
bogdanm 0:9b334a45a8ff 1755 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1756 * Global Input Multiplexer Array (GIMA) register block structure
bogdanm 0:9b334a45a8ff 1757 */
bogdanm 0:9b334a45a8ff 1758 #define LPC_GIMA_BASE 0x400C7000
bogdanm 0:9b334a45a8ff 1759
bogdanm 0:9b334a45a8ff 1760 typedef struct { /* GIMA Structure */
bogdanm 0:9b334a45a8ff 1761 __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
bogdanm 0:9b334a45a8ff 1762 __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
bogdanm 0:9b334a45a8ff 1763 __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
bogdanm 0:9b334a45a8ff 1764 __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
bogdanm 0:9b334a45a8ff 1765 __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
bogdanm 0:9b334a45a8ff 1766 __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
bogdanm 0:9b334a45a8ff 1767 __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
bogdanm 0:9b334a45a8ff 1768 __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
bogdanm 0:9b334a45a8ff 1769 } LPC_GIMA_T;
bogdanm 0:9b334a45a8ff 1770
bogdanm 0:9b334a45a8ff 1771 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1772 * DAC register block structure
bogdanm 0:9b334a45a8ff 1773 */
bogdanm 0:9b334a45a8ff 1774 #define LPC_DAC_BASE 0x400E1000
bogdanm 0:9b334a45a8ff 1775
bogdanm 0:9b334a45a8ff 1776 typedef struct { /* DAC Structure */
bogdanm 0:9b334a45a8ff 1777 __IO uint32_t CR; /* DAC register. Holds the conversion data. */
bogdanm 0:9b334a45a8ff 1778 __IO uint32_t CTRL; /* DAC control register. */
bogdanm 0:9b334a45a8ff 1779 __IO uint32_t CNTVAL; /* DAC counter value register. */
bogdanm 0:9b334a45a8ff 1780 } LPC_DAC_T;
bogdanm 0:9b334a45a8ff 1781
bogdanm 0:9b334a45a8ff 1782 /* After the selected settling time after this field is written with a
bogdanm 0:9b334a45a8ff 1783 * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
bogdanm 0:9b334a45a8ff 1784 * is VALUE/1024 ? VREF
bogdanm 0:9b334a45a8ff 1785 */
bogdanm 0:9b334a45a8ff 1786 #define DAC_RANGE 0x3FF
bogdanm 0:9b334a45a8ff 1787 #define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
bogdanm 0:9b334a45a8ff 1788 #define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
bogdanm 0:9b334a45a8ff 1789 #define DAC_VALUE(n) DAC_SET(n)
bogdanm 0:9b334a45a8ff 1790 /* If this bit = 0: The settling time of the DAC is 1 microsecond max,
bogdanm 0:9b334a45a8ff 1791 * and the maximum current is 700 microAmpere
bogdanm 0:9b334a45a8ff 1792 * If this bit = 1: The settling time of the DAC is 2.5 microsecond
bogdanm 0:9b334a45a8ff 1793 * and the maximum current is 350 microAmpere
bogdanm 0:9b334a45a8ff 1794 */
bogdanm 0:9b334a45a8ff 1795 #define DAC_BIAS_EN ((uint32_t) (1 << 16))
bogdanm 0:9b334a45a8ff 1796 /* Value to reload interrupt DMA counter */
bogdanm 0:9b334a45a8ff 1797 #define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
bogdanm 0:9b334a45a8ff 1798
bogdanm 0:9b334a45a8ff 1799 #define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
bogdanm 0:9b334a45a8ff 1800 #define DAC_CNT_ENA ((uint32_t) (1 << 2))
bogdanm 0:9b334a45a8ff 1801 #define DAC_DMA_ENA ((uint32_t) (1 << 3))
bogdanm 0:9b334a45a8ff 1802 #define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
bogdanm 0:9b334a45a8ff 1803
bogdanm 0:9b334a45a8ff 1804 /* Current option in DAC configuration option */
bogdanm 0:9b334a45a8ff 1805 typedef enum DAC_CURRENT_OPT {
bogdanm 0:9b334a45a8ff 1806 DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
bogdanm 0:9b334a45a8ff 1807 allows for a maximum update rate of 1 MHz */
bogdanm 0:9b334a45a8ff 1808 DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
bogdanm 0:9b334a45a8ff 1809 allows for a maximum update rate of 400 kHz */
bogdanm 0:9b334a45a8ff 1810 } DAC_CURRENT_OPT_T;
bogdanm 0:9b334a45a8ff 1811
bogdanm 0:9b334a45a8ff 1812 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1813 * ADC register block structure
bogdanm 0:9b334a45a8ff 1814 */
bogdanm 0:9b334a45a8ff 1815 #define LPC_ADC0_BASE 0x400E3000
bogdanm 0:9b334a45a8ff 1816 #define LPC_ADC1_BASE 0x400E4000
bogdanm 0:9b334a45a8ff 1817 #define ADC_ACC_10BITS
bogdanm 0:9b334a45a8ff 1818
bogdanm 0:9b334a45a8ff 1819 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1820 * 10 or 12-bit ADC register block structure
bogdanm 0:9b334a45a8ff 1821 */
bogdanm 0:9b334a45a8ff 1822 typedef struct { /* ADCn Structure */
bogdanm 0:9b334a45a8ff 1823 __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
bogdanm 0:9b334a45a8ff 1824 __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
bogdanm 0:9b334a45a8ff 1825 __I uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 1826 __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
bogdanm 0:9b334a45a8ff 1827 __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
bogdanm 0:9b334a45a8ff 1828 __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
bogdanm 0:9b334a45a8ff 1829 } LPC_ADC_T;
bogdanm 0:9b334a45a8ff 1830
bogdanm 0:9b334a45a8ff 1831 /* ADC register support bitfields and mask */
bogdanm 0:9b334a45a8ff 1832 #define ADC_RANGE 0x3FF
bogdanm 0:9b334a45a8ff 1833 #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
bogdanm 0:9b334a45a8ff 1834 #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
bogdanm 0:9b334a45a8ff 1835 #define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
bogdanm 0:9b334a45a8ff 1836 #define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
bogdanm 0:9b334a45a8ff 1837 #define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
bogdanm 0:9b334a45a8ff 1838 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
bogdanm 0:9b334a45a8ff 1839 #define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
bogdanm 0:9b334a45a8ff 1840 #define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
bogdanm 0:9b334a45a8ff 1841 #define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
bogdanm 0:9b334a45a8ff 1842 #define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
bogdanm 0:9b334a45a8ff 1843 #define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
bogdanm 0:9b334a45a8ff 1844 #define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
bogdanm 0:9b334a45a8ff 1845 #define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
bogdanm 0:9b334a45a8ff 1846 #define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
bogdanm 0:9b334a45a8ff 1847 #define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
bogdanm 0:9b334a45a8ff 1848 #define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
bogdanm 0:9b334a45a8ff 1849 #define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
bogdanm 0:9b334a45a8ff 1850 #define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
bogdanm 0:9b334a45a8ff 1851
bogdanm 0:9b334a45a8ff 1852 /* ADC status register used for IP drivers */
bogdanm 0:9b334a45a8ff 1853 typedef enum ADC_STATUS {
bogdanm 0:9b334a45a8ff 1854 ADC_DR_DONE_STAT, /* ADC data register staus */
bogdanm 0:9b334a45a8ff 1855 ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
bogdanm 0:9b334a45a8ff 1856 ADC_DR_ADINT_STAT /* ADC interrupt status */
bogdanm 0:9b334a45a8ff 1857 } ADC_STATUS_T;
bogdanm 0:9b334a45a8ff 1858
bogdanm 0:9b334a45a8ff 1859 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
bogdanm 0:9b334a45a8ff 1860 typedef enum ADC_START_MODE {
bogdanm 0:9b334a45a8ff 1861 ADC_NO_START = 0,
bogdanm 0:9b334a45a8ff 1862 ADC_START_NOW, /* Start conversion now */
bogdanm 0:9b334a45a8ff 1863 ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
bogdanm 0:9b334a45a8ff 1864 ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
bogdanm 0:9b334a45a8ff 1865 ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
bogdanm 0:9b334a45a8ff 1866 ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
bogdanm 0:9b334a45a8ff 1867 ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
bogdanm 0:9b334a45a8ff 1868 } ADC_START_MODE_T;
bogdanm 0:9b334a45a8ff 1869
bogdanm 0:9b334a45a8ff 1870 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1871 * GPIO port register block structure
bogdanm 0:9b334a45a8ff 1872 */
bogdanm 0:9b334a45a8ff 1873 #define LPC_GPIO_PORT_BASE 0x400F4000
bogdanm 0:9b334a45a8ff 1874 #define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
bogdanm 0:9b334a45a8ff 1875 #define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
bogdanm 0:9b334a45a8ff 1876 #define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
bogdanm 0:9b334a45a8ff 1877 #define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
bogdanm 0:9b334a45a8ff 1878 #define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
bogdanm 0:9b334a45a8ff 1879 #define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
bogdanm 0:9b334a45a8ff 1880 #define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
bogdanm 0:9b334a45a8ff 1881 #define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
bogdanm 0:9b334a45a8ff 1882
bogdanm 0:9b334a45a8ff 1883 typedef struct { /* GPIO_PORT Structure */
bogdanm 0:9b334a45a8ff 1884 __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
bogdanm 0:9b334a45a8ff 1885 __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
bogdanm 0:9b334a45a8ff 1886 __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
bogdanm 0:9b334a45a8ff 1887 __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
bogdanm 0:9b334a45a8ff 1888 __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
bogdanm 0:9b334a45a8ff 1889 __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
bogdanm 0:9b334a45a8ff 1890 __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
bogdanm 0:9b334a45a8ff 1891 __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
bogdanm 0:9b334a45a8ff 1892 __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
bogdanm 0:9b334a45a8ff 1893 } LPC_GPIO_T;
bogdanm 0:9b334a45a8ff 1894
bogdanm 0:9b334a45a8ff 1895 /* Calculate GPIO offset and port register address from group and pin number */
bogdanm 0:9b334a45a8ff 1896 #define GPIO_OFF(port, pin) ((port << 5) + pin)
bogdanm 0:9b334a45a8ff 1897 #define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
bogdanm 0:9b334a45a8ff 1898
bogdanm 0:9b334a45a8ff 1899 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1900 * SPI register block structure
bogdanm 0:9b334a45a8ff 1901 */
bogdanm 0:9b334a45a8ff 1902 #define LPC_SPI_BASE 0x40100000
bogdanm 0:9b334a45a8ff 1903
bogdanm 0:9b334a45a8ff 1904 typedef struct { /* SPI Structure */
bogdanm 0:9b334a45a8ff 1905 __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
bogdanm 0:9b334a45a8ff 1906 __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
bogdanm 0:9b334a45a8ff 1907 __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
bogdanm 0:9b334a45a8ff 1908 __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
bogdanm 0:9b334a45a8ff 1909 __I uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 1910 __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
bogdanm 0:9b334a45a8ff 1911 } LPC_SPI_T;
bogdanm 0:9b334a45a8ff 1912
bogdanm 0:9b334a45a8ff 1913 /* SPI CFG Register BitMask */
bogdanm 0:9b334a45a8ff 1914 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
bogdanm 0:9b334a45a8ff 1915 /* Enable of controlling the number of bits per transfer */
bogdanm 0:9b334a45a8ff 1916 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
bogdanm 0:9b334a45a8ff 1917 /* Mask of field of bit controlling */
bogdanm 0:9b334a45a8ff 1918 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
bogdanm 0:9b334a45a8ff 1919 /* Set the number of bits per a transfer */
bogdanm 0:9b334a45a8ff 1920 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
bogdanm 0:9b334a45a8ff 1921 /* SPI Clock Phase Select*/
bogdanm 0:9b334a45a8ff 1922 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
bogdanm 0:9b334a45a8ff 1923 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
bogdanm 0:9b334a45a8ff 1924 /* SPI Clock Polarity Select*/
bogdanm 0:9b334a45a8ff 1925 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
bogdanm 0:9b334a45a8ff 1926 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
bogdanm 0:9b334a45a8ff 1927 /* SPI Slave Mode Select */
bogdanm 0:9b334a45a8ff 1928 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
bogdanm 0:9b334a45a8ff 1929 /* SPI Master Mode Select */
bogdanm 0:9b334a45a8ff 1930 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
bogdanm 0:9b334a45a8ff 1931 /* SPI MSB First mode enable */
bogdanm 0:9b334a45a8ff 1932 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
bogdanm 0:9b334a45a8ff 1933 /* SPI LSB First mode enable */
bogdanm 0:9b334a45a8ff 1934 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
bogdanm 0:9b334a45a8ff 1935 /* SPI interrupt enable */
bogdanm 0:9b334a45a8ff 1936 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
bogdanm 0:9b334a45a8ff 1937 /* SPI STAT Register BitMask */
bogdanm 0:9b334a45a8ff 1938 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
bogdanm 0:9b334a45a8ff 1939 /* Slave abort Flag */
bogdanm 0:9b334a45a8ff 1940 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
bogdanm 0:9b334a45a8ff 1941 /* Mode fault Flag */
bogdanm 0:9b334a45a8ff 1942 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
bogdanm 0:9b334a45a8ff 1943 /* Read overrun flag*/
bogdanm 0:9b334a45a8ff 1944 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
bogdanm 0:9b334a45a8ff 1945 /* Write collision flag. */
bogdanm 0:9b334a45a8ff 1946 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
bogdanm 0:9b334a45a8ff 1947 /* SPI transfer complete flag. */
bogdanm 0:9b334a45a8ff 1948 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
bogdanm 0:9b334a45a8ff 1949 /* SPI error flag */
bogdanm 0:9b334a45a8ff 1950 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
bogdanm 0:9b334a45a8ff 1951 /* Enable SPI Test Mode */
bogdanm 0:9b334a45a8ff 1952 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
bogdanm 0:9b334a45a8ff 1953 /* SPI interrupt flag */
bogdanm 0:9b334a45a8ff 1954 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
bogdanm 0:9b334a45a8ff 1955 /* Receiver Data */
bogdanm 0:9b334a45a8ff 1956 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
bogdanm 0:9b334a45a8ff 1957
bogdanm 0:9b334a45a8ff 1958 /* SPI Mode*/
bogdanm 0:9b334a45a8ff 1959 typedef enum LPC_SPI_MODE {
bogdanm 0:9b334a45a8ff 1960 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
bogdanm 0:9b334a45a8ff 1961 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
bogdanm 0:9b334a45a8ff 1962 } LPC_SPI_MODE_T;
bogdanm 0:9b334a45a8ff 1963
bogdanm 0:9b334a45a8ff 1964 /* SPI Clock Mode*/
bogdanm 0:9b334a45a8ff 1965 typedef enum LPC_SPI_CLOCK_MODE {
bogdanm 0:9b334a45a8ff 1966 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
bogdanm 0:9b334a45a8ff 1967 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
bogdanm 0:9b334a45a8ff 1968 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
bogdanm 0:9b334a45a8ff 1969 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
bogdanm 0:9b334a45a8ff 1970 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
bogdanm 0:9b334a45a8ff 1971 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
bogdanm 0:9b334a45a8ff 1972 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
bogdanm 0:9b334a45a8ff 1973 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
bogdanm 0:9b334a45a8ff 1974 } LPC_SPI_CLOCK_MODE_T;
bogdanm 0:9b334a45a8ff 1975
bogdanm 0:9b334a45a8ff 1976 /* SPI Data Order Mode*/
bogdanm 0:9b334a45a8ff 1977 typedef enum LPC_SPI_DATA_ORDER {
bogdanm 0:9b334a45a8ff 1978 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
bogdanm 0:9b334a45a8ff 1979 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
bogdanm 0:9b334a45a8ff 1980 } LPC_SPI_DATA_ORDER_T;
bogdanm 0:9b334a45a8ff 1981
bogdanm 0:9b334a45a8ff 1982 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1983 * Serial GPIO register block structure
bogdanm 0:9b334a45a8ff 1984 */
bogdanm 0:9b334a45a8ff 1985 #define LPC_SGPIO_BASE 0x40101000
bogdanm 0:9b334a45a8ff 1986
bogdanm 0:9b334a45a8ff 1987 typedef struct { /* SGPIO Structure */
bogdanm 0:9b334a45a8ff 1988 __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
bogdanm 0:9b334a45a8ff 1989 __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
bogdanm 0:9b334a45a8ff 1990 __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
bogdanm 0:9b334a45a8ff 1991 __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
bogdanm 0:9b334a45a8ff 1992 __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
bogdanm 0:9b334a45a8ff 1993 __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
bogdanm 0:9b334a45a8ff 1994 __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
bogdanm 0:9b334a45a8ff 1995 __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
bogdanm 0:9b334a45a8ff 1996 __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
bogdanm 0:9b334a45a8ff 1997 __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
bogdanm 0:9b334a45a8ff 1998 __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
bogdanm 0:9b334a45a8ff 1999 __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
bogdanm 0:9b334a45a8ff 2000 __I uint32_t GPIO_INREG; /* GPIO input status register */
bogdanm 0:9b334a45a8ff 2001 __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
bogdanm 0:9b334a45a8ff 2002 __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
bogdanm 0:9b334a45a8ff 2003 __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
bogdanm 0:9b334a45a8ff 2004 __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
bogdanm 0:9b334a45a8ff 2005 __I uint32_t RESERVED0[823];
bogdanm 0:9b334a45a8ff 2006 __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
bogdanm 0:9b334a45a8ff 2007 __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
bogdanm 0:9b334a45a8ff 2008 __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
bogdanm 0:9b334a45a8ff 2009 __I uint32_t STATUS_0; /* Shift clock interrupt status */
bogdanm 0:9b334a45a8ff 2010 __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
bogdanm 0:9b334a45a8ff 2011 __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
bogdanm 0:9b334a45a8ff 2012 __I uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 2013 __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
bogdanm 0:9b334a45a8ff 2014 __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
bogdanm 0:9b334a45a8ff 2015 __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
bogdanm 0:9b334a45a8ff 2016 __I uint32_t STATUS_1; /* Capture clock interrupt status */
bogdanm 0:9b334a45a8ff 2017 __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
bogdanm 0:9b334a45a8ff 2018 __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
bogdanm 0:9b334a45a8ff 2019 __I uint32_t RESERVED2[2];
bogdanm 0:9b334a45a8ff 2020 __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
bogdanm 0:9b334a45a8ff 2021 __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
bogdanm 0:9b334a45a8ff 2022 __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
bogdanm 0:9b334a45a8ff 2023 __I uint32_t STATUS_2; /* Pattern match interrupt status */
bogdanm 0:9b334a45a8ff 2024 __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
bogdanm 0:9b334a45a8ff 2025 __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
bogdanm 0:9b334a45a8ff 2026 __I uint32_t RESERVED3[2];
bogdanm 0:9b334a45a8ff 2027 __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
bogdanm 0:9b334a45a8ff 2028 __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
bogdanm 0:9b334a45a8ff 2029 __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
bogdanm 0:9b334a45a8ff 2030 __I uint32_t STATUS_3; /* Input bit match interrupt status */
bogdanm 0:9b334a45a8ff 2031 __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
bogdanm 0:9b334a45a8ff 2032 __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
bogdanm 0:9b334a45a8ff 2033 } LPC_SGPIO_T;
bogdanm 0:9b334a45a8ff 2034
bogdanm 0:9b334a45a8ff 2035 /* End of section using anonymous unions */
bogdanm 0:9b334a45a8ff 2036 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 2037 #pragma pop
bogdanm 0:9b334a45a8ff 2038 #elif defined(__CWCC__)
bogdanm 0:9b334a45a8ff 2039 #pragma pop
bogdanm 0:9b334a45a8ff 2040 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 2041 //#pragma pop // FIXME not usable for IAR
bogdanm 0:9b334a45a8ff 2042 #else /* defined(__GNUC__) and others */
bogdanm 0:9b334a45a8ff 2043 /* Leave anonymous unions enabled */
bogdanm 0:9b334a45a8ff 2044 #endif
bogdanm 0:9b334a45a8ff 2045
bogdanm 0:9b334a45a8ff 2046 /* ---------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2047 * LPC43xx Peripheral register set declarations
bogdanm 0:9b334a45a8ff 2048 */
bogdanm 0:9b334a45a8ff 2049 #define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
bogdanm 0:9b334a45a8ff 2050 #define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
bogdanm 0:9b334a45a8ff 2051 #define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
bogdanm 0:9b334a45a8ff 2052 #define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
bogdanm 0:9b334a45a8ff 2053 #define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
bogdanm 0:9b334a45a8ff 2054 #define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
bogdanm 0:9b334a45a8ff 2055 #define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
bogdanm 0:9b334a45a8ff 2056 #define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
bogdanm 0:9b334a45a8ff 2057 #define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
bogdanm 0:9b334a45a8ff 2058 #define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
bogdanm 0:9b334a45a8ff 2059 #define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
bogdanm 0:9b334a45a8ff 2060 #define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
bogdanm 0:9b334a45a8ff 2061 #define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
bogdanm 0:9b334a45a8ff 2062 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
bogdanm 0:9b334a45a8ff 2063 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
bogdanm 0:9b334a45a8ff 2064 #define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
bogdanm 0:9b334a45a8ff 2065 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
bogdanm 0:9b334a45a8ff 2066 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
bogdanm 0:9b334a45a8ff 2067 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
bogdanm 0:9b334a45a8ff 2068 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
bogdanm 0:9b334a45a8ff 2069 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
bogdanm 0:9b334a45a8ff 2070 #define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
bogdanm 0:9b334a45a8ff 2071 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
bogdanm 0:9b334a45a8ff 2072 #define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
bogdanm 0:9b334a45a8ff 2073 #define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
bogdanm 0:9b334a45a8ff 2074 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
bogdanm 0:9b334a45a8ff 2075 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
bogdanm 0:9b334a45a8ff 2076 #define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
bogdanm 0:9b334a45a8ff 2077 #define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
bogdanm 0:9b334a45a8ff 2078 #define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
bogdanm 0:9b334a45a8ff 2079 #define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
bogdanm 0:9b334a45a8ff 2080 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
bogdanm 0:9b334a45a8ff 2081 #define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
bogdanm 0:9b334a45a8ff 2082 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
bogdanm 0:9b334a45a8ff 2083 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
bogdanm 0:9b334a45a8ff 2084 #define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
bogdanm 0:9b334a45a8ff 2085 #define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
bogdanm 0:9b334a45a8ff 2086 #define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
bogdanm 0:9b334a45a8ff 2087 #define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
bogdanm 0:9b334a45a8ff 2088 #define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
bogdanm 0:9b334a45a8ff 2089 #define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
bogdanm 0:9b334a45a8ff 2090 #define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
bogdanm 0:9b334a45a8ff 2091 #define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
bogdanm 0:9b334a45a8ff 2092 #define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
bogdanm 0:9b334a45a8ff 2093 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
bogdanm 0:9b334a45a8ff 2094 #define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
bogdanm 0:9b334a45a8ff 2095 #define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
bogdanm 0:9b334a45a8ff 2096 #define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
bogdanm 0:9b334a45a8ff 2097 #define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
bogdanm 0:9b334a45a8ff 2098 #define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
bogdanm 0:9b334a45a8ff 2099 #define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
bogdanm 0:9b334a45a8ff 2100 #define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
bogdanm 0:9b334a45a8ff 2101 #define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
bogdanm 0:9b334a45a8ff 2102 #define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
bogdanm 0:9b334a45a8ff 2103 #define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
bogdanm 0:9b334a45a8ff 2104 #define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
bogdanm 0:9b334a45a8ff 2105 #define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
bogdanm 0:9b334a45a8ff 2106 #define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
bogdanm 0:9b334a45a8ff 2107 #define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
bogdanm 0:9b334a45a8ff 2108
bogdanm 0:9b334a45a8ff 2109 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 2110 }
bogdanm 0:9b334a45a8ff 2111 #endif
bogdanm 0:9b334a45a8ff 2112
bogdanm 0:9b334a45a8ff 2113 #endif /* __LPC43XX_H */