Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

targets/TARGET_NXP/TARGET_LPC11U6X/device/LPC11U6x.h@165:2dd56e6daeec, 2017-05-23 (annotated)

Committer:
ranaumarnaeem
Date:
Tue May 23 12:54:50 2017 +0000
Revision:
165:2dd56e6daeec
Parent:
149:156823d33999 
jhjg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1
<> 144:ef7eb2e8f9f7 2 /****************************************************************************************************//**
<> 144:ef7eb2e8f9f7 3 * @file LPC11U6x.h
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 6 * LPC11U6x from .
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @version V0.4
<> 144:ef7eb2e8f9f7 9 * @date 22. October 2013
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @note Generated with SVDConv V2.81a
<> 144:ef7eb2e8f9f7 12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * modified by Keil
<> 144:ef7eb2e8f9f7 15 *******************************************************************************************************/
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 /** @addtogroup (null)
<> 144:ef7eb2e8f9f7 20 * @{
<> 144:ef7eb2e8f9f7 21 */
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /** @addtogroup LPC11U6x
<> 144:ef7eb2e8f9f7 24 * @{
<> 144:ef7eb2e8f9f7 25 */
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 #ifndef LPC11U6X_H
<> 144:ef7eb2e8f9f7 28 #define LPC11U6X_H
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 31 extern "C" {
<> 144:ef7eb2e8f9f7 32 #endif
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 typedef enum {
<> 144:ef7eb2e8f9f7 38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
<> 144:ef7eb2e8f9f7 39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
<> 144:ef7eb2e8f9f7 40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
<> 144:ef7eb2e8f9f7 41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
<> 144:ef7eb2e8f9f7 49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
<> 144:ef7eb2e8f9f7 50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
<> 144:ef7eb2e8f9f7 51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
<> 144:ef7eb2e8f9f7 52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
<> 144:ef7eb2e8f9f7 53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
<> 144:ef7eb2e8f9f7 54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
<> 144:ef7eb2e8f9f7 55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
<> 144:ef7eb2e8f9f7 56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
<> 144:ef7eb2e8f9f7 57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
<> 144:ef7eb2e8f9f7 58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
<> 144:ef7eb2e8f9f7 59 GINT0_IRQn = 8, /*!< 8 GINT0 */
<> 144:ef7eb2e8f9f7 60 GINT1_IRQn = 9, /*!< 9 GINT1 */
<> 144:ef7eb2e8f9f7 61 I2C1_IRQn = 10, /*!< 10 I2C1 */
<> 144:ef7eb2e8f9f7 62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
<> 144:ef7eb2e8f9f7 63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
<> 144:ef7eb2e8f9f7 64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
<> 144:ef7eb2e8f9f7 65 SSP1_IRQn = 14, /*!< 14 SSP1 */
<> 144:ef7eb2e8f9f7 66 I2C0_IRQn = 15, /*!< 15 I2C0 */
<> 144:ef7eb2e8f9f7 67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
<> 144:ef7eb2e8f9f7 68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
<> 144:ef7eb2e8f9f7 69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
<> 144:ef7eb2e8f9f7 70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
<> 144:ef7eb2e8f9f7 71 SSP0_IRQn = 20, /*!< 20 SSP0 */
<> 144:ef7eb2e8f9f7 72 USART0_IRQn = 21, /*!< 21 USART0 */
<> 144:ef7eb2e8f9f7 73 USB_IRQn = 22, /*!< 22 USB */
<> 144:ef7eb2e8f9f7 74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
<> 144:ef7eb2e8f9f7 75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
<> 144:ef7eb2e8f9f7 76 RTC_IRQn = 25, /*!< 25 RTC */
<> 144:ef7eb2e8f9f7 77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
<> 144:ef7eb2e8f9f7 78 FLASH_IRQn = 27, /*!< 27 FLASH */
<> 144:ef7eb2e8f9f7 79 DMA_IRQn = 28, /*!< 28 DMA */
<> 144:ef7eb2e8f9f7 80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
<> 144:ef7eb2e8f9f7 81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
<> 144:ef7eb2e8f9f7 82 } IRQn_Type;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /** @addtogroup Configuration_of_CMSIS
<> 144:ef7eb2e8f9f7 86 * @{
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 91 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 92 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
<> 144:ef7eb2e8f9f7 95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
<> 144:ef7eb2e8f9f7 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
<> 144:ef7eb2e8f9f7 100 /** @} */ /* End of group Configuration_of_CMSIS */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
<> 144:ef7eb2e8f9f7 103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 107 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 108 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** @addtogroup Device_Peripheral_Registers
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* ------------------- Start of section using anonymous unions ------------------ */
<> 144:ef7eb2e8f9f7 117 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 118 #pragma push
<> 144:ef7eb2e8f9f7 119 #pragma anon_unions
<> 144:ef7eb2e8f9f7 120 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 121 #pragma language=extended
<> 144:ef7eb2e8f9f7 122 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 123 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 124 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 125 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 126 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 127 #pragma warning 586
<> 144:ef7eb2e8f9f7 128 #else
<> 144:ef7eb2e8f9f7 129 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 130 #endif
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 135 /* ================ I2C0 ================ */
<> 144:ef7eb2e8f9f7 136 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief I2C-bus controller (I2C0)
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 typedef struct { /*!< I2C0 Structure */
<> 144:ef7eb2e8f9f7 144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
<> 144:ef7eb2e8f9f7 145 this register, the corresponding bit in the I2C control register
<> 144:ef7eb2e8f9f7 146 is set. Writing a zero has no effect on the corresponding bit
<> 144:ef7eb2e8f9f7 147 in the I2C control register. */
<> 144:ef7eb2e8f9f7 148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
<> 144:ef7eb2e8f9f7 149 detailed status codes that allow software to determine the next
<> 144:ef7eb2e8f9f7 150 action needed. */
<> 144:ef7eb2e8f9f7 151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
<> 144:ef7eb2e8f9f7 152 to be transmitted is written to this register. During master
<> 144:ef7eb2e8f9f7 153 or slave receive mode, data that has been received may be read
<> 144:ef7eb2e8f9f7 154 from this register. */
<> 144:ef7eb2e8f9f7 155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
<> 144:ef7eb2e8f9f7 156 for operation of the I2C interface in slave mode, and is not
<> 144:ef7eb2e8f9f7 157 used in master mode. The least significant bit determines whether
<> 144:ef7eb2e8f9f7 158 a slave responds to the General Call address. */
<> 144:ef7eb2e8f9f7 159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
<> 144:ef7eb2e8f9f7 160 time of the I2C clock. */
<> 144:ef7eb2e8f9f7 161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
<> 144:ef7eb2e8f9f7 162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
<> 144:ef7eb2e8f9f7 163 clock frequency generated by an I2C master and certain times
<> 144:ef7eb2e8f9f7 164 used in slave mode. */
<> 144:ef7eb2e8f9f7 165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
<> 144:ef7eb2e8f9f7 166 this register, the corresponding bit in the I2C control register
<> 144:ef7eb2e8f9f7 167 is cleared. Writing a zero has no effect on the corresponding
<> 144:ef7eb2e8f9f7 168 bit in the I2C control register. */
<> 144:ef7eb2e8f9f7 169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
<> 144:ef7eb2e8f9f7 170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
<> 144:ef7eb2e8f9f7 171 for operation of the I2C interface in slave mode, and is not
<> 144:ef7eb2e8f9f7 172 used in master mode. The least significant bit determines whether
<> 144:ef7eb2e8f9f7 173 a slave responds to the General Call address. */
<> 144:ef7eb2e8f9f7 174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
<> 144:ef7eb2e8f9f7 175 for operation of the I2C interface in slave mode, and is not
<> 144:ef7eb2e8f9f7 176 used in master mode. The least significant bit determines whether
<> 144:ef7eb2e8f9f7 177 a slave responds to the General Call address. */
<> 144:ef7eb2e8f9f7 178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
<> 144:ef7eb2e8f9f7 179 for operation of the I2C interface in slave mode, and is not
<> 144:ef7eb2e8f9f7 180 used in master mode. The least significant bit determines whether
<> 144:ef7eb2e8f9f7 181 a slave responds to the General Call address. */
<> 144:ef7eb2e8f9f7 182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
<> 144:ef7eb2e8f9f7 183 shift register will be transferred to the DATA_BUFFER automatically
<> 144:ef7eb2e8f9f7 184 after every nine bits (8 bits of data plus ACK or NACK) has
<> 144:ef7eb2e8f9f7 185 been received on the bus. */
<> 144:ef7eb2e8f9f7 186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
<> 144:ef7eb2e8f9f7 187 with I2ADR0 to determine an address match. The mask register
<> 144:ef7eb2e8f9f7 188 has no effect when comparing to the General Call address (0000000). */
<> 144:ef7eb2e8f9f7 189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
<> 144:ef7eb2e8f9f7 190 with I2ADR0 to determine an address match. The mask register
<> 144:ef7eb2e8f9f7 191 has no effect when comparing to the General Call address (0000000). */
<> 144:ef7eb2e8f9f7 192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
<> 144:ef7eb2e8f9f7 193 with I2ADR0 to determine an address match. The mask register
<> 144:ef7eb2e8f9f7 194 has no effect when comparing to the General Call address (0000000). */
<> 144:ef7eb2e8f9f7 195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
<> 144:ef7eb2e8f9f7 196 with I2ADR0 to determine an address match. The mask register
<> 144:ef7eb2e8f9f7 197 has no effect when comparing to the General Call address (0000000). */
<> 144:ef7eb2e8f9f7 198 } LPC_I2C0_Type;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 202 /* ================ WWDT ================ */
<> 144:ef7eb2e8f9f7 203 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 typedef struct { /*!< WWDT Structure */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
<> 144:ef7eb2e8f9f7 212 and status of the Watchdog Timer. */
<> 144:ef7eb2e8f9f7 213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
<> 144:ef7eb2e8f9f7 214 the time-out value. */
<> 144:ef7eb2e8f9f7 215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
<> 144:ef7eb2e8f9f7 216 to this register reloads the Watchdog timer with the value contained
<> 144:ef7eb2e8f9f7 217 in WDTC. */
<> 144:ef7eb2e8f9f7 218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
<> 144:ef7eb2e8f9f7 219 the current value of the Watchdog timer. */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
<> 144:ef7eb2e8f9f7 222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
<> 144:ef7eb2e8f9f7 223 } LPC_WWDT_Type;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 227 /* ================ USART0 ================ */
<> 144:ef7eb2e8f9f7 228 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @brief USART0 (USART0)
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 typedef struct { /*!< USART0 Structure */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 union {
<> 144:ef7eb2e8f9f7 238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
<> 144:ef7eb2e8f9f7 239 value. The full divisor is used to generate a baud rate from
<> 144:ef7eb2e8f9f7 240 the fractional rate divider. (DLAB=1) */
<> 144:ef7eb2e8f9f7 241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
<> 144:ef7eb2e8f9f7 242 is written here. (DLAB=0) */
<> 144:ef7eb2e8f9f7 243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
<> 144:ef7eb2e8f9f7 244 to be read. (DLAB=0) */
<> 144:ef7eb2e8f9f7 245 };
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 union {
<> 144:ef7eb2e8f9f7 248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
<> 144:ef7eb2e8f9f7 249 bits for the 7 potential USART interrupts. (DLAB=0) */
<> 144:ef7eb2e8f9f7 250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
<> 144:ef7eb2e8f9f7 251 value. The full divisor is used to generate a baud rate from
<> 144:ef7eb2e8f9f7 252 the fractional rate divider. (DLAB=1) */
<> 144:ef7eb2e8f9f7 253 };
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 union {
<> 144:ef7eb2e8f9f7 256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
<> 144:ef7eb2e8f9f7 257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
<> 144:ef7eb2e8f9f7 258 };
<> 144:ef7eb2e8f9f7 259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
<> 144:ef7eb2e8f9f7 260 and break generation. */
<> 144:ef7eb2e8f9f7 261 __IO uint32_t MCR; /*!< Modem Control Register. */
<> 144:ef7eb2e8f9f7 262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
<> 144:ef7eb2e8f9f7 263 status, including line errors. */
<> 144:ef7eb2e8f9f7 264 __I uint32_t MSR; /*!< Modem Status Register. */
<> 144:ef7eb2e8f9f7 265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
<> 144:ef7eb2e8f9f7 266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
<> 144:ef7eb2e8f9f7 267 feature. */
<> 144:ef7eb2e8f9f7 268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
<> 144:ef7eb2e8f9f7 269 control) mode. */
<> 144:ef7eb2e8f9f7 270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
<> 144:ef7eb2e8f9f7 271 baud rate divider. */
<> 144:ef7eb2e8f9f7 272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
<> 144:ef7eb2e8f9f7 273 each bit time. */
<> 144:ef7eb2e8f9f7 274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
<> 144:ef7eb2e8f9f7 275 with software flow control. */
<> 144:ef7eb2e8f9f7 276 __I uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
<> 144:ef7eb2e8f9f7 278 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
<> 144:ef7eb2e8f9f7 280 the Smart Card Interface feature. */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
<> 144:ef7eb2e8f9f7 282 aspects of RS-485/EIA-485 modes. */
<> 144:ef7eb2e8f9f7 283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
<> 144:ef7eb2e8f9f7 284 for RS-485/EIA-485 mode. */
<> 144:ef7eb2e8f9f7 285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
<> 144:ef7eb2e8f9f7 286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
<> 144:ef7eb2e8f9f7 287 } LPC_USART0_Type;
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 291 /* ================ CT16B0 ================ */
<> 144:ef7eb2e8f9f7 292 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 typedef struct { /*!< CT16B0 Structure */
<> 144:ef7eb2e8f9f7 300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
<> 144:ef7eb2e8f9f7 301 The IR can be read to identify which of eight possible interrupt
<> 144:ef7eb2e8f9f7 302 sources are pending. */
<> 144:ef7eb2e8f9f7 303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
<> 144:ef7eb2e8f9f7 304 Counter functions. The Timer Counter can be disabled or reset
<> 144:ef7eb2e8f9f7 305 through the TCR. */
<> 144:ef7eb2e8f9f7 306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
<> 144:ef7eb2e8f9f7 307 of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
<> 144:ef7eb2e8f9f7 309 to this value, the next clock increments the TC and clears the
<> 144:ef7eb2e8f9f7 310 PC. */
<> 144:ef7eb2e8f9f7 311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
<> 144:ef7eb2e8f9f7 312 to the value stored in PR. When the value in PR is reached,
<> 144:ef7eb2e8f9f7 313 the TC is incremented and the PC is cleared. The PC is observable
<> 144:ef7eb2e8f9f7 314 and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
<> 144:ef7eb2e8f9f7 316 is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 318 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 319 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 321 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 322 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 324 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 325 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 327 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 328 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
<> 144:ef7eb2e8f9f7 330 capture inputs are used to load the Capture Registers and whether
<> 144:ef7eb2e8f9f7 331 or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
<> 144:ef7eb2e8f9f7 333 is an event on the CAP input. */
<> 144:ef7eb2e8f9f7 334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
<> 144:ef7eb2e8f9f7 335 is an event on the CAP input. */
<> 144:ef7eb2e8f9f7 336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
<> 144:ef7eb2e8f9f7 337 is an event on the CAP input. */
<> 144:ef7eb2e8f9f7 338 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
<> 144:ef7eb2e8f9f7 340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
<> 144:ef7eb2e8f9f7 341 __I uint32_t RESERVED1[12];
<> 144:ef7eb2e8f9f7 342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
<> 144:ef7eb2e8f9f7 343 mode, and in Counter mode selects the signal and edge(s) for
<> 144:ef7eb2e8f9f7 344 counting. */
<> 144:ef7eb2e8f9f7 345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
<> 144:ef7eb2e8f9f7 346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
<> 144:ef7eb2e8f9f7 347 } LPC_CT16B0_Type;
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 351 /* ================ CT32B0 ================ */
<> 144:ef7eb2e8f9f7 352 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 typedef struct { /*!< CT32B0 Structure */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
<> 144:ef7eb2e8f9f7 361 The IR can be read to identify which of eight possible interrupt
<> 144:ef7eb2e8f9f7 362 sources are pending. */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
<> 144:ef7eb2e8f9f7 364 Counter functions. The Timer Counter can be disabled or reset
<> 144:ef7eb2e8f9f7 365 through the TCR. */
<> 144:ef7eb2e8f9f7 366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
<> 144:ef7eb2e8f9f7 367 of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
<> 144:ef7eb2e8f9f7 369 to this value, the next clock increments the TC and clears the
<> 144:ef7eb2e8f9f7 370 PC. */
<> 144:ef7eb2e8f9f7 371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
<> 144:ef7eb2e8f9f7 372 to the value stored in PR. When the value in PR is reached,
<> 144:ef7eb2e8f9f7 373 the TC is incremented and the PC is cleared. The PC is observable
<> 144:ef7eb2e8f9f7 374 and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
<> 144:ef7eb2e8f9f7 376 is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 378 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 379 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 381 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 382 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 384 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 385 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
<> 144:ef7eb2e8f9f7 387 TC, stop both the TC and PC, and/or generate an interrupt every
<> 144:ef7eb2e8f9f7 388 time MR0 matches the TC. */
<> 144:ef7eb2e8f9f7 389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
<> 144:ef7eb2e8f9f7 390 capture inputs are used to load the Capture Registers and whether
<> 144:ef7eb2e8f9f7 391 or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
<> 144:ef7eb2e8f9f7 393 is an event on the CAP input. */
<> 144:ef7eb2e8f9f7 394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
<> 144:ef7eb2e8f9f7 395 is an event on the CAP input. */
<> 144:ef7eb2e8f9f7 396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
<> 144:ef7eb2e8f9f7 397 is an event on the CAP input. */
<> 144:ef7eb2e8f9f7 398 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
<> 144:ef7eb2e8f9f7 400 and the external match pins CT32Bn_MAT[3:0]. */
<> 144:ef7eb2e8f9f7 401 __I uint32_t RESERVED1[12];
<> 144:ef7eb2e8f9f7 402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
<> 144:ef7eb2e8f9f7 403 mode, and in Counter mode selects the signal and edge(s) for
<> 144:ef7eb2e8f9f7 404 counting. */
<> 144:ef7eb2e8f9f7 405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
<> 144:ef7eb2e8f9f7 406 match pins CT32Bn_MAT[3:0]. */
<> 144:ef7eb2e8f9f7 407 } LPC_CT32B0_Type;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 411 /* ================ ADC ================ */
<> 144:ef7eb2e8f9f7 412 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 typedef struct { /*!< ADC Structure */
<> 144:ef7eb2e8f9f7 420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
<> 144:ef7eb2e8f9f7 421 bits for each sequence and the A/D power-down bit. */
<> 144:ef7eb2e8f9f7 422 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
<> 144:ef7eb2e8f9f7 424 and channel selection for conversion sequence-A. Also specifies
<> 144:ef7eb2e8f9f7 425 interrupt mode for sequence-A. */
<> 144:ef7eb2e8f9f7 426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
<> 144:ef7eb2e8f9f7 427 and channel selection for conversion sequence-B. Also specifies
<> 144:ef7eb2e8f9f7 428 interrupt mode for sequence-B. */
<> 144:ef7eb2e8f9f7 429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
<> 144:ef7eb2e8f9f7 430 the result of the most recent A/D conversion performed under
<> 144:ef7eb2e8f9f7 431 sequence-A */
<> 144:ef7eb2e8f9f7 432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
<> 144:ef7eb2e8f9f7 433 the result of the most recent A/D conversion performed under
<> 144:ef7eb2e8f9f7 434 sequence-B */
<> 144:ef7eb2e8f9f7 435 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
<> 144:ef7eb2e8f9f7 437 of the most recent conversion completed on channel 0. */
<> 144:ef7eb2e8f9f7 438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
<> 144:ef7eb2e8f9f7 439 level for automatic threshold comparison for any channels linked
<> 144:ef7eb2e8f9f7 440 to threshold pair 0. */
<> 144:ef7eb2e8f9f7 441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
<> 144:ef7eb2e8f9f7 442 level for automatic threshold comparison for any channels linked
<> 144:ef7eb2e8f9f7 443 to threshold pair 1. */
<> 144:ef7eb2e8f9f7 444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
<> 144:ef7eb2e8f9f7 445 level for automatic threshold comparison for any channels linked
<> 144:ef7eb2e8f9f7 446 to threshold pair 0. */
<> 144:ef7eb2e8f9f7 447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
<> 144:ef7eb2e8f9f7 448 level for automatic threshold comparison for any channels linked
<> 144:ef7eb2e8f9f7 449 to threshold pair 1. */
<> 144:ef7eb2e8f9f7 450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
<> 144:ef7eb2e8f9f7 451 threshold compare registers are to be used for each channel */
<> 144:ef7eb2e8f9f7 452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
<> 144:ef7eb2e8f9f7 453 bits that enable the sequence-A, sequence-B, threshold compare
<> 144:ef7eb2e8f9f7 454 and data overrun interrupts to be generated. */
<> 144:ef7eb2e8f9f7 455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
<> 144:ef7eb2e8f9f7 456 and the individual component overrun and threshold-compare flags.
<> 144:ef7eb2e8f9f7 457 (The overrun bits replicate information stored in the result
<> 144:ef7eb2e8f9f7 458 registers). */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t TRM; /*!< ADC trim register. */
<> 144:ef7eb2e8f9f7 460 } LPC_ADC_Type;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 464 /* ================ RTC ================ */
<> 144:ef7eb2e8f9f7 465 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /**
<> 144:ef7eb2e8f9f7 469 * @brief Real-Time Clock (RTC) (RTC)
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 typedef struct { /*!< RTC Structure */
<> 144:ef7eb2e8f9f7 473 __IO uint32_t CTRL; /*!< RTC control register */
<> 144:ef7eb2e8f9f7 474 __IO uint32_t MATCH; /*!< RTC match register */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t COUNT; /*!< RTC counter register */
<> 144:ef7eb2e8f9f7 476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
<> 144:ef7eb2e8f9f7 477 } LPC_RTC_Type;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 481 /* ================ DMATRIGMUX ================ */
<> 144:ef7eb2e8f9f7 482 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /**
<> 144:ef7eb2e8f9f7 486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 typedef struct { /*!< DMATRIGMUX Structure */
<> 144:ef7eb2e8f9f7 490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 491 } LPC_DMATRIGMUX_Type;
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 495 /* ================ PMU ================ */
<> 144:ef7eb2e8f9f7 496 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 typedef struct { /*!< PMU Structure */
<> 144:ef7eb2e8f9f7 504 __IO uint32_t PCON; /*!< Power control register */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
<> 144:ef7eb2e8f9f7 510 } LPC_PMU_Type;
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 514 /* ================ FLASHCTRL ================ */
<> 144:ef7eb2e8f9f7 515 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @brief Flash controller (FLASHCTRL)
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 typedef struct { /*!< FLASHCTRL Structure */
<> 144:ef7eb2e8f9f7 523 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
<> 144:ef7eb2e8f9f7 525 __I uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 526 __IO uint32_t FMSSTART; /*!< Signature start address register */
<> 144:ef7eb2e8f9f7 527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
<> 144:ef7eb2e8f9f7 528 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 529 __I uint32_t FMSW0; /*!< Signature Word */
<> 144:ef7eb2e8f9f7 530 } LPC_FLASHCTRL_Type;
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 534 /* ================ SSP0 ================ */
<> 144:ef7eb2e8f9f7 535 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /**
<> 144:ef7eb2e8f9f7 539 * @brief SSP/SPI (SSP0)
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 typedef struct { /*!< SSP0 Structure */
<> 144:ef7eb2e8f9f7 543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
<> 144:ef7eb2e8f9f7 544 and data size. */
<> 144:ef7eb2e8f9f7 545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
<> 144:ef7eb2e8f9f7 546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
<> 144:ef7eb2e8f9f7 547 the receive FIFO. */
<> 144:ef7eb2e8f9f7 548 __I uint32_t SR; /*!< Status Register */
<> 144:ef7eb2e8f9f7 549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
<> 144:ef7eb2e8f9f7 550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
<> 144:ef7eb2e8f9f7 551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
<> 144:ef7eb2e8f9f7 552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
<> 144:ef7eb2e8f9f7 553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 554 } LPC_SSP0_Type;
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 558 /* ================ IOCON ================ */
<> 144:ef7eb2e8f9f7 559 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 typedef struct { /*!< IOCON Structure */
<> 144:ef7eb2e8f9f7 567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
<> 144:ef7eb2e8f9f7 591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
<> 144:ef7eb2e8f9f7 623 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 626 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
<> 144:ef7eb2e8f9f7 649 } LPC_IOCON_Type;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 653 /* ================ SYSCON ================ */
<> 144:ef7eb2e8f9f7 654 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 typedef struct { /*!< SYSCON Structure */
<> 144:ef7eb2e8f9f7 662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
<> 144:ef7eb2e8f9f7 663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
<> 144:ef7eb2e8f9f7 664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
<> 144:ef7eb2e8f9f7 665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
<> 144:ef7eb2e8f9f7 666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
<> 144:ef7eb2e8f9f7 667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
<> 144:ef7eb2e8f9f7 668 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
<> 144:ef7eb2e8f9f7 670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
<> 144:ef7eb2e8f9f7 671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
<> 144:ef7eb2e8f9f7 672 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
<> 144:ef7eb2e8f9f7 674 __I uint32_t RESERVED2[3];
<> 144:ef7eb2e8f9f7 675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
<> 144:ef7eb2e8f9f7 676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
<> 144:ef7eb2e8f9f7 677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
<> 144:ef7eb2e8f9f7 678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
<> 144:ef7eb2e8f9f7 679 __I uint32_t RESERVED3[8];
<> 144:ef7eb2e8f9f7 680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
<> 144:ef7eb2e8f9f7 681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
<> 144:ef7eb2e8f9f7 682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
<> 144:ef7eb2e8f9f7 683 __I uint32_t RESERVED4;
<> 144:ef7eb2e8f9f7 684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
<> 144:ef7eb2e8f9f7 685 __I uint32_t RESERVED5[4];
<> 144:ef7eb2e8f9f7 686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
<> 144:ef7eb2e8f9f7 687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
<> 144:ef7eb2e8f9f7 688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
<> 144:ef7eb2e8f9f7 689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
<> 144:ef7eb2e8f9f7 690 of USART1 to USART4 */
<> 144:ef7eb2e8f9f7 691 __I uint32_t RESERVED6[7];
<> 144:ef7eb2e8f9f7 692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
<> 144:ef7eb2e8f9f7 693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
<> 144:ef7eb2e8f9f7 694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
<> 144:ef7eb2e8f9f7 695 __I uint32_t RESERVED7[5];
<> 144:ef7eb2e8f9f7 696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
<> 144:ef7eb2e8f9f7 697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
<> 144:ef7eb2e8f9f7 698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
<> 144:ef7eb2e8f9f7 699 __I uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
<> 144:ef7eb2e8f9f7 701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
<> 144:ef7eb2e8f9f7 702 __I uint32_t RESERVED9;
<> 144:ef7eb2e8f9f7 703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
<> 144:ef7eb2e8f9f7 704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
<> 144:ef7eb2e8f9f7 705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
<> 144:ef7eb2e8f9f7 706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
<> 144:ef7eb2e8f9f7 707 __I uint32_t RESERVED10[10];
<> 144:ef7eb2e8f9f7 708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 709 filter */
<> 144:ef7eb2e8f9f7 710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 711 filter */
<> 144:ef7eb2e8f9f7 712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 713 filter */
<> 144:ef7eb2e8f9f7 714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 715 filter */
<> 144:ef7eb2e8f9f7 716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 717 filter */
<> 144:ef7eb2e8f9f7 718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 719 filter */
<> 144:ef7eb2e8f9f7 720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
<> 144:ef7eb2e8f9f7 721 filter */
<> 144:ef7eb2e8f9f7 722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
<> 144:ef7eb2e8f9f7 723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
<> 144:ef7eb2e8f9f7 724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
<> 144:ef7eb2e8f9f7 725 __I uint32_t RESERVED11[5];
<> 144:ef7eb2e8f9f7 726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
<> 144:ef7eb2e8f9f7 727 __IO uint32_t NMISRC; /*!< NMI Source Control */
<> 144:ef7eb2e8f9f7 728 union {
<> 144:ef7eb2e8f9f7 729 __IO uint32_t PINTSEL[8];
<> 144:ef7eb2e8f9f7 730 struct {
<> 144:ef7eb2e8f9f7 731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 739 };
<> 144:ef7eb2e8f9f7 740 };
<> 144:ef7eb2e8f9f7 741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
<> 144:ef7eb2e8f9f7 742 __I uint32_t USBCLKST; /*!< USB clock status */
<> 144:ef7eb2e8f9f7 743 __I uint32_t RESERVED12[25];
<> 144:ef7eb2e8f9f7 744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
<> 144:ef7eb2e8f9f7 745 __I uint32_t RESERVED13[3];
<> 144:ef7eb2e8f9f7 746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
<> 144:ef7eb2e8f9f7 747 __I uint32_t RESERVED14[6];
<> 144:ef7eb2e8f9f7 748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
<> 144:ef7eb2e8f9f7 749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
<> 144:ef7eb2e8f9f7 750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
<> 144:ef7eb2e8f9f7 751 __I uint32_t RESERVED15[110];
<> 144:ef7eb2e8f9f7 752 __I uint32_t DEVICE_ID; /*!< Device ID */
<> 144:ef7eb2e8f9f7 753 } LPC_SYSCON_Type;
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 757 /* ================ USART4 ================ */
<> 144:ef7eb2e8f9f7 758 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /**
<> 144:ef7eb2e8f9f7 762 * @brief USART4 (USART4)
<> 144:ef7eb2e8f9f7 763 */
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 typedef struct { /*!< USART4 Structure */
<> 144:ef7eb2e8f9f7 766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
<> 144:ef7eb2e8f9f7 767 that typically are not changed during operation. */
<> 144:ef7eb2e8f9f7 768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
<> 144:ef7eb2e8f9f7 769 likely to change during operation. */
<> 144:ef7eb2e8f9f7 770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
<> 144:ef7eb2e8f9f7 771 here. Writing ones clears some bits in the register. Some bits
<> 144:ef7eb2e8f9f7 772 can be cleared by writing a 1 to them. */
<> 144:ef7eb2e8f9f7 773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
<> 144:ef7eb2e8f9f7 774 interrupt enable bit for each potential USART interrupt. A complete
<> 144:ef7eb2e8f9f7 775 value may be read from this register. Writing a 1 to any implemented
<> 144:ef7eb2e8f9f7 776 bit position causes that bit to be set. */
<> 144:ef7eb2e8f9f7 777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
<> 144:ef7eb2e8f9f7 778 of bits in the INTENSET register. Writing a 1 to any implemented
<> 144:ef7eb2e8f9f7 779 bit position causes the corresponding bit to be cleared. */
<> 144:ef7eb2e8f9f7 780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
<> 144:ef7eb2e8f9f7 781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
<> 144:ef7eb2e8f9f7 782 received with the current USART receive status. Allows DMA or
<> 144:ef7eb2e8f9f7 783 software to recover incoming data and status together. */
<> 144:ef7eb2e8f9f7 784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
<> 144:ef7eb2e8f9f7 785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
<> 144:ef7eb2e8f9f7 786 value. */
<> 144:ef7eb2e8f9f7 787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
<> 144:ef7eb2e8f9f7 788 enabled. */
<> 144:ef7eb2e8f9f7 789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
<> 144:ef7eb2e8f9f7 790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
<> 144:ef7eb2e8f9f7 791 } LPC_USART4_Type;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 795 /* ================ GINT0 ================ */
<> 144:ef7eb2e8f9f7 796 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @brief GPIO group interrupt 0 (GINT0)
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 typedef struct { /*!< GINT0 Structure */
<> 144:ef7eb2e8f9f7 804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
<> 144:ef7eb2e8f9f7 805 __I uint32_t RESERVED0[7];
<> 144:ef7eb2e8f9f7 806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
<> 144:ef7eb2e8f9f7 807 __I uint32_t RESERVED1[5];
<> 144:ef7eb2e8f9f7 808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
<> 144:ef7eb2e8f9f7 809 } LPC_GINT0_Type;
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 813 /* ================ USB ================ */
<> 144:ef7eb2e8f9f7 814 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /**
<> 144:ef7eb2e8f9f7 818 * @brief USB device controller (USB)
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 typedef struct { /*!< USB Structure */
<> 144:ef7eb2e8f9f7 822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
<> 144:ef7eb2e8f9f7 823 __IO uint32_t INFO; /*!< USB Info register */
<> 144:ef7eb2e8f9f7 824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
<> 144:ef7eb2e8f9f7 825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
<> 144:ef7eb2e8f9f7 826 __IO uint32_t LPM; /*!< Link Power Management register */
<> 144:ef7eb2e8f9f7 827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
<> 144:ef7eb2e8f9f7 828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
<> 144:ef7eb2e8f9f7 829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
<> 144:ef7eb2e8f9f7 830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
<> 144:ef7eb2e8f9f7 831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
<> 144:ef7eb2e8f9f7 832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
<> 144:ef7eb2e8f9f7 833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
<> 144:ef7eb2e8f9f7 834 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
<> 144:ef7eb2e8f9f7 836 } LPC_USB_Type;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 840 /* ================ CRC ================ */
<> 144:ef7eb2e8f9f7 841 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /**
<> 144:ef7eb2e8f9f7 845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
<> 144:ef7eb2e8f9f7 846 */
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 typedef struct { /*!< CRC Structure */
<> 144:ef7eb2e8f9f7 849 __IO uint32_t MODE; /*!< CRC mode register */
<> 144:ef7eb2e8f9f7 850 __IO uint32_t SEED; /*!< CRC seed register */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 union {
<> 144:ef7eb2e8f9f7 853 __O uint32_t WR_DATA; /*!< CRC data register */
<> 144:ef7eb2e8f9f7 854 __I uint32_t SUM; /*!< CRC checksum register */
<> 144:ef7eb2e8f9f7 855 };
<> 144:ef7eb2e8f9f7 856 } LPC_CRC_Type;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 860 /* ================ DMA ================ */
<> 144:ef7eb2e8f9f7 861 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /**
<> 144:ef7eb2e8f9f7 865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 typedef struct { /*!< DMA Structure */
<> 144:ef7eb2e8f9f7 869 __IO uint32_t CTRL; /*!< DMA control. */
<> 144:ef7eb2e8f9f7 870 __I uint32_t INTSTAT; /*!< Interrupt status. */
<> 144:ef7eb2e8f9f7 871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
<> 144:ef7eb2e8f9f7 872 __I uint32_t RESERVED0[5];
<> 144:ef7eb2e8f9f7 873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
<> 144:ef7eb2e8f9f7 874 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
<> 144:ef7eb2e8f9f7 876 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
<> 144:ef7eb2e8f9f7 878 __I uint32_t RESERVED3;
<> 144:ef7eb2e8f9f7 879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
<> 144:ef7eb2e8f9f7 880 __I uint32_t RESERVED4;
<> 144:ef7eb2e8f9f7 881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
<> 144:ef7eb2e8f9f7 882 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
<> 144:ef7eb2e8f9f7 884 __I uint32_t RESERVED6;
<> 144:ef7eb2e8f9f7 885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
<> 144:ef7eb2e8f9f7 886 __I uint32_t RESERVED7;
<> 144:ef7eb2e8f9f7 887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
<> 144:ef7eb2e8f9f7 888 __I uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
<> 144:ef7eb2e8f9f7 890 __I uint32_t RESERVED9;
<> 144:ef7eb2e8f9f7 891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
<> 144:ef7eb2e8f9f7 892 __I uint32_t RESERVED10;
<> 144:ef7eb2e8f9f7 893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
<> 144:ef7eb2e8f9f7 894 __I uint32_t RESERVED11;
<> 144:ef7eb2e8f9f7 895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
<> 144:ef7eb2e8f9f7 896 __I uint32_t RESERVED12[225];
<> 144:ef7eb2e8f9f7 897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 900 __I uint32_t RESERVED13;
<> 144:ef7eb2e8f9f7 901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 904 __I uint32_t RESERVED14;
<> 144:ef7eb2e8f9f7 905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 908 __I uint32_t RESERVED15;
<> 144:ef7eb2e8f9f7 909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 912 __I uint32_t RESERVED16;
<> 144:ef7eb2e8f9f7 913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 916 __I uint32_t RESERVED17;
<> 144:ef7eb2e8f9f7 917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 920 __I uint32_t RESERVED18;
<> 144:ef7eb2e8f9f7 921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 924 __I uint32_t RESERVED19;
<> 144:ef7eb2e8f9f7 925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 928 __I uint32_t RESERVED20;
<> 144:ef7eb2e8f9f7 929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 932 __I uint32_t RESERVED21;
<> 144:ef7eb2e8f9f7 933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 936 __I uint32_t RESERVED22;
<> 144:ef7eb2e8f9f7 937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 940 __I uint32_t RESERVED23;
<> 144:ef7eb2e8f9f7 941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 944 __I uint32_t RESERVED24;
<> 144:ef7eb2e8f9f7 945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 948 __I uint32_t RESERVED25;
<> 144:ef7eb2e8f9f7 949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 952 __I uint32_t RESERVED26;
<> 144:ef7eb2e8f9f7 953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 956 __I uint32_t RESERVED27;
<> 144:ef7eb2e8f9f7 957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 960 } LPC_DMA_Type;
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 964 /* ================ SCT0 ================ */
<> 144:ef7eb2e8f9f7 965 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /**
<> 144:ef7eb2e8f9f7 969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
<> 144:ef7eb2e8f9f7 970 */
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 typedef struct { /*!< SCT0 Structure */
<> 144:ef7eb2e8f9f7 973 __IO uint32_t CONFIG; /*!< SCT configuration register */
<> 144:ef7eb2e8f9f7 974 __IO uint32_t CTRL; /*!< SCT control register */
<> 144:ef7eb2e8f9f7 975 __IO uint32_t LIMIT; /*!< SCT limit register */
<> 144:ef7eb2e8f9f7 976 __IO uint32_t HALT; /*!< SCT halt condition register */
<> 144:ef7eb2e8f9f7 977 __IO uint32_t STOP; /*!< SCT stop condition register */
<> 144:ef7eb2e8f9f7 978 __IO uint32_t START; /*!< SCT start condition register */
<> 144:ef7eb2e8f9f7 979 __I uint32_t RESERVED0[10];
<> 144:ef7eb2e8f9f7 980 __IO uint32_t COUNT; /*!< SCT counter register */
<> 144:ef7eb2e8f9f7 981 __IO uint32_t STATE; /*!< SCT state register */
<> 144:ef7eb2e8f9f7 982 __I uint32_t INPUT; /*!< SCT input register */
<> 144:ef7eb2e8f9f7 983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
<> 144:ef7eb2e8f9f7 984 __IO uint32_t OUTPUT; /*!< SCT output register */
<> 144:ef7eb2e8f9f7 985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
<> 144:ef7eb2e8f9f7 986 __IO uint32_t RES; /*!< SCT conflict resolution register */
<> 144:ef7eb2e8f9f7 987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
<> 144:ef7eb2e8f9f7 988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
<> 144:ef7eb2e8f9f7 989 __I uint32_t RESERVED1[35];
<> 144:ef7eb2e8f9f7 990 __IO uint32_t EVEN; /*!< SCT event enable register */
<> 144:ef7eb2e8f9f7 991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
<> 144:ef7eb2e8f9f7 992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
<> 144:ef7eb2e8f9f7 993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 union {
<> 144:ef7eb2e8f9f7 996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
<> 144:ef7eb2e8f9f7 997 = 1 */
<> 144:ef7eb2e8f9f7 998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
<> 144:ef7eb2e8f9f7 999 REGMODE4 = 0 */
<> 144:ef7eb2e8f9f7 1000 };
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 union {
<> 144:ef7eb2e8f9f7 1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
<> 144:ef7eb2e8f9f7 1004 = 1 */
<> 144:ef7eb2e8f9f7 1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
<> 144:ef7eb2e8f9f7 1006 REGMODE4 = 0 */
<> 144:ef7eb2e8f9f7 1007 };
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 union {
<> 144:ef7eb2e8f9f7 1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
<> 144:ef7eb2e8f9f7 1011 REGMODE4 = 0 */
<> 144:ef7eb2e8f9f7 1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
<> 144:ef7eb2e8f9f7 1013 = 1 */
<> 144:ef7eb2e8f9f7 1014 };
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 union {
<> 144:ef7eb2e8f9f7 1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
<> 144:ef7eb2e8f9f7 1018 = 1 */
<> 144:ef7eb2e8f9f7 1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
<> 144:ef7eb2e8f9f7 1020 REGMODE4 = 0 */
<> 144:ef7eb2e8f9f7 1021 };
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 union {
<> 144:ef7eb2e8f9f7 1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
<> 144:ef7eb2e8f9f7 1025 = 1 */
<> 144:ef7eb2e8f9f7 1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
<> 144:ef7eb2e8f9f7 1027 REGMODE4 = 0 */
<> 144:ef7eb2e8f9f7 1028 };
<> 144:ef7eb2e8f9f7 1029 __I uint32_t RESERVED2[59];
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 union {
<> 144:ef7eb2e8f9f7 1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
<> 144:ef7eb2e8f9f7 1033 = 1 */
<> 144:ef7eb2e8f9f7 1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
<> 144:ef7eb2e8f9f7 1035 = 0 */
<> 144:ef7eb2e8f9f7 1036 };
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 union {
<> 144:ef7eb2e8f9f7 1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
<> 144:ef7eb2e8f9f7 1040 = 0 */
<> 144:ef7eb2e8f9f7 1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
<> 144:ef7eb2e8f9f7 1042 = 1 */
<> 144:ef7eb2e8f9f7 1043 };
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 union {
<> 144:ef7eb2e8f9f7 1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
<> 144:ef7eb2e8f9f7 1047 = 0 */
<> 144:ef7eb2e8f9f7 1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
<> 144:ef7eb2e8f9f7 1049 = 1 */
<> 144:ef7eb2e8f9f7 1050 };
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 union {
<> 144:ef7eb2e8f9f7 1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
<> 144:ef7eb2e8f9f7 1054 = 1 */
<> 144:ef7eb2e8f9f7 1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
<> 144:ef7eb2e8f9f7 1056 = 0 */
<> 144:ef7eb2e8f9f7 1057 };
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 union {
<> 144:ef7eb2e8f9f7 1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
<> 144:ef7eb2e8f9f7 1061 = 1 */
<> 144:ef7eb2e8f9f7 1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
<> 144:ef7eb2e8f9f7 1063 = 0 */
<> 144:ef7eb2e8f9f7 1064 };
<> 144:ef7eb2e8f9f7 1065 __I uint32_t RESERVED3[59];
<> 144:ef7eb2e8f9f7 1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
<> 144:ef7eb2e8f9f7 1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
<> 144:ef7eb2e8f9f7 1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
<> 144:ef7eb2e8f9f7 1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
<> 144:ef7eb2e8f9f7 1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
<> 144:ef7eb2e8f9f7 1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
<> 144:ef7eb2e8f9f7 1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
<> 144:ef7eb2e8f9f7 1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
<> 144:ef7eb2e8f9f7 1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
<> 144:ef7eb2e8f9f7 1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
<> 144:ef7eb2e8f9f7 1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
<> 144:ef7eb2e8f9f7 1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
<> 144:ef7eb2e8f9f7 1078 __I uint32_t RESERVED4[116];
<> 144:ef7eb2e8f9f7 1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
<> 144:ef7eb2e8f9f7 1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
<> 144:ef7eb2e8f9f7 1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
<> 144:ef7eb2e8f9f7 1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
<> 144:ef7eb2e8f9f7 1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 1087 } LPC_SCT0_Type;
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1091 /* ================ GPIO_PORT ================ */
<> 144:ef7eb2e8f9f7 1092 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /**
<> 144:ef7eb2e8f9f7 1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 typedef struct { /*!< GPIO_PORT Structure */
<> 144:ef7eb2e8f9f7 1100 __IO uint8_t B[88]; /*!< Byte pin registers */
<> 144:ef7eb2e8f9f7 1101 __I uint32_t RESERVED0[42];
<> 144:ef7eb2e8f9f7 1102 __IO uint32_t W[88]; /*!< Word pin registers */
<> 144:ef7eb2e8f9f7 1103 __I uint32_t RESERVED1[1896];
<> 144:ef7eb2e8f9f7 1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
<> 144:ef7eb2e8f9f7 1105 __I uint32_t RESERVED2[29];
<> 144:ef7eb2e8f9f7 1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
<> 144:ef7eb2e8f9f7 1107 __I uint32_t RESERVED3[29];
<> 144:ef7eb2e8f9f7 1108 __IO uint32_t PIN[3]; /*!< Port pin register */
<> 144:ef7eb2e8f9f7 1109 __I uint32_t RESERVED4[29];
<> 144:ef7eb2e8f9f7 1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
<> 144:ef7eb2e8f9f7 1111 __I uint32_t RESERVED5[29];
<> 144:ef7eb2e8f9f7 1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
<> 144:ef7eb2e8f9f7 1113 __I uint32_t RESERVED6[29];
<> 144:ef7eb2e8f9f7 1114 __O uint32_t CLR[3]; /*!< Clear port */
<> 144:ef7eb2e8f9f7 1115 __I uint32_t RESERVED7[29];
<> 144:ef7eb2e8f9f7 1116 __O uint32_t NOT[3]; /*!< Toggle port */
<> 144:ef7eb2e8f9f7 1117 } LPC_GPIO_PORT_Type;
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1121 /* ================ PINT ================ */
<> 144:ef7eb2e8f9f7 1122 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /**
<> 144:ef7eb2e8f9f7 1126 * @brief Pin interruptand pattern match (PINT) (PINT)
<> 144:ef7eb2e8f9f7 1127 */
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 typedef struct { /*!< PINT Structure */
<> 144:ef7eb2e8f9f7 1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
<> 144:ef7eb2e8f9f7 1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
<> 144:ef7eb2e8f9f7 1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
<> 144:ef7eb2e8f9f7 1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
<> 144:ef7eb2e8f9f7 1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
<> 144:ef7eb2e8f9f7 1135 register */
<> 144:ef7eb2e8f9f7 1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
<> 144:ef7eb2e8f9f7 1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
<> 144:ef7eb2e8f9f7 1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
<> 144:ef7eb2e8f9f7 1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
<> 144:ef7eb2e8f9f7 1140 __IO uint32_t IST; /*!< Pin interrupt status register */
<> 144:ef7eb2e8f9f7 1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
<> 144:ef7eb2e8f9f7 1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
<> 144:ef7eb2e8f9f7 1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
<> 144:ef7eb2e8f9f7 1144 } LPC_PINT_Type;
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* -------------------- End of section using anonymous unions ------------------- */
<> 144:ef7eb2e8f9f7 1148 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 1149 #pragma pop
<> 144:ef7eb2e8f9f7 1150 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 1151 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 1152 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 1153 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 1154 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 1155 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 1156 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 1157 #pragma warning restore
<> 144:ef7eb2e8f9f7 1158 #else
<> 144:ef7eb2e8f9f7 1159 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 1160 #endif
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1166 /* ================ Peripheral memory map ================ */
<> 144:ef7eb2e8f9f7 1167 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 #define LPC_I2C0_BASE 0x40000000UL
<> 144:ef7eb2e8f9f7 1170 #define LPC_WWDT_BASE 0x40004000UL
<> 144:ef7eb2e8f9f7 1171 #define LPC_USART0_BASE 0x40008000UL
<> 144:ef7eb2e8f9f7 1172 #define LPC_CT16B0_BASE 0x4000C000UL
<> 144:ef7eb2e8f9f7 1173 #define LPC_CT16B1_BASE 0x40010000UL
<> 144:ef7eb2e8f9f7 1174 #define LPC_CT32B0_BASE 0x40014000UL
<> 144:ef7eb2e8f9f7 1175 #define LPC_CT32B1_BASE 0x40018000UL
<> 144:ef7eb2e8f9f7 1176 #define LPC_ADC_BASE 0x4001C000UL
<> 144:ef7eb2e8f9f7 1177 #define LPC_I2C1_BASE 0x40020000UL
<> 144:ef7eb2e8f9f7 1178 #define LPC_RTC_BASE 0x40024000UL
<> 144:ef7eb2e8f9f7 1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
<> 144:ef7eb2e8f9f7 1180 #define LPC_PMU_BASE 0x40038000UL
<> 144:ef7eb2e8f9f7 1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
<> 144:ef7eb2e8f9f7 1182 #define LPC_SSP0_BASE 0x40040000UL
<> 144:ef7eb2e8f9f7 1183 #define LPC_IOCON_BASE 0x40044000UL
<> 144:ef7eb2e8f9f7 1184 #define LPC_SYSCON_BASE 0x40048000UL
<> 144:ef7eb2e8f9f7 1185 #define LPC_USART4_BASE 0x4004C000UL
<> 144:ef7eb2e8f9f7 1186 #define LPC_SSP1_BASE 0x40058000UL
<> 144:ef7eb2e8f9f7 1187 #define LPC_GINT0_BASE 0x4005C000UL
<> 144:ef7eb2e8f9f7 1188 #define LPC_GINT1_BASE 0x40060000UL
<> 144:ef7eb2e8f9f7 1189 #define LPC_USART1_BASE 0x4006C000UL
<> 144:ef7eb2e8f9f7 1190 #define LPC_USART2_BASE 0x40070000UL
<> 144:ef7eb2e8f9f7 1191 #define LPC_USART3_BASE 0x40074000UL
<> 144:ef7eb2e8f9f7 1192 #define LPC_USB_BASE 0x40080000UL
<> 144:ef7eb2e8f9f7 1193 #define LPC_CRC_BASE 0x50000000UL
<> 144:ef7eb2e8f9f7 1194 #define LPC_DMA_BASE 0x50004000UL
<> 144:ef7eb2e8f9f7 1195 #define LPC_SCT0_BASE 0x5000C000UL
<> 144:ef7eb2e8f9f7 1196 #define LPC_SCT1_BASE 0x5000E000UL
<> 144:ef7eb2e8f9f7 1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
<> 144:ef7eb2e8f9f7 1198 #define LPC_PINT_BASE 0xA0004000UL
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1202 /* ================ Peripheral declaration ================ */
<> 144:ef7eb2e8f9f7 1203 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
<> 144:ef7eb2e8f9f7 1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
<> 144:ef7eb2e8f9f7 1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
<> 144:ef7eb2e8f9f7 1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
<> 144:ef7eb2e8f9f7 1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
<> 144:ef7eb2e8f9f7 1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
<> 144:ef7eb2e8f9f7 1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
<> 144:ef7eb2e8f9f7 1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
<> 144:ef7eb2e8f9f7 1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
<> 144:ef7eb2e8f9f7 1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
<> 144:ef7eb2e8f9f7 1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
<> 144:ef7eb2e8f9f7 1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
<> 144:ef7eb2e8f9f7 1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<> 144:ef7eb2e8f9f7 1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
<> 144:ef7eb2e8f9f7 1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
<> 144:ef7eb2e8f9f7 1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
<> 144:ef7eb2e8f9f7 1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
<> 144:ef7eb2e8f9f7 1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
<> 144:ef7eb2e8f9f7 1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
<> 144:ef7eb2e8f9f7 1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
<> 144:ef7eb2e8f9f7 1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
<> 144:ef7eb2e8f9f7 1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
<> 144:ef7eb2e8f9f7 1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
<> 144:ef7eb2e8f9f7 1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
<> 144:ef7eb2e8f9f7 1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
<> 144:ef7eb2e8f9f7 1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
<> 144:ef7eb2e8f9f7 1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
<> 144:ef7eb2e8f9f7 1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
<> 144:ef7eb2e8f9f7 1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
<> 144:ef7eb2e8f9f7 1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /** @} */ /* End of group Device_Peripheral_Registers */
<> 144:ef7eb2e8f9f7 1238 /** @} */ /* End of group LPC11U6x */
<> 144:ef7eb2e8f9f7 1239 /** @} */ /* End of group (null) */
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 #endif
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 #endif /* LPC11U6x_H */
<> 144:ef7eb2e8f9f7 1247