Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c@165:2dd56e6daeec, 2017-05-23 (annotated)

Committer:
ranaumarnaeem
Date:
Tue May 23 12:54:50 2017 +0000
Revision:
165:2dd56e6daeec
Parent:
157:ff67d9f36b67 
jhjg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /*******************************************************************************
<> 157:ff67d9f36b67 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 3 *
<> 157:ff67d9f36b67 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 5 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 6 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 9 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 10 *
<> 157:ff67d9f36b67 11 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 12 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 13 *
<> 157:ff67d9f36b67 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 21 *
<> 157:ff67d9f36b67 22 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 24 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 28 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 30 * ownership rights.
<> 157:ff67d9f36b67 31 *
<> 157:ff67d9f36b67 32 * $Date: 2016-03-22 12:05:05 -0500 (Tue, 22 Mar 2016) $
<> 157:ff67d9f36b67 33 * $Revision: 22032 $
<> 157:ff67d9f36b67 34 * ******************************************************************************/
<> 157:ff67d9f36b67 35
<> 157:ff67d9f36b67 36 /***** Includes *****/
<> 157:ff67d9f36b67 37 #include "mxc_config.h"
<> 157:ff67d9f36b67 38 #include "mxc_assert.h"
<> 157:ff67d9f36b67 39 #include "lp.h"
<> 157:ff67d9f36b67 40 #include "ioman_regs.h"
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /***** Definitions *****/
<> 157:ff67d9f36b67 43
<> 157:ff67d9f36b67 44 #ifndef LP0_PRE_HOOK
<> 157:ff67d9f36b67 45 #define LP0_PRE_HOOK
<> 157:ff67d9f36b67 46 #endif
<> 157:ff67d9f36b67 47 #ifndef LP1_PRE_HOOK
<> 157:ff67d9f36b67 48 #define LP1_PRE_HOOK
<> 157:ff67d9f36b67 49 #endif
<> 157:ff67d9f36b67 50 #ifndef LP1_POST_HOOK
<> 157:ff67d9f36b67 51 #define LP1_POST_HOOK
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 /***** Globals *****/
<> 157:ff67d9f36b67 55
<> 157:ff67d9f36b67 56 /***** Functions *****/
<> 157:ff67d9f36b67 57
<> 157:ff67d9f36b67 58 /* Clear all wake-up configuration */
<> 157:ff67d9f36b67 59 void LP_ClearWakeUpConfig(void)
<> 157:ff67d9f36b67 60 {
<> 157:ff67d9f36b67 61 /* Clear GPIO WUD event and configuration registers, globally */
<> 157:ff67d9f36b67 62 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
<> 157:ff67d9f36b67 63 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 157:ff67d9f36b67 64 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
<> 157:ff67d9f36b67 65 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 157:ff67d9f36b67 66
<> 157:ff67d9f36b67 67 /* Mask off all wake-up sources */
<> 157:ff67d9f36b67 68 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP |
<> 157:ff67d9f36b67 69 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
<> 157:ff67d9f36b67 70 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP |
<> 157:ff67d9f36b67 71 MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 |
<> 157:ff67d9f36b67 72 MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
<> 157:ff67d9f36b67 73 MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP |
<> 157:ff67d9f36b67 74 MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER);
<> 157:ff67d9f36b67 75 }
<> 157:ff67d9f36b67 76
<> 157:ff67d9f36b67 77 /* Clear wake-up flags */
<> 157:ff67d9f36b67 78 unsigned int LP_ClearWakeUpFlags(void)
<> 157:ff67d9f36b67 79 {
<> 157:ff67d9f36b67 80 unsigned int flags_tmp;
<> 157:ff67d9f36b67 81
<> 157:ff67d9f36b67 82 /* Get flags */
<> 157:ff67d9f36b67 83 flags_tmp = MXC_PWRSEQ->flags;
<> 157:ff67d9f36b67 84
<> 157:ff67d9f36b67 85 /* Clear GPIO WUD event registers, globally */
<> 157:ff67d9f36b67 86 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
<> 157:ff67d9f36b67 87 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89 /* Clear power sequencer event flags (write-1-to-clear) */
<> 157:ff67d9f36b67 90 MXC_PWRSEQ->flags = flags_tmp;
<> 157:ff67d9f36b67 91
<> 157:ff67d9f36b67 92 return flags_tmp;
<> 157:ff67d9f36b67 93 }
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95 /* Configure the selected pin for wake-up detect */
<> 157:ff67d9f36b67 96 int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd)
<> 157:ff67d9f36b67 97 {
<> 157:ff67d9f36b67 98 int result = E_NO_ERROR;
<> 157:ff67d9f36b67 99 unsigned int pin;
<> 157:ff67d9f36b67 100
<> 157:ff67d9f36b67 101 /* Check that port and pin are within range */
<> 157:ff67d9f36b67 102 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
<> 157:ff67d9f36b67 103 MXC_ASSERT(gpio->mask > 0);
<> 157:ff67d9f36b67 104
<> 157:ff67d9f36b67 105 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */
<> 157:ff67d9f36b67 106 if (gpio->port < 4) {
<> 157:ff67d9f36b67 107 MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
<> 157:ff67d9f36b67 108 if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
<> 157:ff67d9f36b67 109 result = E_BUSY;
<> 157:ff67d9f36b67 110 }
<> 157:ff67d9f36b67 111 } else if (gpio->port < 8) {
<> 157:ff67d9f36b67 112 MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
<> 157:ff67d9f36b67 113 if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
<> 157:ff67d9f36b67 114 result = E_BUSY;
<> 157:ff67d9f36b67 115 }
<> 157:ff67d9f36b67 116 } else {
<> 157:ff67d9f36b67 117 MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3));
<> 157:ff67d9f36b67 118 if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */
<> 157:ff67d9f36b67 119 result = E_BUSY;
<> 157:ff67d9f36b67 120 }
<> 157:ff67d9f36b67 121 }
<> 157:ff67d9f36b67 122
<> 157:ff67d9f36b67 123 if (result == E_NO_ERROR) {
<> 157:ff67d9f36b67 124
<> 157:ff67d9f36b67 125 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 157:ff67d9f36b67 126
<> 157:ff67d9f36b67 127 if (gpio->mask & (1 << pin)) {
<> 157:ff67d9f36b67 128
<> 157:ff67d9f36b67 129 /* Enable modifications to WUD configuration */
<> 157:ff67d9f36b67 130 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 157:ff67d9f36b67 131
<> 157:ff67d9f36b67 132 /* Select pad in WUD control */
<> 157:ff67d9f36b67 133 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 157:ff67d9f36b67 134 MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
<> 157:ff67d9f36b67 135
<> 157:ff67d9f36b67 136 /* Configure sense level on this pad */
<> 157:ff67d9f36b67 137 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 if (act_high) {
<> 157:ff67d9f36b67 140 /* Select active high with PULSE0 (backwards from what you'd expect) */
<> 157:ff67d9f36b67 141 MXC_PWRMAN->wud_pulse0 = 1;
<> 157:ff67d9f36b67 142 } else {
<> 157:ff67d9f36b67 143 /* Select active low with PULSE1 (backwards from what you'd expect) */
<> 157:ff67d9f36b67 144 MXC_PWRMAN->wud_pulse1 = 1;
<> 157:ff67d9f36b67 145 }
<> 157:ff67d9f36b67 146
<> 157:ff67d9f36b67 147 /* Clear out the pad mode */
<> 157:ff67d9f36b67 148 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 157:ff67d9f36b67 149
<> 157:ff67d9f36b67 150 /* Select this pad to have the wake-up function enabled */
<> 157:ff67d9f36b67 151 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 157:ff67d9f36b67 152
<> 157:ff67d9f36b67 153 /* Activate with PULSE1 */
<> 157:ff67d9f36b67 154 MXC_PWRMAN->wud_pulse1 = 1;
<> 157:ff67d9f36b67 155
<> 157:ff67d9f36b67 156 if (wk_pu_pd != LP_NO_PULL) {
<> 157:ff67d9f36b67 157 /* Select weak pull-up/pull-down on this pad while in LP1 */
<> 157:ff67d9f36b67 158 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 157:ff67d9f36b67 159
<> 157:ff67d9f36b67 160 /* Again, logic is opposite of what you'd expect */
<> 157:ff67d9f36b67 161 if (wk_pu_pd == LP_WEAK_PULL_UP) {
<> 157:ff67d9f36b67 162 MXC_PWRMAN->wud_pulse0 = 1;
<> 157:ff67d9f36b67 163 } else {
<> 157:ff67d9f36b67 164 MXC_PWRMAN->wud_pulse1 = 1;
<> 157:ff67d9f36b67 165 }
<> 157:ff67d9f36b67 166 }
<> 157:ff67d9f36b67 167
<> 157:ff67d9f36b67 168 /* Disable configuration each time, required by hardware */
<> 157:ff67d9f36b67 169 MXC_PWRMAN->wud_ctrl = 0;
<> 157:ff67d9f36b67 170 }
<> 157:ff67d9f36b67 171 }
<> 157:ff67d9f36b67 172 }
<> 157:ff67d9f36b67 173
<> 157:ff67d9f36b67 174 /* Disable configuration */
<> 157:ff67d9f36b67 175 MXC_IOMAN->wud_req0 = 0;
<> 157:ff67d9f36b67 176 MXC_IOMAN->wud_req1 = 0;
<> 157:ff67d9f36b67 177 MXC_IOMAN->wud_req2 = 0;
<> 157:ff67d9f36b67 178
<> 157:ff67d9f36b67 179 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
<> 157:ff67d9f36b67 180 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
<> 157:ff67d9f36b67 181
<> 157:ff67d9f36b67 182 return result;
<> 157:ff67d9f36b67 183 }
<> 157:ff67d9f36b67 184
<> 157:ff67d9f36b67 185 uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
<> 157:ff67d9f36b67 186 {
<> 157:ff67d9f36b67 187 uint8_t gpioWokeUp = 0;
<> 157:ff67d9f36b67 188
<> 157:ff67d9f36b67 189 /* Check that port and pin are within range */
<> 157:ff67d9f36b67 190 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
<> 157:ff67d9f36b67 191 MXC_ASSERT(gpio->mask > 0);
<> 157:ff67d9f36b67 192
<> 157:ff67d9f36b67 193 /* Ports 0-3 are wud_seen0, while 4-7 are wud_seen1, 8 is wud_seen2 */
<> 157:ff67d9f36b67 194 if (gpio->port < 4) {
<> 157:ff67d9f36b67 195 gpioWokeUp = (MXC_PWRMAN->wud_seen0 >> (gpio->port << 3)) & gpio->mask;
<> 157:ff67d9f36b67 196 } else if (gpio->port < 8) {
<> 157:ff67d9f36b67 197 gpioWokeUp = (MXC_PWRMAN->wud_seen1 >> ((gpio->port - 4) << 3)) & gpio->mask;
<> 157:ff67d9f36b67 198 } else {
<> 157:ff67d9f36b67 199 gpioWokeUp = (MXC_PWRMAN->wud_seen2 >> ((gpio->port - 8) << 3)) & gpio->mask;
<> 157:ff67d9f36b67 200 }
<> 157:ff67d9f36b67 201
<> 157:ff67d9f36b67 202 return gpioWokeUp;
<> 157:ff67d9f36b67 203 }
<> 157:ff67d9f36b67 204
<> 157:ff67d9f36b67 205 int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio)
<> 157:ff67d9f36b67 206 {
<> 157:ff67d9f36b67 207 int result = E_NO_ERROR;
<> 157:ff67d9f36b67 208 unsigned int pin;
<> 157:ff67d9f36b67 209
<> 157:ff67d9f36b67 210 /* Check that port and pin are within range */
<> 157:ff67d9f36b67 211 MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
<> 157:ff67d9f36b67 212 MXC_ASSERT(gpio->mask > 0);
<> 157:ff67d9f36b67 213
<> 157:ff67d9f36b67 214 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */
<> 157:ff67d9f36b67 215 if (gpio->port < 4) {
<> 157:ff67d9f36b67 216 MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
<> 157:ff67d9f36b67 217 if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
<> 157:ff67d9f36b67 218 result = E_BUSY;
<> 157:ff67d9f36b67 219 }
<> 157:ff67d9f36b67 220 } else if (gpio->port < 8) {
<> 157:ff67d9f36b67 221 MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
<> 157:ff67d9f36b67 222 if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
<> 157:ff67d9f36b67 223 result = E_BUSY;
<> 157:ff67d9f36b67 224 }
<> 157:ff67d9f36b67 225 } else {
<> 157:ff67d9f36b67 226 MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3));
<> 157:ff67d9f36b67 227 if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */
<> 157:ff67d9f36b67 228 result = E_BUSY;
<> 157:ff67d9f36b67 229 }
<> 157:ff67d9f36b67 230 }
<> 157:ff67d9f36b67 231
<> 157:ff67d9f36b67 232 if (result == E_NO_ERROR) {
<> 157:ff67d9f36b67 233 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 157:ff67d9f36b67 234 if (gpio->mask & (1 << pin)) {
<> 157:ff67d9f36b67 235
<> 157:ff67d9f36b67 236 /* Enable modifications to WUD configuration */
<> 157:ff67d9f36b67 237 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
<> 157:ff67d9f36b67 238
<> 157:ff67d9f36b67 239 /* Select pad in WUD control */
<> 157:ff67d9f36b67 240 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
<> 157:ff67d9f36b67 241 MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
<> 157:ff67d9f36b67 242
<> 157:ff67d9f36b67 243 /* Clear out the pad mode */
<> 157:ff67d9f36b67 244 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
<> 157:ff67d9f36b67 245
<> 157:ff67d9f36b67 246 /* Select the wake up function on this pad */
<> 157:ff67d9f36b67 247 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
<> 157:ff67d9f36b67 248
<> 157:ff67d9f36b67 249 /* disable wake up with PULSE0 */
<> 157:ff67d9f36b67 250 MXC_PWRMAN->wud_pulse0 = 1;
<> 157:ff67d9f36b67 251
<> 157:ff67d9f36b67 252 /* Disable configuration each time, required by hardware */
<> 157:ff67d9f36b67 253 MXC_PWRMAN->wud_ctrl = 0;
<> 157:ff67d9f36b67 254 }
<> 157:ff67d9f36b67 255 }
<> 157:ff67d9f36b67 256 }
<> 157:ff67d9f36b67 257
<> 157:ff67d9f36b67 258 /* Disable configuration */
<> 157:ff67d9f36b67 259 MXC_IOMAN->wud_req0 = 0;
<> 157:ff67d9f36b67 260 MXC_IOMAN->wud_req1 = 0;
<> 157:ff67d9f36b67 261 MXC_IOMAN->wud_req2 = 0;
<> 157:ff67d9f36b67 262
<> 157:ff67d9f36b67 263 return result;
<> 157:ff67d9f36b67 264 }
<> 157:ff67d9f36b67 265
<> 157:ff67d9f36b67 266 int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en)
<> 157:ff67d9f36b67 267 {
<> 157:ff67d9f36b67 268 /* Enable or disable wake on USB plug-in */
<> 157:ff67d9f36b67 269 if (plug_en) {
<> 157:ff67d9f36b67 270 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP;
<> 157:ff67d9f36b67 271 } else {
<> 157:ff67d9f36b67 272 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP);
<> 157:ff67d9f36b67 273 }
<> 157:ff67d9f36b67 274
<> 157:ff67d9f36b67 275 /* Enable or disable wake on USB unplug */
<> 157:ff67d9f36b67 276 if (unplug_en) {
<> 157:ff67d9f36b67 277 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP;
<> 157:ff67d9f36b67 278 } else {
<> 157:ff67d9f36b67 279 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
<> 157:ff67d9f36b67 280 }
<> 157:ff67d9f36b67 281
<> 157:ff67d9f36b67 282 return E_NO_ERROR;
<> 157:ff67d9f36b67 283 }
<> 157:ff67d9f36b67 284
<> 157:ff67d9f36b67 285 int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en,
<> 157:ff67d9f36b67 286 unsigned int prescale_cmp_en, unsigned int rollover_en)
<> 157:ff67d9f36b67 287 {
<> 157:ff67d9f36b67 288 /* Note: MXC_PWRSEQ.pwr_misc[0] should be set to have the mask be active low */
<> 157:ff67d9f36b67 289
<> 157:ff67d9f36b67 290 /* Enable or disable wake on RTC Compare 0 */
<> 157:ff67d9f36b67 291 if (comp0_en) {
<> 157:ff67d9f36b67 292 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR0;
<> 157:ff67d9f36b67 293
<> 157:ff67d9f36b67 294 } else {
<> 157:ff67d9f36b67 295 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR0);
<> 157:ff67d9f36b67 296 }
<> 157:ff67d9f36b67 297
<> 157:ff67d9f36b67 298 /* Enable or disable wake on RTC Compare 1 */
<> 157:ff67d9f36b67 299 if (comp1_en) {
<> 157:ff67d9f36b67 300 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR1;
<> 157:ff67d9f36b67 301
<> 157:ff67d9f36b67 302 } else {
<> 157:ff67d9f36b67 303 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR1);
<> 157:ff67d9f36b67 304 }
<> 157:ff67d9f36b67 305
<> 157:ff67d9f36b67 306 /* Enable or disable wake on RTC Prescaler */
<> 157:ff67d9f36b67 307 if (prescale_cmp_en) {
<> 157:ff67d9f36b67 308 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP;
<> 157:ff67d9f36b67 309
<> 157:ff67d9f36b67 310 } else {
<> 157:ff67d9f36b67 311 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP);
<> 157:ff67d9f36b67 312 }
<> 157:ff67d9f36b67 313
<> 157:ff67d9f36b67 314 /* Enable or disable wake on RTC Rollover */
<> 157:ff67d9f36b67 315 if (rollover_en) {
<> 157:ff67d9f36b67 316 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER;
<> 157:ff67d9f36b67 317
<> 157:ff67d9f36b67 318 } else {
<> 157:ff67d9f36b67 319 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER);
<> 157:ff67d9f36b67 320 }
<> 157:ff67d9f36b67 321
<> 157:ff67d9f36b67 322 return E_NO_ERROR;
<> 157:ff67d9f36b67 323 }
<> 157:ff67d9f36b67 324
<> 157:ff67d9f36b67 325
<> 157:ff67d9f36b67 326 int LP_EnterLP2(void)
<> 157:ff67d9f36b67 327 {
<> 157:ff67d9f36b67 328 /* Clear SLEEPDEEP bit to avoid LP1/LP0 entry*/
<> 157:ff67d9f36b67 329 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 157:ff67d9f36b67 330
<> 157:ff67d9f36b67 331 /* Go into LP2 mode and wait for an interrupt to wake the processor */
<> 157:ff67d9f36b67 332 __WFI();
<> 157:ff67d9f36b67 333
<> 157:ff67d9f36b67 334 return E_NO_ERROR;
<> 157:ff67d9f36b67 335 }
<> 157:ff67d9f36b67 336
<> 157:ff67d9f36b67 337 int LP_EnterLP1(void)
<> 157:ff67d9f36b67 338 {
<> 157:ff67d9f36b67 339 /* Turn on retention controller */
<> 157:ff67d9f36b67 340 MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
<> 157:ff67d9f36b67 341
<> 157:ff67d9f36b67 342 /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
<> 157:ff67d9f36b67 343 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
<> 157:ff67d9f36b67 344
<> 157:ff67d9f36b67 345 /* Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP */
<> 157:ff67d9f36b67 346 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
<> 157:ff67d9f36b67 347
<> 157:ff67d9f36b67 348 /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
<> 157:ff67d9f36b67 349 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 157:ff67d9f36b67 350
<> 157:ff67d9f36b67 351 /* Performance-measurement hook, may be defined as nothing */
<> 157:ff67d9f36b67 352 LP1_PRE_HOOK;
<> 157:ff67d9f36b67 353
<> 157:ff67d9f36b67 354 /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
<> 157:ff67d9f36b67 355 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
<> 157:ff67d9f36b67 356
<> 157:ff67d9f36b67 357 /* Dummy read to make sure SSB writes are complete */
<> 157:ff67d9f36b67 358 MXC_PWRSEQ->reg0;
<> 157:ff67d9f36b67 359
<> 157:ff67d9f36b67 360 /* Enter LP1 -- sequence is per instructions from ARM, Ltd. */
<> 157:ff67d9f36b67 361 __SEV();
<> 157:ff67d9f36b67 362 __WFE();
<> 157:ff67d9f36b67 363 __WFE();
<> 157:ff67d9f36b67 364
<> 157:ff67d9f36b67 365 /* Performance-measurement hook, may be defined as nothing */
<> 157:ff67d9f36b67 366 LP1_POST_HOOK;
<> 157:ff67d9f36b67 367
<> 157:ff67d9f36b67 368 /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
<> 157:ff67d9f36b67 369 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
<> 157:ff67d9f36b67 370
<> 157:ff67d9f36b67 371 /* Clear SLEEPDEEP bit */
<> 157:ff67d9f36b67 372 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 157:ff67d9f36b67 373
<> 157:ff67d9f36b67 374 /* No error */
<> 157:ff67d9f36b67 375 return E_NO_ERROR;
<> 157:ff67d9f36b67 376 }
<> 157:ff67d9f36b67 377
<> 157:ff67d9f36b67 378 void LP_EnterLP0(void)
<> 157:ff67d9f36b67 379 {
<> 157:ff67d9f36b67 380 /* Disable interrupts, ok not to save state as exit LP0 is a reset */
<> 157:ff67d9f36b67 381 __disable_irq();
<> 157:ff67d9f36b67 382
<> 157:ff67d9f36b67 383 /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
<> 157:ff67d9f36b67 384 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
<> 157:ff67d9f36b67 385
<> 157:ff67d9f36b67 386 /* Turn off retention controller */
<> 157:ff67d9f36b67 387 MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN);
<> 157:ff67d9f36b67 388
<> 157:ff67d9f36b67 389 /* Turn off retention regulator */
<> 157:ff67d9f36b67 390 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
<> 157:ff67d9f36b67 391
<> 157:ff67d9f36b67 392 /* LP0 ONLY to eliminate ~50nA of leakage on VDD12 */
<> 157:ff67d9f36b67 393 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
<> 157:ff67d9f36b67 394
<> 157:ff67d9f36b67 395 /* Clear the LP1 select bit so CPU goes to LP0 during SLEEPDEEP */
<> 157:ff67d9f36b67 396 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_LP1);
<> 157:ff67d9f36b67 397
<> 157:ff67d9f36b67 398 /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
<> 157:ff67d9f36b67 399 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 157:ff67d9f36b67 400
<> 157:ff67d9f36b67 401 /* Performance-measurement hook, may be defined as nothing */
<> 157:ff67d9f36b67 402 LP0_PRE_HOOK;
<> 157:ff67d9f36b67 403
<> 157:ff67d9f36b67 404 /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
<> 157:ff67d9f36b67 405 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
<> 157:ff67d9f36b67 406
<> 157:ff67d9f36b67 407 /* Dummy read to make sure SSB writes are complete */
<> 157:ff67d9f36b67 408 MXC_PWRSEQ->reg0;
<> 157:ff67d9f36b67 409
<> 157:ff67d9f36b67 410 /* Go into LP0 -- sequence is per instructions from ARM, Ltd. */
<> 157:ff67d9f36b67 411 __SEV();
<> 157:ff67d9f36b67 412 __WFE();
<> 157:ff67d9f36b67 413 __WFE();
<> 157:ff67d9f36b67 414
<> 157:ff67d9f36b67 415 /* Catch the case where this code does not properly sleep */
<> 157:ff67d9f36b67 416 /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
<> 157:ff67d9f36b67 417 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
<> 157:ff67d9f36b67 418 MXC_ASSERT_FAIL();
<> 157:ff67d9f36b67 419 while (1) {
<> 157:ff67d9f36b67 420 __NOP();
<> 157:ff67d9f36b67 421 }
<> 157:ff67d9f36b67 422
<> 157:ff67d9f36b67 423 /* Does not actually return */
<> 157:ff67d9f36b67 424 }