Umar Naeem
mbed library sources. Supersedes mbed-src.
Fork of
mbed-dev
by 
Umar Naeem
targets/TARGET_Maxim/TARGET_MAX32630/device/max3263x.h@165:2dd56e6daeec, 2017-05-23 (annotated)
- Committer:
- ranaumarnaeem
- Date:
- Tue May 23 12:54:50 2017 +0000
- Revision:
- 165:2dd56e6daeec
- Parent:
- 157:ff67d9f36b67
jhjg
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 157:ff67d9f36b67 | 1 | /** |
| <> | 157:ff67d9f36b67 | 2 | * @file |
| <> | 157:ff67d9f36b67 | 3 | * @brief MAX3263X device specific definitions for the core, peripherals, |
| <> | 157:ff67d9f36b67 | 4 | * features, memory, and IRQs. |
| <> | 157:ff67d9f36b67 | 5 | */ |
| <> | 157:ff67d9f36b67 | 6 | /* ***************************************************************************** |
| <> | 157:ff67d9f36b67 | 7 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| <> | 157:ff67d9f36b67 | 8 | * |
| <> | 157:ff67d9f36b67 | 9 | * Permission is hereby granted, free of charge, to any person obtaining a |
| <> | 157:ff67d9f36b67 | 10 | * copy of this software and associated documentation files (the "Software"), |
| <> | 157:ff67d9f36b67 | 11 | * to deal in the Software without restriction, including without limitation |
| <> | 157:ff67d9f36b67 | 12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| <> | 157:ff67d9f36b67 | 13 | * and/or sell copies of the Software, and to permit persons to whom the |
| <> | 157:ff67d9f36b67 | 14 | * Software is furnished to do so, subject to the following conditions: |
| <> | 157:ff67d9f36b67 | 15 | * |
| <> | 157:ff67d9f36b67 | 16 | * The above copyright notice and this permission notice shall be included |
| <> | 157:ff67d9f36b67 | 17 | * in all copies or substantial portions of the Software. |
| <> | 157:ff67d9f36b67 | 18 | * |
| <> | 157:ff67d9f36b67 | 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| <> | 157:ff67d9f36b67 | 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| <> | 157:ff67d9f36b67 | 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| <> | 157:ff67d9f36b67 | 22 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| <> | 157:ff67d9f36b67 | 23 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| <> | 157:ff67d9f36b67 | 24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| <> | 157:ff67d9f36b67 | 25 | * OTHER DEALINGS IN THE SOFTWARE. |
| <> | 157:ff67d9f36b67 | 26 | * |
| <> | 157:ff67d9f36b67 | 27 | * Except as contained in this notice, the name of Maxim Integrated |
| <> | 157:ff67d9f36b67 | 28 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| <> | 157:ff67d9f36b67 | 29 | * Products, Inc. Branding Policy. |
| <> | 157:ff67d9f36b67 | 30 | * |
| <> | 157:ff67d9f36b67 | 31 | * The mere transfer of this software does not imply any licenses |
| <> | 157:ff67d9f36b67 | 32 | * of trade secrets, proprietary technology, copyrights, patents, |
| <> | 157:ff67d9f36b67 | 33 | * trademarks, maskwork rights, or any other form of intellectual |
| <> | 157:ff67d9f36b67 | 34 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| <> | 157:ff67d9f36b67 | 35 | * ownership rights. |
| <> | 157:ff67d9f36b67 | 36 | * |
| <> | 157:ff67d9f36b67 | 37 | * |
| <> | 157:ff67d9f36b67 | 38 | * $Date: 2016-10-31 17:08:23 -0500 (Mon, 31 Oct 2016) $ |
| <> | 157:ff67d9f36b67 | 39 | * $Revision: 24858 $ |
| <> | 157:ff67d9f36b67 | 40 | * |
| <> | 157:ff67d9f36b67 | 41 | *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 42 | |
| <> | 157:ff67d9f36b67 | 43 | /* **** Includes **** */ |
| <> | 157:ff67d9f36b67 | 44 | #include <stdint.h> |
| <> | 157:ff67d9f36b67 | 45 | |
| <> | 157:ff67d9f36b67 | 46 | /* Define to prevent redundant inclusion */ |
| <> | 157:ff67d9f36b67 | 47 | #ifndef _MAX3263X_H_ |
| <> | 157:ff67d9f36b67 | 48 | #define _MAX3263X_H_ |
| <> | 157:ff67d9f36b67 | 49 | |
| <> | 157:ff67d9f36b67 | 50 | |
| <> | 157:ff67d9f36b67 | 51 | /** |
| <> | 157:ff67d9f36b67 | 52 | * @ingroup cmsis_product |
| <> | 157:ff67d9f36b67 | 53 | * @defgroup product_name MAX3263X |
| <> | 157:ff67d9f36b67 | 54 | * @brief MAX3263X device specific definitions for the core, peripherals, |
| <> | 157:ff67d9f36b67 | 55 | * features, memory, and IRQs. |
| <> | 157:ff67d9f36b67 | 56 | * @details The <b><em>MAX32630/MAX32631</em></b> is an ARM® |
| <> | 157:ff67d9f36b67 | 57 | * Cortex®-M4F 32-bit microcontroller with a floating point |
| <> | 157:ff67d9f36b67 | 58 | * unit, ideal for the emerging category of wearable medical and |
| <> | 157:ff67d9f36b67 | 59 | * fitness applications. The architecture combines ultra-low power |
| <> | 157:ff67d9f36b67 | 60 | * high-efficiency signal processing functionality with |
| <> | 157:ff67d9f36b67 | 61 | * significantly reduced power consumption and ease of use. The |
| <> | 157:ff67d9f36b67 | 62 | * device features four powerful and flexible power modes. A |
| <> | 157:ff67d9f36b67 | 63 | * peripheral management unit (PMU) enables intelligent peripheral |
| <> | 157:ff67d9f36b67 | 64 | * control with up to six channels to significantly reduce power |
| <> | 157:ff67d9f36b67 | 65 | * consumption. Built-in dynamic clock gating and |
| <> | 157:ff67d9f36b67 | 66 | * firmware-controlled power gating allows the user to optimize |
| <> | 157:ff67d9f36b67 | 67 | * power for the specific application. Multiple SPI, UART and |
| <> | 157:ff67d9f36b67 | 68 | * I²C serial interfaces, as well as 1-Wire® master and |
| <> | 157:ff67d9f36b67 | 69 | * USB, allow for interconnection to a wide variety of external |
| <> | 157:ff67d9f36b67 | 70 | * sensors. A four-input, 10-bit ADC with selectable references is |
| <> | 157:ff67d9f36b67 | 71 | * available to monitor analog input from external sensors and |
| <> | 157:ff67d9f36b67 | 72 | * meters. The small 100-ball WLP package provides a tiny, 4.37mm x |
| <> | 157:ff67d9f36b67 | 73 | * 4.37mm footprint. The <b><em>MAX32630/MAX32631</em></b> include |
| <> | 157:ff67d9f36b67 | 74 | * a hardware AES engine. The <b>@em MAX32631</b> is a secure |
| <> | 157:ff67d9f36b67 | 75 | * version of the <b>@em MAX32630</b>. It incorporates a trust |
| <> | 157:ff67d9f36b67 | 76 | * protection unit (TPU) with encryption and advanced security |
| <> | 157:ff67d9f36b67 | 77 | * features. These features include a modular arithmetic |
| <> | 157:ff67d9f36b67 | 78 | * accelerator (MAA) for fast ECDSA, a hardware PRNG entropy |
| <> | 157:ff67d9f36b67 | 79 | * generator, and a secure boot loader. |
| <> | 157:ff67d9f36b67 | 80 | * @{ |
| <> | 157:ff67d9f36b67 | 81 | */ |
| <> | 157:ff67d9f36b67 | 82 | #ifndef FALSE |
| <> | 157:ff67d9f36b67 | 83 | /** |
| <> | 157:ff67d9f36b67 | 84 | * @internal False |
| <> | 157:ff67d9f36b67 | 85 | */ |
| <> | 157:ff67d9f36b67 | 86 | #define FALSE (0) |
| <> | 157:ff67d9f36b67 | 87 | #endif |
| <> | 157:ff67d9f36b67 | 88 | |
| <> | 157:ff67d9f36b67 | 89 | #ifndef TRUE |
| <> | 157:ff67d9f36b67 | 90 | /** |
| <> | 157:ff67d9f36b67 | 91 | * @internal True |
| <> | 157:ff67d9f36b67 | 92 | */ |
| <> | 157:ff67d9f36b67 | 93 | #define TRUE (1) |
| <> | 157:ff67d9f36b67 | 94 | #endif |
| <> | 157:ff67d9f36b67 | 95 | |
| <> | 157:ff67d9f36b67 | 96 | /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ |
| <> | 157:ff67d9f36b67 | 97 | #if defined ( __GNUC__ ) |
| <> | 157:ff67d9f36b67 | 98 | #define __weak __attribute__((weak)) /**< GNUC weak function keyword. */ |
| <> | 157:ff67d9f36b67 | 99 | #elif defined ( __CC_ARM) |
| <> | 157:ff67d9f36b67 | 100 | #define inline __inline /**< inline keyword for Keil compiler. */ |
| <> | 157:ff67d9f36b67 | 101 | #pragma anon_unions |
| <> | 157:ff67d9f36b67 | 102 | #endif |
| <> | 157:ff67d9f36b67 | 103 | /**@}*/ |
| <> | 157:ff67d9f36b67 | 104 | /** |
| <> | 157:ff67d9f36b67 | 105 | * @ingroup product_name |
| <> | 157:ff67d9f36b67 | 106 | * @defgroup nvic_table Nested Interrupt Vector Table (NVIC) |
| <> | 157:ff67d9f36b67 | 107 | * Device specific interrupt request NVIC entries. |
| <> | 157:ff67d9f36b67 | 108 | * @{ |
| <> | 157:ff67d9f36b67 | 109 | */ |
| <> | 157:ff67d9f36b67 | 110 | /** |
| <> | 157:ff67d9f36b67 | 111 | * \MXIM_Device Nested Interrupt Vector Table (NVIC). |
| <> | 157:ff67d9f36b67 | 112 | * @details |
| <> | 157:ff67d9f36b67 | 113 | * NVIC Peripheral Entry numbers and Offsets are shown in the table below. |
| <> | 157:ff67d9f36b67 | 114 | * |
| <> | 157:ff67d9f36b67 | 115 | * | Entry | Offset | Peripheral | |
| <> | 157:ff67d9f36b67 | 116 | * |-------: | ------: | :------------------------------------ | |
| <> | 157:ff67d9f36b67 | 117 | * | 0x10 | 0x0040 | CLKMAN | |
| <> | 157:ff67d9f36b67 | 118 | * | 0x11 | 0x0044 | PWRMAN | |
| <> | 157:ff67d9f36b67 | 119 | * | 0x12 | 0x0048 | Flash Controller | |
| <> | 157:ff67d9f36b67 | 120 | * | 0x13 | 0x004C | RTC Counter match with Compare 0 | |
| <> | 157:ff67d9f36b67 | 121 | * | 0x14 | 0x0050 | RTC Counter match with Compare 1 | |
| <> | 157:ff67d9f36b67 | 122 | * | 0x15 | 0x0054 | RTC Prescaler interval compare match | |
| <> | 157:ff67d9f36b67 | 123 | * | 0x16 | 0x0058 | RTC Overflow | |
| <> | 157:ff67d9f36b67 | 124 | * | 0x17 | 0x005C | Peripheral Management Unit (PMU/DMA) | |
| <> | 157:ff67d9f36b67 | 125 | * | 0x18 | 0x0060 | USB | |
| <> | 157:ff67d9f36b67 | 126 | * | 0x19 | 0x0064 | AES | |
| <> | 157:ff67d9f36b67 | 127 | * | 0x1A | 0x0068 | MAA | |
| <> | 157:ff67d9f36b67 | 128 | * | 0x1B | 0x006C | Watchdog 0 timeout | |
| <> | 157:ff67d9f36b67 | 129 | * | 0x1C | 0x0070 | Watchdog 0 pre-window (fed too early)| |
| <> | 157:ff67d9f36b67 | 130 | * | 0x1D | 0x0074 | Watchdog 1 timeout | |
| <> | 157:ff67d9f36b67 | 131 | * | 0x1E | 0x0078 | Watchdog 1 pre-window (fed too early)| |
| <> | 157:ff67d9f36b67 | 132 | * | 0x1F | 0x007C | GPIO Port 0 | |
| <> | 157:ff67d9f36b67 | 133 | * | 0x20 | 0x0080 | GPIO Port 1 | |
| <> | 157:ff67d9f36b67 | 134 | * | 0x21 | 0x0084 | GPIO Port 2 | |
| <> | 157:ff67d9f36b67 | 135 | * | 0x22 | 0x0088 | GPIO Port 3 | |
| <> | 157:ff67d9f36b67 | 136 | * | 0x23 | 0x008C | GPIO Port 4 | |
| <> | 157:ff67d9f36b67 | 137 | * | 0x24 | 0x0090 | GPIO Port 5 | |
| <> | 157:ff67d9f36b67 | 138 | * | 0x25 | 0x0094 | GPIO Port 6 | |
| <> | 157:ff67d9f36b67 | 139 | * | 0x26 | 0x0098 | Timer 0 (32-bit, 16-bit #0) | |
| <> | 157:ff67d9f36b67 | 140 | * | 0x27 | 0x009C | Timer 0 (16-bit #1) | |
| <> | 157:ff67d9f36b67 | 141 | * | 0x28 | 0x00A0 | Timer 1 (32-bit, 16-bit #0) | |
| <> | 157:ff67d9f36b67 | 142 | * | 0x29 | 0x00A4 | Timer 1 (16-bit #1) | |
| <> | 157:ff67d9f36b67 | 143 | * | 0x2A | 0x00A8 | Timer 2 (32-bit, 16-bit #0) | |
| <> | 157:ff67d9f36b67 | 144 | * | 0x2B | 0x00AC | Timer 2 (16-bit #1) | |
| <> | 157:ff67d9f36b67 | 145 | * | 0x2C | 0x00B0 | Timer 3 (32-bit, 16-bit #0) | |
| <> | 157:ff67d9f36b67 | 146 | * | 0x2D | 0x00B4 | Timer 3 (16-bit #1) | |
| <> | 157:ff67d9f36b67 | 147 | * | 0x2E | 0x00B8 | Timer 4 (32-bit, 16-bit #0) | |
| <> | 157:ff67d9f36b67 | 148 | * | 0x2F | 0x00BC | Timer 4 (16-bit #1) | |
| <> | 157:ff67d9f36b67 | 149 | * | 0x30 | 0x00C0 | Timer 5 (32-bit, 16-bit #0) | |
| <> | 157:ff67d9f36b67 | 150 | * | 0x31 | 0x00C4 | Timer 5 (16-bit #1) | |
| <> | 157:ff67d9f36b67 | 151 | * | 0x32 | 0x00C8 | UART 0 | |
| <> | 157:ff67d9f36b67 | 152 | * | 0x33 | 0x00CC | UART 1 | |
| <> | 157:ff67d9f36b67 | 153 | * | 0x34 | 0x00D0 | UART 2 | |
| <> | 157:ff67d9f36b67 | 154 | * | 0x35 | 0x00D4 | UART 3 | |
| <> | 157:ff67d9f36b67 | 155 | * | 0x36 | 0x00D8 | Pulse Trains | |
| <> | 157:ff67d9f36b67 | 156 | * | 0x37 | 0x00DC | I2C Master 0 | |
| <> | 157:ff67d9f36b67 | 157 | * | 0x38 | 0x00E0 | I2C Master 1 | |
| <> | 157:ff67d9f36b67 | 158 | * | 0x39 | 0x00E4 | I2C Master 2 | |
| <> | 157:ff67d9f36b67 | 159 | * | 0x3A | 0x00E8 | I2C Slave | |
| <> | 157:ff67d9f36b67 | 160 | * | 0x3B | 0x00EC | SPI Master 0 | |
| <> | 157:ff67d9f36b67 | 161 | * | 0x3C | 0x00F0 | SPI Master 1 | |
| <> | 157:ff67d9f36b67 | 162 | * | 0x3D | 0x00F4 | SPI Master 2 | |
| <> | 157:ff67d9f36b67 | 163 | * | 0x3E | 0x00F8 | SPI Bridge | |
| <> | 157:ff67d9f36b67 | 164 | * | 0x3F | 0x00FC | 1-Wire Master | |
| <> | 157:ff67d9f36b67 | 165 | * | 0x40 | 0x0100 | ADC | |
| <> | 157:ff67d9f36b67 | 166 | * | 0x41 | 0x0104 | SPI Slave | |
| <> | 157:ff67d9f36b67 | 167 | * | 0x42 | 0x0108 | GPIO Port 7 | |
| <> | 157:ff67d9f36b67 | 168 | * | 0x43 | 0x010C | GPIO Port 8 | |
| <> | 157:ff67d9f36b67 | 169 | */ |
| <> | 157:ff67d9f36b67 | 170 | |
| <> | 157:ff67d9f36b67 | 171 | /** |
| <> | 157:ff67d9f36b67 | 172 | * Enumeration type of all \MXIM_Device NVIC entries. |
| <> | 157:ff67d9f36b67 | 173 | */ |
| <> | 157:ff67d9f36b67 | 174 | typedef enum { |
| <> | 157:ff67d9f36b67 | 175 | NonMaskableInt_IRQn = -14, /**< ARM Core : Non-maskable IRQ */ |
| <> | 157:ff67d9f36b67 | 176 | HardFault_IRQn = -13, /**< ARM Core : Hard Fault IRQ */ |
| <> | 157:ff67d9f36b67 | 177 | MemoryManagement_IRQn = -12, /**< ARM Core : Memory Management IRQ */ |
| <> | 157:ff67d9f36b67 | 178 | BusFault_IRQn = -11, /**< ARM Core : Bus Fault IRQ */ |
| <> | 157:ff67d9f36b67 | 179 | UsageFault_IRQn = -10, /**< ARM Core : Usage Fault IRQ */ |
| <> | 157:ff67d9f36b67 | 180 | SVCall_IRQn = -5, /**< ARM Core : SVCall IRQ */ |
| <> | 157:ff67d9f36b67 | 181 | DebugMonitor_IRQn = -4, /**< ARM Core : Debug Monitor IRQ */ |
| <> | 157:ff67d9f36b67 | 182 | PendSV_IRQn = -2, /**< ARM Core : PendSV IRQ */ |
| <> | 157:ff67d9f36b67 | 183 | SysTick_IRQn = -1, /**< ARM Core : SysTick IRQ */ |
| <> | 157:ff67d9f36b67 | 184 | CLKMAN_IRQn = 0, /**< CLKMAN */ |
| <> | 157:ff67d9f36b67 | 185 | PWRMAN_IRQn, /**< PWRMAN */ |
| <> | 157:ff67d9f36b67 | 186 | FLC_IRQn, /**< Flash Controller */ |
| <> | 157:ff67d9f36b67 | 187 | RTC0_IRQn, /**< RTC Counter match with Compare 0 */ |
| <> | 157:ff67d9f36b67 | 188 | RTC1_IRQn, /**< RTC Counter match with Compare 1 */ |
| <> | 157:ff67d9f36b67 | 189 | RTC2_IRQn, /**< RTC Prescaler interval compare match */ |
| <> | 157:ff67d9f36b67 | 190 | RTC3_IRQn, /**< RTC Overflow */ |
| <> | 157:ff67d9f36b67 | 191 | PMU_IRQn, /**< Peripheral Management Unit (PMU/DMA) */ |
| <> | 157:ff67d9f36b67 | 192 | USB_IRQn, /**< USB */ |
| <> | 157:ff67d9f36b67 | 193 | AES_IRQn, /**< AES */ |
| <> | 157:ff67d9f36b67 | 194 | MAA_IRQn, /**< MAA */ |
| <> | 157:ff67d9f36b67 | 195 | WDT0_IRQn, /**< Watchdog 0 timeout */ |
| <> | 157:ff67d9f36b67 | 196 | WDT0_P_IRQn, /**< Watchdog 0 pre-window (fed too early) */ |
| <> | 157:ff67d9f36b67 | 197 | WDT1_IRQn, /**< Watchdog 1 timeout */ |
| <> | 157:ff67d9f36b67 | 198 | WDT1_P_IRQn, /**< Watchdog 1 pre-window (fed too early) */ |
| <> | 157:ff67d9f36b67 | 199 | GPIO_P0_IRQn, /**< GPIO Port 0 */ |
| <> | 157:ff67d9f36b67 | 200 | GPIO_P1_IRQn, /**< GPIO Port 1 */ |
| <> | 157:ff67d9f36b67 | 201 | GPIO_P2_IRQn, /**< GPIO Port 2 */ |
| <> | 157:ff67d9f36b67 | 202 | GPIO_P3_IRQn, /**< GPIO Port 3 */ |
| <> | 157:ff67d9f36b67 | 203 | GPIO_P4_IRQn, /**< GPIO Port 4 */ |
| <> | 157:ff67d9f36b67 | 204 | GPIO_P5_IRQn, /**< GPIO Port 5 */ |
| <> | 157:ff67d9f36b67 | 205 | GPIO_P6_IRQn, /**< GPIO Port 6 */ |
| <> | 157:ff67d9f36b67 | 206 | TMR0_0_IRQn, /**< Timer 0 (32-bit, 16-bit #0) */ |
| <> | 157:ff67d9f36b67 | 207 | TMR0_1_IRQn, /**< Timer 0 (16-bit #1) */ |
| <> | 157:ff67d9f36b67 | 208 | TMR1_0_IRQn, /**< Timer 1 (32-bit, 16-bit #0) */ |
| <> | 157:ff67d9f36b67 | 209 | TMR1_1_IRQn, /**< Timer 1 (16-bit #1) */ |
| <> | 157:ff67d9f36b67 | 210 | TMR2_0_IRQn, /**< Timer 2 (32-bit, 16-bit #0) */ |
| <> | 157:ff67d9f36b67 | 211 | TMR2_1_IRQn, /**< Timer 2 (16-bit #1) */ |
| <> | 157:ff67d9f36b67 | 212 | TMR3_0_IRQn, /**< Timer 3 (32-bit, 16-bit #0) */ |
| <> | 157:ff67d9f36b67 | 213 | TMR3_1_IRQn, /**< Timer 3 (16-bit #1) */ |
| <> | 157:ff67d9f36b67 | 214 | TMR4_0_IRQn, /**< Timer 4 (32-bit, 16-bit #0) */ |
| <> | 157:ff67d9f36b67 | 215 | TMR4_1_IRQn, /**< Timer 4 (16-bit #1) */ |
| <> | 157:ff67d9f36b67 | 216 | TMR5_0_IRQn, /**< Timer 5 (32-bit, 16-bit #0) */ |
| <> | 157:ff67d9f36b67 | 217 | TMR5_1_IRQn, /**< Timer 5 (16-bit #1) */ |
| <> | 157:ff67d9f36b67 | 218 | UART0_IRQn, /**< UART 0 */ |
| <> | 157:ff67d9f36b67 | 219 | UART1_IRQn, /**< UART 1 */ |
| <> | 157:ff67d9f36b67 | 220 | UART2_IRQn, /**< UART 2 */ |
| <> | 157:ff67d9f36b67 | 221 | UART3_IRQn, /**< UART 3 */ |
| <> | 157:ff67d9f36b67 | 222 | PT_IRQn, /**< Pulse Trains */ |
| <> | 157:ff67d9f36b67 | 223 | I2CM0_IRQn, /**< I2C Master 0 */ |
| <> | 157:ff67d9f36b67 | 224 | I2CM1_IRQn, /**< I2C Master 1 */ |
| <> | 157:ff67d9f36b67 | 225 | I2CM2_IRQn, /**< I2C Master 2 */ |
| <> | 157:ff67d9f36b67 | 226 | I2CS_IRQn, /**< I2C Slave */ |
| <> | 157:ff67d9f36b67 | 227 | SPIM0_IRQn, /**< SPI Master 0 */ |
| <> | 157:ff67d9f36b67 | 228 | SPIM1_IRQn, /**< SPI Master 1 */ |
| <> | 157:ff67d9f36b67 | 229 | SPIM2_IRQn, /**< SPI Master 2 */ |
| <> | 157:ff67d9f36b67 | 230 | SPIB_IRQn, /**< SPI Bridge */ |
| <> | 157:ff67d9f36b67 | 231 | OWM_IRQn, /**< 1-Wire Master */ |
| <> | 157:ff67d9f36b67 | 232 | AFE_IRQn, /**< ADC */ |
| <> | 157:ff67d9f36b67 | 233 | SPIS_IRQn, /**< SPI Slave */ |
| <> | 157:ff67d9f36b67 | 234 | GPIO_P7_IRQn, /**< GPIO Port 7 */ |
| <> | 157:ff67d9f36b67 | 235 | GPIO_P8_IRQn, /**< GPIO Port 8 */ |
| <> | 157:ff67d9f36b67 | 236 | MXC_IRQ_EXT_COUNT /**< Total number of non-core IRQ vectors. */ |
| <> | 157:ff67d9f36b67 | 237 | } IRQn_Type; |
| <> | 157:ff67d9f36b67 | 238 | |
| <> | 157:ff67d9f36b67 | 239 | #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) /**< Total number of device IRQs inclusive of core and non-core IRQ vectors. */ |
| <> | 157:ff67d9f36b67 | 240 | /**@}end of group nvic_table*/ |
| <> | 157:ff67d9f36b67 | 241 | |
| <> | 157:ff67d9f36b67 | 242 | /* ================================================================================ */ |
| <> | 157:ff67d9f36b67 | 243 | /* ================ Processor and Core Peripheral Section ================ */ |
| <> | 157:ff67d9f36b67 | 244 | /* ================================================================================ */ |
| <> | 157:ff67d9f36b67 | 245 | /** |
| <> | 157:ff67d9f36b67 | 246 | * @ingroup product_name |
| <> | 157:ff67d9f36b67 | 247 | * @defgroup Cortex_M4 Cortex-M Configuration |
| <> | 157:ff67d9f36b67 | 248 | * @{ |
| <> | 157:ff67d9f36b67 | 249 | */ |
| <> | 157:ff67d9f36b67 | 250 | /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ |
| <> | 157:ff67d9f36b67 | 251 | #define __CM4_REV 0x0100 /**< Cortex-M4 Core Revision */ |
| <> | 157:ff67d9f36b67 | 252 | #define __MPU_PRESENT 1 /**< MPU is present */ |
| <> | 157:ff67d9f36b67 | 253 | #define __NVIC_PRIO_BITS 3 /**< Number of Bits used for IRQ Priority Levels */ |
| <> | 157:ff67d9f36b67 | 254 | #define __Vendor_SysTickConfig 0 /**< Using standard CMSIS SysTickConfig */ |
| <> | 157:ff67d9f36b67 | 255 | #define __FPU_PRESENT 1 /**< FPU is Present */ |
| <> | 157:ff67d9f36b67 | 256 | /**@} end of ingroup Cortex_M4*/ |
| <> | 157:ff67d9f36b67 | 257 | #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ |
| <> | 157:ff67d9f36b67 | 258 | #include "system_max3263x.h" /*!< System Header */ |
| <> | 157:ff67d9f36b67 | 259 | |
| <> | 157:ff67d9f36b67 | 260 | |
| <> | 157:ff67d9f36b67 | 261 | /* ================================================================================ */ |
| <> | 157:ff67d9f36b67 | 262 | /* ================== Device Specific Memory Section ================== */ |
| <> | 157:ff67d9f36b67 | 263 | /* ================================================================================ */ |
| <> | 157:ff67d9f36b67 | 264 | /** |
| <> | 157:ff67d9f36b67 | 265 | * @ingroup product_name |
| <> | 157:ff67d9f36b67 | 266 | * @{ |
| <> | 157:ff67d9f36b67 | 267 | */ |
| <> | 157:ff67d9f36b67 | 268 | #define MXC_FLASH_MEM_BASE 0x00000000UL /**< Internal Flash Memory Start Address. */ |
| <> | 157:ff67d9f36b67 | 269 | #define MXC_FLASH_PAGE_SIZE 0x00002000UL /**< Internal Flash Memory Page Size. */ |
| <> | 157:ff67d9f36b67 | 270 | #define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL /**< Internal Flash Memory Size. */ |
| <> | 157:ff67d9f36b67 | 271 | #define MXC_SYS_MEM_BASE 0x20000000UL /**< System Memory Start Address. */ |
| <> | 157:ff67d9f36b67 | 272 | #define MXC_SRAM_FULL_MEM_SIZE 0x00080000UL /**< Internal SRAM Size. */ |
| <> | 157:ff67d9f36b67 | 273 | #define MXC_EXT_FLASH_MEM_BASE 0x10000000UL /**< External Flash Memory Start Address, SPIX interface. */ |
| <> | 157:ff67d9f36b67 | 274 | |
| <> | 157:ff67d9f36b67 | 275 | /* ================================================================================ */ |
| <> | 157:ff67d9f36b67 | 276 | /* ================ Device Specific Peripheral Section ================ */ |
| <> | 157:ff67d9f36b67 | 277 | /* ================================================================================ */ |
| <> | 157:ff67d9f36b67 | 278 | |
| <> | 157:ff67d9f36b67 | 279 | |
| <> | 157:ff67d9f36b67 | 280 | /* |
| <> | 157:ff67d9f36b67 | 281 | Base addresses and configuration settings for all MAX3263X peripheral modules. |
| <> | 157:ff67d9f36b67 | 282 | */ |
| <> | 157:ff67d9f36b67 | 283 | |
| <> | 157:ff67d9f36b67 | 284 | |
| <> | 157:ff67d9f36b67 | 285 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 286 | /* System Manager Settings */ |
| <> | 157:ff67d9f36b67 | 287 | |
| <> | 157:ff67d9f36b67 | 288 | #define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL) |
| <> | 157:ff67d9f36b67 | 289 | #define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN) |
| <> | 157:ff67d9f36b67 | 290 | |
| <> | 157:ff67d9f36b67 | 291 | |
| <> | 157:ff67d9f36b67 | 292 | |
| <> | 157:ff67d9f36b67 | 293 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 294 | /* System Clock Manager */ |
| <> | 157:ff67d9f36b67 | 295 | |
| <> | 157:ff67d9f36b67 | 296 | #define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL) |
| <> | 157:ff67d9f36b67 | 297 | #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) |
| <> | 157:ff67d9f36b67 | 298 | |
| <> | 157:ff67d9f36b67 | 299 | |
| <> | 157:ff67d9f36b67 | 300 | |
| <> | 157:ff67d9f36b67 | 301 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 302 | /* System Power Manager */ |
| <> | 157:ff67d9f36b67 | 303 | |
| <> | 157:ff67d9f36b67 | 304 | #define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL) |
| <> | 157:ff67d9f36b67 | 305 | #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) |
| <> | 157:ff67d9f36b67 | 306 | |
| <> | 157:ff67d9f36b67 | 307 | |
| <> | 157:ff67d9f36b67 | 308 | |
| <> | 157:ff67d9f36b67 | 309 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 310 | /* Real Time Clock */ |
| <> | 157:ff67d9f36b67 | 311 | |
| <> | 157:ff67d9f36b67 | 312 | #define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL) |
| <> | 157:ff67d9f36b67 | 313 | #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) |
| <> | 157:ff67d9f36b67 | 314 | #define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL) |
| <> | 157:ff67d9f36b67 | 315 | #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) |
| <> | 157:ff67d9f36b67 | 316 | |
| <> | 157:ff67d9f36b67 | 317 | #define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 318 | i == 1 ? RTC1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 319 | i == 2 ? RTC2_IRQn : \ |
| <> | 157:ff67d9f36b67 | 320 | i == 3 ? RTC3_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 321 | |
| <> | 157:ff67d9f36b67 | 322 | |
| <> | 157:ff67d9f36b67 | 323 | |
| <> | 157:ff67d9f36b67 | 324 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 325 | /* Power Sequencer */ |
| <> | 157:ff67d9f36b67 | 326 | |
| <> | 157:ff67d9f36b67 | 327 | #define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL) |
| <> | 157:ff67d9f36b67 | 328 | #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) |
| <> | 157:ff67d9f36b67 | 329 | |
| <> | 157:ff67d9f36b67 | 330 | |
| <> | 157:ff67d9f36b67 | 331 | |
| <> | 157:ff67d9f36b67 | 332 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 333 | /* System I/O Manager */ |
| <> | 157:ff67d9f36b67 | 334 | /**@} end of ingroup product_name*/ |
| <> | 157:ff67d9f36b67 | 335 | /** |
| <> | 157:ff67d9f36b67 | 336 | * @ingroup ioman_registers |
| <> | 157:ff67d9f36b67 | 337 | * @{ |
| <> | 157:ff67d9f36b67 | 338 | */ |
| <> | 157:ff67d9f36b67 | 339 | #define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) /**< Base Peripheral Address for IOMAN */ |
| <> | 157:ff67d9f36b67 | 340 | #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) /**< Pointer to the #mxc_ioman_regs_t structure representing the IOMAN Registers. */ |
| <> | 157:ff67d9f36b67 | 341 | /**@}*/ |
| <> | 157:ff67d9f36b67 | 342 | |
| <> | 157:ff67d9f36b67 | 343 | /** |
| <> | 157:ff67d9f36b67 | 344 | * @ingroup product_name |
| <> | 157:ff67d9f36b67 | 345 | * @{ |
| <> | 157:ff67d9f36b67 | 346 | */ |
| <> | 157:ff67d9f36b67 | 347 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 348 | /* Shadow Trim Registers */ |
| <> | 157:ff67d9f36b67 | 349 | |
| <> | 157:ff67d9f36b67 | 350 | #define MXC_BASE_TRIM ((uint32_t)0x40001000UL) |
| <> | 157:ff67d9f36b67 | 351 | #define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM) |
| <> | 157:ff67d9f36b67 | 352 | |
| <> | 157:ff67d9f36b67 | 353 | |
| <> | 157:ff67d9f36b67 | 354 | |
| <> | 157:ff67d9f36b67 | 355 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 356 | /* Flash Controller */ |
| <> | 157:ff67d9f36b67 | 357 | |
| <> | 157:ff67d9f36b67 | 358 | #define MXC_BASE_FLC ((uint32_t)0x40002000UL) |
| <> | 157:ff67d9f36b67 | 359 | #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) |
| <> | 157:ff67d9f36b67 | 360 | |
| <> | 157:ff67d9f36b67 | 361 | #define MXC_FLC_PAGE_SIZE_SHIFT (13) |
| <> | 157:ff67d9f36b67 | 362 | #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) |
| <> | 157:ff67d9f36b67 | 363 | #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT |
| <> | 157:ff67d9f36b67 | 364 | |
| <> | 157:ff67d9f36b67 | 365 | |
| <> | 157:ff67d9f36b67 | 366 | |
| <> | 157:ff67d9f36b67 | 367 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 368 | /* Instruction Cache */ |
| <> | 157:ff67d9f36b67 | 369 | |
| <> | 157:ff67d9f36b67 | 370 | #define MXC_BASE_ICC ((uint32_t)0x40003000UL) |
| <> | 157:ff67d9f36b67 | 371 | #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) |
| <> | 157:ff67d9f36b67 | 372 | |
| <> | 157:ff67d9f36b67 | 373 | |
| <> | 157:ff67d9f36b67 | 374 | /**@} end of ingroup product_name*/ |
| <> | 157:ff67d9f36b67 | 375 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 376 | /* SPI XIP Interface */ |
| <> | 157:ff67d9f36b67 | 377 | /** |
| <> | 157:ff67d9f36b67 | 378 | * @ingroup spix_registers |
| <> | 157:ff67d9f36b67 | 379 | * @{ |
| <> | 157:ff67d9f36b67 | 380 | */ |
| <> | 157:ff67d9f36b67 | 381 | #define MXC_BASE_SPIX ((uint32_t)0x40004000UL) /**< SPIX Base Peripheral Address. */ |
| <> | 157:ff67d9f36b67 | 382 | #define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX) /**< SPIX pointer to the #mxc_spix_regs_t register structure type. */ |
| <> | 157:ff67d9f36b67 | 383 | /**@} end of ingroup spix_registers*/ |
| <> | 157:ff67d9f36b67 | 384 | |
| <> | 157:ff67d9f36b67 | 385 | /** |
| <> | 157:ff67d9f36b67 | 386 | * @ingroup product_name |
| <> | 157:ff67d9f36b67 | 387 | * @{ |
| <> | 157:ff67d9f36b67 | 388 | */ |
| <> | 157:ff67d9f36b67 | 389 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 390 | /* Peripheral Management Unit */ |
| <> | 157:ff67d9f36b67 | 391 | |
| <> | 157:ff67d9f36b67 | 392 | #define MXC_CFG_PMU_CHANNELS (6) |
| <> | 157:ff67d9f36b67 | 393 | |
| <> | 157:ff67d9f36b67 | 394 | #define MXC_BASE_PMU0 ((uint32_t)0x40005000UL) |
| <> | 157:ff67d9f36b67 | 395 | #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) |
| <> | 157:ff67d9f36b67 | 396 | #define MXC_BASE_PMU1 ((uint32_t)0x40005020UL) |
| <> | 157:ff67d9f36b67 | 397 | #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) |
| <> | 157:ff67d9f36b67 | 398 | #define MXC_BASE_PMU2 ((uint32_t)0x40005040UL) |
| <> | 157:ff67d9f36b67 | 399 | #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) |
| <> | 157:ff67d9f36b67 | 400 | #define MXC_BASE_PMU3 ((uint32_t)0x40005060UL) |
| <> | 157:ff67d9f36b67 | 401 | #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) |
| <> | 157:ff67d9f36b67 | 402 | #define MXC_BASE_PMU4 ((uint32_t)0x40005080UL) |
| <> | 157:ff67d9f36b67 | 403 | #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) |
| <> | 157:ff67d9f36b67 | 404 | #define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL) |
| <> | 157:ff67d9f36b67 | 405 | #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) |
| <> | 157:ff67d9f36b67 | 406 | |
| <> | 157:ff67d9f36b67 | 407 | #define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \ |
| <> | 157:ff67d9f36b67 | 408 | (i) == 1 ? MXC_BASE_PMU1 : \ |
| <> | 157:ff67d9f36b67 | 409 | (i) == 2 ? MXC_BASE_PMU2 : \ |
| <> | 157:ff67d9f36b67 | 410 | (i) == 3 ? MXC_BASE_PMU3 : \ |
| <> | 157:ff67d9f36b67 | 411 | (i) == 4 ? MXC_BASE_PMU4 : \ |
| <> | 157:ff67d9f36b67 | 412 | (i) == 5 ? MXC_BASE_PMU5 : 0) |
| <> | 157:ff67d9f36b67 | 413 | |
| <> | 157:ff67d9f36b67 | 414 | #define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \ |
| <> | 157:ff67d9f36b67 | 415 | (i) == 1 ? MXC_PMU1 : \ |
| <> | 157:ff67d9f36b67 | 416 | (i) == 2 ? MXC_PMU2 : \ |
| <> | 157:ff67d9f36b67 | 417 | (i) == 3 ? MXC_PMU3 : \ |
| <> | 157:ff67d9f36b67 | 418 | (i) == 4 ? MXC_PMU4 : \ |
| <> | 157:ff67d9f36b67 | 419 | (i) == 5 ? MXC_PMU5 : 0) |
| <> | 157:ff67d9f36b67 | 420 | |
| <> | 157:ff67d9f36b67 | 421 | #define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \ |
| <> | 157:ff67d9f36b67 | 422 | (p) == MXC_PMU1 ? 1 : \ |
| <> | 157:ff67d9f36b67 | 423 | (p) == MXC_PMU2 ? 2 : \ |
| <> | 157:ff67d9f36b67 | 424 | (p) == MXC_PMU3 ? 3 : \ |
| <> | 157:ff67d9f36b67 | 425 | (p) == MXC_PMU4 ? 4 : \ |
| <> | 157:ff67d9f36b67 | 426 | (p) == MXC_PMU5 ? 5 : -1) |
| <> | 157:ff67d9f36b67 | 427 | |
| <> | 157:ff67d9f36b67 | 428 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 429 | /* USB Device Controller */ |
| <> | 157:ff67d9f36b67 | 430 | |
| <> | 157:ff67d9f36b67 | 431 | #define MXC_BASE_USB ((uint32_t)0x40100000UL) |
| <> | 157:ff67d9f36b67 | 432 | #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) |
| <> | 157:ff67d9f36b67 | 433 | |
| <> | 157:ff67d9f36b67 | 434 | #define MXC_USB_MAX_PACKET (64) |
| <> | 157:ff67d9f36b67 | 435 | #define MXC_USB_NUM_EP (8) |
| <> | 157:ff67d9f36b67 | 436 | |
| <> | 157:ff67d9f36b67 | 437 | |
| <> | 157:ff67d9f36b67 | 438 | |
| <> | 157:ff67d9f36b67 | 439 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 440 | /* CRC-16/CRC-32 Engine */ |
| <> | 157:ff67d9f36b67 | 441 | |
| <> | 157:ff67d9f36b67 | 442 | #define MXC_BASE_CRC ((uint32_t)0x40006000UL) |
| <> | 157:ff67d9f36b67 | 443 | #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC) |
| <> | 157:ff67d9f36b67 | 444 | #define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL) |
| <> | 157:ff67d9f36b67 | 445 | #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) |
| <> | 157:ff67d9f36b67 | 446 | |
| <> | 157:ff67d9f36b67 | 447 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 448 | /* Pseudo-random number generator (PRNG) */ |
| <> | 157:ff67d9f36b67 | 449 | |
| <> | 157:ff67d9f36b67 | 450 | #define MXC_BASE_PRNG ((uint32_t)0x40007000UL) |
| <> | 157:ff67d9f36b67 | 451 | #define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG) |
| <> | 157:ff67d9f36b67 | 452 | |
| <> | 157:ff67d9f36b67 | 453 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 454 | /* AES Cryptographic Engine */ |
| <> | 157:ff67d9f36b67 | 455 | |
| <> | 157:ff67d9f36b67 | 456 | #define MXC_BASE_AES ((uint32_t)0x40007400UL) |
| <> | 157:ff67d9f36b67 | 457 | #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) |
| <> | 157:ff67d9f36b67 | 458 | #define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL) |
| <> | 157:ff67d9f36b67 | 459 | #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) |
| <> | 157:ff67d9f36b67 | 460 | |
| <> | 157:ff67d9f36b67 | 461 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 462 | /* MAA Cryptographic Engine */ |
| <> | 157:ff67d9f36b67 | 463 | |
| <> | 157:ff67d9f36b67 | 464 | #define MXC_BASE_MAA ((uint32_t)0x40007800UL) |
| <> | 157:ff67d9f36b67 | 465 | #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) |
| <> | 157:ff67d9f36b67 | 466 | #define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL) |
| <> | 157:ff67d9f36b67 | 467 | #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) |
| <> | 157:ff67d9f36b67 | 468 | |
| <> | 157:ff67d9f36b67 | 469 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 470 | /* Trust Protection Unit (TPU) */ |
| <> | 157:ff67d9f36b67 | 471 | |
| <> | 157:ff67d9f36b67 | 472 | #define MXC_BASE_TPU ((uint32_t)0x40007000UL) |
| <> | 157:ff67d9f36b67 | 473 | #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) |
| <> | 157:ff67d9f36b67 | 474 | #define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL) |
| <> | 157:ff67d9f36b67 | 475 | #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) |
| <> | 157:ff67d9f36b67 | 476 | /**@} end of ingroup product_name*/ |
| <> | 157:ff67d9f36b67 | 477 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 478 | /* Watchdog Timers */ |
| <> | 157:ff67d9f36b67 | 479 | /** |
| <> | 157:ff67d9f36b67 | 480 | * @ingroup wdt_registers |
| <> | 157:ff67d9f36b67 | 481 | * @{ |
| <> | 157:ff67d9f36b67 | 482 | */ |
| <> | 157:ff67d9f36b67 | 483 | #define MXC_CFG_WDT_INSTANCES (2) /**< Define for the number of timers on the \MXIM_Device */ |
| <> | 157:ff67d9f36b67 | 484 | |
| <> | 157:ff67d9f36b67 | 485 | #define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) /**< Base Peripheral Address for WDT 0 */ |
| <> | 157:ff67d9f36b67 | 486 | #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT0 Registers. */ |
| <> | 157:ff67d9f36b67 | 487 | #define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) /**< Base Peripheral Address for WDT 1 */ |
| <> | 157:ff67d9f36b67 | 488 | #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT1 Registers. */ |
| <> | 157:ff67d9f36b67 | 489 | /** |
| <> | 157:ff67d9f36b67 | 490 | * Macro that returns the WDT[i] IRQ, where i=0 to i < #MXC_CFG_WDT_INSTANCES. |
| <> | 157:ff67d9f36b67 | 491 | */ |
| <> | 157:ff67d9f36b67 | 492 | #define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 493 | (i) == 1 ? WDT1_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 494 | |
| <> | 157:ff67d9f36b67 | 495 | #define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \ |
| <> | 157:ff67d9f36b67 | 496 | (i) == 1 ? WDT1_P_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 497 | /** |
| <> | 157:ff67d9f36b67 | 498 | * Macro to return the base address for a requested Watchdog Timer index number. |
| <> | 157:ff67d9f36b67 | 499 | * @p i WDT instance number. |
| <> | 157:ff67d9f36b67 | 500 | * @p returns the base peripheral address for the requested Watchdog Timer instance. |
| <> | 157:ff67d9f36b67 | 501 | */ |
| <> | 157:ff67d9f36b67 | 502 | #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ |
| <> | 157:ff67d9f36b67 | 503 | (i) == 1 ? MXC_BASE_WDT1 : 0) |
| <> | 157:ff67d9f36b67 | 504 | /** |
| <> | 157:ff67d9f36b67 | 505 | * Macro to return a pointer to the #mxc_tmr_regs_t object for the requested Watchdog Timer. |
| <> | 157:ff67d9f36b67 | 506 | * @p i Watchdog Timer instance number. |
| <> | 157:ff67d9f36b67 | 507 | * @p returns a pointer to a #mxc_wdt_regs_t for the requested WDT number. |
| <> | 157:ff67d9f36b67 | 508 | */ |
| <> | 157:ff67d9f36b67 | 509 | #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ |
| <> | 157:ff67d9f36b67 | 510 | (i) == 1 ? MXC_WDT1 : 0) |
| <> | 157:ff67d9f36b67 | 511 | /** |
| <> | 157:ff67d9f36b67 | 512 | * Macro to return the index number for a given #mxc_wdt_regs_t structure. |
| <> | 157:ff67d9f36b67 | 513 | * @p p pointer to a #mxc_wdt_regs_t structure. |
| <> | 157:ff67d9f36b67 | 514 | * @p returns a watchdog timer instance number. |
| <> | 157:ff67d9f36b67 | 515 | */ |
| <> | 157:ff67d9f36b67 | 516 | #define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \ |
| <> | 157:ff67d9f36b67 | 517 | (i) == MXC_WDT1 ? 1: -1) |
| <> | 157:ff67d9f36b67 | 518 | |
| <> | 157:ff67d9f36b67 | 519 | /**@} end of ingroup wdt_registers */ |
| <> | 157:ff67d9f36b67 | 520 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 521 | /* Always-On Watchdog Timer */ |
| <> | 157:ff67d9f36b67 | 522 | /** |
| <> | 157:ff67d9f36b67 | 523 | * @ingroup wdt2_registers |
| <> | 157:ff67d9f36b67 | 524 | * @{ |
| <> | 157:ff67d9f36b67 | 525 | */ |
| <> | 157:ff67d9f36b67 | 526 | #define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL) /**< Base Peripheral Address for WDT 2 */ |
| <> | 157:ff67d9f36b67 | 527 | #define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2) /**< Pointer to the #mxc_wdt2_regs_t structure representing the WDT2 hardware registers. */ |
| <> | 157:ff67d9f36b67 | 528 | /**@} end of ingroup wdt2_registers */ |
| <> | 157:ff67d9f36b67 | 529 | |
| <> | 157:ff67d9f36b67 | 530 | |
| <> | 157:ff67d9f36b67 | 531 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 532 | /* General Purpose I/O Ports (GPIO) */ |
| <> | 157:ff67d9f36b67 | 533 | /** |
| <> | 157:ff67d9f36b67 | 534 | * @ingroup gpio_registers |
| <> | 157:ff67d9f36b67 | 535 | * @{ |
| <> | 157:ff67d9f36b67 | 536 | */ |
| <> | 157:ff67d9f36b67 | 537 | #define MXC_GPIO_NUM_PORTS (9) /**< Number of GPIO Ports for the \MXIM_Device. */ |
| <> | 157:ff67d9f36b67 | 538 | #define MXC_GPIO_MAX_PINS_PER_PORT (8) /**< Number of port pins per port for the \MXIM_Device */ |
| <> | 157:ff67d9f36b67 | 539 | |
| <> | 157:ff67d9f36b67 | 540 | #define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) /**< GPIO Base Peripheral Offset */ |
| <> | 157:ff67d9f36b67 | 541 | #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) /**< Pointer to the #mxc_gpio_regs_t object representing GPIO Registers. */ |
| <> | 157:ff67d9f36b67 | 542 | /** |
| <> | 157:ff67d9f36b67 | 543 | * Macro that returns the GPIO[i] IRQ, where i=0 to i < #MXC_GPIO_NUM_PORTS. |
| <> | 157:ff67d9f36b67 | 544 | */ |
| <> | 157:ff67d9f36b67 | 545 | #define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 546 | (i) == 1 ? GPIO_P1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 547 | (i) == 2 ? GPIO_P2_IRQn : \ |
| <> | 157:ff67d9f36b67 | 548 | (i) == 3 ? GPIO_P3_IRQn : \ |
| <> | 157:ff67d9f36b67 | 549 | (i) == 4 ? GPIO_P4_IRQn : \ |
| <> | 157:ff67d9f36b67 | 550 | (i) == 5 ? GPIO_P5_IRQn : \ |
| <> | 157:ff67d9f36b67 | 551 | (i) == 6 ? GPIO_P6_IRQn : \ |
| <> | 157:ff67d9f36b67 | 552 | (i) == 7 ? GPIO_P7_IRQn : \ |
| <> | 157:ff67d9f36b67 | 553 | (i) == 8 ? GPIO_P8_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 554 | |
| <> | 157:ff67d9f36b67 | 555 | /**@} end of ingroup gpio_registers */ |
| <> | 157:ff67d9f36b67 | 556 | |
| <> | 157:ff67d9f36b67 | 557 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 558 | /* 16/32 bit Timer/Counters */ |
| <> | 157:ff67d9f36b67 | 559 | /** |
| <> | 157:ff67d9f36b67 | 560 | * @ingroup tmr_registers |
| <> | 157:ff67d9f36b67 | 561 | * @{ |
| <> | 157:ff67d9f36b67 | 562 | */ |
| <> | 157:ff67d9f36b67 | 563 | #define MXC_CFG_TMR_INSTANCES (6) /**< Define for the number of timers on the \MXIM_Device */ |
| <> | 157:ff67d9f36b67 | 564 | #define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) /**< Base Address for Timer 0 */ |
| <> | 157:ff67d9f36b67 | 565 | #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 0 */ |
| <> | 157:ff67d9f36b67 | 566 | #define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) /**< Base Address for Timer 1 */ |
| <> | 157:ff67d9f36b67 | 567 | #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 1 */ |
| <> | 157:ff67d9f36b67 | 568 | #define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) /**< Base Address for Timer 2 */ |
| <> | 157:ff67d9f36b67 | 569 | #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 2 */ |
| <> | 157:ff67d9f36b67 | 570 | #define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) /**< Base Address for Timer 3 */ |
| <> | 157:ff67d9f36b67 | 571 | #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 3 */ |
| <> | 157:ff67d9f36b67 | 572 | #define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) /**< Base Address for Timer 4 */ |
| <> | 157:ff67d9f36b67 | 573 | #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 4 */ |
| <> | 157:ff67d9f36b67 | 574 | #define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) /**< Base Address for Timer 5 */ |
| <> | 157:ff67d9f36b67 | 575 | #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 5 */ |
| <> | 157:ff67d9f36b67 | 576 | |
| <> | 157:ff67d9f36b67 | 577 | /** |
| <> | 157:ff67d9f36b67 | 578 | * Macro that returns an #IRQn_Type for the requested 32-bit timer interrupt. |
| <> | 157:ff67d9f36b67 | 579 | */ |
| <> | 157:ff67d9f36b67 | 580 | #define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 581 | (i) == 1 ? TMR1_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 582 | (i) == 2 ? TMR2_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 583 | (i) == 3 ? TMR3_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 584 | (i) == 4 ? TMR4_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 585 | (i) == 5 ? TMR5_0_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 586 | /** |
| <> | 157:ff67d9f36b67 | 587 | * Macro that returns an IRQn_Type for the requested 16-bit timer interrupt number. |
| <> | 157:ff67d9f36b67 | 588 | */ |
| <> | 157:ff67d9f36b67 | 589 | #define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 590 | (i) == 1 ? TMR1_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 591 | (i) == 2 ? TMR2_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 592 | (i) == 3 ? TMR3_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 593 | (i) == 4 ? TMR4_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 594 | (i) == 5 ? TMR5_0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 595 | (i) == 6 ? TMR0_1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 596 | (i) == 7 ? TMR1_1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 597 | (i) == 8 ? TMR2_1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 598 | (i) == 9 ? TMR3_1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 599 | (i) == 10 ? TMR4_1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 600 | (i) == 11 ? TMR5_1_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 601 | /** |
| <> | 157:ff67d9f36b67 | 602 | * Macro to return the base address for a given Timer index number. |
| <> | 157:ff67d9f36b67 | 603 | * @p i Timer instance number. |
| <> | 157:ff67d9f36b67 | 604 | * @p returns the base peripheral address for the requested timer instance. |
| <> | 157:ff67d9f36b67 | 605 | */ |
| <> | 157:ff67d9f36b67 | 606 | #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ |
| <> | 157:ff67d9f36b67 | 607 | (i) == 1 ? MXC_BASE_TMR1 : \ |
| <> | 157:ff67d9f36b67 | 608 | (i) == 2 ? MXC_BASE_TMR2 : \ |
| <> | 157:ff67d9f36b67 | 609 | (i) == 3 ? MXC_BASE_TMR3 : \ |
| <> | 157:ff67d9f36b67 | 610 | (i) == 4 ? MXC_BASE_TMR4 : \ |
| <> | 157:ff67d9f36b67 | 611 | (i) == 5 ? MXC_BASE_TMR5 : 0) |
| <> | 157:ff67d9f36b67 | 612 | /** |
| <> | 157:ff67d9f36b67 | 613 | * Macro to return a pointer to the #mxc_tmr_regs_t structure for a given Timer Instance. |
| <> | 157:ff67d9f36b67 | 614 | * @p i Timer instance number. |
| <> | 157:ff67d9f36b67 | 615 | * @p returns a pointer to a #mxc_tmr_regs_t for the requested timer number. |
| <> | 157:ff67d9f36b67 | 616 | */ |
| <> | 157:ff67d9f36b67 | 617 | #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ |
| <> | 157:ff67d9f36b67 | 618 | (i) == 1 ? MXC_TMR1 : \ |
| <> | 157:ff67d9f36b67 | 619 | (i) == 2 ? MXC_TMR2 : \ |
| <> | 157:ff67d9f36b67 | 620 | (i) == 3 ? MXC_TMR3 : \ |
| <> | 157:ff67d9f36b67 | 621 | (i) == 4 ? MXC_TMR4 : \ |
| <> | 157:ff67d9f36b67 | 622 | (i) == 5 ? MXC_TMR5 : 0) |
| <> | 157:ff67d9f36b67 | 623 | /** |
| <> | 157:ff67d9f36b67 | 624 | * Macro to return the index number for a given pointer to a #mxc_tmr_regs_t structure. |
| <> | 157:ff67d9f36b67 | 625 | * @p p pointer to a #mxc_tmr_regs_t structure. |
| <> | 157:ff67d9f36b67 | 626 | * @p returns a timer instance number. |
| <> | 157:ff67d9f36b67 | 627 | */ |
| <> | 157:ff67d9f36b67 | 628 | #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ |
| <> | 157:ff67d9f36b67 | 629 | (p) == MXC_TMR1 ? 1 : \ |
| <> | 157:ff67d9f36b67 | 630 | (p) == MXC_TMR2 ? 2 : \ |
| <> | 157:ff67d9f36b67 | 631 | (p) == MXC_TMR3 ? 3 : \ |
| <> | 157:ff67d9f36b67 | 632 | (p) == MXC_TMR4 ? 4 : \ |
| <> | 157:ff67d9f36b67 | 633 | (p) == MXC_TMR5 ? 5 : -1) |
| <> | 157:ff67d9f36b67 | 634 | |
| <> | 157:ff67d9f36b67 | 635 | /**@} end of ingroup tmr_registers */ |
| <> | 157:ff67d9f36b67 | 636 | |
| <> | 157:ff67d9f36b67 | 637 | /** |
| <> | 157:ff67d9f36b67 | 638 | * @ingroup product_name |
| <> | 157:ff67d9f36b67 | 639 | * @{ |
| <> | 157:ff67d9f36b67 | 640 | */ |
| <> | 157:ff67d9f36b67 | 641 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 642 | /* Pulse Train Generation */ |
| <> | 157:ff67d9f36b67 | 643 | #define MXC_CFG_PT_INSTANCES (16) |
| <> | 157:ff67d9f36b67 | 644 | |
| <> | 157:ff67d9f36b67 | 645 | #define MXC_BASE_PTG ((uint32_t)0x40011000UL) |
| <> | 157:ff67d9f36b67 | 646 | #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) |
| <> | 157:ff67d9f36b67 | 647 | #define MXC_BASE_PT0 ((uint32_t)0x40011020UL) |
| <> | 157:ff67d9f36b67 | 648 | #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) |
| <> | 157:ff67d9f36b67 | 649 | #define MXC_BASE_PT1 ((uint32_t)0x40011040UL) |
| <> | 157:ff67d9f36b67 | 650 | #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) |
| <> | 157:ff67d9f36b67 | 651 | #define MXC_BASE_PT2 ((uint32_t)0x40011060UL) |
| <> | 157:ff67d9f36b67 | 652 | #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) |
| <> | 157:ff67d9f36b67 | 653 | #define MXC_BASE_PT3 ((uint32_t)0x40011080UL) |
| <> | 157:ff67d9f36b67 | 654 | #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) |
| <> | 157:ff67d9f36b67 | 655 | #define MXC_BASE_PT4 ((uint32_t)0x400110A0UL) |
| <> | 157:ff67d9f36b67 | 656 | #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) |
| <> | 157:ff67d9f36b67 | 657 | #define MXC_BASE_PT5 ((uint32_t)0x400110C0UL) |
| <> | 157:ff67d9f36b67 | 658 | #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) |
| <> | 157:ff67d9f36b67 | 659 | #define MXC_BASE_PT6 ((uint32_t)0x400110E0UL) |
| <> | 157:ff67d9f36b67 | 660 | #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) |
| <> | 157:ff67d9f36b67 | 661 | #define MXC_BASE_PT7 ((uint32_t)0x40011100UL) |
| <> | 157:ff67d9f36b67 | 662 | #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) |
| <> | 157:ff67d9f36b67 | 663 | #define MXC_BASE_PT8 ((uint32_t)0x40011120UL) |
| <> | 157:ff67d9f36b67 | 664 | #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8) |
| <> | 157:ff67d9f36b67 | 665 | #define MXC_BASE_PT9 ((uint32_t)0x40011140UL) |
| <> | 157:ff67d9f36b67 | 666 | #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9) |
| <> | 157:ff67d9f36b67 | 667 | #define MXC_BASE_PT10 ((uint32_t)0x40011160UL) |
| <> | 157:ff67d9f36b67 | 668 | #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10) |
| <> | 157:ff67d9f36b67 | 669 | #define MXC_BASE_PT11 ((uint32_t)0x40011180UL) |
| <> | 157:ff67d9f36b67 | 670 | #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11) |
| <> | 157:ff67d9f36b67 | 671 | #define MXC_BASE_PT12 ((uint32_t)0x400111A0UL) |
| <> | 157:ff67d9f36b67 | 672 | #define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12) |
| <> | 157:ff67d9f36b67 | 673 | #define MXC_BASE_PT13 ((uint32_t)0x400111C0UL) |
| <> | 157:ff67d9f36b67 | 674 | #define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13) |
| <> | 157:ff67d9f36b67 | 675 | #define MXC_BASE_PT14 ((uint32_t)0x400111E0UL) |
| <> | 157:ff67d9f36b67 | 676 | #define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14) |
| <> | 157:ff67d9f36b67 | 677 | #define MXC_BASE_PT15 ((uint32_t)0x40011200UL) |
| <> | 157:ff67d9f36b67 | 678 | #define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15) |
| <> | 157:ff67d9f36b67 | 679 | |
| <> | 157:ff67d9f36b67 | 680 | #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \ |
| <> | 157:ff67d9f36b67 | 681 | (i) == 1 ? MXC_BASE_PT1 : \ |
| <> | 157:ff67d9f36b67 | 682 | (i) == 2 ? MXC_BASE_PT2 : \ |
| <> | 157:ff67d9f36b67 | 683 | (i) == 3 ? MXC_BASE_PT3 : \ |
| <> | 157:ff67d9f36b67 | 684 | (i) == 4 ? MXC_BASE_PT4 : \ |
| <> | 157:ff67d9f36b67 | 685 | (i) == 5 ? MXC_BASE_PT5 : \ |
| <> | 157:ff67d9f36b67 | 686 | (i) == 6 ? MXC_BASE_PT6 : \ |
| <> | 157:ff67d9f36b67 | 687 | (i) == 7 ? MXC_BASE_PT7 : \ |
| <> | 157:ff67d9f36b67 | 688 | (i) == 8 ? MXC_BASE_PT8 : \ |
| <> | 157:ff67d9f36b67 | 689 | (i) == 9 ? MXC_BASE_PT9 : \ |
| <> | 157:ff67d9f36b67 | 690 | (i) == 10 ? MXC_BASE_PT10 : \ |
| <> | 157:ff67d9f36b67 | 691 | (i) == 11 ? MXC_BASE_PT11 : \ |
| <> | 157:ff67d9f36b67 | 692 | (i) == 12 ? MXC_BASE_PT12 : \ |
| <> | 157:ff67d9f36b67 | 693 | (i) == 13 ? MXC_BASE_PT13 : \ |
| <> | 157:ff67d9f36b67 | 694 | (i) == 14 ? MXC_BASE_PT14 : \ |
| <> | 157:ff67d9f36b67 | 695 | (i) == 15 ? MXC_BASE_PT15 : 0) |
| <> | 157:ff67d9f36b67 | 696 | |
| <> | 157:ff67d9f36b67 | 697 | #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \ |
| <> | 157:ff67d9f36b67 | 698 | (i) == 1 ? MXC_PT1 : \ |
| <> | 157:ff67d9f36b67 | 699 | (i) == 2 ? MXC_PT2 : \ |
| <> | 157:ff67d9f36b67 | 700 | (i) == 3 ? MXC_PT3 : \ |
| <> | 157:ff67d9f36b67 | 701 | (i) == 4 ? MXC_PT4 : \ |
| <> | 157:ff67d9f36b67 | 702 | (i) == 5 ? MXC_PT5 : \ |
| <> | 157:ff67d9f36b67 | 703 | (i) == 6 ? MXC_PT6 : \ |
| <> | 157:ff67d9f36b67 | 704 | (i) == 7 ? MXC_PT7 : \ |
| <> | 157:ff67d9f36b67 | 705 | (i) == 8 ? MXC_PT8 : \ |
| <> | 157:ff67d9f36b67 | 706 | (i) == 9 ? MXC_PT9 : \ |
| <> | 157:ff67d9f36b67 | 707 | (i) == 10 ? MXC_PT10 : \ |
| <> | 157:ff67d9f36b67 | 708 | (i) == 11 ? MXC_PT11 : \ |
| <> | 157:ff67d9f36b67 | 709 | (i) == 12 ? MXC_PT12 : \ |
| <> | 157:ff67d9f36b67 | 710 | (i) == 13 ? MXC_PT13 : \ |
| <> | 157:ff67d9f36b67 | 711 | (i) == 14 ? MXC_PT14 : \ |
| <> | 157:ff67d9f36b67 | 712 | (i) == 15 ? MXC_PT15 : 0) |
| <> | 157:ff67d9f36b67 | 713 | |
| <> | 157:ff67d9f36b67 | 714 | #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \ |
| <> | 157:ff67d9f36b67 | 715 | (p) == MXC_PT1 ? 1 : \ |
| <> | 157:ff67d9f36b67 | 716 | (p) == MXC_PT2 ? 2 : \ |
| <> | 157:ff67d9f36b67 | 717 | (p) == MXC_PT3 ? 3 : \ |
| <> | 157:ff67d9f36b67 | 718 | (p) == MXC_PT4 ? 4 : \ |
| <> | 157:ff67d9f36b67 | 719 | (p) == MXC_PT5 ? 5 : \ |
| <> | 157:ff67d9f36b67 | 720 | (p) == MXC_PT6 ? 6 : \ |
| <> | 157:ff67d9f36b67 | 721 | (p) == MXC_PT7 ? 7 : \ |
| <> | 157:ff67d9f36b67 | 722 | (p) == MXC_PT8 ? 8 : \ |
| <> | 157:ff67d9f36b67 | 723 | (p) == MXC_PT9 ? 9 : \ |
| <> | 157:ff67d9f36b67 | 724 | (p) == MXC_PT10 ? 10 : \ |
| <> | 157:ff67d9f36b67 | 725 | (p) == MXC_PT11 ? 11 : \ |
| <> | 157:ff67d9f36b67 | 726 | (p) == MXC_PT12 ? 12 : \ |
| <> | 157:ff67d9f36b67 | 727 | (p) == MXC_PT13 ? 13 : \ |
| <> | 157:ff67d9f36b67 | 728 | (p) == MXC_PT14 ? 14 : \ |
| <> | 157:ff67d9f36b67 | 729 | (p) == MXC_PT15 ? 15 : -1) |
| <> | 157:ff67d9f36b67 | 730 | |
| <> | 157:ff67d9f36b67 | 731 | |
| <> | 157:ff67d9f36b67 | 732 | |
| <> | 157:ff67d9f36b67 | 733 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 734 | /* UART / Serial Port Interface */ |
| <> | 157:ff67d9f36b67 | 735 | |
| <> | 157:ff67d9f36b67 | 736 | #define MXC_CFG_UART_INSTANCES (4) |
| <> | 157:ff67d9f36b67 | 737 | #define MXC_UART_FIFO_DEPTH (32) |
| <> | 157:ff67d9f36b67 | 738 | |
| <> | 157:ff67d9f36b67 | 739 | #define MXC_BASE_UART0 ((uint32_t)0x40012000UL) |
| <> | 157:ff67d9f36b67 | 740 | #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) |
| <> | 157:ff67d9f36b67 | 741 | #define MXC_BASE_UART1 ((uint32_t)0x40013000UL) |
| <> | 157:ff67d9f36b67 | 742 | #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) /**< UART Port 1 Base Address */ |
| <> | 157:ff67d9f36b67 | 743 | #define MXC_BASE_UART2 ((uint32_t)0x40014000UL) |
| <> | 157:ff67d9f36b67 | 744 | #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) |
| <> | 157:ff67d9f36b67 | 745 | #define MXC_BASE_UART3 ((uint32_t)0x40015000UL) |
| <> | 157:ff67d9f36b67 | 746 | #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) |
| <> | 157:ff67d9f36b67 | 747 | #define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL) |
| <> | 157:ff67d9f36b67 | 748 | #define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO) |
| <> | 157:ff67d9f36b67 | 749 | #define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL) |
| <> | 157:ff67d9f36b67 | 750 | #define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO) |
| <> | 157:ff67d9f36b67 | 751 | #define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL) |
| <> | 157:ff67d9f36b67 | 752 | #define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO) |
| <> | 157:ff67d9f36b67 | 753 | #define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL) |
| <> | 157:ff67d9f36b67 | 754 | #define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO) |
| <> | 157:ff67d9f36b67 | 755 | |
| <> | 157:ff67d9f36b67 | 756 | #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 757 | (i) == 1 ? UART1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 758 | (i) == 2 ? UART2_IRQn : \ |
| <> | 157:ff67d9f36b67 | 759 | (i) == 3 ? UART3_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 760 | |
| <> | 157:ff67d9f36b67 | 761 | #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ |
| <> | 157:ff67d9f36b67 | 762 | (i) == 1 ? MXC_BASE_UART1 : \ |
| <> | 157:ff67d9f36b67 | 763 | (i) == 2 ? MXC_BASE_UART2 : \ |
| <> | 157:ff67d9f36b67 | 764 | (i) == 3 ? MXC_BASE_UART3 : 0) |
| <> | 157:ff67d9f36b67 | 765 | |
| <> | 157:ff67d9f36b67 | 766 | #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ |
| <> | 157:ff67d9f36b67 | 767 | (i) == 1 ? MXC_UART1 : \ |
| <> | 157:ff67d9f36b67 | 768 | (i) == 2 ? MXC_UART2 : \ |
| <> | 157:ff67d9f36b67 | 769 | (i) == 3 ? MXC_UART3 : 0) |
| <> | 157:ff67d9f36b67 | 770 | |
| <> | 157:ff67d9f36b67 | 771 | #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ |
| <> | 157:ff67d9f36b67 | 772 | (p) == MXC_UART1 ? 1 : \ |
| <> | 157:ff67d9f36b67 | 773 | (p) == MXC_UART2 ? 2 : \ |
| <> | 157:ff67d9f36b67 | 774 | (p) == MXC_UART3 ? 3 : -1) |
| <> | 157:ff67d9f36b67 | 775 | |
| <> | 157:ff67d9f36b67 | 776 | #define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \ |
| <> | 157:ff67d9f36b67 | 777 | (i) == 1 ? MXC_BASE_UART1_FIFO : \ |
| <> | 157:ff67d9f36b67 | 778 | (i) == 2 ? MXC_BASE_UART2_FIFO : \ |
| <> | 157:ff67d9f36b67 | 779 | (i) == 3 ? MXC_BASE_UART3_FIFO : 0) |
| <> | 157:ff67d9f36b67 | 780 | |
| <> | 157:ff67d9f36b67 | 781 | #define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \ |
| <> | 157:ff67d9f36b67 | 782 | (i) == 1 ? MXC_UART1_FIFO : \ |
| <> | 157:ff67d9f36b67 | 783 | (i) == 2 ? MXC_UART2_FIFO : \ |
| <> | 157:ff67d9f36b67 | 784 | (i) == 3 ? MXC_UART3_FIFO : 0) |
| <> | 157:ff67d9f36b67 | 785 | |
| <> | 157:ff67d9f36b67 | 786 | |
| <> | 157:ff67d9f36b67 | 787 | |
| <> | 157:ff67d9f36b67 | 788 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 789 | /* I2C Master Interface */ |
| <> | 157:ff67d9f36b67 | 790 | |
| <> | 157:ff67d9f36b67 | 791 | #define MXC_CFG_I2CM_INSTANCES (3) |
| <> | 157:ff67d9f36b67 | 792 | #define MXC_I2CM_FIFO_DEPTH (8) |
| <> | 157:ff67d9f36b67 | 793 | |
| <> | 157:ff67d9f36b67 | 794 | #define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL) |
| <> | 157:ff67d9f36b67 | 795 | #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) |
| <> | 157:ff67d9f36b67 | 796 | #define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL) |
| <> | 157:ff67d9f36b67 | 797 | #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) |
| <> | 157:ff67d9f36b67 | 798 | #define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL) |
| <> | 157:ff67d9f36b67 | 799 | #define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2) |
| <> | 157:ff67d9f36b67 | 800 | #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL) |
| <> | 157:ff67d9f36b67 | 801 | #define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO) |
| <> | 157:ff67d9f36b67 | 802 | #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL) |
| <> | 157:ff67d9f36b67 | 803 | #define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO) |
| <> | 157:ff67d9f36b67 | 804 | #define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL) |
| <> | 157:ff67d9f36b67 | 805 | #define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO) |
| <> | 157:ff67d9f36b67 | 806 | |
| <> | 157:ff67d9f36b67 | 807 | #define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 808 | (i) == 1 ? I2CM1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 809 | (i) == 2 ? I2CM2_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 810 | |
| <> | 157:ff67d9f36b67 | 811 | #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ |
| <> | 157:ff67d9f36b67 | 812 | (i) == 1 ? MXC_BASE_I2CM1 : \ |
| <> | 157:ff67d9f36b67 | 813 | (i) == 2 ? MXC_BASE_I2CM2 : 0) |
| <> | 157:ff67d9f36b67 | 814 | |
| <> | 157:ff67d9f36b67 | 815 | #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ |
| <> | 157:ff67d9f36b67 | 816 | (i) == 1 ? MXC_I2CM1 : \ |
| <> | 157:ff67d9f36b67 | 817 | (i) == 2 ? MXC_I2CM2 : 0) |
| <> | 157:ff67d9f36b67 | 818 | |
| <> | 157:ff67d9f36b67 | 819 | #define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \ |
| <> | 157:ff67d9f36b67 | 820 | (p) == MXC_I2CM1 ? 1 : \ |
| <> | 157:ff67d9f36b67 | 821 | (p) == MXC_I2CM2 ? 2 : -1) |
| <> | 157:ff67d9f36b67 | 822 | |
| <> | 157:ff67d9f36b67 | 823 | #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \ |
| <> | 157:ff67d9f36b67 | 824 | (i) == 1 ? MXC_BASE_I2CM1_FIFO : \ |
| <> | 157:ff67d9f36b67 | 825 | (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0) |
| <> | 157:ff67d9f36b67 | 826 | |
| <> | 157:ff67d9f36b67 | 827 | #define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \ |
| <> | 157:ff67d9f36b67 | 828 | (i) == 1 ? MXC_I2CM1_FIFO : \ |
| <> | 157:ff67d9f36b67 | 829 | (i) == 2 ? MXC_I2CM2_FIFO : 0) |
| <> | 157:ff67d9f36b67 | 830 | |
| <> | 157:ff67d9f36b67 | 831 | |
| <> | 157:ff67d9f36b67 | 832 | |
| <> | 157:ff67d9f36b67 | 833 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 834 | /* I2C Slave Interface (Mailbox type) */ |
| <> | 157:ff67d9f36b67 | 835 | |
| <> | 157:ff67d9f36b67 | 836 | #define MXC_CFG_I2CS_INSTANCES (1) |
| <> | 157:ff67d9f36b67 | 837 | #define MXC_CFG_I2CS_BUFFER_SIZE (32) |
| <> | 157:ff67d9f36b67 | 838 | |
| <> | 157:ff67d9f36b67 | 839 | #define MXC_BASE_I2CS ((uint32_t)0x40019000UL) |
| <> | 157:ff67d9f36b67 | 840 | #define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS) |
| <> | 157:ff67d9f36b67 | 841 | |
| <> | 157:ff67d9f36b67 | 842 | #define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 843 | |
| <> | 157:ff67d9f36b67 | 844 | #define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0) |
| <> | 157:ff67d9f36b67 | 845 | |
| <> | 157:ff67d9f36b67 | 846 | #define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0) |
| <> | 157:ff67d9f36b67 | 847 | |
| <> | 157:ff67d9f36b67 | 848 | #define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1) |
| <> | 157:ff67d9f36b67 | 849 | |
| <> | 157:ff67d9f36b67 | 850 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 851 | /* SPI Master Interface */ |
| <> | 157:ff67d9f36b67 | 852 | |
| <> | 157:ff67d9f36b67 | 853 | #define MXC_CFG_SPIM_INSTANCES (3) |
| <> | 157:ff67d9f36b67 | 854 | #define MXC_CFG_SPIM_FIFO_DEPTH (16) |
| <> | 157:ff67d9f36b67 | 855 | |
| <> | 157:ff67d9f36b67 | 856 | #define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL) |
| <> | 157:ff67d9f36b67 | 857 | #define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0) |
| <> | 157:ff67d9f36b67 | 858 | #define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL) |
| <> | 157:ff67d9f36b67 | 859 | #define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1) |
| <> | 157:ff67d9f36b67 | 860 | #define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL) |
| <> | 157:ff67d9f36b67 | 861 | #define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2) |
| <> | 157:ff67d9f36b67 | 862 | #define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL) |
| <> | 157:ff67d9f36b67 | 863 | #define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO) |
| <> | 157:ff67d9f36b67 | 864 | #define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL) |
| <> | 157:ff67d9f36b67 | 865 | #define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO) |
| <> | 157:ff67d9f36b67 | 866 | #define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL) |
| <> | 157:ff67d9f36b67 | 867 | #define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO) |
| <> | 157:ff67d9f36b67 | 868 | |
| <> | 157:ff67d9f36b67 | 869 | #define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \ |
| <> | 157:ff67d9f36b67 | 870 | (i) == 1 ? SPIM1_IRQn : \ |
| <> | 157:ff67d9f36b67 | 871 | (i) == 2 ? SPIM2_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 872 | |
| <> | 157:ff67d9f36b67 | 873 | #define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \ |
| <> | 157:ff67d9f36b67 | 874 | (i) == 1 ? MXC_BASE_SPIM1 : \ |
| <> | 157:ff67d9f36b67 | 875 | (i) == 2 ? MXC_BASE_SPIM2 : 0) |
| <> | 157:ff67d9f36b67 | 876 | |
| <> | 157:ff67d9f36b67 | 877 | #define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \ |
| <> | 157:ff67d9f36b67 | 878 | (i) == 1 ? MXC_SPIM1 : \ |
| <> | 157:ff67d9f36b67 | 879 | (i) == 2 ? MXC_SPIM2 : 0) |
| <> | 157:ff67d9f36b67 | 880 | |
| <> | 157:ff67d9f36b67 | 881 | #define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \ |
| <> | 157:ff67d9f36b67 | 882 | (p) == MXC_SPIM1 ? 1 : \ |
| <> | 157:ff67d9f36b67 | 883 | (p) == MXC_SPIM2 ? 2 : -1) |
| <> | 157:ff67d9f36b67 | 884 | |
| <> | 157:ff67d9f36b67 | 885 | #define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \ |
| <> | 157:ff67d9f36b67 | 886 | (i) == 1 ? MXC_BASE_SPIM1_FIFO : \ |
| <> | 157:ff67d9f36b67 | 887 | (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0) |
| <> | 157:ff67d9f36b67 | 888 | |
| <> | 157:ff67d9f36b67 | 889 | #define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \ |
| <> | 157:ff67d9f36b67 | 890 | (i) == 1 ? MXC_SPIM1_FIFO : \ |
| <> | 157:ff67d9f36b67 | 891 | (i) == 2 ? MXC_SPIM2_FIFO : 0) |
| <> | 157:ff67d9f36b67 | 892 | |
| <> | 157:ff67d9f36b67 | 893 | |
| <> | 157:ff67d9f36b67 | 894 | |
| <> | 157:ff67d9f36b67 | 895 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 896 | /* 1-Wire Master Interface */ |
| <> | 157:ff67d9f36b67 | 897 | |
| <> | 157:ff67d9f36b67 | 898 | #define MXC_CFG_OWM_INSTANCES (1) |
| <> | 157:ff67d9f36b67 | 899 | |
| <> | 157:ff67d9f36b67 | 900 | #define MXC_BASE_OWM ((uint32_t)0x4001E000UL) |
| <> | 157:ff67d9f36b67 | 901 | #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) |
| <> | 157:ff67d9f36b67 | 902 | |
| <> | 157:ff67d9f36b67 | 903 | #define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0) |
| <> | 157:ff67d9f36b67 | 904 | |
| <> | 157:ff67d9f36b67 | 905 | #define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0) |
| <> | 157:ff67d9f36b67 | 906 | |
| <> | 157:ff67d9f36b67 | 907 | #define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0) |
| <> | 157:ff67d9f36b67 | 908 | |
| <> | 157:ff67d9f36b67 | 909 | #define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1) |
| <> | 157:ff67d9f36b67 | 910 | |
| <> | 157:ff67d9f36b67 | 911 | |
| <> | 157:ff67d9f36b67 | 912 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 913 | /* ADC / AFE */ |
| <> | 157:ff67d9f36b67 | 914 | |
| <> | 157:ff67d9f36b67 | 915 | #define MXC_CFG_ADC_FIFO_DEPTH (32) |
| <> | 157:ff67d9f36b67 | 916 | |
| <> | 157:ff67d9f36b67 | 917 | #define MXC_BASE_ADC ((uint32_t)0x4001F000UL) |
| <> | 157:ff67d9f36b67 | 918 | #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) |
| <> | 157:ff67d9f36b67 | 919 | |
| <> | 157:ff67d9f36b67 | 920 | |
| <> | 157:ff67d9f36b67 | 921 | |
| <> | 157:ff67d9f36b67 | 922 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 923 | /* SPIB AHB-to-SPI Bridge */ |
| <> | 157:ff67d9f36b67 | 924 | |
| <> | 157:ff67d9f36b67 | 925 | #define MXC_BASE_SPIB ((uint32_t)0x4000D000UL) |
| <> | 157:ff67d9f36b67 | 926 | #define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB) |
| <> | 157:ff67d9f36b67 | 927 | |
| <> | 157:ff67d9f36b67 | 928 | |
| <> | 157:ff67d9f36b67 | 929 | |
| <> | 157:ff67d9f36b67 | 930 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 931 | /* SPI Slave Interface */ |
| <> | 157:ff67d9f36b67 | 932 | |
| <> | 157:ff67d9f36b67 | 933 | #define MXC_BASE_SPIS ((uint32_t)0x40020000UL) |
| <> | 157:ff67d9f36b67 | 934 | #define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS) |
| <> | 157:ff67d9f36b67 | 935 | #define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL) |
| <> | 157:ff67d9f36b67 | 936 | #define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO) |
| <> | 157:ff67d9f36b67 | 937 | |
| <> | 157:ff67d9f36b67 | 938 | |
| <> | 157:ff67d9f36b67 | 939 | |
| <> | 157:ff67d9f36b67 | 940 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 941 | /* Bit Shifting */ |
| <> | 157:ff67d9f36b67 | 942 | |
| <> | 157:ff67d9f36b67 | 943 | #define MXC_F_BIT_0 (1 << 0) |
| <> | 157:ff67d9f36b67 | 944 | #define MXC_F_BIT_1 (1 << 1) |
| <> | 157:ff67d9f36b67 | 945 | #define MXC_F_BIT_2 (1 << 2) |
| <> | 157:ff67d9f36b67 | 946 | #define MXC_F_BIT_3 (1 << 3) |
| <> | 157:ff67d9f36b67 | 947 | #define MXC_F_BIT_4 (1 << 4) |
| <> | 157:ff67d9f36b67 | 948 | #define MXC_F_BIT_5 (1 << 5) |
| <> | 157:ff67d9f36b67 | 949 | #define MXC_F_BIT_6 (1 << 6) |
| <> | 157:ff67d9f36b67 | 950 | #define MXC_F_BIT_7 (1 << 7) |
| <> | 157:ff67d9f36b67 | 951 | #define MXC_F_BIT_8 (1 << 8) |
| <> | 157:ff67d9f36b67 | 952 | #define MXC_F_BIT_9 (1 << 9) |
| <> | 157:ff67d9f36b67 | 953 | #define MXC_F_BIT_10 (1 << 10) |
| <> | 157:ff67d9f36b67 | 954 | #define MXC_F_BIT_11 (1 << 11) |
| <> | 157:ff67d9f36b67 | 955 | #define MXC_F_BIT_12 (1 << 12) |
| <> | 157:ff67d9f36b67 | 956 | #define MXC_F_BIT_13 (1 << 13) |
| <> | 157:ff67d9f36b67 | 957 | #define MXC_F_BIT_14 (1 << 14) |
| <> | 157:ff67d9f36b67 | 958 | #define MXC_F_BIT_15 (1 << 15) |
| <> | 157:ff67d9f36b67 | 959 | #define MXC_F_BIT_16 (1 << 16) |
| <> | 157:ff67d9f36b67 | 960 | #define MXC_F_BIT_17 (1 << 17) |
| <> | 157:ff67d9f36b67 | 961 | #define MXC_F_BIT_18 (1 << 18) |
| <> | 157:ff67d9f36b67 | 962 | #define MXC_F_BIT_19 (1 << 19) |
| <> | 157:ff67d9f36b67 | 963 | #define MXC_F_BIT_20 (1 << 20) |
| <> | 157:ff67d9f36b67 | 964 | #define MXC_F_BIT_21 (1 << 21) |
| <> | 157:ff67d9f36b67 | 965 | #define MXC_F_BIT_22 (1 << 22) |
| <> | 157:ff67d9f36b67 | 966 | #define MXC_F_BIT_23 (1 << 23) |
| <> | 157:ff67d9f36b67 | 967 | #define MXC_F_BIT_24 (1 << 24) |
| <> | 157:ff67d9f36b67 | 968 | #define MXC_F_BIT_25 (1 << 25) |
| <> | 157:ff67d9f36b67 | 969 | #define MXC_F_BIT_26 (1 << 26) |
| <> | 157:ff67d9f36b67 | 970 | #define MXC_F_BIT_27 (1 << 27) |
| <> | 157:ff67d9f36b67 | 971 | #define MXC_F_BIT_28 (1 << 28) |
| <> | 157:ff67d9f36b67 | 972 | #define MXC_F_BIT_29 (1 << 29) |
| <> | 157:ff67d9f36b67 | 973 | #define MXC_F_BIT_30 (1 << 30) |
| <> | 157:ff67d9f36b67 | 974 | #define MXC_F_BIT_31 (1 << 31) |
| <> | 157:ff67d9f36b67 | 975 | |
| <> | 157:ff67d9f36b67 | 976 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 977 | |
| <> | 157:ff67d9f36b67 | 978 | #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set)) |
| <> | 157:ff67d9f36b67 | 979 | |
| <> | 157:ff67d9f36b67 | 980 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 981 | |
| <> | 157:ff67d9f36b67 | 982 | #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) |
| <> | 157:ff67d9f36b67 | 983 | #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) |
| <> | 157:ff67d9f36b67 | 984 | #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) |
| <> | 157:ff67d9f36b67 | 985 | #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) |
| <> | 157:ff67d9f36b67 | 986 | |
| <> | 157:ff67d9f36b67 | 987 | |
| <> | 157:ff67d9f36b67 | 988 | /* *************************************************************************** */ |
| <> | 157:ff67d9f36b67 | 989 | |
| <> | 157:ff67d9f36b67 | 990 | /* SCB CPACR Register Definitions */ |
| <> | 157:ff67d9f36b67 | 991 | /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ |
| <> | 157:ff67d9f36b67 | 992 | #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ |
| <> | 157:ff67d9f36b67 | 993 | #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ |
| <> | 157:ff67d9f36b67 | 994 | #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ |
| <> | 157:ff67d9f36b67 | 995 | #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ |
| <> | 157:ff67d9f36b67 | 996 | /**@} end of ingroup product_name */ |
| <> | 157:ff67d9f36b67 | 997 | #endif /* _MAX3263X_H_ */ |
| <> | 157:ff67d9f36b67 | 998 |