Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c@165:2dd56e6daeec, 2017-05-23 (annotated)

Committer:
ranaumarnaeem
Date:
Tue May 23 12:54:50 2017 +0000
Revision:
165:2dd56e6daeec
Parent:
157:ff67d9f36b67 
jhjg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /*******************************************************************************
<> 157:ff67d9f36b67 2 * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 3 *
<> 157:ff67d9f36b67 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 5 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 6 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 9 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 10 *
<> 157:ff67d9f36b67 11 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 12 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 13 *
<> 157:ff67d9f36b67 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 21 *
<> 157:ff67d9f36b67 22 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 24 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 28 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 30 * ownership rights.
<> 157:ff67d9f36b67 31 *******************************************************************************
<> 157:ff67d9f36b67 32 */
<> 157:ff67d9f36b67 33
<> 157:ff67d9f36b67 34 #include "device.h"
<> 157:ff67d9f36b67 35 #include "PeripheralPins.h"
<> 157:ff67d9f36b67 36 #include "ioman_regs.h"
<> 157:ff67d9f36b67 37 #include "ioman.h"
<> 157:ff67d9f36b67 38 #include "adc.h"
<> 157:ff67d9f36b67 39
<> 157:ff67d9f36b67 40 /*
<> 157:ff67d9f36b67 41 * To select a peripheral function on Maxim microcontrollers, multiple
<> 157:ff67d9f36b67 42 * configurations must be made. The mbed PinMap structure only includes one
<> 157:ff67d9f36b67 43 * data member to hold this information. To extend the configuration storage,
<> 157:ff67d9f36b67 44 * the "function" data member is used as a pointer to a pin_function_t
<> 157:ff67d9f36b67 45 * structure. This structure is defined in objects.h. The definitions below
<> 157:ff67d9f36b67 46 * include the creation of the pin_function_t structures and the assignment of
<> 157:ff67d9f36b67 47 * the pointers to the "function" data members.
<> 157:ff67d9f36b67 48 */
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 #ifdef TOOLCHAIN_ARM_STD
<> 157:ff67d9f36b67 51 #pragma diag_suppress 1296
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 /************I2C***************/
<> 157:ff67d9f36b67 55 const PinMap PinMap_I2C_SDA[] = {
<> 157:ff67d9f36b67 56 { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
<> 157:ff67d9f36b67 57 { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 58 { P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 59 { P7_1, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 60 { P6_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 61 { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 62 { P7_3, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 63 { NC, NC, 0 }
<> 157:ff67d9f36b67 64 };
<> 157:ff67d9f36b67 65
<> 157:ff67d9f36b67 66 const PinMap PinMap_I2C_SCL[] = {
<> 157:ff67d9f36b67 67 { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
<> 157:ff67d9f36b67 68 { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 69 { P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 70 { P7_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 71 { P7_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 72 { P8_0, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 73 { P7_4, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
<> 157:ff67d9f36b67 74 { NC, NC, 0 }
<> 157:ff67d9f36b67 75 };
<> 157:ff67d9f36b67 76
<> 157:ff67d9f36b67 77 /************UART***************/
<> 157:ff67d9f36b67 78 const PinMap PinMap_UART_TX[] = {
<> 157:ff67d9f36b67 79 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 80 { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 81 { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 82 { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 83 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 84 { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 85 { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 86 { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 87 { NC, NC, 0 }
<> 157:ff67d9f36b67 88 };
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 const PinMap PinMap_UART_RX[] = {
<> 157:ff67d9f36b67 91 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 92 { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 93 { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 94 { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 95 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 96 { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 97 { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 98 { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
<> 157:ff67d9f36b67 99 { NC, NC, 0 }
<> 157:ff67d9f36b67 100 };
<> 157:ff67d9f36b67 101
<> 157:ff67d9f36b67 102 const PinMap PinMap_UART_CTS[] = {
<> 157:ff67d9f36b67 103 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 104 { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 105 { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 106 { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 107 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 108 { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 109 { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 110 { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
<> 157:ff67d9f36b67 111 { NC, NC, 0 }
<> 157:ff67d9f36b67 112 };
<> 157:ff67d9f36b67 113
<> 157:ff67d9f36b67 114 const PinMap PinMap_UART_RTS[] = {
<> 157:ff67d9f36b67 115 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 116 { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 117 { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 118 { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 119 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 120 { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 121 { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 122 { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
<> 157:ff67d9f36b67 123 { NC, NC, 0 }
<> 157:ff67d9f36b67 124 };
<> 157:ff67d9f36b67 125
<> 157:ff67d9f36b67 126 /************SPI***************/
<> 157:ff67d9f36b67 127 const PinMap PinMap_SPI_SCLK[] = {
<> 157:ff67d9f36b67 128 { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
<> 157:ff67d9f36b67 129 { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
<> 157:ff67d9f36b67 130 { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 131 { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 132 { P6_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 133 { NC, NC, 0 }
<> 157:ff67d9f36b67 134 };
<> 157:ff67d9f36b67 135
<> 157:ff67d9f36b67 136 const PinMap PinMap_SPI_MOSI[] = {
<> 157:ff67d9f36b67 137 { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
<> 157:ff67d9f36b67 138 { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
<> 157:ff67d9f36b67 139 { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 140 { P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 141 { P6_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 142 { NC, NC, 0 }
<> 157:ff67d9f36b67 143 };
<> 157:ff67d9f36b67 144
<> 157:ff67d9f36b67 145 const PinMap PinMap_SPI_MISO[] = {
<> 157:ff67d9f36b67 146 { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
<> 157:ff67d9f36b67 147 { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
<> 157:ff67d9f36b67 148 { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 149 { P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 150 { P6_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
<> 157:ff67d9f36b67 151 { NC, NC, 0 }
<> 157:ff67d9f36b67 152 };
<> 157:ff67d9f36b67 153
<> 157:ff67d9f36b67 154 const PinMap PinMap_SPI_SSEL[] = {
<> 157:ff67d9f36b67 155 { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK}) },
<> 157:ff67d9f36b67 156 { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK}) },
<> 157:ff67d9f36b67 157 { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
<> 157:ff67d9f36b67 158 { P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
<> 157:ff67d9f36b67 159 { P6_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
<> 157:ff67d9f36b67 160 { NC, NC, 0 }
<> 157:ff67d9f36b67 161 };
<> 157:ff67d9f36b67 162
<> 157:ff67d9f36b67 163 /************PWM***************/
<> 157:ff67d9f36b67 164 const PinMap PinMap_PWM[] = {
<> 157:ff67d9f36b67 165 { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, { P6_0, PWM_0, 1 }, { P8_0, PWM_0, 1 },
<> 157:ff67d9f36b67 166 { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, { P6_1, PWM_1, 1 }, { P8_1, PWM_1, 1 },
<> 157:ff67d9f36b67 167 { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, { P6_2, PWM_2, 1 },
<> 157:ff67d9f36b67 168 { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, { P6_3, PWM_3, 1 },
<> 157:ff67d9f36b67 169 { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, { P6_4, PWM_4, 1 },
<> 157:ff67d9f36b67 170 { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, { P6_5, PWM_5, 1 },
<> 157:ff67d9f36b67 171 { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, { P6_6, PWM_6, 1 },
<> 157:ff67d9f36b67 172 { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, { P6_7, PWM_7, 1 },
<> 157:ff67d9f36b67 173 { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, { P7_0, PWM_8, 1 },
<> 157:ff67d9f36b67 174 { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, { P7_1, PWM_9, 1 },
<> 157:ff67d9f36b67 175 { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, { P7_2, PWM_10, 1 },
<> 157:ff67d9f36b67 176 { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, { P7_3, PWM_11, 1 },
<> 157:ff67d9f36b67 177 { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, { P7_4, PWM_12, 1 },
<> 157:ff67d9f36b67 178 { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, { P7_5, PWM_13, 1 },
<> 157:ff67d9f36b67 179 { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, { P7_6, PWM_14, 1 },
<> 157:ff67d9f36b67 180 { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, { P7_7, PWM_15, 1 },
<> 157:ff67d9f36b67 181 { NC, NC, 0 }
<> 157:ff67d9f36b67 182 };
<> 157:ff67d9f36b67 183
<> 157:ff67d9f36b67 184 /************ADC***************/
<> 157:ff67d9f36b67 185 const PinMap PinMap_ADC[] = {
<> 157:ff67d9f36b67 186 { AIN_0, ADC, ADC_CH_0 },
<> 157:ff67d9f36b67 187 { AIN_1, ADC, ADC_CH_1 },
<> 157:ff67d9f36b67 188 { AIN_2, ADC, ADC_CH_2 },
<> 157:ff67d9f36b67 189 { AIN_3, ADC, ADC_CH_3 },
<> 157:ff67d9f36b67 190 { AIN_4, ADC, ADC_CH_0_DIV_5 },
<> 157:ff67d9f36b67 191 { AIN_5, ADC, ADC_CH_1_DIV_5 },
<> 157:ff67d9f36b67 192 { AIN_6, ADC, ADC_CH_VDDB_DIV_4 },
<> 157:ff67d9f36b67 193 { AIN_7, ADC, ADC_CH_VDD18 },
<> 157:ff67d9f36b67 194 { AIN_8, ADC, ADC_CH_VDD12 },
<> 157:ff67d9f36b67 195 { AIN_9, ADC, ADC_CH_VRTC_DIV_2 },
<> 157:ff67d9f36b67 196 { NC, NC, 0 }
<> 157:ff67d9f36b67 197 };