Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

cmsis/core_cm0plus.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/core_cm0plus.h@144:ef7eb2e8f9f7
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_cm0plus.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
<> 144:ef7eb2e8f9f7 4 * @version V4.10
<> 144:ef7eb2e8f9f7 5 * @date 18. March 2015
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #if defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 144:ef7eb2e8f9f7 40 #endif
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifndef __CORE_CM0PLUS_H_GENERIC
<> 144:ef7eb2e8f9f7 43 #define __CORE_CM0PLUS_H_GENERIC
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 46 extern "C" {
<> 144:ef7eb2e8f9f7 47 #endif
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 144:ef7eb2e8f9f7 50 CMSIS violates the following MISRA-C:2004 rules:
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 144:ef7eb2e8f9f7 53 Function definitions in header files are used to allow 'inlining'.
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 144:ef7eb2e8f9f7 56 Unions are used for effective representation of core registers.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 144:ef7eb2e8f9f7 59 Function-like macros are used to allow more efficient code.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /*******************************************************************************
<> 144:ef7eb2e8f9f7 64 * CMSIS definitions
<> 144:ef7eb2e8f9f7 65 ******************************************************************************/
<> 144:ef7eb2e8f9f7 66 /** \ingroup Cortex-M0+
<> 144:ef7eb2e8f9f7 67 @{
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* CMSIS CM0P definitions */
<> 144:ef7eb2e8f9f7 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 144:ef7eb2e8f9f7 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 144:ef7eb2e8f9f7 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
<> 144:ef7eb2e8f9f7 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 144:ef7eb2e8f9f7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 144:ef7eb2e8f9f7 82 #define __STATIC_INLINE static __inline
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #elif defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 144:ef7eb2e8f9f7 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 144:ef7eb2e8f9f7 87 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #elif defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 144:ef7eb2e8f9f7 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 144:ef7eb2e8f9f7 92 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #elif defined ( __TMS470__ )
<> 144:ef7eb2e8f9f7 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 144:ef7eb2e8f9f7 96 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #elif defined ( __TASKING__ )
<> 144:ef7eb2e8f9f7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 144:ef7eb2e8f9f7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 144:ef7eb2e8f9f7 101 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #elif defined ( __CSMC__ )
<> 144:ef7eb2e8f9f7 104 #define __packed
<> 144:ef7eb2e8f9f7 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 144:ef7eb2e8f9f7 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 144:ef7eb2e8f9f7 107 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #endif
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 144:ef7eb2e8f9f7 112 This core does not support an FPU at all
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 117 #if defined __TARGET_FPU_VFP
<> 144:ef7eb2e8f9f7 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 119 #endif
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #elif defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 144:ef7eb2e8f9f7 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 124 #endif
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #elif defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 127 #if defined __ARMVFP__
<> 144:ef7eb2e8f9f7 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 129 #endif
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 #elif defined ( __TMS470__ )
<> 144:ef7eb2e8f9f7 132 #if defined __TI__VFP_SUPPORT____
<> 144:ef7eb2e8f9f7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 #elif defined ( __TASKING__ )
<> 144:ef7eb2e8f9f7 137 #if defined __FPU_VFP__
<> 144:ef7eb2e8f9f7 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 139 #endif
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 144:ef7eb2e8f9f7 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 144:ef7eb2e8f9f7 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 144 #endif
<> 144:ef7eb2e8f9f7 145 #endif
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 #include <stdint.h> /* standard types definitions */
<> 144:ef7eb2e8f9f7 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 144:ef7eb2e8f9f7 149 #include <core_cmFunc.h> /* Core Function Access */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153 #endif
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #ifndef __CMSIS_GENERIC
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
<> 144:ef7eb2e8f9f7 160 #define __CORE_CM0PLUS_H_DEPENDANT
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 163 extern "C" {
<> 144:ef7eb2e8f9f7 164 #endif
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* check device defines and use defaults */
<> 144:ef7eb2e8f9f7 167 #if defined __CHECK_DEVICE_DEFINES
<> 144:ef7eb2e8f9f7 168 #ifndef __CM0PLUS_REV
<> 144:ef7eb2e8f9f7 169 #define __CM0PLUS_REV 0x0000
<> 144:ef7eb2e8f9f7 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 171 #endif
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #ifndef __MPU_PRESENT
<> 144:ef7eb2e8f9f7 174 #define __MPU_PRESENT 0
<> 144:ef7eb2e8f9f7 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 #ifndef __VTOR_PRESENT
<> 144:ef7eb2e8f9f7 179 #define __VTOR_PRESENT 0
<> 144:ef7eb2e8f9f7 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 181 #endif
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #ifndef __NVIC_PRIO_BITS
<> 144:ef7eb2e8f9f7 184 #define __NVIC_PRIO_BITS 2
<> 144:ef7eb2e8f9f7 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 186 #endif
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #ifndef __Vendor_SysTickConfig
<> 144:ef7eb2e8f9f7 189 #define __Vendor_SysTickConfig 0
<> 144:ef7eb2e8f9f7 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 191 #endif
<> 144:ef7eb2e8f9f7 192 #endif
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* IO definitions (access restrictions to peripheral registers) */
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 <strong>IO Type Qualifiers</strong> are used
<> 144:ef7eb2e8f9f7 199 \li to specify the access to peripheral variables.
<> 144:ef7eb2e8f9f7 200 \li for automatic generation of peripheral register debug information.
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 203 #define __I volatile /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 204 #else
<> 144:ef7eb2e8f9f7 205 #define __I volatile const /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 206 #endif
<> 144:ef7eb2e8f9f7 207 #define __O volatile /*!< Defines 'write only' permissions */
<> 144:ef7eb2e8f9f7 208 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /*@} end of group Cortex-M0+ */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /*******************************************************************************
<> 144:ef7eb2e8f9f7 215 * Register Abstraction
<> 144:ef7eb2e8f9f7 216 Core Register contain:
<> 144:ef7eb2e8f9f7 217 - Core Register
<> 144:ef7eb2e8f9f7 218 - Core NVIC Register
<> 144:ef7eb2e8f9f7 219 - Core SCB Register
<> 144:ef7eb2e8f9f7 220 - Core SysTick Register
<> 144:ef7eb2e8f9f7 221 - Core MPU Register
<> 144:ef7eb2e8f9f7 222 ******************************************************************************/
<> 144:ef7eb2e8f9f7 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 144:ef7eb2e8f9f7 224 \brief Type definitions and defines for Cortex-M processor based devices.
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 228 \defgroup CMSIS_CORE Status and Control Registers
<> 144:ef7eb2e8f9f7 229 \brief Core Register type definitions.
<> 144:ef7eb2e8f9f7 230 @{
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /** \brief Union type to access the Application Program Status Register (APSR).
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 typedef union
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 struct
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 144:ef7eb2e8f9f7 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 144:ef7eb2e8f9f7 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 144:ef7eb2e8f9f7 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 144:ef7eb2e8f9f7 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 144:ef7eb2e8f9f7 244 } b; /*!< Structure used for bit access */
<> 144:ef7eb2e8f9f7 245 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 246 } APSR_Type;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* APSR Register Definitions */
<> 144:ef7eb2e8f9f7 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 144:ef7eb2e8f9f7 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 144:ef7eb2e8f9f7 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 144:ef7eb2e8f9f7 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 144:ef7eb2e8f9f7 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 typedef union
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 struct
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 144:ef7eb2e8f9f7 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 144:ef7eb2e8f9f7 270 } b; /*!< Structure used for bit access */
<> 144:ef7eb2e8f9f7 271 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 272 } IPSR_Type;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* IPSR Register Definitions */
<> 144:ef7eb2e8f9f7 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 144:ef7eb2e8f9f7 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 typedef union
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 struct
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 144:ef7eb2e8f9f7 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 144:ef7eb2e8f9f7 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 144:ef7eb2e8f9f7 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 144:ef7eb2e8f9f7 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 144:ef7eb2e8f9f7 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 144:ef7eb2e8f9f7 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 144:ef7eb2e8f9f7 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 144:ef7eb2e8f9f7 293 } b; /*!< Structure used for bit access */
<> 144:ef7eb2e8f9f7 294 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 295 } xPSR_Type;
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* xPSR Register Definitions */
<> 144:ef7eb2e8f9f7 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 144:ef7eb2e8f9f7 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 144:ef7eb2e8f9f7 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 144:ef7eb2e8f9f7 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 144:ef7eb2e8f9f7 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 144:ef7eb2e8f9f7 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 144:ef7eb2e8f9f7 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** \brief Union type to access the Control Registers (CONTROL).
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 typedef union
<> 144:ef7eb2e8f9f7 320 {
<> 144:ef7eb2e8f9f7 321 struct
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 144:ef7eb2e8f9f7 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 144:ef7eb2e8f9f7 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 144:ef7eb2e8f9f7 326 } b; /*!< Structure used for bit access */
<> 144:ef7eb2e8f9f7 327 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 328 } CONTROL_Type;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* CONTROL Register Definitions */
<> 144:ef7eb2e8f9f7 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 144:ef7eb2e8f9f7 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 144:ef7eb2e8f9f7 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /*@} end of group CMSIS_CORE */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 144:ef7eb2e8f9f7 342 \brief Type definitions for the NVIC Registers
<> 144:ef7eb2e8f9f7 343 @{
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 typedef struct
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 144:ef7eb2e8f9f7 351 uint32_t RESERVED0[31];
<> 144:ef7eb2e8f9f7 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 144:ef7eb2e8f9f7 353 uint32_t RSERVED1[31];
<> 144:ef7eb2e8f9f7 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 144:ef7eb2e8f9f7 355 uint32_t RESERVED2[31];
<> 144:ef7eb2e8f9f7 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 144:ef7eb2e8f9f7 357 uint32_t RESERVED3[31];
<> 144:ef7eb2e8f9f7 358 uint32_t RESERVED4[64];
<> 144:ef7eb2e8f9f7 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 144:ef7eb2e8f9f7 360 } NVIC_Type;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /*@} end of group CMSIS_NVIC */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 366 \defgroup CMSIS_SCB System Control Block (SCB)
<> 144:ef7eb2e8f9f7 367 \brief Type definitions for the System Control Block Registers
<> 144:ef7eb2e8f9f7 368 @{
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /** \brief Structure type to access the System Control Block (SCB).
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 typedef struct
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 144:ef7eb2e8f9f7 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 144:ef7eb2e8f9f7 377 #if (__VTOR_PRESENT == 1)
<> 144:ef7eb2e8f9f7 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 144:ef7eb2e8f9f7 379 #else
<> 144:ef7eb2e8f9f7 380 uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 381 #endif
<> 144:ef7eb2e8f9f7 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 144:ef7eb2e8f9f7 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 144:ef7eb2e8f9f7 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 144:ef7eb2e8f9f7 385 uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 144:ef7eb2e8f9f7 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 144:ef7eb2e8f9f7 388 } SCB_Type;
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* SCB CPUID Register Definitions */
<> 144:ef7eb2e8f9f7 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 144:ef7eb2e8f9f7 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 144:ef7eb2e8f9f7 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 144:ef7eb2e8f9f7 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 144:ef7eb2e8f9f7 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 144:ef7eb2e8f9f7 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* SCB Interrupt Control State Register Definitions */
<> 144:ef7eb2e8f9f7 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 144:ef7eb2e8f9f7 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 144:ef7eb2e8f9f7 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 144:ef7eb2e8f9f7 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 144:ef7eb2e8f9f7 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 144:ef7eb2e8f9f7 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 144:ef7eb2e8f9f7 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 144:ef7eb2e8f9f7 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 144:ef7eb2e8f9f7 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 144:ef7eb2e8f9f7 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #if (__VTOR_PRESENT == 1)
<> 144:ef7eb2e8f9f7 435 /* SCB Interrupt Control State Register Definitions */
<> 144:ef7eb2e8f9f7 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
<> 144:ef7eb2e8f9f7 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 144:ef7eb2e8f9f7 438 #endif
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 144:ef7eb2e8f9f7 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 144:ef7eb2e8f9f7 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 144:ef7eb2e8f9f7 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 144:ef7eb2e8f9f7 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 144:ef7eb2e8f9f7 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 144:ef7eb2e8f9f7 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* SCB System Control Register Definitions */
<> 144:ef7eb2e8f9f7 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 144:ef7eb2e8f9f7 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 144:ef7eb2e8f9f7 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 144:ef7eb2e8f9f7 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* SCB Configuration Control Register Definitions */
<> 144:ef7eb2e8f9f7 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 144:ef7eb2e8f9f7 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 144:ef7eb2e8f9f7 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* SCB System Handler Control and State Register Definitions */
<> 144:ef7eb2e8f9f7 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 144:ef7eb2e8f9f7 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /*@} end of group CMSIS_SCB */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 144:ef7eb2e8f9f7 482 \brief Type definitions for the System Timer Registers.
<> 144:ef7eb2e8f9f7 483 @{
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /** \brief Structure type to access the System Timer (SysTick).
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 typedef struct
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 144:ef7eb2e8f9f7 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 144:ef7eb2e8f9f7 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 144:ef7eb2e8f9f7 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 144:ef7eb2e8f9f7 494 } SysTick_Type;
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* SysTick Control / Status Register Definitions */
<> 144:ef7eb2e8f9f7 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 144:ef7eb2e8f9f7 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 144:ef7eb2e8f9f7 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 144:ef7eb2e8f9f7 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 144:ef7eb2e8f9f7 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* SysTick Reload Register Definitions */
<> 144:ef7eb2e8f9f7 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 144:ef7eb2e8f9f7 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* SysTick Current Register Definitions */
<> 144:ef7eb2e8f9f7 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 144:ef7eb2e8f9f7 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* SysTick Calibration Register Definitions */
<> 144:ef7eb2e8f9f7 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 144:ef7eb2e8f9f7 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 144:ef7eb2e8f9f7 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 144:ef7eb2e8f9f7 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /*@} end of group CMSIS_SysTick */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 530 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 144:ef7eb2e8f9f7 532 \brief Type definitions for the Memory Protection Unit (MPU)
<> 144:ef7eb2e8f9f7 533 @{
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 typedef struct
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 144:ef7eb2e8f9f7 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 144:ef7eb2e8f9f7 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 144:ef7eb2e8f9f7 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 144:ef7eb2e8f9f7 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 144:ef7eb2e8f9f7 545 } MPU_Type;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* MPU Type Register */
<> 144:ef7eb2e8f9f7 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 144:ef7eb2e8f9f7 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 144:ef7eb2e8f9f7 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 144:ef7eb2e8f9f7 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* MPU Control Register */
<> 144:ef7eb2e8f9f7 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 144:ef7eb2e8f9f7 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 144:ef7eb2e8f9f7 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 144:ef7eb2e8f9f7 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* MPU Region Number Register */
<> 144:ef7eb2e8f9f7 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 144:ef7eb2e8f9f7 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* MPU Region Base Address Register */
<> 144:ef7eb2e8f9f7 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 144:ef7eb2e8f9f7 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 144:ef7eb2e8f9f7 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 144:ef7eb2e8f9f7 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* MPU Region Attribute and Size Register */
<> 144:ef7eb2e8f9f7 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 144:ef7eb2e8f9f7 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 144:ef7eb2e8f9f7 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 144:ef7eb2e8f9f7 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 144:ef7eb2e8f9f7 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 144:ef7eb2e8f9f7 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 144:ef7eb2e8f9f7 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 144:ef7eb2e8f9f7 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 144:ef7eb2e8f9f7 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 144:ef7eb2e8f9f7 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 144:ef7eb2e8f9f7 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /*@} end of group CMSIS_MPU */
<> 144:ef7eb2e8f9f7 613 #endif
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 144:ef7eb2e8f9f7 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 144:ef7eb2e8f9f7 619 are only accessible over DAP and not via processor. Therefore
<> 144:ef7eb2e8f9f7 620 they are not covered by the Cortex-M0 header file.
<> 144:ef7eb2e8f9f7 621 @{
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623 /*@} end of group CMSIS_CoreDebug */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 627 \defgroup CMSIS_core_base Core Definitions
<> 144:ef7eb2e8f9f7 628 \brief Definitions for base addresses, unions, and structures.
<> 144:ef7eb2e8f9f7 629 @{
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Memory mapping of Cortex-M0+ Hardware */
<> 144:ef7eb2e8f9f7 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 144:ef7eb2e8f9f7 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 144:ef7eb2e8f9f7 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 144:ef7eb2e8f9f7 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 144:ef7eb2e8f9f7 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 144:ef7eb2e8f9f7 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 144:ef7eb2e8f9f7 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 144:ef7eb2e8f9f7 645 #endif
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /*@} */
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /*******************************************************************************
<> 144:ef7eb2e8f9f7 652 * Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 653 Core Function Interface contains:
<> 144:ef7eb2e8f9f7 654 - Core NVIC Functions
<> 144:ef7eb2e8f9f7 655 - Core SysTick Functions
<> 144:ef7eb2e8f9f7 656 - Core Register Access Functions
<> 144:ef7eb2e8f9f7 657 ******************************************************************************/
<> 144:ef7eb2e8f9f7 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* ########################## NVIC functions #################################### */
<> 144:ef7eb2e8f9f7 664 /** \ingroup CMSIS_Core_FunctionInterface
<> 144:ef7eb2e8f9f7 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 144:ef7eb2e8f9f7 666 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 144:ef7eb2e8f9f7 667 @{
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 144:ef7eb2e8f9f7 671 /* The following MACROS handle generation of the register offset and byte masks */
<> 144:ef7eb2e8f9f7 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 144:ef7eb2e8f9f7 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 144:ef7eb2e8f9f7 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /** \brief Enable External Interrupt
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 144:ef7eb2e8f9f7 682 */
<> 144:ef7eb2e8f9f7 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /** \brief Disable External Interrupt
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /** \brief Get Pending Interrupt
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 The function reads the pending register in the NVIC and returns the pending bit
<> 144:ef7eb2e8f9f7 704 for the specified interrupt.
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 \return 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 709 \return 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /** \brief Set Pending Interrupt
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 The function sets the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 144:ef7eb2e8f9f7 722 */
<> 144:ef7eb2e8f9f7 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /** \brief Clear Pending Interrupt
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 The function clears the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /** \brief Set Interrupt Priority
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 The function sets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 \note The priority cannot be set for every core interrupt.
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 748 \param [in] priority Priority to set.
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 if((int32_t)(IRQn) < 0) {
<> 144:ef7eb2e8f9f7 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 144:ef7eb2e8f9f7 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 144:ef7eb2e8f9f7 755 }
<> 144:ef7eb2e8f9f7 756 else {
<> 144:ef7eb2e8f9f7 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 144:ef7eb2e8f9f7 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /** \brief Get Interrupt Priority
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 The function reads the priority of an interrupt. The interrupt
<> 144:ef7eb2e8f9f7 766 number can be positive to specify an external (device specific)
<> 144:ef7eb2e8f9f7 767 interrupt, or negative to specify an internal (core) interrupt.
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 \param [in] IRQn Interrupt number.
<> 144:ef7eb2e8f9f7 771 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 144:ef7eb2e8f9f7 772 priority bits of the microcontroller.
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 775 {
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 if((int32_t)(IRQn) < 0) {
<> 144:ef7eb2e8f9f7 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780 else {
<> 144:ef7eb2e8f9f7 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /** \brief System Reset
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 The function initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790 __STATIC_INLINE void NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 __DSB(); /* Ensure all outstanding memory accesses included
<> 144:ef7eb2e8f9f7 793 buffered write are completed before reset */
<> 144:ef7eb2e8f9f7 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 144:ef7eb2e8f9f7 795 SCB_AIRCR_SYSRESETREQ_Msk);
<> 144:ef7eb2e8f9f7 796 __DSB(); /* Ensure completion of memory access */
<> 144:ef7eb2e8f9f7 797 while(1) { __NOP(); } /* wait until reset */
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /*@} end of CMSIS_Core_NVICFunctions */
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* ################################## SysTick function ############################################ */
<> 144:ef7eb2e8f9f7 805 /** \ingroup CMSIS_Core_FunctionInterface
<> 144:ef7eb2e8f9f7 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 144:ef7eb2e8f9f7 807 \brief Functions that configure the System.
<> 144:ef7eb2e8f9f7 808 @{
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 #if (__Vendor_SysTickConfig == 0)
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /** \brief System Tick Configuration
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 816 Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 \param [in] ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 \return 0 Function succeeded.
<> 144:ef7eb2e8f9f7 821 \return 1 Function failed.
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 144:ef7eb2e8f9f7 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 144:ef7eb2e8f9f7 825 must contain a vendor-specific implementation of this function.
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 */
<> 144:ef7eb2e8f9f7 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 144:ef7eb2e8f9f7 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 144:ef7eb2e8f9f7 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 144:ef7eb2e8f9f7 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 144:ef7eb2e8f9f7 836 SysTick_CTRL_TICKINT_Msk |
<> 144:ef7eb2e8f9f7 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 144:ef7eb2e8f9f7 838 return (0UL); /* Function successful */
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 #endif
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /*@} end of CMSIS_Core_SysTickFunctions */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 #endif
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 #endif /* __CMSIS_GENERIC */