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mbed-client/test/mbedclient/utest/stub/m2minterfaceimpl_stub.cpp@0:a2cb7295a1f7, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:35:07 2017 +0000
Revision:
0:a2cb7295a1f7
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a2cb7295a1f7 1 /*
ram54288 0:a2cb7295a1f7 2 * Copyright (c) 2015 ARM Limited. All rights reserved.
ram54288 0:a2cb7295a1f7 3 * SPDX-License-Identifier: Apache-2.0
ram54288 0:a2cb7295a1f7 4 * Licensed under the Apache License, Version 2.0 (the License); you may
ram54288 0:a2cb7295a1f7 5 * not use this file except in compliance with the License.
ram54288 0:a2cb7295a1f7 6 * You may obtain a copy of the License at
ram54288 0:a2cb7295a1f7 7 *
ram54288 0:a2cb7295a1f7 8 * http://www.apache.org/licenses/LICENSE-2.0
ram54288 0:a2cb7295a1f7 9 *
ram54288 0:a2cb7295a1f7 10 * Unless required by applicable law or agreed to in writing, software
ram54288 0:a2cb7295a1f7 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ram54288 0:a2cb7295a1f7 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ram54288 0:a2cb7295a1f7 13 * See the License for the specific language governing permissions and
ram54288 0:a2cb7295a1f7 14 * limitations under the License.
ram54288 0:a2cb7295a1f7 15 */
ram54288 0:a2cb7295a1f7 16 #include "m2minterfaceimpl_stub.h"
ram54288 0:a2cb7295a1f7 17 #include "common_stub.h"
ram54288 0:a2cb7295a1f7 18
ram54288 0:a2cb7295a1f7 19 u_int8_t m2minterfaceimpl_stub::int_value;
ram54288 0:a2cb7295a1f7 20 bool m2minterfaceimpl_stub::bool_value;
ram54288 0:a2cb7295a1f7 21
ram54288 0:a2cb7295a1f7 22 void m2minterfaceimpl_stub::clear()
ram54288 0:a2cb7295a1f7 23 {
ram54288 0:a2cb7295a1f7 24 int_value = 0;
ram54288 0:a2cb7295a1f7 25 bool_value = false;
ram54288 0:a2cb7295a1f7 26 }
ram54288 0:a2cb7295a1f7 27
ram54288 0:a2cb7295a1f7 28 M2MInterfaceImpl::M2MInterfaceImpl(M2MInterfaceObserver& observer,
ram54288 0:a2cb7295a1f7 29 const String &,
ram54288 0:a2cb7295a1f7 30 const String &,
ram54288 0:a2cb7295a1f7 31 const int32_t,
ram54288 0:a2cb7295a1f7 32 const uint16_t,
ram54288 0:a2cb7295a1f7 33 const String &,
ram54288 0:a2cb7295a1f7 34 M2MInterface::BindingMode mode,
ram54288 0:a2cb7295a1f7 35 M2MInterface::NetworkStack stack,
ram54288 0:a2cb7295a1f7 36 const String &)
ram54288 0:a2cb7295a1f7 37 : _observer(observer),
ram54288 0:a2cb7295a1f7 38 _current_state(0),
ram54288 0:a2cb7295a1f7 39 _max_states( STATE_MAX_STATES ),
ram54288 0:a2cb7295a1f7 40 _event_generated(false),
ram54288 0:a2cb7295a1f7 41 _event_data(NULL),
ram54288 0:a2cb7295a1f7 42 _nsdl_interface(*this),
ram54288 0:a2cb7295a1f7 43 _queue_sleep_timer(*this),
ram54288 0:a2cb7295a1f7 44 _retry_timer(*this),
ram54288 0:a2cb7295a1f7 45 _connection_handler(*this, NULL, mode, stack)
ram54288 0:a2cb7295a1f7 46 {
ram54288 0:a2cb7295a1f7 47 }
ram54288 0:a2cb7295a1f7 48
ram54288 0:a2cb7295a1f7 49 M2MInterfaceImpl::~M2MInterfaceImpl()
ram54288 0:a2cb7295a1f7 50 {
ram54288 0:a2cb7295a1f7 51 }
ram54288 0:a2cb7295a1f7 52 void M2MInterfaceImpl::bootstrap(M2MSecurity *)
ram54288 0:a2cb7295a1f7 53 {
ram54288 0:a2cb7295a1f7 54 }
ram54288 0:a2cb7295a1f7 55
ram54288 0:a2cb7295a1f7 56 void M2MInterfaceImpl::cancel_bootstrap()
ram54288 0:a2cb7295a1f7 57 {
ram54288 0:a2cb7295a1f7 58 }
ram54288 0:a2cb7295a1f7 59
ram54288 0:a2cb7295a1f7 60 void M2MInterfaceImpl::register_object(M2MSecurity *, const M2MObjectList &)
ram54288 0:a2cb7295a1f7 61 {
ram54288 0:a2cb7295a1f7 62 }
ram54288 0:a2cb7295a1f7 63
ram54288 0:a2cb7295a1f7 64 void M2MInterfaceImpl::update_registration(M2MSecurity *, const uint32_t)
ram54288 0:a2cb7295a1f7 65 {
ram54288 0:a2cb7295a1f7 66 }
ram54288 0:a2cb7295a1f7 67 void M2MInterfaceImpl::update_registration(M2MSecurity *,
ram54288 0:a2cb7295a1f7 68 const M2MObjectList &,
ram54288 0:a2cb7295a1f7 69 const uint32_t)
ram54288 0:a2cb7295a1f7 70 {
ram54288 0:a2cb7295a1f7 71 }
ram54288 0:a2cb7295a1f7 72
ram54288 0:a2cb7295a1f7 73 void M2MInterfaceImpl::unregister_object(M2MSecurity*)
ram54288 0:a2cb7295a1f7 74 {
ram54288 0:a2cb7295a1f7 75 }
ram54288 0:a2cb7295a1f7 76
ram54288 0:a2cb7295a1f7 77 void M2MInterfaceImpl::set_queue_sleep_handler(callback_handler)
ram54288 0:a2cb7295a1f7 78 {
ram54288 0:a2cb7295a1f7 79
ram54288 0:a2cb7295a1f7 80 }
ram54288 0:a2cb7295a1f7 81
ram54288 0:a2cb7295a1f7 82 void M2MInterfaceImpl::set_platform_network_handler(void *)
ram54288 0:a2cb7295a1f7 83 {
ram54288 0:a2cb7295a1f7 84
ram54288 0:a2cb7295a1f7 85 }
ram54288 0:a2cb7295a1f7 86
ram54288 0:a2cb7295a1f7 87 void M2MInterfaceImpl::set_random_number_callback(random_number_cb)
ram54288 0:a2cb7295a1f7 88 {
ram54288 0:a2cb7295a1f7 89
ram54288 0:a2cb7295a1f7 90 }
ram54288 0:a2cb7295a1f7 91
ram54288 0:a2cb7295a1f7 92 void M2MInterfaceImpl::set_entropy_callback(entropy_cb)
ram54288 0:a2cb7295a1f7 93 {
ram54288 0:a2cb7295a1f7 94
ram54288 0:a2cb7295a1f7 95 }
ram54288 0:a2cb7295a1f7 96
ram54288 0:a2cb7295a1f7 97 void M2MInterfaceImpl::coap_message_ready(uint8_t *,
ram54288 0:a2cb7295a1f7 98 uint16_t ,
ram54288 0:a2cb7295a1f7 99 sn_nsdl_addr_s *)
ram54288 0:a2cb7295a1f7 100 {
ram54288 0:a2cb7295a1f7 101
ram54288 0:a2cb7295a1f7 102 }
ram54288 0:a2cb7295a1f7 103
ram54288 0:a2cb7295a1f7 104 void M2MInterfaceImpl::client_registered(M2MServer*)
ram54288 0:a2cb7295a1f7 105 {
ram54288 0:a2cb7295a1f7 106
ram54288 0:a2cb7295a1f7 107 }
ram54288 0:a2cb7295a1f7 108
ram54288 0:a2cb7295a1f7 109 void M2MInterfaceImpl::registration_error(uint8_t, bool)
ram54288 0:a2cb7295a1f7 110 {
ram54288 0:a2cb7295a1f7 111
ram54288 0:a2cb7295a1f7 112 }
ram54288 0:a2cb7295a1f7 113
ram54288 0:a2cb7295a1f7 114 void M2MInterfaceImpl::client_unregistered()
ram54288 0:a2cb7295a1f7 115 {
ram54288 0:a2cb7295a1f7 116
ram54288 0:a2cb7295a1f7 117 }
ram54288 0:a2cb7295a1f7 118
ram54288 0:a2cb7295a1f7 119 void M2MInterfaceImpl::bootstrap_done(M2MSecurity *)
ram54288 0:a2cb7295a1f7 120 {
ram54288 0:a2cb7295a1f7 121
ram54288 0:a2cb7295a1f7 122 }
ram54288 0:a2cb7295a1f7 123
ram54288 0:a2cb7295a1f7 124 void M2MInterfaceImpl::bootstrap_wait(M2MSecurity *)
ram54288 0:a2cb7295a1f7 125 {
ram54288 0:a2cb7295a1f7 126
ram54288 0:a2cb7295a1f7 127 }
ram54288 0:a2cb7295a1f7 128
ram54288 0:a2cb7295a1f7 129 void M2MInterfaceImpl::bootstrap_error()
ram54288 0:a2cb7295a1f7 130 {
ram54288 0:a2cb7295a1f7 131
ram54288 0:a2cb7295a1f7 132 }
ram54288 0:a2cb7295a1f7 133
ram54288 0:a2cb7295a1f7 134 void M2MInterfaceImpl::coap_data_processed()
ram54288 0:a2cb7295a1f7 135 {
ram54288 0:a2cb7295a1f7 136
ram54288 0:a2cb7295a1f7 137 }
ram54288 0:a2cb7295a1f7 138
ram54288 0:a2cb7295a1f7 139 void M2MInterfaceImpl::data_available(uint8_t*,
ram54288 0:a2cb7295a1f7 140 uint16_t,
ram54288 0:a2cb7295a1f7 141 const M2MConnectionObserver::SocketAddress &)
ram54288 0:a2cb7295a1f7 142 {
ram54288 0:a2cb7295a1f7 143
ram54288 0:a2cb7295a1f7 144 }
ram54288 0:a2cb7295a1f7 145
ram54288 0:a2cb7295a1f7 146 void M2MInterfaceImpl::socket_error(uint8_t, bool)
ram54288 0:a2cb7295a1f7 147 {
ram54288 0:a2cb7295a1f7 148
ram54288 0:a2cb7295a1f7 149 }
ram54288 0:a2cb7295a1f7 150
ram54288 0:a2cb7295a1f7 151 void M2MInterfaceImpl::address_ready(const M2MConnectionObserver::SocketAddress &,
ram54288 0:a2cb7295a1f7 152 M2MConnectionObserver::ServerType,
ram54288 0:a2cb7295a1f7 153 const uint16_t)
ram54288 0:a2cb7295a1f7 154 {
ram54288 0:a2cb7295a1f7 155
ram54288 0:a2cb7295a1f7 156 }
ram54288 0:a2cb7295a1f7 157
ram54288 0:a2cb7295a1f7 158 void M2MInterfaceImpl::data_sent()
ram54288 0:a2cb7295a1f7 159 {
ram54288 0:a2cb7295a1f7 160 }
ram54288 0:a2cb7295a1f7 161
ram54288 0:a2cb7295a1f7 162 void M2MInterfaceImpl::timer_expired(M2MTimerObserver::Type)
ram54288 0:a2cb7295a1f7 163 {
ram54288 0:a2cb7295a1f7 164
ram54288 0:a2cb7295a1f7 165 }
ram54288 0:a2cb7295a1f7 166
ram54288 0:a2cb7295a1f7 167 void M2MInterfaceImpl::registration_updated(const M2MServer &)
ram54288 0:a2cb7295a1f7 168 {
ram54288 0:a2cb7295a1f7 169 }
ram54288 0:a2cb7295a1f7 170
ram54288 0:a2cb7295a1f7 171 void M2MInterfaceImpl::value_updated(M2MBase *)
ram54288 0:a2cb7295a1f7 172 {
ram54288 0:a2cb7295a1f7 173
ram54288 0:a2cb7295a1f7 174 }
ram54288 0:a2cb7295a1f7 175