Ram Gandikota / Mbed OS IOTMetronome

FRDM K64F Metronome

easy-connect/mcr20a-rf-driver/source/MCR20Reg.h@0:dbad57390bd1, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:37:05 2017 +0000
Revision:
0:dbad57390bd1
Initial commit

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ram54288 0:dbad57390bd1 1 /*!
ram54288 0:dbad57390bd1 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:dbad57390bd1 3 * All rights reserved.
ram54288 0:dbad57390bd1 4 *
ram54288 0:dbad57390bd1 5 * \file MCR20reg.h
ram54288 0:dbad57390bd1 6 * MCR20 Registers
ram54288 0:dbad57390bd1 7 *
ram54288 0:dbad57390bd1 8 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:dbad57390bd1 9 * are permitted provided that the following conditions are met:
ram54288 0:dbad57390bd1 10 *
ram54288 0:dbad57390bd1 11 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:dbad57390bd1 12 * of conditions and the following disclaimer.
ram54288 0:dbad57390bd1 13 *
ram54288 0:dbad57390bd1 14 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:dbad57390bd1 15 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:dbad57390bd1 16 * other materials provided with the distribution.
ram54288 0:dbad57390bd1 17 *
ram54288 0:dbad57390bd1 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:dbad57390bd1 19 * contributors may be used to endorse or promote products derived from this
ram54288 0:dbad57390bd1 20 * software without specific prior written permission.
ram54288 0:dbad57390bd1 21 *
ram54288 0:dbad57390bd1 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:dbad57390bd1 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:dbad57390bd1 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:dbad57390bd1 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:dbad57390bd1 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:dbad57390bd1 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:dbad57390bd1 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:dbad57390bd1 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:dbad57390bd1 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:dbad57390bd1 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:dbad57390bd1 32 */
ram54288 0:dbad57390bd1 33
ram54288 0:dbad57390bd1 34 #ifndef __MCR20_REG_H__
ram54288 0:dbad57390bd1 35 #define __MCR20_REG_H__
ram54288 0:dbad57390bd1 36 /*****************************************************************************
ram54288 0:dbad57390bd1 37 * INCLUDED HEADERS *
ram54288 0:dbad57390bd1 38 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 39 * Add to this section all the headers that this module needs to include. *
ram54288 0:dbad57390bd1 40 * Note that it is not a good practice to include header files into header *
ram54288 0:dbad57390bd1 41 * files, so use this section only if there is no other better solution. *
ram54288 0:dbad57390bd1 42 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 43 *****************************************************************************/
ram54288 0:dbad57390bd1 44
ram54288 0:dbad57390bd1 45 /****************************************************************************/
ram54288 0:dbad57390bd1 46 /* Transceiver SPI Registers */
ram54288 0:dbad57390bd1 47 /****************************************************************************/
ram54288 0:dbad57390bd1 48
ram54288 0:dbad57390bd1 49 #define TransceiverSPI_IARIndexReg (0x3E)
ram54288 0:dbad57390bd1 50
ram54288 0:dbad57390bd1 51 #define TransceiverSPI_ReadSelect (1<<7)
ram54288 0:dbad57390bd1 52 #define TransceiverSPI_WriteSelect (0<<7)
ram54288 0:dbad57390bd1 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
ram54288 0:dbad57390bd1 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
ram54288 0:dbad57390bd1 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
ram54288 0:dbad57390bd1 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
ram54288 0:dbad57390bd1 57
ram54288 0:dbad57390bd1 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
ram54288 0:dbad57390bd1 59
ram54288 0:dbad57390bd1 60 #define IRQSTS1 0x00
ram54288 0:dbad57390bd1 61 #define IRQSTS2 0x01
ram54288 0:dbad57390bd1 62 #define IRQSTS3 0x02
ram54288 0:dbad57390bd1 63 #define PHY_CTRL1 0x03
ram54288 0:dbad57390bd1 64 #define PHY_CTRL2 0x04
ram54288 0:dbad57390bd1 65 #define PHY_CTRL3 0x05
ram54288 0:dbad57390bd1 66 #define RX_FRM_LEN 0x06
ram54288 0:dbad57390bd1 67 #define PHY_CTRL4 0x07
ram54288 0:dbad57390bd1 68 #define SRC_CTRL 0x08
ram54288 0:dbad57390bd1 69 #define SRC_ADDRS_SUM_LSB 0x09
ram54288 0:dbad57390bd1 70 #define SRC_ADDRS_SUM_MSB 0x0A
ram54288 0:dbad57390bd1 71 #define CCA1_ED_FNL 0x0B
ram54288 0:dbad57390bd1 72 #define EVENT_TMR_LSB 0x0C
ram54288 0:dbad57390bd1 73 #define EVENT_TMR_MSB 0x0D
ram54288 0:dbad57390bd1 74 #define EVENT_TMR_USB 0x0E
ram54288 0:dbad57390bd1 75 #define TIMESTAMP_LSB 0x0F
ram54288 0:dbad57390bd1 76 #define TIMESTAMP_MSB 0x10
ram54288 0:dbad57390bd1 77 #define TIMESTAMP_USB 0x11
ram54288 0:dbad57390bd1 78 #define T3CMP_LSB 0x12
ram54288 0:dbad57390bd1 79 #define T3CMP_MSB 0x13
ram54288 0:dbad57390bd1 80 #define T3CMP_USB 0x14
ram54288 0:dbad57390bd1 81 #define T2PRIMECMP_LSB 0x15
ram54288 0:dbad57390bd1 82 #define T2PRIMECMP_MSB 0x16
ram54288 0:dbad57390bd1 83 #define T1CMP_LSB 0x17
ram54288 0:dbad57390bd1 84 #define T1CMP_MSB 0x18
ram54288 0:dbad57390bd1 85 #define T1CMP_USB 0x19
ram54288 0:dbad57390bd1 86 #define T2CMP_LSB 0x1A
ram54288 0:dbad57390bd1 87 #define T2CMP_MSB 0x1B
ram54288 0:dbad57390bd1 88 #define T2CMP_USB 0x1C
ram54288 0:dbad57390bd1 89 #define T4CMP_LSB 0x1D
ram54288 0:dbad57390bd1 90 #define T4CMP_MSB 0x1E
ram54288 0:dbad57390bd1 91 #define T4CMP_USB 0x1F
ram54288 0:dbad57390bd1 92 #define PLL_INT0 0x20
ram54288 0:dbad57390bd1 93 #define PLL_FRAC0_LSB 0x21
ram54288 0:dbad57390bd1 94 #define PLL_FRAC0_MSB 0x22
ram54288 0:dbad57390bd1 95 #define PA_PWR 0x23
ram54288 0:dbad57390bd1 96 #define SEQ_STATE 0x24
ram54288 0:dbad57390bd1 97 #define LQI_VALUE 0x25
ram54288 0:dbad57390bd1 98 #define RSSI_CCA_CONT 0x26
ram54288 0:dbad57390bd1 99 //-------------- 0x27
ram54288 0:dbad57390bd1 100 #define ASM_CTRL1 0x28
ram54288 0:dbad57390bd1 101 #define ASM_CTRL2 0x29
ram54288 0:dbad57390bd1 102 #define ASM_DATA_0 0x2A
ram54288 0:dbad57390bd1 103 #define ASM_DATA_1 0x2B
ram54288 0:dbad57390bd1 104 #define ASM_DATA_2 0x2C
ram54288 0:dbad57390bd1 105 #define ASM_DATA_3 0x2D
ram54288 0:dbad57390bd1 106 #define ASM_DATA_4 0x2E
ram54288 0:dbad57390bd1 107 #define ASM_DATA_5 0x2F
ram54288 0:dbad57390bd1 108 #define ASM_DATA_6 0x30
ram54288 0:dbad57390bd1 109 #define ASM_DATA_7 0x31
ram54288 0:dbad57390bd1 110 #define ASM_DATA_8 0x32
ram54288 0:dbad57390bd1 111 #define ASM_DATA_9 0x33
ram54288 0:dbad57390bd1 112 #define ASM_DATA_A 0x34
ram54288 0:dbad57390bd1 113 #define ASM_DATA_B 0x35
ram54288 0:dbad57390bd1 114 #define ASM_DATA_C 0x36
ram54288 0:dbad57390bd1 115 #define ASM_DATA_D 0x37
ram54288 0:dbad57390bd1 116 #define ASM_DATA_E 0x38
ram54288 0:dbad57390bd1 117 #define ASM_DATA_F 0x39
ram54288 0:dbad57390bd1 118 //------------------- 0x3A
ram54288 0:dbad57390bd1 119 #define OVERWRITE_VER 0x3B
ram54288 0:dbad57390bd1 120 #define CLK_OUT_CTRL 0x3C
ram54288 0:dbad57390bd1 121 #define PWR_MODES 0x3D
ram54288 0:dbad57390bd1 122 #define IAR_INDEX 0x3E
ram54288 0:dbad57390bd1 123 #define IAR_DATA 0x3F
ram54288 0:dbad57390bd1 124
ram54288 0:dbad57390bd1 125
ram54288 0:dbad57390bd1 126 #define PART_ID 0x00
ram54288 0:dbad57390bd1 127 #define XTAL_TRIM 0x01
ram54288 0:dbad57390bd1 128 #define PMC_LP_TRIM 0x02
ram54288 0:dbad57390bd1 129 #define MACPANID0_LSB 0x03
ram54288 0:dbad57390bd1 130 #define MACPANID0_MSB 0x04
ram54288 0:dbad57390bd1 131 #define MACSHORTADDRS0_LSB 0x05
ram54288 0:dbad57390bd1 132 #define MACSHORTADDRS0_MSB 0x06
ram54288 0:dbad57390bd1 133 #define MACLONGADDRS0_0 0x07
ram54288 0:dbad57390bd1 134 #define MACLONGADDRS0_8 0x08
ram54288 0:dbad57390bd1 135 #define MACLONGADDRS0_16 0x09
ram54288 0:dbad57390bd1 136 #define MACLONGADDRS0_24 0x0A
ram54288 0:dbad57390bd1 137 #define MACLONGADDRS0_32 0x0B
ram54288 0:dbad57390bd1 138 #define MACLONGADDRS0_40 0x0C
ram54288 0:dbad57390bd1 139 #define MACLONGADDRS0_48 0x0D
ram54288 0:dbad57390bd1 140 #define MACLONGADDRS0_56 0x0E
ram54288 0:dbad57390bd1 141 #define RX_FRAME_FILTER 0x0F
ram54288 0:dbad57390bd1 142 #define PLL_INT1 0x10
ram54288 0:dbad57390bd1 143 #define PLL_FRAC1_LSB 0x11
ram54288 0:dbad57390bd1 144 #define PLL_FRAC1_MSB 0x12
ram54288 0:dbad57390bd1 145 #define MACPANID1_LSB 0x13
ram54288 0:dbad57390bd1 146 #define MACPANID1_MSB 0x14
ram54288 0:dbad57390bd1 147 #define MACSHORTADDRS1_LSB 0x15
ram54288 0:dbad57390bd1 148 #define MACSHORTADDRS1_MSB 0x16
ram54288 0:dbad57390bd1 149 #define MACLONGADDRS1_0 0x17
ram54288 0:dbad57390bd1 150 #define MACLONGADDRS1_8 0x18
ram54288 0:dbad57390bd1 151 #define MACLONGADDRS1_16 0x19
ram54288 0:dbad57390bd1 152 #define MACLONGADDRS1_24 0x1A
ram54288 0:dbad57390bd1 153 #define MACLONGADDRS1_32 0x1B
ram54288 0:dbad57390bd1 154 #define MACLONGADDRS1_40 0x1C
ram54288 0:dbad57390bd1 155 #define MACLONGADDRS1_48 0x1D
ram54288 0:dbad57390bd1 156 #define MACLONGADDRS1_56 0x1E
ram54288 0:dbad57390bd1 157 #define DUAL_PAN_CTRL 0x1F
ram54288 0:dbad57390bd1 158 #define DUAL_PAN_DWELL 0x20
ram54288 0:dbad57390bd1 159 #define DUAL_PAN_STS 0x21
ram54288 0:dbad57390bd1 160 #define CCA1_THRESH 0x22
ram54288 0:dbad57390bd1 161 #define CCA1_ED_OFFSET_COMP 0x23
ram54288 0:dbad57390bd1 162 #define LQI_OFFSET_COMP 0x24
ram54288 0:dbad57390bd1 163 #define CCA_CTRL 0x25
ram54288 0:dbad57390bd1 164 #define CCA2_CORR_PEAKS 0x26
ram54288 0:dbad57390bd1 165 #define CCA2_CORR_THRESH 0x27
ram54288 0:dbad57390bd1 166 #define TMR_PRESCALE 0x28
ram54288 0:dbad57390bd1 167 //---------------- 0x29
ram54288 0:dbad57390bd1 168 #define GPIO_DATA 0x2A
ram54288 0:dbad57390bd1 169 #define GPIO_DIR 0x2B
ram54288 0:dbad57390bd1 170 #define GPIO_PUL_EN 0x2C
ram54288 0:dbad57390bd1 171 #define GPIO_PUL_SEL 0x2D
ram54288 0:dbad57390bd1 172 #define GPIO_DS 0x2E
ram54288 0:dbad57390bd1 173 //-------------- 0x2F
ram54288 0:dbad57390bd1 174 #define ANT_PAD_CTRL 0x30
ram54288 0:dbad57390bd1 175 #define MISC_PAD_CTRL 0x31
ram54288 0:dbad57390bd1 176 #define BSM_CTRL 0x32
ram54288 0:dbad57390bd1 177 //--------------- 0x33
ram54288 0:dbad57390bd1 178 #define _RNG 0x34
ram54288 0:dbad57390bd1 179 #define RX_BYTE_COUNT 0x35
ram54288 0:dbad57390bd1 180 #define RX_WTR_MARK 0x36
ram54288 0:dbad57390bd1 181 #define SOFT_RESET 0x37
ram54288 0:dbad57390bd1 182 #define TXDELAY 0x38
ram54288 0:dbad57390bd1 183 #define ACKDELAY 0x39
ram54288 0:dbad57390bd1 184 #define SEQ_MGR_CTRL 0x3A
ram54288 0:dbad57390bd1 185 #define SEQ_MGR_STS 0x3B
ram54288 0:dbad57390bd1 186 #define SEQ_T_STS 0x3C
ram54288 0:dbad57390bd1 187 #define ABORT_STS 0x3D
ram54288 0:dbad57390bd1 188 #define CCCA_BUSY_CNT 0x3E
ram54288 0:dbad57390bd1 189 #define SRC_ADDR_CHECKSUM1 0x3F
ram54288 0:dbad57390bd1 190 #define SRC_ADDR_CHECKSUM2 0x40
ram54288 0:dbad57390bd1 191 #define SRC_TBL_VALID1 0x41
ram54288 0:dbad57390bd1 192 #define SRC_TBL_VALID2 0x42
ram54288 0:dbad57390bd1 193 #define FILTERFAIL_CODE1 0x43
ram54288 0:dbad57390bd1 194 #define FILTERFAIL_CODE2 0x44
ram54288 0:dbad57390bd1 195 #define SLOT_PRELOAD 0x45
ram54288 0:dbad57390bd1 196 //---------------- 0x46
ram54288 0:dbad57390bd1 197 #define CORR_VT 0x47
ram54288 0:dbad57390bd1 198 #define SYNC_CTRL 0x48
ram54288 0:dbad57390bd1 199 #define PN_LSB_0 0x49
ram54288 0:dbad57390bd1 200 #define PN_LSB_1 0x4A
ram54288 0:dbad57390bd1 201 #define PN_MSB_0 0x4B
ram54288 0:dbad57390bd1 202 #define PN_MSB_1 0x4C
ram54288 0:dbad57390bd1 203 #define CORR_NVAL 0x4D
ram54288 0:dbad57390bd1 204 #define TX_MODE_CTRL 0x4E
ram54288 0:dbad57390bd1 205 #define SNF_THR 0x4F
ram54288 0:dbad57390bd1 206 #define FAD_THR 0x50
ram54288 0:dbad57390bd1 207 #define ANT_AGC_CTRL 0x51
ram54288 0:dbad57390bd1 208 #define AGC_THR1 0x52
ram54288 0:dbad57390bd1 209 #define AGC_THR2 0x53
ram54288 0:dbad57390bd1 210 #define AGC_HYS 0x54
ram54288 0:dbad57390bd1 211 #define AFC 0x55
ram54288 0:dbad57390bd1 212 //--------------- 0x56
ram54288 0:dbad57390bd1 213 //--------------- 0x57
ram54288 0:dbad57390bd1 214 #define PHY_STS 0x58
ram54288 0:dbad57390bd1 215 #define RX_MAX_CORR 0x59
ram54288 0:dbad57390bd1 216 #define RX_MAX_PREAMBLE 0x5A
ram54288 0:dbad57390bd1 217 #define RSSI 0x5B
ram54288 0:dbad57390bd1 218 //--------------- 0x5C
ram54288 0:dbad57390bd1 219 //--------------- 0x5D
ram54288 0:dbad57390bd1 220 #define PLL_DIG_CTRL 0x5E
ram54288 0:dbad57390bd1 221 #define VCO_CAL 0x5F
ram54288 0:dbad57390bd1 222 #define VCO_BEST_DIFF 0x60
ram54288 0:dbad57390bd1 223 #define VCO_BIAS 0x61
ram54288 0:dbad57390bd1 224 #define KMOD_CTRL 0x62
ram54288 0:dbad57390bd1 225 #define KMOD_CAL 0x63
ram54288 0:dbad57390bd1 226 #define PA_CAL 0x64
ram54288 0:dbad57390bd1 227 #define PA_PWRCAL 0x65
ram54288 0:dbad57390bd1 228 #define ATT_RSSI1 0x66
ram54288 0:dbad57390bd1 229 #define ATT_RSSI2 0x67
ram54288 0:dbad57390bd1 230 #define RSSI_OFFSET 0x68
ram54288 0:dbad57390bd1 231 #define RSSI_SLOPE 0x69
ram54288 0:dbad57390bd1 232 #define RSSI_CAL1 0x6A
ram54288 0:dbad57390bd1 233 #define RSSI_CAL2 0x6B
ram54288 0:dbad57390bd1 234 //--------------- 0x6C
ram54288 0:dbad57390bd1 235 //--------------- 0x6D
ram54288 0:dbad57390bd1 236 #define XTAL_CTRL 0x6E
ram54288 0:dbad57390bd1 237 #define XTAL_COMP_MIN 0x6F
ram54288 0:dbad57390bd1 238 #define XTAL_COMP_MAX 0x70
ram54288 0:dbad57390bd1 239 #define XTAL_GM 0x71
ram54288 0:dbad57390bd1 240 //--------------- 0x72
ram54288 0:dbad57390bd1 241 //--------------- 0x73
ram54288 0:dbad57390bd1 242 #define LNA_TUNE 0x74
ram54288 0:dbad57390bd1 243 #define LNA_AGCGAIN 0x75
ram54288 0:dbad57390bd1 244 //--------------- 0x76
ram54288 0:dbad57390bd1 245 //--------------- 0x77
ram54288 0:dbad57390bd1 246 #define CHF_PMA_GAIN 0x78
ram54288 0:dbad57390bd1 247 #define CHF_IBUF 0x79
ram54288 0:dbad57390bd1 248 #define CHF_QBUF 0x7A
ram54288 0:dbad57390bd1 249 #define CHF_IRIN 0x7B
ram54288 0:dbad57390bd1 250 #define CHF_QRIN 0x7C
ram54288 0:dbad57390bd1 251 #define CHF_IL 0x7D
ram54288 0:dbad57390bd1 252 #define CHF_QL 0x7E
ram54288 0:dbad57390bd1 253 #define CHF_CC1 0x7F
ram54288 0:dbad57390bd1 254 #define CHF_CCL 0x80
ram54288 0:dbad57390bd1 255 #define CHF_CC2 0x81
ram54288 0:dbad57390bd1 256 #define CHF_IROUT 0x82
ram54288 0:dbad57390bd1 257 #define CHF_QROUT 0x83
ram54288 0:dbad57390bd1 258 //--------------- 0x84
ram54288 0:dbad57390bd1 259 //--------------- 0x85
ram54288 0:dbad57390bd1 260 #define RSSI_CTRL 0x86
ram54288 0:dbad57390bd1 261 //--------------- 0x87
ram54288 0:dbad57390bd1 262 //--------------- 0x88
ram54288 0:dbad57390bd1 263 #define PA_BIAS 0x89
ram54288 0:dbad57390bd1 264 #define PA_TUNING 0x8A
ram54288 0:dbad57390bd1 265 //--------------- 0x8B
ram54288 0:dbad57390bd1 266 //--------------- 0x8C
ram54288 0:dbad57390bd1 267 #define PMC_HP_TRIM 0x8D
ram54288 0:dbad57390bd1 268 #define VREGA_TRIM 0x8E
ram54288 0:dbad57390bd1 269 //--------------- 0x8F
ram54288 0:dbad57390bd1 270 //--------------- 0x90
ram54288 0:dbad57390bd1 271 #define VCO_CTRL1 0x91
ram54288 0:dbad57390bd1 272 #define VCO_CTRL2 0x92
ram54288 0:dbad57390bd1 273 //--------------- 0x93
ram54288 0:dbad57390bd1 274 //--------------- 0x94
ram54288 0:dbad57390bd1 275 #define ANA_SPARE_OUT1 0x95
ram54288 0:dbad57390bd1 276 #define ANA_SPARE_OUT2 0x96
ram54288 0:dbad57390bd1 277 #define ANA_SPARE_IN 0x97
ram54288 0:dbad57390bd1 278 #define MISCELLANEOUS 0x98
ram54288 0:dbad57390bd1 279 //--------------- 0x99
ram54288 0:dbad57390bd1 280 #define SEQ_MGR_OVRD0 0x9A
ram54288 0:dbad57390bd1 281 #define SEQ_MGR_OVRD1 0x9B
ram54288 0:dbad57390bd1 282 #define SEQ_MGR_OVRD2 0x9C
ram54288 0:dbad57390bd1 283 #define SEQ_MGR_OVRD3 0x9D
ram54288 0:dbad57390bd1 284 #define SEQ_MGR_OVRD4 0x9E
ram54288 0:dbad57390bd1 285 #define SEQ_MGR_OVRD5 0x9F
ram54288 0:dbad57390bd1 286 #define SEQ_MGR_OVRD6 0xA0
ram54288 0:dbad57390bd1 287 #define SEQ_MGR_OVRD7 0xA1
ram54288 0:dbad57390bd1 288 //--------------- 0xA2
ram54288 0:dbad57390bd1 289 #define TESTMODE_CTRL 0xA3
ram54288 0:dbad57390bd1 290 #define DTM_CTRL1 0xA4
ram54288 0:dbad57390bd1 291 #define DTM_CTRL2 0xA5
ram54288 0:dbad57390bd1 292 #define ATM_CTRL1 0xA6
ram54288 0:dbad57390bd1 293 #define ATM_CTRL2 0xA7
ram54288 0:dbad57390bd1 294 #define ATM_CTRL3 0xA8
ram54288 0:dbad57390bd1 295 //--------------- 0xA9
ram54288 0:dbad57390bd1 296 #define LIM_FE_TEST_CTRL 0xAA
ram54288 0:dbad57390bd1 297 #define CHF_TEST_CTRL 0xAB
ram54288 0:dbad57390bd1 298 #define VCO_TEST_CTRL 0xAC
ram54288 0:dbad57390bd1 299 #define PLL_TEST_CTRL 0xAD
ram54288 0:dbad57390bd1 300 #define PA_TEST_CTRL 0xAE
ram54288 0:dbad57390bd1 301 #define PMC_TEST_CTRL 0xAF
ram54288 0:dbad57390bd1 302 #define SCAN_DTM_PROTECT_1 0xFE
ram54288 0:dbad57390bd1 303 #define SCAN_DTM_PROTECT_0 0xFF
ram54288 0:dbad57390bd1 304
ram54288 0:dbad57390bd1 305 // IRQSTS1 bits
ram54288 0:dbad57390bd1 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
ram54288 0:dbad57390bd1 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
ram54288 0:dbad57390bd1 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
ram54288 0:dbad57390bd1 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
ram54288 0:dbad57390bd1 310 #define cIRQSTS1_CCAIRQ (1<<3)
ram54288 0:dbad57390bd1 311 #define cIRQSTS1_RXIRQ (1<<2)
ram54288 0:dbad57390bd1 312 #define cIRQSTS1_TXIRQ (1<<1)
ram54288 0:dbad57390bd1 313 #define cIRQSTS1_SEQIRQ (1<<0)
ram54288 0:dbad57390bd1 314
ram54288 0:dbad57390bd1 315 typedef union regIRQSTS1_tag{
ram54288 0:dbad57390bd1 316 uint8_t byte;
ram54288 0:dbad57390bd1 317 struct{
ram54288 0:dbad57390bd1 318 uint8_t SEQIRQ:1;
ram54288 0:dbad57390bd1 319 uint8_t TXIRQ:1;
ram54288 0:dbad57390bd1 320 uint8_t RXIRQ:1;
ram54288 0:dbad57390bd1 321 uint8_t CCAIRQ:1;
ram54288 0:dbad57390bd1 322 uint8_t RXWTRMRKIRQ:1;
ram54288 0:dbad57390bd1 323 uint8_t FILTERFAIL_IRQ:1;
ram54288 0:dbad57390bd1 324 uint8_t PLL_UNLOCK_IRQ:1;
ram54288 0:dbad57390bd1 325 uint8_t RX_FRM_PEND:1;
ram54288 0:dbad57390bd1 326 }bit;
ram54288 0:dbad57390bd1 327 } regIRQSTS1_t;
ram54288 0:dbad57390bd1 328
ram54288 0:dbad57390bd1 329 // IRQSTS2 bits
ram54288 0:dbad57390bd1 330 #define cIRQSTS2_CRCVALID (1<<7)
ram54288 0:dbad57390bd1 331 #define cIRQSTS2_CCA (1<<6)
ram54288 0:dbad57390bd1 332 #define cIRQSTS2_SRCADDR (1<<5)
ram54288 0:dbad57390bd1 333 #define cIRQSTS2_PI (1<<4)
ram54288 0:dbad57390bd1 334 #define cIRQSTS2_TMRSTATUS (1<<3)
ram54288 0:dbad57390bd1 335 #define cIRQSTS2_ASM_IRQ (1<<2)
ram54288 0:dbad57390bd1 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
ram54288 0:dbad57390bd1 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
ram54288 0:dbad57390bd1 338
ram54288 0:dbad57390bd1 339 typedef union regIRQSTS2_tag{
ram54288 0:dbad57390bd1 340 uint8_t byte;
ram54288 0:dbad57390bd1 341 struct{
ram54288 0:dbad57390bd1 342 uint8_t WAKE_IRQ:1;
ram54288 0:dbad57390bd1 343 uint8_t PB_ERR_IRQ:1;
ram54288 0:dbad57390bd1 344 uint8_t ASM_IRQ:1;
ram54288 0:dbad57390bd1 345 uint8_t TMRSTATUS:1;
ram54288 0:dbad57390bd1 346 uint8_t PI:1;
ram54288 0:dbad57390bd1 347 uint8_t SRCADDR:1;
ram54288 0:dbad57390bd1 348 uint8_t CCA:1;
ram54288 0:dbad57390bd1 349 uint8_t CRCVALID:1;
ram54288 0:dbad57390bd1 350 }bit;
ram54288 0:dbad57390bd1 351 } regIRQSTS2_t;
ram54288 0:dbad57390bd1 352
ram54288 0:dbad57390bd1 353 // IRQSTS3 bits
ram54288 0:dbad57390bd1 354 #define cIRQSTS3_TMR4MSK (1<<7)
ram54288 0:dbad57390bd1 355 #define cIRQSTS3_TMR3MSK (1<<6)
ram54288 0:dbad57390bd1 356 #define cIRQSTS3_TMR2MSK (1<<5)
ram54288 0:dbad57390bd1 357 #define cIRQSTS3_TMR1MSK (1<<4)
ram54288 0:dbad57390bd1 358 #define cIRQSTS3_TMR4IRQ (1<<3)
ram54288 0:dbad57390bd1 359 #define cIRQSTS3_TMR3IRQ (1<<2)
ram54288 0:dbad57390bd1 360 #define cIRQSTS3_TMR2IRQ (1<<1)
ram54288 0:dbad57390bd1 361 #define cIRQSTS3_TMR1IRQ (1<<0)
ram54288 0:dbad57390bd1 362
ram54288 0:dbad57390bd1 363 typedef union regIRQSTS3_tag{
ram54288 0:dbad57390bd1 364 uint8_t byte;
ram54288 0:dbad57390bd1 365 struct{
ram54288 0:dbad57390bd1 366 uint8_t TMR1IRQ:1;
ram54288 0:dbad57390bd1 367 uint8_t TMR2IRQ:1;
ram54288 0:dbad57390bd1 368 uint8_t TMR3IRQ:1;
ram54288 0:dbad57390bd1 369 uint8_t TMR4IRQ:1;
ram54288 0:dbad57390bd1 370 uint8_t TMR1MSK:1;
ram54288 0:dbad57390bd1 371 uint8_t TMR2MSK:1;
ram54288 0:dbad57390bd1 372 uint8_t TMR3MSK:1;
ram54288 0:dbad57390bd1 373 uint8_t TMR4MSK:1;
ram54288 0:dbad57390bd1 374 }bit;
ram54288 0:dbad57390bd1 375 } regIRQSTS3_t;
ram54288 0:dbad57390bd1 376
ram54288 0:dbad57390bd1 377 // PHY_CTRL1 bits
ram54288 0:dbad57390bd1 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
ram54288 0:dbad57390bd1 379 #define cPHY_CTRL1_SLOTTED (1<<6)
ram54288 0:dbad57390bd1 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
ram54288 0:dbad57390bd1 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
ram54288 0:dbad57390bd1 382 #define cPHY_CTRL1_AUTOACK (1<<3)
ram54288 0:dbad57390bd1 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
ram54288 0:dbad57390bd1 384
ram54288 0:dbad57390bd1 385 typedef union regPHY_CTRL1_tag{
ram54288 0:dbad57390bd1 386 uint8_t byte;
ram54288 0:dbad57390bd1 387 struct{
ram54288 0:dbad57390bd1 388 uint8_t XCVSEQ:3;
ram54288 0:dbad57390bd1 389 uint8_t AUTOACK:1;
ram54288 0:dbad57390bd1 390 uint8_t RXACKRQD:1;
ram54288 0:dbad57390bd1 391 uint8_t CCABFRTX:1;
ram54288 0:dbad57390bd1 392 uint8_t SLOTTED:1;
ram54288 0:dbad57390bd1 393 uint8_t TMRTRIGEN:1;
ram54288 0:dbad57390bd1 394 }bit;
ram54288 0:dbad57390bd1 395 } regPHY_CTRL1_t;
ram54288 0:dbad57390bd1 396
ram54288 0:dbad57390bd1 397 // PHY_CTRL2 bits
ram54288 0:dbad57390bd1 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
ram54288 0:dbad57390bd1 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
ram54288 0:dbad57390bd1 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
ram54288 0:dbad57390bd1 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
ram54288 0:dbad57390bd1 402 #define cPHY_CTRL2_CCAMSK (1<<3)
ram54288 0:dbad57390bd1 403 #define cPHY_CTRL2_RXMSK (1<<2)
ram54288 0:dbad57390bd1 404 #define cPHY_CTRL2_TXMSK (1<<1)
ram54288 0:dbad57390bd1 405 #define cPHY_CTRL2_SEQMSK (1<<0)
ram54288 0:dbad57390bd1 406
ram54288 0:dbad57390bd1 407 typedef union regPHY_CTRL2_tag{
ram54288 0:dbad57390bd1 408 uint8_t byte;
ram54288 0:dbad57390bd1 409 struct{
ram54288 0:dbad57390bd1 410 uint8_t SEQMSK:1;
ram54288 0:dbad57390bd1 411 uint8_t TXMSK:1;
ram54288 0:dbad57390bd1 412 uint8_t RXMSK:1;
ram54288 0:dbad57390bd1 413 uint8_t CCAMSK:1;
ram54288 0:dbad57390bd1 414 uint8_t RX_WMRK_MSK:1;
ram54288 0:dbad57390bd1 415 uint8_t FILTERFAIL_MSK:1;
ram54288 0:dbad57390bd1 416 uint8_t PLL_UNLOCK_MSK:1;
ram54288 0:dbad57390bd1 417 uint8_t CRC_MSK:1;
ram54288 0:dbad57390bd1 418 }bit;
ram54288 0:dbad57390bd1 419 } regPHY_CTRL2_t;
ram54288 0:dbad57390bd1 420
ram54288 0:dbad57390bd1 421 // PHY_CTRL3 bits
ram54288 0:dbad57390bd1 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
ram54288 0:dbad57390bd1 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
ram54288 0:dbad57390bd1 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
ram54288 0:dbad57390bd1 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
ram54288 0:dbad57390bd1 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
ram54288 0:dbad57390bd1 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
ram54288 0:dbad57390bd1 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
ram54288 0:dbad57390bd1 429
ram54288 0:dbad57390bd1 430 typedef union regPHY_CTRL3_tag{
ram54288 0:dbad57390bd1 431 uint8_t byte;
ram54288 0:dbad57390bd1 432 struct{
ram54288 0:dbad57390bd1 433 uint8_t WAKE_MSK:1;
ram54288 0:dbad57390bd1 434 uint8_t PB_ERR_MSK:1;
ram54288 0:dbad57390bd1 435 uint8_t ASM_MSK:1;
ram54288 0:dbad57390bd1 436 uint8_t RESERVED:1;
ram54288 0:dbad57390bd1 437 uint8_t TMR1CMP_EN:1;
ram54288 0:dbad57390bd1 438 uint8_t TMR2CMP_EN:1;
ram54288 0:dbad57390bd1 439 uint8_t TMR3CMP_EN:1;
ram54288 0:dbad57390bd1 440 uint8_t TMR4CMP_EN:1;
ram54288 0:dbad57390bd1 441 }bit;
ram54288 0:dbad57390bd1 442 } regPHY_CTRL3_t;
ram54288 0:dbad57390bd1 443
ram54288 0:dbad57390bd1 444 // RX_FRM_LEN bits
ram54288 0:dbad57390bd1 445 #define cRX_FRAME_LENGTH (0x7F)
ram54288 0:dbad57390bd1 446
ram54288 0:dbad57390bd1 447 // PHY_CTRL4 bits
ram54288 0:dbad57390bd1 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
ram54288 0:dbad57390bd1 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
ram54288 0:dbad57390bd1 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
ram54288 0:dbad57390bd1 451 #define cPHY_CTRL4_CCATYPE (3<<0)
ram54288 0:dbad57390bd1 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
ram54288 0:dbad57390bd1 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
ram54288 0:dbad57390bd1 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
ram54288 0:dbad57390bd1 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
ram54288 0:dbad57390bd1 456
ram54288 0:dbad57390bd1 457 typedef union regPHY_CTRL4_tag{
ram54288 0:dbad57390bd1 458 uint8_t byte;
ram54288 0:dbad57390bd1 459 struct{
ram54288 0:dbad57390bd1 460 uint8_t TC2PRIME_EN:1;
ram54288 0:dbad57390bd1 461 uint8_t PROMISCUOUS:1;
ram54288 0:dbad57390bd1 462 uint8_t TMRLOAD:1;
ram54288 0:dbad57390bd1 463 uint8_t CCATYPE:2;
ram54288 0:dbad57390bd1 464 uint8_t PANCORDNTR0:1;
ram54288 0:dbad57390bd1 465 uint8_t TC3TMOUT:1;
ram54288 0:dbad57390bd1 466 uint8_t TRCV_MSK:1;
ram54288 0:dbad57390bd1 467 }bit;
ram54288 0:dbad57390bd1 468 } regPHY_CTRL4_t;
ram54288 0:dbad57390bd1 469
ram54288 0:dbad57390bd1 470 // SRC_CTRL bits
ram54288 0:dbad57390bd1 471 #define cSRC_CTRL_INDEX (0x0F)
ram54288 0:dbad57390bd1 472 #define cSRC_CTRL_INDEX_Shift_c (4)
ram54288 0:dbad57390bd1 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
ram54288 0:dbad57390bd1 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
ram54288 0:dbad57390bd1 475 #define cSRC_CTRL_INDEX_EN (1<<1)
ram54288 0:dbad57390bd1 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
ram54288 0:dbad57390bd1 477
ram54288 0:dbad57390bd1 478 typedef union regSRC_CTRL_tag{
ram54288 0:dbad57390bd1 479 uint8_t byte;
ram54288 0:dbad57390bd1 480 struct{
ram54288 0:dbad57390bd1 481 uint8_t INDEX_DISABLE:1;
ram54288 0:dbad57390bd1 482 uint8_t INDEX_EN:1;
ram54288 0:dbad57390bd1 483 uint8_t SRCADDR_EN:1;
ram54288 0:dbad57390bd1 484 uint8_t ACK_FRM_PND:1;
ram54288 0:dbad57390bd1 485 uint8_t INDEX:4;
ram54288 0:dbad57390bd1 486 }bit;
ram54288 0:dbad57390bd1 487 } regSRC_CTRL_t;
ram54288 0:dbad57390bd1 488
ram54288 0:dbad57390bd1 489 // ASM_CTRL1 bits
ram54288 0:dbad57390bd1 490 #define cASM_CTRL1_CLEAR (1<<7)
ram54288 0:dbad57390bd1 491 #define cASM_CTRL1_START (1<<6)
ram54288 0:dbad57390bd1 492 #define cASM_CTRL1_SELFTST (1<<5)
ram54288 0:dbad57390bd1 493 #define cASM_CTRL1_CTR (1<<4)
ram54288 0:dbad57390bd1 494 #define cASM_CTRL1_CBC (1<<3)
ram54288 0:dbad57390bd1 495 #define cASM_CTRL1_AES (1<<2)
ram54288 0:dbad57390bd1 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
ram54288 0:dbad57390bd1 497
ram54288 0:dbad57390bd1 498 // ASM_CTRL2 bits
ram54288 0:dbad57390bd1 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
ram54288 0:dbad57390bd1 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
ram54288 0:dbad57390bd1 501 #define cASM_CTRL2_TSTPAS (1<<1)
ram54288 0:dbad57390bd1 502
ram54288 0:dbad57390bd1 503 // CLK_OUT_CTRL bits
ram54288 0:dbad57390bd1 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
ram54288 0:dbad57390bd1 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
ram54288 0:dbad57390bd1 506 #define cCLK_OUT_CTRL_SR (1<<5)
ram54288 0:dbad57390bd1 507 #define cCLK_OUT_CTRL_DS (1<<4)
ram54288 0:dbad57390bd1 508 #define cCLK_OUT_CTRL_EN (1<<3)
ram54288 0:dbad57390bd1 509 #define cCLK_OUT_CTRL_DIV (7)
ram54288 0:dbad57390bd1 510
ram54288 0:dbad57390bd1 511 // PWR_MODES bits
ram54288 0:dbad57390bd1 512 #define cPWR_MODES_XTAL_READY (1<<5)
ram54288 0:dbad57390bd1 513 #define cPWR_MODES_XTALEN (1<<4)
ram54288 0:dbad57390bd1 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
ram54288 0:dbad57390bd1 515 #define cPWR_MODES_AUTODOZE (1<<1)
ram54288 0:dbad57390bd1 516 #define cPWR_MODES_PMC_MODE (1<<0)
ram54288 0:dbad57390bd1 517
ram54288 0:dbad57390bd1 518 // RX_FRAME_FILTER bits
ram54288 0:dbad57390bd1 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
ram54288 0:dbad57390bd1 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
ram54288 0:dbad57390bd1 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
ram54288 0:dbad57390bd1 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
ram54288 0:dbad57390bd1 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
ram54288 0:dbad57390bd1 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
ram54288 0:dbad57390bd1 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
ram54288 0:dbad57390bd1 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
ram54288 0:dbad57390bd1 527
ram54288 0:dbad57390bd1 528 typedef union regRX_FRAME_FILTER_tag{
ram54288 0:dbad57390bd1 529 uint8_t byte;
ram54288 0:dbad57390bd1 530 struct{
ram54288 0:dbad57390bd1 531 uint8_t FRAME_FLT_BEACON_FT:1;
ram54288 0:dbad57390bd1 532 uint8_t FRAME_FLT_DATA_FT:1;
ram54288 0:dbad57390bd1 533 uint8_t FRAME_FLT_ACK_FT:1;
ram54288 0:dbad57390bd1 534 uint8_t FRAME_FLT_CMD_FT:1;
ram54288 0:dbad57390bd1 535 uint8_t FRAME_FLT_NS_FT:1;
ram54288 0:dbad57390bd1 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
ram54288 0:dbad57390bd1 537 uint8_t FRAME_FLT_FRM_VER:2;
ram54288 0:dbad57390bd1 538 }bit;
ram54288 0:dbad57390bd1 539 } regRX_FRAME_FILTER_t;
ram54288 0:dbad57390bd1 540
ram54288 0:dbad57390bd1 541 // DUAL_PAN_CTRL bits
ram54288 0:dbad57390bd1 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
ram54288 0:dbad57390bd1 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
ram54288 0:dbad57390bd1 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
ram54288 0:dbad57390bd1 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
ram54288 0:dbad57390bd1 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
ram54288 0:dbad57390bd1 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
ram54288 0:dbad57390bd1 548
ram54288 0:dbad57390bd1 549 // DUAL_PAN_STS bits
ram54288 0:dbad57390bd1 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
ram54288 0:dbad57390bd1 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
ram54288 0:dbad57390bd1 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
ram54288 0:dbad57390bd1 553
ram54288 0:dbad57390bd1 554 // CCA_CTRL bits
ram54288 0:dbad57390bd1 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
ram54288 0:dbad57390bd1 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
ram54288 0:dbad57390bd1 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
ram54288 0:dbad57390bd1 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
ram54288 0:dbad57390bd1 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
ram54288 0:dbad57390bd1 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
ram54288 0:dbad57390bd1 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
ram54288 0:dbad57390bd1 562
ram54288 0:dbad57390bd1 563 // GPIO_DATA bits
ram54288 0:dbad57390bd1 564 #define cGPIO_DATA_7 (1<<7)
ram54288 0:dbad57390bd1 565 #define cGPIO_DATA_6 (1<<6)
ram54288 0:dbad57390bd1 566 #define cGPIO_DATA_5 (1<<5)
ram54288 0:dbad57390bd1 567 #define cGPIO_DATA_4 (1<<4)
ram54288 0:dbad57390bd1 568 #define cGPIO_DATA_3 (1<<3)
ram54288 0:dbad57390bd1 569 #define cGPIO_DATA_2 (1<<2)
ram54288 0:dbad57390bd1 570 #define cGPIO_DATA_1 (1<<1)
ram54288 0:dbad57390bd1 571 #define cGPIO_DATA_0 (1<<0)
ram54288 0:dbad57390bd1 572
ram54288 0:dbad57390bd1 573 // GPIO_DIR bits
ram54288 0:dbad57390bd1 574 #define cGPIO_DIR_7 (1<<7)
ram54288 0:dbad57390bd1 575 #define cGPIO_DIR_6 (1<<6)
ram54288 0:dbad57390bd1 576 #define cGPIO_DIR_5 (1<<5)
ram54288 0:dbad57390bd1 577 #define cGPIO_DIR_4 (1<<4)
ram54288 0:dbad57390bd1 578 #define cGPIO_DIR_3 (1<<3)
ram54288 0:dbad57390bd1 579 #define cGPIO_DIR_2 (1<<2)
ram54288 0:dbad57390bd1 580 #define cGPIO_DIR_1 (1<<1)
ram54288 0:dbad57390bd1 581 #define cGPIO_DIR_0 (1<<0)
ram54288 0:dbad57390bd1 582
ram54288 0:dbad57390bd1 583 // GPIO_PUL_EN bits
ram54288 0:dbad57390bd1 584 #define cGPIO_PUL_EN_7 (1<<7)
ram54288 0:dbad57390bd1 585 #define cGPIO_PUL_EN_6 (1<<6)
ram54288 0:dbad57390bd1 586 #define cGPIO_PUL_EN_5 (1<<5)
ram54288 0:dbad57390bd1 587 #define cGPIO_PUL_EN_4 (1<<4)
ram54288 0:dbad57390bd1 588 #define cGPIO_PUL_EN_3 (1<<3)
ram54288 0:dbad57390bd1 589 #define cGPIO_PUL_EN_2 (1<<2)
ram54288 0:dbad57390bd1 590 #define cGPIO_PUL_EN_1 (1<<1)
ram54288 0:dbad57390bd1 591 #define cGPIO_PUL_EN_0 (1<<0)
ram54288 0:dbad57390bd1 592
ram54288 0:dbad57390bd1 593 // GPIO_PUL_SEL bits
ram54288 0:dbad57390bd1 594 #define cGPIO_PUL_SEL_7 (1<<7)
ram54288 0:dbad57390bd1 595 #define cGPIO_PUL_SEL_6 (1<<6)
ram54288 0:dbad57390bd1 596 #define cGPIO_PUL_SEL_5 (1<<5)
ram54288 0:dbad57390bd1 597 #define cGPIO_PUL_SEL_4 (1<<4)
ram54288 0:dbad57390bd1 598 #define cGPIO_PUL_SEL_3 (1<<3)
ram54288 0:dbad57390bd1 599 #define cGPIO_PUL_SEL_2 (1<<2)
ram54288 0:dbad57390bd1 600 #define cGPIO_PUL_SEL_1 (1<<1)
ram54288 0:dbad57390bd1 601 #define cGPIO_PUL_SEL_0 (1<<0)
ram54288 0:dbad57390bd1 602
ram54288 0:dbad57390bd1 603 // GPIO_DS bits
ram54288 0:dbad57390bd1 604 #define cGPIO_DS_7 (1<<7)
ram54288 0:dbad57390bd1 605 #define cGPIO_DS_6 (1<<6)
ram54288 0:dbad57390bd1 606 #define cGPIO_DS_5 (1<<5)
ram54288 0:dbad57390bd1 607 #define cGPIO_DS_4 (1<<4)
ram54288 0:dbad57390bd1 608 #define cGPIO_DS_3 (1<<3)
ram54288 0:dbad57390bd1 609 #define cGPIO_DS_2 (1<<2)
ram54288 0:dbad57390bd1 610 #define cGPIO_DS_1 (1<<1)
ram54288 0:dbad57390bd1 611 #define cGPIO_DS_0 (1<<0)
ram54288 0:dbad57390bd1 612
ram54288 0:dbad57390bd1 613 // SPI_CTRL bits
ram54288 0:dbad57390bd1 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
ram54288 0:dbad57390bd1 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
ram54288 0:dbad57390bd1 616
ram54288 0:dbad57390bd1 617 // ANT_PAD_CTRL bits
ram54288 0:dbad57390bd1 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
ram54288 0:dbad57390bd1 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
ram54288 0:dbad57390bd1 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
ram54288 0:dbad57390bd1 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
ram54288 0:dbad57390bd1 622 #define cANT_PAD_CTRL_ANTX_EN (3)
ram54288 0:dbad57390bd1 623
ram54288 0:dbad57390bd1 624 // MISC_PAD_CTRL bits
ram54288 0:dbad57390bd1 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
ram54288 0:dbad57390bd1 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
ram54288 0:dbad57390bd1 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
ram54288 0:dbad57390bd1 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
ram54288 0:dbad57390bd1 629
ram54288 0:dbad57390bd1 630 // ANT_AGC_CTRL bits
ram54288 0:dbad57390bd1 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
ram54288 0:dbad57390bd1 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
ram54288 0:dbad57390bd1 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
ram54288 0:dbad57390bd1 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
ram54288 0:dbad57390bd1 635
ram54288 0:dbad57390bd1 636 // BSM_CTRL bits
ram54288 0:dbad57390bd1 637 #define cBSM_CTRL_BSM_EN (1<<0)
ram54288 0:dbad57390bd1 638
ram54288 0:dbad57390bd1 639 // SOFT_RESET bits
ram54288 0:dbad57390bd1 640 #define cSOFT_RESET_SOG_RST (1<<7)
ram54288 0:dbad57390bd1 641 #define cSOFT_RESET_REGS_RST (1<<4)
ram54288 0:dbad57390bd1 642 #define cSOFT_RESET_PLL_RST (1<<3)
ram54288 0:dbad57390bd1 643 #define cSOFT_RESET_TX_RST (1<<2)
ram54288 0:dbad57390bd1 644 #define cSOFT_RESET_RX_RST (1<<1)
ram54288 0:dbad57390bd1 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
ram54288 0:dbad57390bd1 646
ram54288 0:dbad57390bd1 647 // SEQ_MGR_CTRL bits
ram54288 0:dbad57390bd1 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
ram54288 0:dbad57390bd1 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
ram54288 0:dbad57390bd1 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
ram54288 0:dbad57390bd1 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
ram54288 0:dbad57390bd1 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
ram54288 0:dbad57390bd1 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
ram54288 0:dbad57390bd1 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
ram54288 0:dbad57390bd1 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
ram54288 0:dbad57390bd1 656
ram54288 0:dbad57390bd1 657 // SEQ_MGR_STS bits
ram54288 0:dbad57390bd1 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
ram54288 0:dbad57390bd1 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
ram54288 0:dbad57390bd1 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
ram54288 0:dbad57390bd1 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
ram54288 0:dbad57390bd1 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
ram54288 0:dbad57390bd1 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
ram54288 0:dbad57390bd1 664
ram54288 0:dbad57390bd1 665 // ABORT_STS bits
ram54288 0:dbad57390bd1 666 #define cABORT_STS_PLL_ABORTED (1<<2)
ram54288 0:dbad57390bd1 667 #define cABORT_STS_TC3_ABORTED (1<<1)
ram54288 0:dbad57390bd1 668 #define cABORT_STS_SW_ABORTED (1<<0)
ram54288 0:dbad57390bd1 669
ram54288 0:dbad57390bd1 670 // FILTERFAIL_CODE2 bits
ram54288 0:dbad57390bd1 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
ram54288 0:dbad57390bd1 672 #define cFILTERFAIL_CODE2_9_8 (3)
ram54288 0:dbad57390bd1 673
ram54288 0:dbad57390bd1 674 // PHY_STS bits
ram54288 0:dbad57390bd1 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
ram54288 0:dbad57390bd1 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
ram54288 0:dbad57390bd1 677 #define cPHY_STS_PLL_LOCK (1<<5)
ram54288 0:dbad57390bd1 678 #define cPHY_STS_CRCVALID (1<<3)
ram54288 0:dbad57390bd1 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
ram54288 0:dbad57390bd1 680 #define cPHY_STS_SFD_DET (1<<1)
ram54288 0:dbad57390bd1 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
ram54288 0:dbad57390bd1 682
ram54288 0:dbad57390bd1 683 // TESTMODE_CTRL bits
ram54288 0:dbad57390bd1 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
ram54288 0:dbad57390bd1 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
ram54288 0:dbad57390bd1 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
ram54288 0:dbad57390bd1 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
ram54288 0:dbad57390bd1 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
ram54288 0:dbad57390bd1 689
ram54288 0:dbad57390bd1 690 // DTM_CTRL1 bits
ram54288 0:dbad57390bd1 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
ram54288 0:dbad57390bd1 692 #define cDTM_CTRL1_DTM_EN (1<<6)
ram54288 0:dbad57390bd1 693 #define cDTM_CTRL1_PAGE5 (1<<5)
ram54288 0:dbad57390bd1 694 #define cDTM_CTRL1_PAGE4 (1<<4)
ram54288 0:dbad57390bd1 695 #define cDTM_CTRL1_PAGE3 (1<<3)
ram54288 0:dbad57390bd1 696 #define cDTM_CTRL1_PAGE2 (1<<2)
ram54288 0:dbad57390bd1 697 #define cDTM_CTRL1_PAGE1 (1<<1)
ram54288 0:dbad57390bd1 698 #define cDTM_CTRL1_PAGE0 (1<<0)
ram54288 0:dbad57390bd1 699
ram54288 0:dbad57390bd1 700 // TX_MODE_CTRL
ram54288 0:dbad57390bd1 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
ram54288 0:dbad57390bd1 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
ram54288 0:dbad57390bd1 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
ram54288 0:dbad57390bd1 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
ram54288 0:dbad57390bd1 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
ram54288 0:dbad57390bd1 706
ram54288 0:dbad57390bd1 707 #define cTX_MODE_CTRL_DTS_MASK (7)
ram54288 0:dbad57390bd1 708
ram54288 0:dbad57390bd1 709 // CLK_OUT_CTRL bits
ram54288 0:dbad57390bd1 710 #define cCLK_OUT_EXTEND (1<<7)
ram54288 0:dbad57390bd1 711 #define cCLK_OUT_HIZ (1<<6)
ram54288 0:dbad57390bd1 712 #define cCLK_OUT_SR (1<<5)
ram54288 0:dbad57390bd1 713 #define cCLK_OUT_DS (1<<4)
ram54288 0:dbad57390bd1 714 #define cCLK_OUT_EN (1<<3)
ram54288 0:dbad57390bd1 715 #define cCLK_OUT_DIV_Mask (7<<0)
ram54288 0:dbad57390bd1 716
ram54288 0:dbad57390bd1 717 #define gCLK_OUT_FREQ_32_MHz (0)
ram54288 0:dbad57390bd1 718 #define gCLK_OUT_FREQ_16_MHz (1)
ram54288 0:dbad57390bd1 719 #define gCLK_OUT_FREQ_8_MHz (2)
ram54288 0:dbad57390bd1 720 #define gCLK_OUT_FREQ_4_MHz (3)
ram54288 0:dbad57390bd1 721 #define gCLK_OUT_FREQ_1_MHz (4)
ram54288 0:dbad57390bd1 722 #define gCLK_OUT_FREQ_250_KHz (5)
ram54288 0:dbad57390bd1 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
ram54288 0:dbad57390bd1 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
ram54288 0:dbad57390bd1 725 #define gCLK_OUT_FREQ_DISABLE (8)
ram54288 0:dbad57390bd1 726
ram54288 0:dbad57390bd1 727
ram54288 0:dbad57390bd1 728
ram54288 0:dbad57390bd1 729
ram54288 0:dbad57390bd1 730 #endif /* __MCR20_REG_H__ */