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easy-connect/mcr20a-rf-driver/source/MCR20Drv.h@0:dbad57390bd1, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:37:05 2017 +0000
Revision:
0:dbad57390bd1
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:dbad57390bd1 1 /*!
ram54288 0:dbad57390bd1 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:dbad57390bd1 3 * All rights reserved.
ram54288 0:dbad57390bd1 4 *
ram54288 0:dbad57390bd1 5 * \file MCR20Drv.h
ram54288 0:dbad57390bd1 6 *
ram54288 0:dbad57390bd1 7 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:dbad57390bd1 8 * are permitted provided that the following conditions are met:
ram54288 0:dbad57390bd1 9 *
ram54288 0:dbad57390bd1 10 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:dbad57390bd1 11 * of conditions and the following disclaimer.
ram54288 0:dbad57390bd1 12 *
ram54288 0:dbad57390bd1 13 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:dbad57390bd1 14 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:dbad57390bd1 15 * other materials provided with the distribution.
ram54288 0:dbad57390bd1 16 *
ram54288 0:dbad57390bd1 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:dbad57390bd1 18 * contributors may be used to endorse or promote products derived from this
ram54288 0:dbad57390bd1 19 * software without specific prior written permission.
ram54288 0:dbad57390bd1 20 *
ram54288 0:dbad57390bd1 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:dbad57390bd1 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:dbad57390bd1 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:dbad57390bd1 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:dbad57390bd1 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:dbad57390bd1 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:dbad57390bd1 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:dbad57390bd1 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:dbad57390bd1 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:dbad57390bd1 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:dbad57390bd1 31 */
ram54288 0:dbad57390bd1 32
ram54288 0:dbad57390bd1 33 #ifndef __MCR20_DRV_H__
ram54288 0:dbad57390bd1 34 #define __MCR20_DRV_H__
ram54288 0:dbad57390bd1 35
ram54288 0:dbad57390bd1 36
ram54288 0:dbad57390bd1 37 /*****************************************************************************
ram54288 0:dbad57390bd1 38 * INCLUDED HEADERS *
ram54288 0:dbad57390bd1 39 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 40 * Add to this section all the headers that this module needs to include. *
ram54288 0:dbad57390bd1 41 * Note that it is not a good practice to include header files into header *
ram54288 0:dbad57390bd1 42 * files, so use this section only if there is no other better solution. *
ram54288 0:dbad57390bd1 43 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 44 *****************************************************************************/
ram54288 0:dbad57390bd1 45
ram54288 0:dbad57390bd1 46 /*****************************************************************************
ram54288 0:dbad57390bd1 47 * PRIVATE MACROS *
ram54288 0:dbad57390bd1 48 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 49 * Add to this section all the access macros, registers mappings, bit access *
ram54288 0:dbad57390bd1 50 * macros, masks, flags etc ...
ram54288 0:dbad57390bd1 51 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 52 *****************************************************************************/
ram54288 0:dbad57390bd1 53
ram54288 0:dbad57390bd1 54 /* Disable XCVR clock output by default, to reduce power consumption */
ram54288 0:dbad57390bd1 55 #ifndef gMCR20_ClkOutFreq_d
ram54288 0:dbad57390bd1 56 #define gMCR20_ClkOutFreq_d gCLK_OUT_FREQ_DISABLE
ram54288 0:dbad57390bd1 57 #endif
ram54288 0:dbad57390bd1 58
ram54288 0:dbad57390bd1 59 /*****************************************************************************
ram54288 0:dbad57390bd1 60 * PUBLIC FUNCTIONS *
ram54288 0:dbad57390bd1 61 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 62 * Add to this section all the global functions prototype preceded (as a *
ram54288 0:dbad57390bd1 63 * good practice) by the keyword 'extern' *
ram54288 0:dbad57390bd1 64 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 65 *****************************************************************************/
ram54288 0:dbad57390bd1 66
ram54288 0:dbad57390bd1 67 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 68 * Name: MCR20Drv_Init
ram54288 0:dbad57390bd1 69 * Description: -
ram54288 0:dbad57390bd1 70 * Parameters: -
ram54288 0:dbad57390bd1 71 * Return: -
ram54288 0:dbad57390bd1 72 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 73 extern void MCR20Drv_Init
ram54288 0:dbad57390bd1 74 (
ram54288 0:dbad57390bd1 75 void
ram54288 0:dbad57390bd1 76 );
ram54288 0:dbad57390bd1 77
ram54288 0:dbad57390bd1 78 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 79 * Name: MCR20Drv_SPI_DMA_Init
ram54288 0:dbad57390bd1 80 * Description: -
ram54288 0:dbad57390bd1 81 * Parameters: -
ram54288 0:dbad57390bd1 82 * Return: -
ram54288 0:dbad57390bd1 83 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 84 void MCR20Drv_SPI_DMA_Init
ram54288 0:dbad57390bd1 85 (
ram54288 0:dbad57390bd1 86 void
ram54288 0:dbad57390bd1 87 );
ram54288 0:dbad57390bd1 88
ram54288 0:dbad57390bd1 89 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 90 * Name: MCR20Drv_Start_PB_DMA_SPI_Write
ram54288 0:dbad57390bd1 91 * Description: -
ram54288 0:dbad57390bd1 92 * Parameters: -
ram54288 0:dbad57390bd1 93 * Return: -
ram54288 0:dbad57390bd1 94 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 95 void MCR20Drv_Start_PB_DMA_SPI_Write
ram54288 0:dbad57390bd1 96 (
ram54288 0:dbad57390bd1 97 uint8_t * srcAddress,
ram54288 0:dbad57390bd1 98 uint8_t numOfBytes
ram54288 0:dbad57390bd1 99 );
ram54288 0:dbad57390bd1 100
ram54288 0:dbad57390bd1 101 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 102 * Name: MCR20Drv_Start_PB_DMA_SPI_Read
ram54288 0:dbad57390bd1 103 * Description: -
ram54288 0:dbad57390bd1 104 * Parameters: -
ram54288 0:dbad57390bd1 105 * Return: -
ram54288 0:dbad57390bd1 106 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 107 void MCR20Drv_Start_PB_DMA_SPI_Read
ram54288 0:dbad57390bd1 108 (
ram54288 0:dbad57390bd1 109 uint8_t * dstAddress,
ram54288 0:dbad57390bd1 110 uint8_t numOfBytes
ram54288 0:dbad57390bd1 111 );
ram54288 0:dbad57390bd1 112
ram54288 0:dbad57390bd1 113 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 114 * Name: MCR20Drv_DirectAccessSPIWrite
ram54288 0:dbad57390bd1 115 * Description: -
ram54288 0:dbad57390bd1 116 * Parameters: -
ram54288 0:dbad57390bd1 117 * Return: -
ram54288 0:dbad57390bd1 118 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 119 void MCR20Drv_DirectAccessSPIWrite
ram54288 0:dbad57390bd1 120 (
ram54288 0:dbad57390bd1 121 uint8_t address,
ram54288 0:dbad57390bd1 122 uint8_t value
ram54288 0:dbad57390bd1 123 );
ram54288 0:dbad57390bd1 124
ram54288 0:dbad57390bd1 125 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 126 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 127 * Description: -
ram54288 0:dbad57390bd1 128 * Parameters: -
ram54288 0:dbad57390bd1 129 * Return: -
ram54288 0:dbad57390bd1 130 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 131 void MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 132 (
ram54288 0:dbad57390bd1 133 uint8_t startAddress,
ram54288 0:dbad57390bd1 134 uint8_t * byteArray,
ram54288 0:dbad57390bd1 135 uint8_t numOfBytes
ram54288 0:dbad57390bd1 136 );
ram54288 0:dbad57390bd1 137
ram54288 0:dbad57390bd1 138 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 139 * Name: MCR20Drv_PB_SPIBurstWrite
ram54288 0:dbad57390bd1 140 * Description: -
ram54288 0:dbad57390bd1 141 * Parameters: -
ram54288 0:dbad57390bd1 142 * Return: -
ram54288 0:dbad57390bd1 143 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 144 void MCR20Drv_PB_SPIBurstWrite
ram54288 0:dbad57390bd1 145 (
ram54288 0:dbad57390bd1 146 uint8_t * byteArray,
ram54288 0:dbad57390bd1 147 uint8_t numOfBytes
ram54288 0:dbad57390bd1 148 );
ram54288 0:dbad57390bd1 149
ram54288 0:dbad57390bd1 150 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 151 * Name: MCR20Drv_DirectAccessSPIRead
ram54288 0:dbad57390bd1 152 * Description: -
ram54288 0:dbad57390bd1 153 * Parameters: -
ram54288 0:dbad57390bd1 154 * Return: -
ram54288 0:dbad57390bd1 155 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 156 uint8_t MCR20Drv_DirectAccessSPIRead
ram54288 0:dbad57390bd1 157 (
ram54288 0:dbad57390bd1 158 uint8_t address
ram54288 0:dbad57390bd1 159 );
ram54288 0:dbad57390bd1 160
ram54288 0:dbad57390bd1 161 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 162 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
ram54288 0:dbad57390bd1 163 * Description: -
ram54288 0:dbad57390bd1 164 * Parameters: -
ram54288 0:dbad57390bd1 165 * Return: -
ram54288 0:dbad57390bd1 166 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 167
ram54288 0:dbad57390bd1 168 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
ram54288 0:dbad57390bd1 169 (
ram54288 0:dbad57390bd1 170 uint8_t startAddress,
ram54288 0:dbad57390bd1 171 uint8_t * byteArray,
ram54288 0:dbad57390bd1 172 uint8_t numOfBytes
ram54288 0:dbad57390bd1 173 );
ram54288 0:dbad57390bd1 174
ram54288 0:dbad57390bd1 175 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 176 * Name: MCR20Drv_PB_SPIByteWrite
ram54288 0:dbad57390bd1 177 * Description: -
ram54288 0:dbad57390bd1 178 * Parameters: -
ram54288 0:dbad57390bd1 179 * Return: -
ram54288 0:dbad57390bd1 180 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 181 void MCR20Drv_PB_SPIByteWrite
ram54288 0:dbad57390bd1 182 (
ram54288 0:dbad57390bd1 183 uint8_t address,
ram54288 0:dbad57390bd1 184 uint8_t value
ram54288 0:dbad57390bd1 185 );
ram54288 0:dbad57390bd1 186
ram54288 0:dbad57390bd1 187 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 188 * Name: MCR20Drv_PB_SPIBurstRead
ram54288 0:dbad57390bd1 189 * Description: -
ram54288 0:dbad57390bd1 190 * Parameters: -
ram54288 0:dbad57390bd1 191 * Return: -
ram54288 0:dbad57390bd1 192 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 193 uint8_t MCR20Drv_PB_SPIBurstRead
ram54288 0:dbad57390bd1 194 (
ram54288 0:dbad57390bd1 195 uint8_t * byteArray,
ram54288 0:dbad57390bd1 196 uint8_t numOfBytes
ram54288 0:dbad57390bd1 197 );
ram54288 0:dbad57390bd1 198
ram54288 0:dbad57390bd1 199 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 200 * Name: MCR20Drv_IndirectAccessSPIWrite
ram54288 0:dbad57390bd1 201 * Description: -
ram54288 0:dbad57390bd1 202 * Parameters: -
ram54288 0:dbad57390bd1 203 * Return: -
ram54288 0:dbad57390bd1 204 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 205 void MCR20Drv_IndirectAccessSPIWrite
ram54288 0:dbad57390bd1 206 (
ram54288 0:dbad57390bd1 207 uint8_t address,
ram54288 0:dbad57390bd1 208 uint8_t value
ram54288 0:dbad57390bd1 209 );
ram54288 0:dbad57390bd1 210
ram54288 0:dbad57390bd1 211 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 212 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 213 * Description: -
ram54288 0:dbad57390bd1 214 * Parameters: -
ram54288 0:dbad57390bd1 215 * Return: -
ram54288 0:dbad57390bd1 216 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 217 void MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 218 (
ram54288 0:dbad57390bd1 219 uint8_t startAddress,
ram54288 0:dbad57390bd1 220 uint8_t * byteArray,
ram54288 0:dbad57390bd1 221 uint8_t numOfBytes
ram54288 0:dbad57390bd1 222 );
ram54288 0:dbad57390bd1 223
ram54288 0:dbad57390bd1 224 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 225 * Name: MCR20Drv_IndirectAccessSPIRead
ram54288 0:dbad57390bd1 226 * Description: -
ram54288 0:dbad57390bd1 227 * Parameters: -
ram54288 0:dbad57390bd1 228 * Return: -
ram54288 0:dbad57390bd1 229 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 230 uint8_t MCR20Drv_IndirectAccessSPIRead
ram54288 0:dbad57390bd1 231 (
ram54288 0:dbad57390bd1 232 uint8_t address
ram54288 0:dbad57390bd1 233 );
ram54288 0:dbad57390bd1 234 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 235 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:dbad57390bd1 236 * Description: -
ram54288 0:dbad57390bd1 237 * Parameters: -
ram54288 0:dbad57390bd1 238 * Return: -
ram54288 0:dbad57390bd1 239 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 240 void MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:dbad57390bd1 241 (
ram54288 0:dbad57390bd1 242 uint8_t startAddress,
ram54288 0:dbad57390bd1 243 uint8_t * byteArray,
ram54288 0:dbad57390bd1 244 uint8_t numOfBytes
ram54288 0:dbad57390bd1 245 );
ram54288 0:dbad57390bd1 246
ram54288 0:dbad57390bd1 247 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 248 * Name: MCR20Drv_IsIrqPending
ram54288 0:dbad57390bd1 249 * Description: -
ram54288 0:dbad57390bd1 250 * Parameters: -
ram54288 0:dbad57390bd1 251 * Return: -
ram54288 0:dbad57390bd1 252 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 253 uint32_t MCR20Drv_IsIrqPending
ram54288 0:dbad57390bd1 254 (
ram54288 0:dbad57390bd1 255 void
ram54288 0:dbad57390bd1 256 );
ram54288 0:dbad57390bd1 257
ram54288 0:dbad57390bd1 258 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 259 * Name: MCR20Drv_IRQ_Disable
ram54288 0:dbad57390bd1 260 * Description: -
ram54288 0:dbad57390bd1 261 * Parameters: -
ram54288 0:dbad57390bd1 262 * Return: -
ram54288 0:dbad57390bd1 263 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 264 void MCR20Drv_IRQ_Disable
ram54288 0:dbad57390bd1 265 (
ram54288 0:dbad57390bd1 266 void
ram54288 0:dbad57390bd1 267 );
ram54288 0:dbad57390bd1 268
ram54288 0:dbad57390bd1 269 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 270 * Name: MCR20Drv_IRQ_Enable
ram54288 0:dbad57390bd1 271 * Description: -
ram54288 0:dbad57390bd1 272 * Parameters: -
ram54288 0:dbad57390bd1 273 * Return: -
ram54288 0:dbad57390bd1 274 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 275 void MCR20Drv_IRQ_Enable
ram54288 0:dbad57390bd1 276 (
ram54288 0:dbad57390bd1 277 void
ram54288 0:dbad57390bd1 278 );
ram54288 0:dbad57390bd1 279
ram54288 0:dbad57390bd1 280 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 281 * Name: MCR20Drv_RST_PortConfig
ram54288 0:dbad57390bd1 282 * Description: -
ram54288 0:dbad57390bd1 283 * Parameters: -
ram54288 0:dbad57390bd1 284 * Return: -
ram54288 0:dbad57390bd1 285 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 286 void MCR20Drv_RST_B_PortConfig
ram54288 0:dbad57390bd1 287 (
ram54288 0:dbad57390bd1 288 void
ram54288 0:dbad57390bd1 289 );
ram54288 0:dbad57390bd1 290
ram54288 0:dbad57390bd1 291 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 292 * Name: MCR20Drv_RST_Assert
ram54288 0:dbad57390bd1 293 * Description: -
ram54288 0:dbad57390bd1 294 * Parameters: -
ram54288 0:dbad57390bd1 295 * Return: -
ram54288 0:dbad57390bd1 296 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 297 void MCR20Drv_RST_B_Assert
ram54288 0:dbad57390bd1 298 (
ram54288 0:dbad57390bd1 299 void
ram54288 0:dbad57390bd1 300 );
ram54288 0:dbad57390bd1 301
ram54288 0:dbad57390bd1 302 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 303 * Name: MCR20Drv_RST_Deassert
ram54288 0:dbad57390bd1 304 * Description: -
ram54288 0:dbad57390bd1 305 * Parameters: -
ram54288 0:dbad57390bd1 306 * Return: -
ram54288 0:dbad57390bd1 307 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 308 void MCR20Drv_RST_B_Deassert
ram54288 0:dbad57390bd1 309 (
ram54288 0:dbad57390bd1 310 void
ram54288 0:dbad57390bd1 311 );
ram54288 0:dbad57390bd1 312
ram54288 0:dbad57390bd1 313 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 314 * Name: MCR20Drv_SoftRST_Assert
ram54288 0:dbad57390bd1 315 * Description: -
ram54288 0:dbad57390bd1 316 * Parameters: -
ram54288 0:dbad57390bd1 317 * Return: -
ram54288 0:dbad57390bd1 318 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 319 void MCR20Drv_SoftRST_Assert
ram54288 0:dbad57390bd1 320 (
ram54288 0:dbad57390bd1 321 void
ram54288 0:dbad57390bd1 322 );
ram54288 0:dbad57390bd1 323
ram54288 0:dbad57390bd1 324 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 325 * Name: MCR20Drv_SoftRST_Deassert
ram54288 0:dbad57390bd1 326 * Description: -
ram54288 0:dbad57390bd1 327 * Parameters: -
ram54288 0:dbad57390bd1 328 * Return: -
ram54288 0:dbad57390bd1 329 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 330 void MCR20Drv_SoftRST_Deassert
ram54288 0:dbad57390bd1 331 (
ram54288 0:dbad57390bd1 332 void
ram54288 0:dbad57390bd1 333 );
ram54288 0:dbad57390bd1 334
ram54288 0:dbad57390bd1 335
ram54288 0:dbad57390bd1 336 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 337 * Name: MCR20Drv_RESET
ram54288 0:dbad57390bd1 338 * Description: -
ram54288 0:dbad57390bd1 339 * Parameters: -
ram54288 0:dbad57390bd1 340 * Return: -
ram54288 0:dbad57390bd1 341 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 342 void MCR20Drv_RESET
ram54288 0:dbad57390bd1 343 (
ram54288 0:dbad57390bd1 344 void
ram54288 0:dbad57390bd1 345 );
ram54288 0:dbad57390bd1 346
ram54288 0:dbad57390bd1 347 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 348 * Name: MCR20Drv_Soft_RESET
ram54288 0:dbad57390bd1 349 * Description: -
ram54288 0:dbad57390bd1 350 * Parameters: -
ram54288 0:dbad57390bd1 351 * Return: -
ram54288 0:dbad57390bd1 352 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 353 void MCR20Drv_Soft_RESET
ram54288 0:dbad57390bd1 354 (
ram54288 0:dbad57390bd1 355 void
ram54288 0:dbad57390bd1 356 );
ram54288 0:dbad57390bd1 357
ram54288 0:dbad57390bd1 358 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 359 * Name: MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:dbad57390bd1 360 * Description: -
ram54288 0:dbad57390bd1 361 * Parameters: -
ram54288 0:dbad57390bd1 362 * Return: -
ram54288 0:dbad57390bd1 363 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 364 void MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:dbad57390bd1 365 (
ram54288 0:dbad57390bd1 366 uint8_t freqDiv
ram54288 0:dbad57390bd1 367 );
ram54288 0:dbad57390bd1 368
ram54288 0:dbad57390bd1 369 #define ProtectFromMCR20Interrupt() MCR20Drv_IRQ_Disable()
ram54288 0:dbad57390bd1 370 #define UnprotectFromMCR20Interrupt() MCR20Drv_IRQ_Enable()
ram54288 0:dbad57390bd1 371
ram54288 0:dbad57390bd1 372 #endif /* __MCR20_DRV_H__ */