Ram Gandikota / Mbed OS IOTMetronome

FRDM K64F Metronome

easy-connect/mcr20a-rf-driver/source/MCR20Drv.c@0:dbad57390bd1, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:37:05 2017 +0000
Revision:
0:dbad57390bd1
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:dbad57390bd1 1 /*!
ram54288 0:dbad57390bd1 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:dbad57390bd1 3 * All rights reserved.
ram54288 0:dbad57390bd1 4 *
ram54288 0:dbad57390bd1 5 * \file MCR20Drv.c
ram54288 0:dbad57390bd1 6 *
ram54288 0:dbad57390bd1 7 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:dbad57390bd1 8 * are permitted provided that the following conditions are met:
ram54288 0:dbad57390bd1 9 *
ram54288 0:dbad57390bd1 10 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:dbad57390bd1 11 * of conditions and the following disclaimer.
ram54288 0:dbad57390bd1 12 *
ram54288 0:dbad57390bd1 13 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:dbad57390bd1 14 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:dbad57390bd1 15 * other materials provided with the distribution.
ram54288 0:dbad57390bd1 16 *
ram54288 0:dbad57390bd1 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:dbad57390bd1 18 * contributors may be used to endorse or promote products derived from this
ram54288 0:dbad57390bd1 19 * software without specific prior written permission.
ram54288 0:dbad57390bd1 20 *
ram54288 0:dbad57390bd1 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:dbad57390bd1 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:dbad57390bd1 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:dbad57390bd1 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:dbad57390bd1 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:dbad57390bd1 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:dbad57390bd1 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:dbad57390bd1 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:dbad57390bd1 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:dbad57390bd1 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:dbad57390bd1 31 */
ram54288 0:dbad57390bd1 32
ram54288 0:dbad57390bd1 33
ram54288 0:dbad57390bd1 34 /*****************************************************************************
ram54288 0:dbad57390bd1 35 * INCLUDED HEADERS *
ram54288 0:dbad57390bd1 36 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 37 * Add to this section all the headers that this module needs to include. *
ram54288 0:dbad57390bd1 38 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 39 *****************************************************************************/
ram54288 0:dbad57390bd1 40
ram54288 0:dbad57390bd1 41 #include "platform/arm_hal_interrupt.h"
ram54288 0:dbad57390bd1 42 #include "MCR20Drv.h"
ram54288 0:dbad57390bd1 43 #include "MCR20Reg.h"
ram54288 0:dbad57390bd1 44 #include "XcvrSpi.h"
ram54288 0:dbad57390bd1 45
ram54288 0:dbad57390bd1 46
ram54288 0:dbad57390bd1 47 /*****************************************************************************
ram54288 0:dbad57390bd1 48 * PRIVATE VARIABLES *
ram54288 0:dbad57390bd1 49 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 50 * Add to this section all the variables and constants that have local *
ram54288 0:dbad57390bd1 51 * (file) scope. *
ram54288 0:dbad57390bd1 52 * Each of this declarations shall be preceded by the 'static' keyword. *
ram54288 0:dbad57390bd1 53 * These variables / constants cannot be accessed outside this module. *
ram54288 0:dbad57390bd1 54 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 55 *****************************************************************************/
ram54288 0:dbad57390bd1 56 uint32_t mPhyIrqDisableCnt = 1;
ram54288 0:dbad57390bd1 57
ram54288 0:dbad57390bd1 58 /*****************************************************************************
ram54288 0:dbad57390bd1 59 * PUBLIC VARIABLES *
ram54288 0:dbad57390bd1 60 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 61 * Add to this section all the variables and constants that have global *
ram54288 0:dbad57390bd1 62 * (project) scope. *
ram54288 0:dbad57390bd1 63 * These variables / constants can be accessed outside this module. *
ram54288 0:dbad57390bd1 64 * These variables / constants shall be preceded by the 'extern' keyword in *
ram54288 0:dbad57390bd1 65 * the interface header. *
ram54288 0:dbad57390bd1 66 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 67 *****************************************************************************/
ram54288 0:dbad57390bd1 68
ram54288 0:dbad57390bd1 69 /*****************************************************************************
ram54288 0:dbad57390bd1 70 * PRIVATE FUNCTIONS PROTOTYPES *
ram54288 0:dbad57390bd1 71 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 72 * Add to this section all the functions prototypes that have local (file) *
ram54288 0:dbad57390bd1 73 * scope. *
ram54288 0:dbad57390bd1 74 * These functions cannot be accessed outside this module. *
ram54288 0:dbad57390bd1 75 * These declarations shall be preceded by the 'static' keyword. *
ram54288 0:dbad57390bd1 76 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 77 *****************************************************************************/
ram54288 0:dbad57390bd1 78
ram54288 0:dbad57390bd1 79 /*****************************************************************************
ram54288 0:dbad57390bd1 80 * PRIVATE FUNCTIONS *
ram54288 0:dbad57390bd1 81 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 82 * Add to this section all the functions that have local (file) scope. *
ram54288 0:dbad57390bd1 83 * These functions cannot be accessed outside this module. *
ram54288 0:dbad57390bd1 84 * These definitions shall be preceded by the 'static' keyword. *
ram54288 0:dbad57390bd1 85 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 86 *****************************************************************************/
ram54288 0:dbad57390bd1 87
ram54288 0:dbad57390bd1 88
ram54288 0:dbad57390bd1 89 /*****************************************************************************
ram54288 0:dbad57390bd1 90 * PUBLIC FUNCTIONS *
ram54288 0:dbad57390bd1 91 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 92 * Add to this section all the functions that have global (project) scope. *
ram54288 0:dbad57390bd1 93 * These functions can be accessed outside this module. *
ram54288 0:dbad57390bd1 94 * These functions shall have their declarations (prototypes) within the *
ram54288 0:dbad57390bd1 95 * interface header file and shall be preceded by the 'extern' keyword. *
ram54288 0:dbad57390bd1 96 *---------------------------------------------------------------------------*
ram54288 0:dbad57390bd1 97 *****************************************************************************/
ram54288 0:dbad57390bd1 98
ram54288 0:dbad57390bd1 99 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 100 * Name: MCR20Drv_Init
ram54288 0:dbad57390bd1 101 * Description: -
ram54288 0:dbad57390bd1 102 * Parameters: -
ram54288 0:dbad57390bd1 103 * Return: -
ram54288 0:dbad57390bd1 104 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 105 void MCR20Drv_Init
ram54288 0:dbad57390bd1 106 (
ram54288 0:dbad57390bd1 107 void
ram54288 0:dbad57390bd1 108 )
ram54288 0:dbad57390bd1 109 {
ram54288 0:dbad57390bd1 110 xcvr_spi_init(gXcvrSpiInstance_c);
ram54288 0:dbad57390bd1 111 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:dbad57390bd1 112
ram54288 0:dbad57390bd1 113 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 114 MCR20Drv_RST_B_Deassert();
ram54288 0:dbad57390bd1 115 RF_IRQ_Init();
ram54288 0:dbad57390bd1 116 RF_IRQ_Disable();
ram54288 0:dbad57390bd1 117 mPhyIrqDisableCnt = 1;
ram54288 0:dbad57390bd1 118 }
ram54288 0:dbad57390bd1 119
ram54288 0:dbad57390bd1 120 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 121 * Name: MCR20Drv_DirectAccessSPIWrite
ram54288 0:dbad57390bd1 122 * Description: -
ram54288 0:dbad57390bd1 123 * Parameters: -
ram54288 0:dbad57390bd1 124 * Return: -
ram54288 0:dbad57390bd1 125 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 126 void MCR20Drv_DirectAccessSPIWrite
ram54288 0:dbad57390bd1 127 (
ram54288 0:dbad57390bd1 128 uint8_t address,
ram54288 0:dbad57390bd1 129 uint8_t value
ram54288 0:dbad57390bd1 130 )
ram54288 0:dbad57390bd1 131 {
ram54288 0:dbad57390bd1 132 uint16_t txData;
ram54288 0:dbad57390bd1 133
ram54288 0:dbad57390bd1 134 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 135
ram54288 0:dbad57390bd1 136 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:dbad57390bd1 137
ram54288 0:dbad57390bd1 138 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 139
ram54288 0:dbad57390bd1 140 txData = (address & TransceiverSPI_DirectRegisterAddressMask);
ram54288 0:dbad57390bd1 141 txData |= value << 8;
ram54288 0:dbad57390bd1 142
ram54288 0:dbad57390bd1 143 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
ram54288 0:dbad57390bd1 144
ram54288 0:dbad57390bd1 145 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 146 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 147 }
ram54288 0:dbad57390bd1 148
ram54288 0:dbad57390bd1 149 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 150 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 151 * Description: -
ram54288 0:dbad57390bd1 152 * Parameters: -
ram54288 0:dbad57390bd1 153 * Return: -
ram54288 0:dbad57390bd1 154 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 155 void MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 156 (
ram54288 0:dbad57390bd1 157 uint8_t startAddress,
ram54288 0:dbad57390bd1 158 uint8_t * byteArray,
ram54288 0:dbad57390bd1 159 uint8_t numOfBytes
ram54288 0:dbad57390bd1 160 )
ram54288 0:dbad57390bd1 161 {
ram54288 0:dbad57390bd1 162 uint8_t txData;
ram54288 0:dbad57390bd1 163
ram54288 0:dbad57390bd1 164 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:dbad57390bd1 165 {
ram54288 0:dbad57390bd1 166 return;
ram54288 0:dbad57390bd1 167 }
ram54288 0:dbad57390bd1 168
ram54288 0:dbad57390bd1 169 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 170
ram54288 0:dbad57390bd1 171 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:dbad57390bd1 172
ram54288 0:dbad57390bd1 173 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 174
ram54288 0:dbad57390bd1 175 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
ram54288 0:dbad57390bd1 176
ram54288 0:dbad57390bd1 177 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
ram54288 0:dbad57390bd1 178 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
ram54288 0:dbad57390bd1 179
ram54288 0:dbad57390bd1 180 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 181 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 182 }
ram54288 0:dbad57390bd1 183
ram54288 0:dbad57390bd1 184 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 185 * Name: MCR20Drv_PB_SPIByteWrite
ram54288 0:dbad57390bd1 186 * Description: -
ram54288 0:dbad57390bd1 187 * Parameters: -
ram54288 0:dbad57390bd1 188 * Return: -
ram54288 0:dbad57390bd1 189 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 190 void MCR20Drv_PB_SPIByteWrite
ram54288 0:dbad57390bd1 191 (
ram54288 0:dbad57390bd1 192 uint8_t address,
ram54288 0:dbad57390bd1 193 uint8_t value
ram54288 0:dbad57390bd1 194 )
ram54288 0:dbad57390bd1 195 {
ram54288 0:dbad57390bd1 196 uint32_t txData;
ram54288 0:dbad57390bd1 197
ram54288 0:dbad57390bd1 198 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 199
ram54288 0:dbad57390bd1 200 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:dbad57390bd1 201
ram54288 0:dbad57390bd1 202 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 203
ram54288 0:dbad57390bd1 204 txData = TransceiverSPI_WriteSelect |
ram54288 0:dbad57390bd1 205 TransceiverSPI_PacketBuffAccessSelect |
ram54288 0:dbad57390bd1 206 TransceiverSPI_PacketBuffByteModeSelect;
ram54288 0:dbad57390bd1 207 txData |= (address) << 8;
ram54288 0:dbad57390bd1 208 txData |= (value) << 16;
ram54288 0:dbad57390bd1 209
ram54288 0:dbad57390bd1 210 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
ram54288 0:dbad57390bd1 211
ram54288 0:dbad57390bd1 212 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 213 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 214 }
ram54288 0:dbad57390bd1 215
ram54288 0:dbad57390bd1 216 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 217 * Name: MCR20Drv_PB_SPIBurstWrite
ram54288 0:dbad57390bd1 218 * Description: -
ram54288 0:dbad57390bd1 219 * Parameters: -
ram54288 0:dbad57390bd1 220 * Return: -
ram54288 0:dbad57390bd1 221 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 222 void MCR20Drv_PB_SPIBurstWrite
ram54288 0:dbad57390bd1 223 (
ram54288 0:dbad57390bd1 224 uint8_t * byteArray,
ram54288 0:dbad57390bd1 225 uint8_t numOfBytes
ram54288 0:dbad57390bd1 226 )
ram54288 0:dbad57390bd1 227 {
ram54288 0:dbad57390bd1 228 uint8_t txData;
ram54288 0:dbad57390bd1 229
ram54288 0:dbad57390bd1 230 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:dbad57390bd1 231 {
ram54288 0:dbad57390bd1 232 return;
ram54288 0:dbad57390bd1 233 }
ram54288 0:dbad57390bd1 234
ram54288 0:dbad57390bd1 235 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 236
ram54288 0:dbad57390bd1 237 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:dbad57390bd1 238
ram54288 0:dbad57390bd1 239 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 240
ram54288 0:dbad57390bd1 241 txData = TransceiverSPI_WriteSelect |
ram54288 0:dbad57390bd1 242 TransceiverSPI_PacketBuffAccessSelect |
ram54288 0:dbad57390bd1 243 TransceiverSPI_PacketBuffBurstModeSelect;
ram54288 0:dbad57390bd1 244
ram54288 0:dbad57390bd1 245 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, 1);
ram54288 0:dbad57390bd1 246 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
ram54288 0:dbad57390bd1 247
ram54288 0:dbad57390bd1 248 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 249 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 250 }
ram54288 0:dbad57390bd1 251
ram54288 0:dbad57390bd1 252 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 253 * Name: MCR20Drv_DirectAccessSPIRead
ram54288 0:dbad57390bd1 254 * Description: -
ram54288 0:dbad57390bd1 255 * Parameters: -
ram54288 0:dbad57390bd1 256 * Return: -
ram54288 0:dbad57390bd1 257 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 258
ram54288 0:dbad57390bd1 259 uint8_t MCR20Drv_DirectAccessSPIRead
ram54288 0:dbad57390bd1 260 (
ram54288 0:dbad57390bd1 261 uint8_t address
ram54288 0:dbad57390bd1 262 )
ram54288 0:dbad57390bd1 263 {
ram54288 0:dbad57390bd1 264 uint8_t txData;
ram54288 0:dbad57390bd1 265 uint8_t rxData;
ram54288 0:dbad57390bd1 266
ram54288 0:dbad57390bd1 267 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 268
ram54288 0:dbad57390bd1 269 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:dbad57390bd1 270
ram54288 0:dbad57390bd1 271 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 272
ram54288 0:dbad57390bd1 273 txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
ram54288 0:dbad57390bd1 274 TransceiverSPI_ReadSelect;
ram54288 0:dbad57390bd1 275
ram54288 0:dbad57390bd1 276 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
ram54288 0:dbad57390bd1 277 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
ram54288 0:dbad57390bd1 278
ram54288 0:dbad57390bd1 279 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 280 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 281
ram54288 0:dbad57390bd1 282 return rxData;
ram54288 0:dbad57390bd1 283
ram54288 0:dbad57390bd1 284 }
ram54288 0:dbad57390bd1 285
ram54288 0:dbad57390bd1 286 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 287 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
ram54288 0:dbad57390bd1 288 * Description: -
ram54288 0:dbad57390bd1 289 * Parameters: -
ram54288 0:dbad57390bd1 290 * Return: -
ram54288 0:dbad57390bd1 291 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 292 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
ram54288 0:dbad57390bd1 293 (
ram54288 0:dbad57390bd1 294 uint8_t startAddress,
ram54288 0:dbad57390bd1 295 uint8_t * byteArray,
ram54288 0:dbad57390bd1 296 uint8_t numOfBytes
ram54288 0:dbad57390bd1 297 )
ram54288 0:dbad57390bd1 298 {
ram54288 0:dbad57390bd1 299 uint8_t txData;
ram54288 0:dbad57390bd1 300 uint8_t phyIRQSTS1;
ram54288 0:dbad57390bd1 301
ram54288 0:dbad57390bd1 302 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:dbad57390bd1 303 {
ram54288 0:dbad57390bd1 304 return 0;
ram54288 0:dbad57390bd1 305 }
ram54288 0:dbad57390bd1 306
ram54288 0:dbad57390bd1 307 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 308
ram54288 0:dbad57390bd1 309 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:dbad57390bd1 310
ram54288 0:dbad57390bd1 311 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 312
ram54288 0:dbad57390bd1 313 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
ram54288 0:dbad57390bd1 314 TransceiverSPI_ReadSelect;
ram54288 0:dbad57390bd1 315
ram54288 0:dbad57390bd1 316 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
ram54288 0:dbad57390bd1 317 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
ram54288 0:dbad57390bd1 318
ram54288 0:dbad57390bd1 319 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 320 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 321
ram54288 0:dbad57390bd1 322 return phyIRQSTS1;
ram54288 0:dbad57390bd1 323 }
ram54288 0:dbad57390bd1 324
ram54288 0:dbad57390bd1 325 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 326 * Name: MCR20Drv_PB_SPIBurstRead
ram54288 0:dbad57390bd1 327 * Description: -
ram54288 0:dbad57390bd1 328 * Parameters: -
ram54288 0:dbad57390bd1 329 * Return: -
ram54288 0:dbad57390bd1 330 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 331 uint8_t MCR20Drv_PB_SPIBurstRead
ram54288 0:dbad57390bd1 332 (
ram54288 0:dbad57390bd1 333 uint8_t * byteArray,
ram54288 0:dbad57390bd1 334 uint8_t numOfBytes
ram54288 0:dbad57390bd1 335 )
ram54288 0:dbad57390bd1 336 {
ram54288 0:dbad57390bd1 337 uint8_t txData;
ram54288 0:dbad57390bd1 338 uint8_t phyIRQSTS1;
ram54288 0:dbad57390bd1 339
ram54288 0:dbad57390bd1 340 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:dbad57390bd1 341 {
ram54288 0:dbad57390bd1 342 return 0;
ram54288 0:dbad57390bd1 343 }
ram54288 0:dbad57390bd1 344
ram54288 0:dbad57390bd1 345 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 346
ram54288 0:dbad57390bd1 347 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:dbad57390bd1 348
ram54288 0:dbad57390bd1 349 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 350
ram54288 0:dbad57390bd1 351 txData = TransceiverSPI_ReadSelect |
ram54288 0:dbad57390bd1 352 TransceiverSPI_PacketBuffAccessSelect |
ram54288 0:dbad57390bd1 353 TransceiverSPI_PacketBuffBurstModeSelect;
ram54288 0:dbad57390bd1 354
ram54288 0:dbad57390bd1 355 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
ram54288 0:dbad57390bd1 356 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
ram54288 0:dbad57390bd1 357
ram54288 0:dbad57390bd1 358 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 359 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 360
ram54288 0:dbad57390bd1 361 return phyIRQSTS1;
ram54288 0:dbad57390bd1 362 }
ram54288 0:dbad57390bd1 363
ram54288 0:dbad57390bd1 364 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 365 * Name: MCR20Drv_IndirectAccessSPIWrite
ram54288 0:dbad57390bd1 366 * Description: -
ram54288 0:dbad57390bd1 367 * Parameters: -
ram54288 0:dbad57390bd1 368 * Return: -
ram54288 0:dbad57390bd1 369 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 370 void MCR20Drv_IndirectAccessSPIWrite
ram54288 0:dbad57390bd1 371 (
ram54288 0:dbad57390bd1 372 uint8_t address,
ram54288 0:dbad57390bd1 373 uint8_t value
ram54288 0:dbad57390bd1 374 )
ram54288 0:dbad57390bd1 375 {
ram54288 0:dbad57390bd1 376 uint32_t txData;
ram54288 0:dbad57390bd1 377
ram54288 0:dbad57390bd1 378 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 379
ram54288 0:dbad57390bd1 380 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:dbad57390bd1 381
ram54288 0:dbad57390bd1 382 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 383
ram54288 0:dbad57390bd1 384 txData = TransceiverSPI_IARIndexReg;
ram54288 0:dbad57390bd1 385 txData |= (address) << 8;
ram54288 0:dbad57390bd1 386 txData |= (value) << 16;
ram54288 0:dbad57390bd1 387
ram54288 0:dbad57390bd1 388 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
ram54288 0:dbad57390bd1 389
ram54288 0:dbad57390bd1 390 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 391 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 392 }
ram54288 0:dbad57390bd1 393
ram54288 0:dbad57390bd1 394 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 395 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 396 * Description: -
ram54288 0:dbad57390bd1 397 * Parameters: -
ram54288 0:dbad57390bd1 398 * Return: -
ram54288 0:dbad57390bd1 399 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 400 void MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:dbad57390bd1 401 (
ram54288 0:dbad57390bd1 402 uint8_t startAddress,
ram54288 0:dbad57390bd1 403 uint8_t * byteArray,
ram54288 0:dbad57390bd1 404 uint8_t numOfBytes
ram54288 0:dbad57390bd1 405 )
ram54288 0:dbad57390bd1 406 {
ram54288 0:dbad57390bd1 407 uint16_t txData;
ram54288 0:dbad57390bd1 408
ram54288 0:dbad57390bd1 409 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:dbad57390bd1 410 {
ram54288 0:dbad57390bd1 411 return;
ram54288 0:dbad57390bd1 412 }
ram54288 0:dbad57390bd1 413
ram54288 0:dbad57390bd1 414 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 415
ram54288 0:dbad57390bd1 416 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:dbad57390bd1 417
ram54288 0:dbad57390bd1 418 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 419
ram54288 0:dbad57390bd1 420 txData = TransceiverSPI_IARIndexReg;
ram54288 0:dbad57390bd1 421 txData |= (startAddress) << 8;
ram54288 0:dbad57390bd1 422
ram54288 0:dbad57390bd1 423 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
ram54288 0:dbad57390bd1 424 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes);
ram54288 0:dbad57390bd1 425
ram54288 0:dbad57390bd1 426 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 427 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 428 }
ram54288 0:dbad57390bd1 429
ram54288 0:dbad57390bd1 430 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 431 * Name: MCR20Drv_IndirectAccessSPIRead
ram54288 0:dbad57390bd1 432 * Description: -
ram54288 0:dbad57390bd1 433 * Parameters: -
ram54288 0:dbad57390bd1 434 * Return: -
ram54288 0:dbad57390bd1 435 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 436 uint8_t MCR20Drv_IndirectAccessSPIRead
ram54288 0:dbad57390bd1 437 (
ram54288 0:dbad57390bd1 438 uint8_t address
ram54288 0:dbad57390bd1 439 )
ram54288 0:dbad57390bd1 440 {
ram54288 0:dbad57390bd1 441 uint16_t txData;
ram54288 0:dbad57390bd1 442 uint8_t rxData;
ram54288 0:dbad57390bd1 443
ram54288 0:dbad57390bd1 444 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 445
ram54288 0:dbad57390bd1 446 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:dbad57390bd1 447
ram54288 0:dbad57390bd1 448 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 449
ram54288 0:dbad57390bd1 450 txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
ram54288 0:dbad57390bd1 451 txData |= (address) << 8;
ram54288 0:dbad57390bd1 452
ram54288 0:dbad57390bd1 453 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
ram54288 0:dbad57390bd1 454 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
ram54288 0:dbad57390bd1 455
ram54288 0:dbad57390bd1 456 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 457 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 458
ram54288 0:dbad57390bd1 459 return rxData;
ram54288 0:dbad57390bd1 460 }
ram54288 0:dbad57390bd1 461
ram54288 0:dbad57390bd1 462 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 463 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:dbad57390bd1 464 * Description: -
ram54288 0:dbad57390bd1 465 * Parameters: -
ram54288 0:dbad57390bd1 466 * Return: -
ram54288 0:dbad57390bd1 467 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 468 void MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:dbad57390bd1 469 (
ram54288 0:dbad57390bd1 470 uint8_t startAddress,
ram54288 0:dbad57390bd1 471 uint8_t * byteArray,
ram54288 0:dbad57390bd1 472 uint8_t numOfBytes
ram54288 0:dbad57390bd1 473 )
ram54288 0:dbad57390bd1 474 {
ram54288 0:dbad57390bd1 475 uint16_t txData;
ram54288 0:dbad57390bd1 476
ram54288 0:dbad57390bd1 477 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:dbad57390bd1 478 {
ram54288 0:dbad57390bd1 479 return;
ram54288 0:dbad57390bd1 480 }
ram54288 0:dbad57390bd1 481
ram54288 0:dbad57390bd1 482 ProtectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 483
ram54288 0:dbad57390bd1 484 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:dbad57390bd1 485
ram54288 0:dbad57390bd1 486 gXcvrAssertCS_d();
ram54288 0:dbad57390bd1 487
ram54288 0:dbad57390bd1 488 txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
ram54288 0:dbad57390bd1 489 txData |= (startAddress) << 8;
ram54288 0:dbad57390bd1 490
ram54288 0:dbad57390bd1 491 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
ram54288 0:dbad57390bd1 492 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
ram54288 0:dbad57390bd1 493
ram54288 0:dbad57390bd1 494 gXcvrDeassertCS_d();
ram54288 0:dbad57390bd1 495 UnprotectFromMCR20Interrupt();
ram54288 0:dbad57390bd1 496 }
ram54288 0:dbad57390bd1 497
ram54288 0:dbad57390bd1 498 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 499 * Name: MCR20Drv_IsIrqPending
ram54288 0:dbad57390bd1 500 * Description: -
ram54288 0:dbad57390bd1 501 * Parameters: -
ram54288 0:dbad57390bd1 502 * Return: -
ram54288 0:dbad57390bd1 503 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 504 uint32_t MCR20Drv_IsIrqPending
ram54288 0:dbad57390bd1 505 (
ram54288 0:dbad57390bd1 506 void
ram54288 0:dbad57390bd1 507 )
ram54288 0:dbad57390bd1 508 {
ram54288 0:dbad57390bd1 509 return RF_isIRQ_Pending();
ram54288 0:dbad57390bd1 510 }
ram54288 0:dbad57390bd1 511
ram54288 0:dbad57390bd1 512 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 513 * Name: MCR20Drv_IRQ_Disable
ram54288 0:dbad57390bd1 514 * Description: -
ram54288 0:dbad57390bd1 515 * Parameters: -
ram54288 0:dbad57390bd1 516 * Return: -
ram54288 0:dbad57390bd1 517 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 518 void MCR20Drv_IRQ_Disable
ram54288 0:dbad57390bd1 519 (
ram54288 0:dbad57390bd1 520 void
ram54288 0:dbad57390bd1 521 )
ram54288 0:dbad57390bd1 522 {
ram54288 0:dbad57390bd1 523 platform_enter_critical();
ram54288 0:dbad57390bd1 524
ram54288 0:dbad57390bd1 525 if( mPhyIrqDisableCnt == 0 )
ram54288 0:dbad57390bd1 526 {
ram54288 0:dbad57390bd1 527 RF_IRQ_Disable();
ram54288 0:dbad57390bd1 528 }
ram54288 0:dbad57390bd1 529
ram54288 0:dbad57390bd1 530 mPhyIrqDisableCnt++;
ram54288 0:dbad57390bd1 531
ram54288 0:dbad57390bd1 532 platform_exit_critical();
ram54288 0:dbad57390bd1 533 }
ram54288 0:dbad57390bd1 534
ram54288 0:dbad57390bd1 535 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 536 * Name: MCR20Drv_IRQ_Enable
ram54288 0:dbad57390bd1 537 * Description: -
ram54288 0:dbad57390bd1 538 * Parameters: -
ram54288 0:dbad57390bd1 539 * Return: -
ram54288 0:dbad57390bd1 540 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 541 void MCR20Drv_IRQ_Enable
ram54288 0:dbad57390bd1 542 (
ram54288 0:dbad57390bd1 543 void
ram54288 0:dbad57390bd1 544 )
ram54288 0:dbad57390bd1 545 {
ram54288 0:dbad57390bd1 546 platform_enter_critical();
ram54288 0:dbad57390bd1 547
ram54288 0:dbad57390bd1 548 if( mPhyIrqDisableCnt )
ram54288 0:dbad57390bd1 549 {
ram54288 0:dbad57390bd1 550 mPhyIrqDisableCnt--;
ram54288 0:dbad57390bd1 551
ram54288 0:dbad57390bd1 552 if( mPhyIrqDisableCnt == 0 )
ram54288 0:dbad57390bd1 553 {
ram54288 0:dbad57390bd1 554 RF_IRQ_Enable();
ram54288 0:dbad57390bd1 555 }
ram54288 0:dbad57390bd1 556 }
ram54288 0:dbad57390bd1 557
ram54288 0:dbad57390bd1 558 platform_exit_critical();
ram54288 0:dbad57390bd1 559 }
ram54288 0:dbad57390bd1 560
ram54288 0:dbad57390bd1 561 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 562 * Name: MCR20Drv_RST_Assert
ram54288 0:dbad57390bd1 563 * Description: -
ram54288 0:dbad57390bd1 564 * Parameters: -
ram54288 0:dbad57390bd1 565 * Return: -
ram54288 0:dbad57390bd1 566 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 567 void MCR20Drv_RST_B_Assert
ram54288 0:dbad57390bd1 568 (
ram54288 0:dbad57390bd1 569 void
ram54288 0:dbad57390bd1 570 )
ram54288 0:dbad57390bd1 571 {
ram54288 0:dbad57390bd1 572 RF_RST_Set(0);
ram54288 0:dbad57390bd1 573 }
ram54288 0:dbad57390bd1 574
ram54288 0:dbad57390bd1 575 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 576 * Name: MCR20Drv_RST_Deassert
ram54288 0:dbad57390bd1 577 * Description: -
ram54288 0:dbad57390bd1 578 * Parameters: -
ram54288 0:dbad57390bd1 579 * Return: -
ram54288 0:dbad57390bd1 580 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 581 void MCR20Drv_RST_B_Deassert
ram54288 0:dbad57390bd1 582 (
ram54288 0:dbad57390bd1 583 void
ram54288 0:dbad57390bd1 584 )
ram54288 0:dbad57390bd1 585 {
ram54288 0:dbad57390bd1 586 RF_RST_Set(1);
ram54288 0:dbad57390bd1 587 }
ram54288 0:dbad57390bd1 588
ram54288 0:dbad57390bd1 589 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 590 * Name: MCR20Drv_SoftRST_Assert
ram54288 0:dbad57390bd1 591 * Description: -
ram54288 0:dbad57390bd1 592 * Parameters: -
ram54288 0:dbad57390bd1 593 * Return: -
ram54288 0:dbad57390bd1 594 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 595 void MCR20Drv_SoftRST_Assert
ram54288 0:dbad57390bd1 596 (
ram54288 0:dbad57390bd1 597 void
ram54288 0:dbad57390bd1 598 )
ram54288 0:dbad57390bd1 599 {
ram54288 0:dbad57390bd1 600 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
ram54288 0:dbad57390bd1 601 }
ram54288 0:dbad57390bd1 602
ram54288 0:dbad57390bd1 603 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 604 * Name: MCR20Drv_SoftRST_Deassert
ram54288 0:dbad57390bd1 605 * Description: -
ram54288 0:dbad57390bd1 606 * Parameters: -
ram54288 0:dbad57390bd1 607 * Return: -
ram54288 0:dbad57390bd1 608 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 609 void MCR20Drv_SoftRST_Deassert
ram54288 0:dbad57390bd1 610 (
ram54288 0:dbad57390bd1 611 void
ram54288 0:dbad57390bd1 612 )
ram54288 0:dbad57390bd1 613 {
ram54288 0:dbad57390bd1 614 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
ram54288 0:dbad57390bd1 615 }
ram54288 0:dbad57390bd1 616
ram54288 0:dbad57390bd1 617 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 618 * Name: MCR20Drv_Soft_RESET
ram54288 0:dbad57390bd1 619 * Description: -
ram54288 0:dbad57390bd1 620 * Parameters: -
ram54288 0:dbad57390bd1 621 * Return: -
ram54288 0:dbad57390bd1 622 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 623 void MCR20Drv_Soft_RESET
ram54288 0:dbad57390bd1 624 (
ram54288 0:dbad57390bd1 625 void
ram54288 0:dbad57390bd1 626 )
ram54288 0:dbad57390bd1 627 {
ram54288 0:dbad57390bd1 628 //assert SOG_RST
ram54288 0:dbad57390bd1 629 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
ram54288 0:dbad57390bd1 630
ram54288 0:dbad57390bd1 631 //deassert SOG_RST
ram54288 0:dbad57390bd1 632 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
ram54288 0:dbad57390bd1 633 }
ram54288 0:dbad57390bd1 634
ram54288 0:dbad57390bd1 635 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 636 * Name: MCR20Drv_RESET
ram54288 0:dbad57390bd1 637 * Description: -
ram54288 0:dbad57390bd1 638 * Parameters: -
ram54288 0:dbad57390bd1 639 * Return: -
ram54288 0:dbad57390bd1 640 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 641 void MCR20Drv_RESET
ram54288 0:dbad57390bd1 642 (
ram54288 0:dbad57390bd1 643 void
ram54288 0:dbad57390bd1 644 )
ram54288 0:dbad57390bd1 645 {
ram54288 0:dbad57390bd1 646 volatile uint32_t delay = 1000;
ram54288 0:dbad57390bd1 647 //assert RST_B
ram54288 0:dbad57390bd1 648 MCR20Drv_RST_B_Assert();
ram54288 0:dbad57390bd1 649
ram54288 0:dbad57390bd1 650 while(delay--);
ram54288 0:dbad57390bd1 651
ram54288 0:dbad57390bd1 652 //deassert RST_B
ram54288 0:dbad57390bd1 653 MCR20Drv_RST_B_Deassert();
ram54288 0:dbad57390bd1 654 }
ram54288 0:dbad57390bd1 655
ram54288 0:dbad57390bd1 656 /*---------------------------------------------------------------------------
ram54288 0:dbad57390bd1 657 * Name: MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:dbad57390bd1 658 * Description: -
ram54288 0:dbad57390bd1 659 * Parameters: -
ram54288 0:dbad57390bd1 660 * Return: -
ram54288 0:dbad57390bd1 661 *---------------------------------------------------------------------------*/
ram54288 0:dbad57390bd1 662 void MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:dbad57390bd1 663 (
ram54288 0:dbad57390bd1 664 uint8_t freqDiv
ram54288 0:dbad57390bd1 665 )
ram54288 0:dbad57390bd1 666 {
ram54288 0:dbad57390bd1 667 uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
ram54288 0:dbad57390bd1 668
ram54288 0:dbad57390bd1 669 if(freqDiv == gCLK_OUT_FREQ_DISABLE)
ram54288 0:dbad57390bd1 670 {
ram54288 0:dbad57390bd1 671 clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
ram54288 0:dbad57390bd1 672 }
ram54288 0:dbad57390bd1 673
ram54288 0:dbad57390bd1 674 MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
ram54288 0:dbad57390bd1 675 }