Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

mbed-client/test/mbedclient/utest/stub/m2minterfaceimpl_stub.cpp@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /*
ram54288 0:a7a43371b306 2 * Copyright (c) 2015 ARM Limited. All rights reserved.
ram54288 0:a7a43371b306 3 * SPDX-License-Identifier: Apache-2.0
ram54288 0:a7a43371b306 4 * Licensed under the Apache License, Version 2.0 (the License); you may
ram54288 0:a7a43371b306 5 * not use this file except in compliance with the License.
ram54288 0:a7a43371b306 6 * You may obtain a copy of the License at
ram54288 0:a7a43371b306 7 *
ram54288 0:a7a43371b306 8 * http://www.apache.org/licenses/LICENSE-2.0
ram54288 0:a7a43371b306 9 *
ram54288 0:a7a43371b306 10 * Unless required by applicable law or agreed to in writing, software
ram54288 0:a7a43371b306 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ram54288 0:a7a43371b306 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ram54288 0:a7a43371b306 13 * See the License for the specific language governing permissions and
ram54288 0:a7a43371b306 14 * limitations under the License.
ram54288 0:a7a43371b306 15 */
ram54288 0:a7a43371b306 16 #include "m2minterfaceimpl_stub.h"
ram54288 0:a7a43371b306 17 #include "common_stub.h"
ram54288 0:a7a43371b306 18
ram54288 0:a7a43371b306 19 u_int8_t m2minterfaceimpl_stub::int_value;
ram54288 0:a7a43371b306 20 bool m2minterfaceimpl_stub::bool_value;
ram54288 0:a7a43371b306 21
ram54288 0:a7a43371b306 22 void m2minterfaceimpl_stub::clear()
ram54288 0:a7a43371b306 23 {
ram54288 0:a7a43371b306 24 int_value = 0;
ram54288 0:a7a43371b306 25 bool_value = false;
ram54288 0:a7a43371b306 26 }
ram54288 0:a7a43371b306 27
ram54288 0:a7a43371b306 28 M2MInterfaceImpl::M2MInterfaceImpl(M2MInterfaceObserver& observer,
ram54288 0:a7a43371b306 29 const String &,
ram54288 0:a7a43371b306 30 const String &,
ram54288 0:a7a43371b306 31 const int32_t,
ram54288 0:a7a43371b306 32 const uint16_t,
ram54288 0:a7a43371b306 33 const String &,
ram54288 0:a7a43371b306 34 M2MInterface::BindingMode mode,
ram54288 0:a7a43371b306 35 M2MInterface::NetworkStack stack,
ram54288 0:a7a43371b306 36 const String &)
ram54288 0:a7a43371b306 37 : _observer(observer),
ram54288 0:a7a43371b306 38 _current_state(0),
ram54288 0:a7a43371b306 39 _max_states( STATE_MAX_STATES ),
ram54288 0:a7a43371b306 40 _event_generated(false),
ram54288 0:a7a43371b306 41 _event_data(NULL),
ram54288 0:a7a43371b306 42 _nsdl_interface(*this),
ram54288 0:a7a43371b306 43 _queue_sleep_timer(*this),
ram54288 0:a7a43371b306 44 _retry_timer(*this),
ram54288 0:a7a43371b306 45 _connection_handler(*this, NULL, mode, stack)
ram54288 0:a7a43371b306 46 {
ram54288 0:a7a43371b306 47 }
ram54288 0:a7a43371b306 48
ram54288 0:a7a43371b306 49 M2MInterfaceImpl::~M2MInterfaceImpl()
ram54288 0:a7a43371b306 50 {
ram54288 0:a7a43371b306 51 }
ram54288 0:a7a43371b306 52 void M2MInterfaceImpl::bootstrap(M2MSecurity *)
ram54288 0:a7a43371b306 53 {
ram54288 0:a7a43371b306 54 }
ram54288 0:a7a43371b306 55
ram54288 0:a7a43371b306 56 void M2MInterfaceImpl::cancel_bootstrap()
ram54288 0:a7a43371b306 57 {
ram54288 0:a7a43371b306 58 }
ram54288 0:a7a43371b306 59
ram54288 0:a7a43371b306 60 void M2MInterfaceImpl::register_object(M2MSecurity *, const M2MObjectList &)
ram54288 0:a7a43371b306 61 {
ram54288 0:a7a43371b306 62 }
ram54288 0:a7a43371b306 63
ram54288 0:a7a43371b306 64 void M2MInterfaceImpl::update_registration(M2MSecurity *, const uint32_t)
ram54288 0:a7a43371b306 65 {
ram54288 0:a7a43371b306 66 }
ram54288 0:a7a43371b306 67 void M2MInterfaceImpl::update_registration(M2MSecurity *,
ram54288 0:a7a43371b306 68 const M2MObjectList &,
ram54288 0:a7a43371b306 69 const uint32_t)
ram54288 0:a7a43371b306 70 {
ram54288 0:a7a43371b306 71 }
ram54288 0:a7a43371b306 72
ram54288 0:a7a43371b306 73 void M2MInterfaceImpl::unregister_object(M2MSecurity*)
ram54288 0:a7a43371b306 74 {
ram54288 0:a7a43371b306 75 }
ram54288 0:a7a43371b306 76
ram54288 0:a7a43371b306 77 void M2MInterfaceImpl::set_queue_sleep_handler(callback_handler)
ram54288 0:a7a43371b306 78 {
ram54288 0:a7a43371b306 79
ram54288 0:a7a43371b306 80 }
ram54288 0:a7a43371b306 81
ram54288 0:a7a43371b306 82 void M2MInterfaceImpl::set_platform_network_handler(void *)
ram54288 0:a7a43371b306 83 {
ram54288 0:a7a43371b306 84
ram54288 0:a7a43371b306 85 }
ram54288 0:a7a43371b306 86
ram54288 0:a7a43371b306 87 void M2MInterfaceImpl::set_random_number_callback(random_number_cb)
ram54288 0:a7a43371b306 88 {
ram54288 0:a7a43371b306 89
ram54288 0:a7a43371b306 90 }
ram54288 0:a7a43371b306 91
ram54288 0:a7a43371b306 92 void M2MInterfaceImpl::set_entropy_callback(entropy_cb)
ram54288 0:a7a43371b306 93 {
ram54288 0:a7a43371b306 94
ram54288 0:a7a43371b306 95 }
ram54288 0:a7a43371b306 96
ram54288 0:a7a43371b306 97 void M2MInterfaceImpl::coap_message_ready(uint8_t *,
ram54288 0:a7a43371b306 98 uint16_t ,
ram54288 0:a7a43371b306 99 sn_nsdl_addr_s *)
ram54288 0:a7a43371b306 100 {
ram54288 0:a7a43371b306 101
ram54288 0:a7a43371b306 102 }
ram54288 0:a7a43371b306 103
ram54288 0:a7a43371b306 104 void M2MInterfaceImpl::client_registered(M2MServer*)
ram54288 0:a7a43371b306 105 {
ram54288 0:a7a43371b306 106
ram54288 0:a7a43371b306 107 }
ram54288 0:a7a43371b306 108
ram54288 0:a7a43371b306 109 void M2MInterfaceImpl::registration_error(uint8_t, bool)
ram54288 0:a7a43371b306 110 {
ram54288 0:a7a43371b306 111
ram54288 0:a7a43371b306 112 }
ram54288 0:a7a43371b306 113
ram54288 0:a7a43371b306 114 void M2MInterfaceImpl::client_unregistered()
ram54288 0:a7a43371b306 115 {
ram54288 0:a7a43371b306 116
ram54288 0:a7a43371b306 117 }
ram54288 0:a7a43371b306 118
ram54288 0:a7a43371b306 119 void M2MInterfaceImpl::bootstrap_done(M2MSecurity *)
ram54288 0:a7a43371b306 120 {
ram54288 0:a7a43371b306 121
ram54288 0:a7a43371b306 122 }
ram54288 0:a7a43371b306 123
ram54288 0:a7a43371b306 124 void M2MInterfaceImpl::bootstrap_wait(M2MSecurity *)
ram54288 0:a7a43371b306 125 {
ram54288 0:a7a43371b306 126
ram54288 0:a7a43371b306 127 }
ram54288 0:a7a43371b306 128
ram54288 0:a7a43371b306 129 void M2MInterfaceImpl::bootstrap_error()
ram54288 0:a7a43371b306 130 {
ram54288 0:a7a43371b306 131
ram54288 0:a7a43371b306 132 }
ram54288 0:a7a43371b306 133
ram54288 0:a7a43371b306 134 void M2MInterfaceImpl::coap_data_processed()
ram54288 0:a7a43371b306 135 {
ram54288 0:a7a43371b306 136
ram54288 0:a7a43371b306 137 }
ram54288 0:a7a43371b306 138
ram54288 0:a7a43371b306 139 void M2MInterfaceImpl::data_available(uint8_t*,
ram54288 0:a7a43371b306 140 uint16_t,
ram54288 0:a7a43371b306 141 const M2MConnectionObserver::SocketAddress &)
ram54288 0:a7a43371b306 142 {
ram54288 0:a7a43371b306 143
ram54288 0:a7a43371b306 144 }
ram54288 0:a7a43371b306 145
ram54288 0:a7a43371b306 146 void M2MInterfaceImpl::socket_error(uint8_t, bool)
ram54288 0:a7a43371b306 147 {
ram54288 0:a7a43371b306 148
ram54288 0:a7a43371b306 149 }
ram54288 0:a7a43371b306 150
ram54288 0:a7a43371b306 151 void M2MInterfaceImpl::address_ready(const M2MConnectionObserver::SocketAddress &,
ram54288 0:a7a43371b306 152 M2MConnectionObserver::ServerType,
ram54288 0:a7a43371b306 153 const uint16_t)
ram54288 0:a7a43371b306 154 {
ram54288 0:a7a43371b306 155
ram54288 0:a7a43371b306 156 }
ram54288 0:a7a43371b306 157
ram54288 0:a7a43371b306 158 void M2MInterfaceImpl::data_sent()
ram54288 0:a7a43371b306 159 {
ram54288 0:a7a43371b306 160 }
ram54288 0:a7a43371b306 161
ram54288 0:a7a43371b306 162 void M2MInterfaceImpl::timer_expired(M2MTimerObserver::Type)
ram54288 0:a7a43371b306 163 {
ram54288 0:a7a43371b306 164
ram54288 0:a7a43371b306 165 }
ram54288 0:a7a43371b306 166
ram54288 0:a7a43371b306 167 void M2MInterfaceImpl::registration_updated(const M2MServer &)
ram54288 0:a7a43371b306 168 {
ram54288 0:a7a43371b306 169 }
ram54288 0:a7a43371b306 170
ram54288 0:a7a43371b306 171 void M2MInterfaceImpl::value_updated(M2MBase *)
ram54288 0:a7a43371b306 172 {
ram54288 0:a7a43371b306 173
ram54288 0:a7a43371b306 174 }
ram54288 0:a7a43371b306 175