Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

mbed-client/test/mbedclient/utest/common/CThunk.h@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /* General C++ Object Thunking class
ram54288 0:a7a43371b306 2 *
ram54288 0:a7a43371b306 3 * - allows direct callbacks to non-static C++ class functions
ram54288 0:a7a43371b306 4 * - keeps track for the corresponding class instance
ram54288 0:a7a43371b306 5 * - supports an optional context parameter for the called function
ram54288 0:a7a43371b306 6 * - ideally suited for class object receiving interrupts (NVIC_SetVector)
ram54288 0:a7a43371b306 7 *
ram54288 0:a7a43371b306 8 * Copyright (c) 2014-2015 ARM Limited
ram54288 0:a7a43371b306 9 *
ram54288 0:a7a43371b306 10 * Licensed under the Apache License, Version 2.0 (the "License");
ram54288 0:a7a43371b306 11 * you may not use this file except in compliance with the License.
ram54288 0:a7a43371b306 12 * You may obtain a copy of the License at
ram54288 0:a7a43371b306 13 *
ram54288 0:a7a43371b306 14 * http://www.apache.org/licenses/LICENSE-2.0
ram54288 0:a7a43371b306 15 *
ram54288 0:a7a43371b306 16 * Unless required by applicable law or agreed to in writing, software
ram54288 0:a7a43371b306 17 * distributed under the License is distributed on an "AS IS" BASIS,
ram54288 0:a7a43371b306 18 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ram54288 0:a7a43371b306 19 * See the License for the specific language governing permissions and
ram54288 0:a7a43371b306 20 * limitations under the License.
ram54288 0:a7a43371b306 21 */
ram54288 0:a7a43371b306 22 #ifndef __CTHUNK_H__
ram54288 0:a7a43371b306 23 #define __CTHUNK_H__
ram54288 0:a7a43371b306 24
ram54288 0:a7a43371b306 25 #define CTHUNK_ADDRESS 1
ram54288 0:a7a43371b306 26
ram54288 0:a7a43371b306 27 #if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)
ram54288 0:a7a43371b306 28 #define CTHUNK_VARIABLES volatile uint32_t code[1]
ram54288 0:a7a43371b306 29 /**
ram54288 0:a7a43371b306 30 * CTHUNK disassembly for Cortex-M3/M4 (thumb2):
ram54288 0:a7a43371b306 31 * * ldm.w pc,{r0,r1,r2,pc}
ram54288 0:a7a43371b306 32 *
ram54288 0:a7a43371b306 33 * This instruction loads the arguments for the static thunking function to r0-r2, and
ram54288 0:a7a43371b306 34 * branches to that function by loading its address into PC.
ram54288 0:a7a43371b306 35 *
ram54288 0:a7a43371b306 36 * This is safe for both regular calling and interrupt calling, since it only touches scratch registers
ram54288 0:a7a43371b306 37 * which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
ram54288 0:a7a43371b306 38 */
ram54288 0:a7a43371b306 39 #define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
ram54288 0:a7a43371b306 40
ram54288 0:a7a43371b306 41 #elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)
ram54288 0:a7a43371b306 42 /*
ram54288 0:a7a43371b306 43 * CTHUNK disassembly for Cortex M0 (thumb):
ram54288 0:a7a43371b306 44 * * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
ram54288 0:a7a43371b306 45 * * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
ram54288 0:a7a43371b306 46 * * add r4,pc set up address to load arguments from (immediately following this code block) (2)
ram54288 0:a7a43371b306 47 * * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
ram54288 0:a7a43371b306 48 * * blx r3 call static thunk function
ram54288 0:a7a43371b306 49 * * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
ram54288 0:a7a43371b306 50 */
ram54288 0:a7a43371b306 51 #define CTHUNK_VARIABLES volatile uint32_t code[3]
ram54288 0:a7a43371b306 52 #define CTHUNK_ASSIGMENT do { \
ram54288 0:a7a43371b306 53 m_thunk.code[0] = 0x2404B51F; \
ram54288 0:a7a43371b306 54 m_thunk.code[1] = 0xCC0F447C; \
ram54288 0:a7a43371b306 55 m_thunk.code[2] = 0xBD1F4798; \
ram54288 0:a7a43371b306 56 } while (0)
ram54288 0:a7a43371b306 57
ram54288 0:a7a43371b306 58 #else
ram54288 0:a7a43371b306 59 #error "Target is not currently suported."
ram54288 0:a7a43371b306 60 #endif
ram54288 0:a7a43371b306 61
ram54288 0:a7a43371b306 62 /* IRQ/Exception compatible thunk entry function */
ram54288 0:a7a43371b306 63 typedef void (*CThunkEntry)(void);
ram54288 0:a7a43371b306 64
ram54288 0:a7a43371b306 65 template<class T>
ram54288 0:a7a43371b306 66 class CThunk
ram54288 0:a7a43371b306 67 {
ram54288 0:a7a43371b306 68 public:
ram54288 0:a7a43371b306 69 typedef void (T::*CCallbackSimple)(void);
ram54288 0:a7a43371b306 70 typedef void (T::*CCallback)(void* context);
ram54288 0:a7a43371b306 71
ram54288 0:a7a43371b306 72 inline CThunk(T *instance)
ram54288 0:a7a43371b306 73 {
ram54288 0:a7a43371b306 74 init(instance, NULL, NULL);
ram54288 0:a7a43371b306 75 }
ram54288 0:a7a43371b306 76
ram54288 0:a7a43371b306 77 inline CThunk(T *instance, CCallback cb)
ram54288 0:a7a43371b306 78 {
ram54288 0:a7a43371b306 79 init(instance, cb, NULL);
ram54288 0:a7a43371b306 80 }
ram54288 0:a7a43371b306 81
ram54288 0:a7a43371b306 82 ~CThunk() {
ram54288 0:a7a43371b306 83
ram54288 0:a7a43371b306 84 }
ram54288 0:a7a43371b306 85
ram54288 0:a7a43371b306 86 inline CThunk(T *instance, CCallbackSimple cb)
ram54288 0:a7a43371b306 87 {
ram54288 0:a7a43371b306 88 init(instance, (CCallback)cb, NULL);
ram54288 0:a7a43371b306 89 }
ram54288 0:a7a43371b306 90
ram54288 0:a7a43371b306 91 inline CThunk(T &instance, CCallback cb)
ram54288 0:a7a43371b306 92 {
ram54288 0:a7a43371b306 93 init(instance, cb, NULL);
ram54288 0:a7a43371b306 94 }
ram54288 0:a7a43371b306 95
ram54288 0:a7a43371b306 96 inline CThunk(T &instance, CCallbackSimple cb)
ram54288 0:a7a43371b306 97 {
ram54288 0:a7a43371b306 98 init(instance, (CCallback)cb, NULL);
ram54288 0:a7a43371b306 99 }
ram54288 0:a7a43371b306 100
ram54288 0:a7a43371b306 101 inline CThunk(T &instance, CCallback cb, void* ctx)
ram54288 0:a7a43371b306 102 {
ram54288 0:a7a43371b306 103 init(instance, cb, ctx);
ram54288 0:a7a43371b306 104 }
ram54288 0:a7a43371b306 105
ram54288 0:a7a43371b306 106 inline void callback(CCallback cb)
ram54288 0:a7a43371b306 107 {
ram54288 0:a7a43371b306 108 m_callback = cb;
ram54288 0:a7a43371b306 109 }
ram54288 0:a7a43371b306 110
ram54288 0:a7a43371b306 111 inline void callback(CCallbackSimple cb)
ram54288 0:a7a43371b306 112 {
ram54288 0:a7a43371b306 113 m_callback = (CCallback)cb;
ram54288 0:a7a43371b306 114 }
ram54288 0:a7a43371b306 115
ram54288 0:a7a43371b306 116 inline void context(void* ctx)
ram54288 0:a7a43371b306 117 {
ram54288 0:a7a43371b306 118 m_thunk.context = (uint32_t)ctx;
ram54288 0:a7a43371b306 119 }
ram54288 0:a7a43371b306 120
ram54288 0:a7a43371b306 121 inline void context(uint32_t ctx)
ram54288 0:a7a43371b306 122 {
ram54288 0:a7a43371b306 123 m_thunk.context = ctx;
ram54288 0:a7a43371b306 124 }
ram54288 0:a7a43371b306 125
ram54288 0:a7a43371b306 126 inline uint32_t entry(void)
ram54288 0:a7a43371b306 127 {
ram54288 0:a7a43371b306 128 return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
ram54288 0:a7a43371b306 129 }
ram54288 0:a7a43371b306 130
ram54288 0:a7a43371b306 131 /* get thunk entry point for connecting rhunk to an IRQ table */
ram54288 0:a7a43371b306 132 inline operator CThunkEntry(void)
ram54288 0:a7a43371b306 133 {
ram54288 0:a7a43371b306 134 return (CThunkEntry)entry();
ram54288 0:a7a43371b306 135 }
ram54288 0:a7a43371b306 136
ram54288 0:a7a43371b306 137 /* get thunk entry point for connecting rhunk to an IRQ table */
ram54288 0:a7a43371b306 138 inline operator uint32_t(void)
ram54288 0:a7a43371b306 139 {
ram54288 0:a7a43371b306 140 return entry();
ram54288 0:a7a43371b306 141 }
ram54288 0:a7a43371b306 142
ram54288 0:a7a43371b306 143 /* simple test function */
ram54288 0:a7a43371b306 144 inline void call(void)
ram54288 0:a7a43371b306 145 {
ram54288 0:a7a43371b306 146 (((CThunkEntry)(entry()))());
ram54288 0:a7a43371b306 147 }
ram54288 0:a7a43371b306 148
ram54288 0:a7a43371b306 149 private:
ram54288 0:a7a43371b306 150 T* m_instance;
ram54288 0:a7a43371b306 151 volatile CCallback m_callback;
ram54288 0:a7a43371b306 152
ram54288 0:a7a43371b306 153 // TODO: this needs proper fix, to refactor toolchain header file and all its use
ram54288 0:a7a43371b306 154 // PACKED there is not defined properly for IAR
ram54288 0:a7a43371b306 155 #if defined (__ICCARM__)
ram54288 0:a7a43371b306 156 typedef __packed struct
ram54288 0:a7a43371b306 157 {
ram54288 0:a7a43371b306 158 CTHUNK_VARIABLES;
ram54288 0:a7a43371b306 159 volatile uint32_t instance;
ram54288 0:a7a43371b306 160 volatile uint32_t context;
ram54288 0:a7a43371b306 161 volatile uint32_t callback;
ram54288 0:a7a43371b306 162 volatile uint32_t trampoline;
ram54288 0:a7a43371b306 163 } CThunkTrampoline;
ram54288 0:a7a43371b306 164 #else
ram54288 0:a7a43371b306 165 typedef struct
ram54288 0:a7a43371b306 166 {
ram54288 0:a7a43371b306 167 CTHUNK_VARIABLES;
ram54288 0:a7a43371b306 168 volatile uint32_t instance;
ram54288 0:a7a43371b306 169 volatile uint32_t context;
ram54288 0:a7a43371b306 170 volatile uint32_t callback;
ram54288 0:a7a43371b306 171 volatile uint32_t trampoline;
ram54288 0:a7a43371b306 172 } __attribute__((__packed__)) CThunkTrampoline;
ram54288 0:a7a43371b306 173 #endif
ram54288 0:a7a43371b306 174
ram54288 0:a7a43371b306 175 static void trampoline(T* instance, void* ctx, CCallback* cb)
ram54288 0:a7a43371b306 176 {
ram54288 0:a7a43371b306 177 if(instance && *cb) {
ram54288 0:a7a43371b306 178 (static_cast<T*>(instance)->**cb)(ctx);
ram54288 0:a7a43371b306 179 }
ram54288 0:a7a43371b306 180 }
ram54288 0:a7a43371b306 181
ram54288 0:a7a43371b306 182 volatile CThunkTrampoline m_thunk;
ram54288 0:a7a43371b306 183
ram54288 0:a7a43371b306 184 inline void init(T *instance, CCallback cb, void* ctx)
ram54288 0:a7a43371b306 185 {
ram54288 0:a7a43371b306 186 /* remember callback - need to add this level of redirection
ram54288 0:a7a43371b306 187 as pointer size for member functions differs between platforms */
ram54288 0:a7a43371b306 188 m_callback = cb;
ram54288 0:a7a43371b306 189
ram54288 0:a7a43371b306 190 /* populate thunking trampoline */
ram54288 0:a7a43371b306 191 // CTHUNK_ASSIGMENT;
ram54288 0:a7a43371b306 192 // m_thunk.context = (uint32_t)ctx;
ram54288 0:a7a43371b306 193 // m_thunk.instance = (uint32_t)instance;
ram54288 0:a7a43371b306 194 // m_thunk.callback = (uint32_t)&m_callback;
ram54288 0:a7a43371b306 195 // m_thunk.trampoline = (uint32_t)&trampoline;
ram54288 0:a7a43371b306 196
ram54288 0:a7a43371b306 197 // __ISB();
ram54288 0:a7a43371b306 198 // __DSB();
ram54288 0:a7a43371b306 199 }
ram54288 0:a7a43371b306 200 };
ram54288 0:a7a43371b306 201
ram54288 0:a7a43371b306 202 #endif/*__CTHUNK_H__*/