Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

easy-connect/mcr20a-rf-driver/source/MCR20Reg.h@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /*!
ram54288 0:a7a43371b306 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:a7a43371b306 3 * All rights reserved.
ram54288 0:a7a43371b306 4 *
ram54288 0:a7a43371b306 5 * \file MCR20reg.h
ram54288 0:a7a43371b306 6 * MCR20 Registers
ram54288 0:a7a43371b306 7 *
ram54288 0:a7a43371b306 8 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:a7a43371b306 9 * are permitted provided that the following conditions are met:
ram54288 0:a7a43371b306 10 *
ram54288 0:a7a43371b306 11 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:a7a43371b306 12 * of conditions and the following disclaimer.
ram54288 0:a7a43371b306 13 *
ram54288 0:a7a43371b306 14 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:a7a43371b306 15 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:a7a43371b306 16 * other materials provided with the distribution.
ram54288 0:a7a43371b306 17 *
ram54288 0:a7a43371b306 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:a7a43371b306 19 * contributors may be used to endorse or promote products derived from this
ram54288 0:a7a43371b306 20 * software without specific prior written permission.
ram54288 0:a7a43371b306 21 *
ram54288 0:a7a43371b306 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:a7a43371b306 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:a7a43371b306 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:a7a43371b306 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:a7a43371b306 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:a7a43371b306 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:a7a43371b306 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:a7a43371b306 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:a7a43371b306 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:a7a43371b306 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:a7a43371b306 32 */
ram54288 0:a7a43371b306 33
ram54288 0:a7a43371b306 34 #ifndef __MCR20_REG_H__
ram54288 0:a7a43371b306 35 #define __MCR20_REG_H__
ram54288 0:a7a43371b306 36 /*****************************************************************************
ram54288 0:a7a43371b306 37 * INCLUDED HEADERS *
ram54288 0:a7a43371b306 38 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 39 * Add to this section all the headers that this module needs to include. *
ram54288 0:a7a43371b306 40 * Note that it is not a good practice to include header files into header *
ram54288 0:a7a43371b306 41 * files, so use this section only if there is no other better solution. *
ram54288 0:a7a43371b306 42 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 43 *****************************************************************************/
ram54288 0:a7a43371b306 44
ram54288 0:a7a43371b306 45 /****************************************************************************/
ram54288 0:a7a43371b306 46 /* Transceiver SPI Registers */
ram54288 0:a7a43371b306 47 /****************************************************************************/
ram54288 0:a7a43371b306 48
ram54288 0:a7a43371b306 49 #define TransceiverSPI_IARIndexReg (0x3E)
ram54288 0:a7a43371b306 50
ram54288 0:a7a43371b306 51 #define TransceiverSPI_ReadSelect (1<<7)
ram54288 0:a7a43371b306 52 #define TransceiverSPI_WriteSelect (0<<7)
ram54288 0:a7a43371b306 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
ram54288 0:a7a43371b306 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
ram54288 0:a7a43371b306 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
ram54288 0:a7a43371b306 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
ram54288 0:a7a43371b306 57
ram54288 0:a7a43371b306 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
ram54288 0:a7a43371b306 59
ram54288 0:a7a43371b306 60 #define IRQSTS1 0x00
ram54288 0:a7a43371b306 61 #define IRQSTS2 0x01
ram54288 0:a7a43371b306 62 #define IRQSTS3 0x02
ram54288 0:a7a43371b306 63 #define PHY_CTRL1 0x03
ram54288 0:a7a43371b306 64 #define PHY_CTRL2 0x04
ram54288 0:a7a43371b306 65 #define PHY_CTRL3 0x05
ram54288 0:a7a43371b306 66 #define RX_FRM_LEN 0x06
ram54288 0:a7a43371b306 67 #define PHY_CTRL4 0x07
ram54288 0:a7a43371b306 68 #define SRC_CTRL 0x08
ram54288 0:a7a43371b306 69 #define SRC_ADDRS_SUM_LSB 0x09
ram54288 0:a7a43371b306 70 #define SRC_ADDRS_SUM_MSB 0x0A
ram54288 0:a7a43371b306 71 #define CCA1_ED_FNL 0x0B
ram54288 0:a7a43371b306 72 #define EVENT_TMR_LSB 0x0C
ram54288 0:a7a43371b306 73 #define EVENT_TMR_MSB 0x0D
ram54288 0:a7a43371b306 74 #define EVENT_TMR_USB 0x0E
ram54288 0:a7a43371b306 75 #define TIMESTAMP_LSB 0x0F
ram54288 0:a7a43371b306 76 #define TIMESTAMP_MSB 0x10
ram54288 0:a7a43371b306 77 #define TIMESTAMP_USB 0x11
ram54288 0:a7a43371b306 78 #define T3CMP_LSB 0x12
ram54288 0:a7a43371b306 79 #define T3CMP_MSB 0x13
ram54288 0:a7a43371b306 80 #define T3CMP_USB 0x14
ram54288 0:a7a43371b306 81 #define T2PRIMECMP_LSB 0x15
ram54288 0:a7a43371b306 82 #define T2PRIMECMP_MSB 0x16
ram54288 0:a7a43371b306 83 #define T1CMP_LSB 0x17
ram54288 0:a7a43371b306 84 #define T1CMP_MSB 0x18
ram54288 0:a7a43371b306 85 #define T1CMP_USB 0x19
ram54288 0:a7a43371b306 86 #define T2CMP_LSB 0x1A
ram54288 0:a7a43371b306 87 #define T2CMP_MSB 0x1B
ram54288 0:a7a43371b306 88 #define T2CMP_USB 0x1C
ram54288 0:a7a43371b306 89 #define T4CMP_LSB 0x1D
ram54288 0:a7a43371b306 90 #define T4CMP_MSB 0x1E
ram54288 0:a7a43371b306 91 #define T4CMP_USB 0x1F
ram54288 0:a7a43371b306 92 #define PLL_INT0 0x20
ram54288 0:a7a43371b306 93 #define PLL_FRAC0_LSB 0x21
ram54288 0:a7a43371b306 94 #define PLL_FRAC0_MSB 0x22
ram54288 0:a7a43371b306 95 #define PA_PWR 0x23
ram54288 0:a7a43371b306 96 #define SEQ_STATE 0x24
ram54288 0:a7a43371b306 97 #define LQI_VALUE 0x25
ram54288 0:a7a43371b306 98 #define RSSI_CCA_CONT 0x26
ram54288 0:a7a43371b306 99 //-------------- 0x27
ram54288 0:a7a43371b306 100 #define ASM_CTRL1 0x28
ram54288 0:a7a43371b306 101 #define ASM_CTRL2 0x29
ram54288 0:a7a43371b306 102 #define ASM_DATA_0 0x2A
ram54288 0:a7a43371b306 103 #define ASM_DATA_1 0x2B
ram54288 0:a7a43371b306 104 #define ASM_DATA_2 0x2C
ram54288 0:a7a43371b306 105 #define ASM_DATA_3 0x2D
ram54288 0:a7a43371b306 106 #define ASM_DATA_4 0x2E
ram54288 0:a7a43371b306 107 #define ASM_DATA_5 0x2F
ram54288 0:a7a43371b306 108 #define ASM_DATA_6 0x30
ram54288 0:a7a43371b306 109 #define ASM_DATA_7 0x31
ram54288 0:a7a43371b306 110 #define ASM_DATA_8 0x32
ram54288 0:a7a43371b306 111 #define ASM_DATA_9 0x33
ram54288 0:a7a43371b306 112 #define ASM_DATA_A 0x34
ram54288 0:a7a43371b306 113 #define ASM_DATA_B 0x35
ram54288 0:a7a43371b306 114 #define ASM_DATA_C 0x36
ram54288 0:a7a43371b306 115 #define ASM_DATA_D 0x37
ram54288 0:a7a43371b306 116 #define ASM_DATA_E 0x38
ram54288 0:a7a43371b306 117 #define ASM_DATA_F 0x39
ram54288 0:a7a43371b306 118 //------------------- 0x3A
ram54288 0:a7a43371b306 119 #define OVERWRITE_VER 0x3B
ram54288 0:a7a43371b306 120 #define CLK_OUT_CTRL 0x3C
ram54288 0:a7a43371b306 121 #define PWR_MODES 0x3D
ram54288 0:a7a43371b306 122 #define IAR_INDEX 0x3E
ram54288 0:a7a43371b306 123 #define IAR_DATA 0x3F
ram54288 0:a7a43371b306 124
ram54288 0:a7a43371b306 125
ram54288 0:a7a43371b306 126 #define PART_ID 0x00
ram54288 0:a7a43371b306 127 #define XTAL_TRIM 0x01
ram54288 0:a7a43371b306 128 #define PMC_LP_TRIM 0x02
ram54288 0:a7a43371b306 129 #define MACPANID0_LSB 0x03
ram54288 0:a7a43371b306 130 #define MACPANID0_MSB 0x04
ram54288 0:a7a43371b306 131 #define MACSHORTADDRS0_LSB 0x05
ram54288 0:a7a43371b306 132 #define MACSHORTADDRS0_MSB 0x06
ram54288 0:a7a43371b306 133 #define MACLONGADDRS0_0 0x07
ram54288 0:a7a43371b306 134 #define MACLONGADDRS0_8 0x08
ram54288 0:a7a43371b306 135 #define MACLONGADDRS0_16 0x09
ram54288 0:a7a43371b306 136 #define MACLONGADDRS0_24 0x0A
ram54288 0:a7a43371b306 137 #define MACLONGADDRS0_32 0x0B
ram54288 0:a7a43371b306 138 #define MACLONGADDRS0_40 0x0C
ram54288 0:a7a43371b306 139 #define MACLONGADDRS0_48 0x0D
ram54288 0:a7a43371b306 140 #define MACLONGADDRS0_56 0x0E
ram54288 0:a7a43371b306 141 #define RX_FRAME_FILTER 0x0F
ram54288 0:a7a43371b306 142 #define PLL_INT1 0x10
ram54288 0:a7a43371b306 143 #define PLL_FRAC1_LSB 0x11
ram54288 0:a7a43371b306 144 #define PLL_FRAC1_MSB 0x12
ram54288 0:a7a43371b306 145 #define MACPANID1_LSB 0x13
ram54288 0:a7a43371b306 146 #define MACPANID1_MSB 0x14
ram54288 0:a7a43371b306 147 #define MACSHORTADDRS1_LSB 0x15
ram54288 0:a7a43371b306 148 #define MACSHORTADDRS1_MSB 0x16
ram54288 0:a7a43371b306 149 #define MACLONGADDRS1_0 0x17
ram54288 0:a7a43371b306 150 #define MACLONGADDRS1_8 0x18
ram54288 0:a7a43371b306 151 #define MACLONGADDRS1_16 0x19
ram54288 0:a7a43371b306 152 #define MACLONGADDRS1_24 0x1A
ram54288 0:a7a43371b306 153 #define MACLONGADDRS1_32 0x1B
ram54288 0:a7a43371b306 154 #define MACLONGADDRS1_40 0x1C
ram54288 0:a7a43371b306 155 #define MACLONGADDRS1_48 0x1D
ram54288 0:a7a43371b306 156 #define MACLONGADDRS1_56 0x1E
ram54288 0:a7a43371b306 157 #define DUAL_PAN_CTRL 0x1F
ram54288 0:a7a43371b306 158 #define DUAL_PAN_DWELL 0x20
ram54288 0:a7a43371b306 159 #define DUAL_PAN_STS 0x21
ram54288 0:a7a43371b306 160 #define CCA1_THRESH 0x22
ram54288 0:a7a43371b306 161 #define CCA1_ED_OFFSET_COMP 0x23
ram54288 0:a7a43371b306 162 #define LQI_OFFSET_COMP 0x24
ram54288 0:a7a43371b306 163 #define CCA_CTRL 0x25
ram54288 0:a7a43371b306 164 #define CCA2_CORR_PEAKS 0x26
ram54288 0:a7a43371b306 165 #define CCA2_CORR_THRESH 0x27
ram54288 0:a7a43371b306 166 #define TMR_PRESCALE 0x28
ram54288 0:a7a43371b306 167 //---------------- 0x29
ram54288 0:a7a43371b306 168 #define GPIO_DATA 0x2A
ram54288 0:a7a43371b306 169 #define GPIO_DIR 0x2B
ram54288 0:a7a43371b306 170 #define GPIO_PUL_EN 0x2C
ram54288 0:a7a43371b306 171 #define GPIO_PUL_SEL 0x2D
ram54288 0:a7a43371b306 172 #define GPIO_DS 0x2E
ram54288 0:a7a43371b306 173 //-------------- 0x2F
ram54288 0:a7a43371b306 174 #define ANT_PAD_CTRL 0x30
ram54288 0:a7a43371b306 175 #define MISC_PAD_CTRL 0x31
ram54288 0:a7a43371b306 176 #define BSM_CTRL 0x32
ram54288 0:a7a43371b306 177 //--------------- 0x33
ram54288 0:a7a43371b306 178 #define _RNG 0x34
ram54288 0:a7a43371b306 179 #define RX_BYTE_COUNT 0x35
ram54288 0:a7a43371b306 180 #define RX_WTR_MARK 0x36
ram54288 0:a7a43371b306 181 #define SOFT_RESET 0x37
ram54288 0:a7a43371b306 182 #define TXDELAY 0x38
ram54288 0:a7a43371b306 183 #define ACKDELAY 0x39
ram54288 0:a7a43371b306 184 #define SEQ_MGR_CTRL 0x3A
ram54288 0:a7a43371b306 185 #define SEQ_MGR_STS 0x3B
ram54288 0:a7a43371b306 186 #define SEQ_T_STS 0x3C
ram54288 0:a7a43371b306 187 #define ABORT_STS 0x3D
ram54288 0:a7a43371b306 188 #define CCCA_BUSY_CNT 0x3E
ram54288 0:a7a43371b306 189 #define SRC_ADDR_CHECKSUM1 0x3F
ram54288 0:a7a43371b306 190 #define SRC_ADDR_CHECKSUM2 0x40
ram54288 0:a7a43371b306 191 #define SRC_TBL_VALID1 0x41
ram54288 0:a7a43371b306 192 #define SRC_TBL_VALID2 0x42
ram54288 0:a7a43371b306 193 #define FILTERFAIL_CODE1 0x43
ram54288 0:a7a43371b306 194 #define FILTERFAIL_CODE2 0x44
ram54288 0:a7a43371b306 195 #define SLOT_PRELOAD 0x45
ram54288 0:a7a43371b306 196 //---------------- 0x46
ram54288 0:a7a43371b306 197 #define CORR_VT 0x47
ram54288 0:a7a43371b306 198 #define SYNC_CTRL 0x48
ram54288 0:a7a43371b306 199 #define PN_LSB_0 0x49
ram54288 0:a7a43371b306 200 #define PN_LSB_1 0x4A
ram54288 0:a7a43371b306 201 #define PN_MSB_0 0x4B
ram54288 0:a7a43371b306 202 #define PN_MSB_1 0x4C
ram54288 0:a7a43371b306 203 #define CORR_NVAL 0x4D
ram54288 0:a7a43371b306 204 #define TX_MODE_CTRL 0x4E
ram54288 0:a7a43371b306 205 #define SNF_THR 0x4F
ram54288 0:a7a43371b306 206 #define FAD_THR 0x50
ram54288 0:a7a43371b306 207 #define ANT_AGC_CTRL 0x51
ram54288 0:a7a43371b306 208 #define AGC_THR1 0x52
ram54288 0:a7a43371b306 209 #define AGC_THR2 0x53
ram54288 0:a7a43371b306 210 #define AGC_HYS 0x54
ram54288 0:a7a43371b306 211 #define AFC 0x55
ram54288 0:a7a43371b306 212 //--------------- 0x56
ram54288 0:a7a43371b306 213 //--------------- 0x57
ram54288 0:a7a43371b306 214 #define PHY_STS 0x58
ram54288 0:a7a43371b306 215 #define RX_MAX_CORR 0x59
ram54288 0:a7a43371b306 216 #define RX_MAX_PREAMBLE 0x5A
ram54288 0:a7a43371b306 217 #define RSSI 0x5B
ram54288 0:a7a43371b306 218 //--------------- 0x5C
ram54288 0:a7a43371b306 219 //--------------- 0x5D
ram54288 0:a7a43371b306 220 #define PLL_DIG_CTRL 0x5E
ram54288 0:a7a43371b306 221 #define VCO_CAL 0x5F
ram54288 0:a7a43371b306 222 #define VCO_BEST_DIFF 0x60
ram54288 0:a7a43371b306 223 #define VCO_BIAS 0x61
ram54288 0:a7a43371b306 224 #define KMOD_CTRL 0x62
ram54288 0:a7a43371b306 225 #define KMOD_CAL 0x63
ram54288 0:a7a43371b306 226 #define PA_CAL 0x64
ram54288 0:a7a43371b306 227 #define PA_PWRCAL 0x65
ram54288 0:a7a43371b306 228 #define ATT_RSSI1 0x66
ram54288 0:a7a43371b306 229 #define ATT_RSSI2 0x67
ram54288 0:a7a43371b306 230 #define RSSI_OFFSET 0x68
ram54288 0:a7a43371b306 231 #define RSSI_SLOPE 0x69
ram54288 0:a7a43371b306 232 #define RSSI_CAL1 0x6A
ram54288 0:a7a43371b306 233 #define RSSI_CAL2 0x6B
ram54288 0:a7a43371b306 234 //--------------- 0x6C
ram54288 0:a7a43371b306 235 //--------------- 0x6D
ram54288 0:a7a43371b306 236 #define XTAL_CTRL 0x6E
ram54288 0:a7a43371b306 237 #define XTAL_COMP_MIN 0x6F
ram54288 0:a7a43371b306 238 #define XTAL_COMP_MAX 0x70
ram54288 0:a7a43371b306 239 #define XTAL_GM 0x71
ram54288 0:a7a43371b306 240 //--------------- 0x72
ram54288 0:a7a43371b306 241 //--------------- 0x73
ram54288 0:a7a43371b306 242 #define LNA_TUNE 0x74
ram54288 0:a7a43371b306 243 #define LNA_AGCGAIN 0x75
ram54288 0:a7a43371b306 244 //--------------- 0x76
ram54288 0:a7a43371b306 245 //--------------- 0x77
ram54288 0:a7a43371b306 246 #define CHF_PMA_GAIN 0x78
ram54288 0:a7a43371b306 247 #define CHF_IBUF 0x79
ram54288 0:a7a43371b306 248 #define CHF_QBUF 0x7A
ram54288 0:a7a43371b306 249 #define CHF_IRIN 0x7B
ram54288 0:a7a43371b306 250 #define CHF_QRIN 0x7C
ram54288 0:a7a43371b306 251 #define CHF_IL 0x7D
ram54288 0:a7a43371b306 252 #define CHF_QL 0x7E
ram54288 0:a7a43371b306 253 #define CHF_CC1 0x7F
ram54288 0:a7a43371b306 254 #define CHF_CCL 0x80
ram54288 0:a7a43371b306 255 #define CHF_CC2 0x81
ram54288 0:a7a43371b306 256 #define CHF_IROUT 0x82
ram54288 0:a7a43371b306 257 #define CHF_QROUT 0x83
ram54288 0:a7a43371b306 258 //--------------- 0x84
ram54288 0:a7a43371b306 259 //--------------- 0x85
ram54288 0:a7a43371b306 260 #define RSSI_CTRL 0x86
ram54288 0:a7a43371b306 261 //--------------- 0x87
ram54288 0:a7a43371b306 262 //--------------- 0x88
ram54288 0:a7a43371b306 263 #define PA_BIAS 0x89
ram54288 0:a7a43371b306 264 #define PA_TUNING 0x8A
ram54288 0:a7a43371b306 265 //--------------- 0x8B
ram54288 0:a7a43371b306 266 //--------------- 0x8C
ram54288 0:a7a43371b306 267 #define PMC_HP_TRIM 0x8D
ram54288 0:a7a43371b306 268 #define VREGA_TRIM 0x8E
ram54288 0:a7a43371b306 269 //--------------- 0x8F
ram54288 0:a7a43371b306 270 //--------------- 0x90
ram54288 0:a7a43371b306 271 #define VCO_CTRL1 0x91
ram54288 0:a7a43371b306 272 #define VCO_CTRL2 0x92
ram54288 0:a7a43371b306 273 //--------------- 0x93
ram54288 0:a7a43371b306 274 //--------------- 0x94
ram54288 0:a7a43371b306 275 #define ANA_SPARE_OUT1 0x95
ram54288 0:a7a43371b306 276 #define ANA_SPARE_OUT2 0x96
ram54288 0:a7a43371b306 277 #define ANA_SPARE_IN 0x97
ram54288 0:a7a43371b306 278 #define MISCELLANEOUS 0x98
ram54288 0:a7a43371b306 279 //--------------- 0x99
ram54288 0:a7a43371b306 280 #define SEQ_MGR_OVRD0 0x9A
ram54288 0:a7a43371b306 281 #define SEQ_MGR_OVRD1 0x9B
ram54288 0:a7a43371b306 282 #define SEQ_MGR_OVRD2 0x9C
ram54288 0:a7a43371b306 283 #define SEQ_MGR_OVRD3 0x9D
ram54288 0:a7a43371b306 284 #define SEQ_MGR_OVRD4 0x9E
ram54288 0:a7a43371b306 285 #define SEQ_MGR_OVRD5 0x9F
ram54288 0:a7a43371b306 286 #define SEQ_MGR_OVRD6 0xA0
ram54288 0:a7a43371b306 287 #define SEQ_MGR_OVRD7 0xA1
ram54288 0:a7a43371b306 288 //--------------- 0xA2
ram54288 0:a7a43371b306 289 #define TESTMODE_CTRL 0xA3
ram54288 0:a7a43371b306 290 #define DTM_CTRL1 0xA4
ram54288 0:a7a43371b306 291 #define DTM_CTRL2 0xA5
ram54288 0:a7a43371b306 292 #define ATM_CTRL1 0xA6
ram54288 0:a7a43371b306 293 #define ATM_CTRL2 0xA7
ram54288 0:a7a43371b306 294 #define ATM_CTRL3 0xA8
ram54288 0:a7a43371b306 295 //--------------- 0xA9
ram54288 0:a7a43371b306 296 #define LIM_FE_TEST_CTRL 0xAA
ram54288 0:a7a43371b306 297 #define CHF_TEST_CTRL 0xAB
ram54288 0:a7a43371b306 298 #define VCO_TEST_CTRL 0xAC
ram54288 0:a7a43371b306 299 #define PLL_TEST_CTRL 0xAD
ram54288 0:a7a43371b306 300 #define PA_TEST_CTRL 0xAE
ram54288 0:a7a43371b306 301 #define PMC_TEST_CTRL 0xAF
ram54288 0:a7a43371b306 302 #define SCAN_DTM_PROTECT_1 0xFE
ram54288 0:a7a43371b306 303 #define SCAN_DTM_PROTECT_0 0xFF
ram54288 0:a7a43371b306 304
ram54288 0:a7a43371b306 305 // IRQSTS1 bits
ram54288 0:a7a43371b306 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
ram54288 0:a7a43371b306 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
ram54288 0:a7a43371b306 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
ram54288 0:a7a43371b306 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
ram54288 0:a7a43371b306 310 #define cIRQSTS1_CCAIRQ (1<<3)
ram54288 0:a7a43371b306 311 #define cIRQSTS1_RXIRQ (1<<2)
ram54288 0:a7a43371b306 312 #define cIRQSTS1_TXIRQ (1<<1)
ram54288 0:a7a43371b306 313 #define cIRQSTS1_SEQIRQ (1<<0)
ram54288 0:a7a43371b306 314
ram54288 0:a7a43371b306 315 typedef union regIRQSTS1_tag{
ram54288 0:a7a43371b306 316 uint8_t byte;
ram54288 0:a7a43371b306 317 struct{
ram54288 0:a7a43371b306 318 uint8_t SEQIRQ:1;
ram54288 0:a7a43371b306 319 uint8_t TXIRQ:1;
ram54288 0:a7a43371b306 320 uint8_t RXIRQ:1;
ram54288 0:a7a43371b306 321 uint8_t CCAIRQ:1;
ram54288 0:a7a43371b306 322 uint8_t RXWTRMRKIRQ:1;
ram54288 0:a7a43371b306 323 uint8_t FILTERFAIL_IRQ:1;
ram54288 0:a7a43371b306 324 uint8_t PLL_UNLOCK_IRQ:1;
ram54288 0:a7a43371b306 325 uint8_t RX_FRM_PEND:1;
ram54288 0:a7a43371b306 326 }bit;
ram54288 0:a7a43371b306 327 } regIRQSTS1_t;
ram54288 0:a7a43371b306 328
ram54288 0:a7a43371b306 329 // IRQSTS2 bits
ram54288 0:a7a43371b306 330 #define cIRQSTS2_CRCVALID (1<<7)
ram54288 0:a7a43371b306 331 #define cIRQSTS2_CCA (1<<6)
ram54288 0:a7a43371b306 332 #define cIRQSTS2_SRCADDR (1<<5)
ram54288 0:a7a43371b306 333 #define cIRQSTS2_PI (1<<4)
ram54288 0:a7a43371b306 334 #define cIRQSTS2_TMRSTATUS (1<<3)
ram54288 0:a7a43371b306 335 #define cIRQSTS2_ASM_IRQ (1<<2)
ram54288 0:a7a43371b306 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
ram54288 0:a7a43371b306 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
ram54288 0:a7a43371b306 338
ram54288 0:a7a43371b306 339 typedef union regIRQSTS2_tag{
ram54288 0:a7a43371b306 340 uint8_t byte;
ram54288 0:a7a43371b306 341 struct{
ram54288 0:a7a43371b306 342 uint8_t WAKE_IRQ:1;
ram54288 0:a7a43371b306 343 uint8_t PB_ERR_IRQ:1;
ram54288 0:a7a43371b306 344 uint8_t ASM_IRQ:1;
ram54288 0:a7a43371b306 345 uint8_t TMRSTATUS:1;
ram54288 0:a7a43371b306 346 uint8_t PI:1;
ram54288 0:a7a43371b306 347 uint8_t SRCADDR:1;
ram54288 0:a7a43371b306 348 uint8_t CCA:1;
ram54288 0:a7a43371b306 349 uint8_t CRCVALID:1;
ram54288 0:a7a43371b306 350 }bit;
ram54288 0:a7a43371b306 351 } regIRQSTS2_t;
ram54288 0:a7a43371b306 352
ram54288 0:a7a43371b306 353 // IRQSTS3 bits
ram54288 0:a7a43371b306 354 #define cIRQSTS3_TMR4MSK (1<<7)
ram54288 0:a7a43371b306 355 #define cIRQSTS3_TMR3MSK (1<<6)
ram54288 0:a7a43371b306 356 #define cIRQSTS3_TMR2MSK (1<<5)
ram54288 0:a7a43371b306 357 #define cIRQSTS3_TMR1MSK (1<<4)
ram54288 0:a7a43371b306 358 #define cIRQSTS3_TMR4IRQ (1<<3)
ram54288 0:a7a43371b306 359 #define cIRQSTS3_TMR3IRQ (1<<2)
ram54288 0:a7a43371b306 360 #define cIRQSTS3_TMR2IRQ (1<<1)
ram54288 0:a7a43371b306 361 #define cIRQSTS3_TMR1IRQ (1<<0)
ram54288 0:a7a43371b306 362
ram54288 0:a7a43371b306 363 typedef union regIRQSTS3_tag{
ram54288 0:a7a43371b306 364 uint8_t byte;
ram54288 0:a7a43371b306 365 struct{
ram54288 0:a7a43371b306 366 uint8_t TMR1IRQ:1;
ram54288 0:a7a43371b306 367 uint8_t TMR2IRQ:1;
ram54288 0:a7a43371b306 368 uint8_t TMR3IRQ:1;
ram54288 0:a7a43371b306 369 uint8_t TMR4IRQ:1;
ram54288 0:a7a43371b306 370 uint8_t TMR1MSK:1;
ram54288 0:a7a43371b306 371 uint8_t TMR2MSK:1;
ram54288 0:a7a43371b306 372 uint8_t TMR3MSK:1;
ram54288 0:a7a43371b306 373 uint8_t TMR4MSK:1;
ram54288 0:a7a43371b306 374 }bit;
ram54288 0:a7a43371b306 375 } regIRQSTS3_t;
ram54288 0:a7a43371b306 376
ram54288 0:a7a43371b306 377 // PHY_CTRL1 bits
ram54288 0:a7a43371b306 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
ram54288 0:a7a43371b306 379 #define cPHY_CTRL1_SLOTTED (1<<6)
ram54288 0:a7a43371b306 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
ram54288 0:a7a43371b306 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
ram54288 0:a7a43371b306 382 #define cPHY_CTRL1_AUTOACK (1<<3)
ram54288 0:a7a43371b306 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
ram54288 0:a7a43371b306 384
ram54288 0:a7a43371b306 385 typedef union regPHY_CTRL1_tag{
ram54288 0:a7a43371b306 386 uint8_t byte;
ram54288 0:a7a43371b306 387 struct{
ram54288 0:a7a43371b306 388 uint8_t XCVSEQ:3;
ram54288 0:a7a43371b306 389 uint8_t AUTOACK:1;
ram54288 0:a7a43371b306 390 uint8_t RXACKRQD:1;
ram54288 0:a7a43371b306 391 uint8_t CCABFRTX:1;
ram54288 0:a7a43371b306 392 uint8_t SLOTTED:1;
ram54288 0:a7a43371b306 393 uint8_t TMRTRIGEN:1;
ram54288 0:a7a43371b306 394 }bit;
ram54288 0:a7a43371b306 395 } regPHY_CTRL1_t;
ram54288 0:a7a43371b306 396
ram54288 0:a7a43371b306 397 // PHY_CTRL2 bits
ram54288 0:a7a43371b306 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
ram54288 0:a7a43371b306 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
ram54288 0:a7a43371b306 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
ram54288 0:a7a43371b306 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
ram54288 0:a7a43371b306 402 #define cPHY_CTRL2_CCAMSK (1<<3)
ram54288 0:a7a43371b306 403 #define cPHY_CTRL2_RXMSK (1<<2)
ram54288 0:a7a43371b306 404 #define cPHY_CTRL2_TXMSK (1<<1)
ram54288 0:a7a43371b306 405 #define cPHY_CTRL2_SEQMSK (1<<0)
ram54288 0:a7a43371b306 406
ram54288 0:a7a43371b306 407 typedef union regPHY_CTRL2_tag{
ram54288 0:a7a43371b306 408 uint8_t byte;
ram54288 0:a7a43371b306 409 struct{
ram54288 0:a7a43371b306 410 uint8_t SEQMSK:1;
ram54288 0:a7a43371b306 411 uint8_t TXMSK:1;
ram54288 0:a7a43371b306 412 uint8_t RXMSK:1;
ram54288 0:a7a43371b306 413 uint8_t CCAMSK:1;
ram54288 0:a7a43371b306 414 uint8_t RX_WMRK_MSK:1;
ram54288 0:a7a43371b306 415 uint8_t FILTERFAIL_MSK:1;
ram54288 0:a7a43371b306 416 uint8_t PLL_UNLOCK_MSK:1;
ram54288 0:a7a43371b306 417 uint8_t CRC_MSK:1;
ram54288 0:a7a43371b306 418 }bit;
ram54288 0:a7a43371b306 419 } regPHY_CTRL2_t;
ram54288 0:a7a43371b306 420
ram54288 0:a7a43371b306 421 // PHY_CTRL3 bits
ram54288 0:a7a43371b306 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
ram54288 0:a7a43371b306 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
ram54288 0:a7a43371b306 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
ram54288 0:a7a43371b306 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
ram54288 0:a7a43371b306 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
ram54288 0:a7a43371b306 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
ram54288 0:a7a43371b306 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
ram54288 0:a7a43371b306 429
ram54288 0:a7a43371b306 430 typedef union regPHY_CTRL3_tag{
ram54288 0:a7a43371b306 431 uint8_t byte;
ram54288 0:a7a43371b306 432 struct{
ram54288 0:a7a43371b306 433 uint8_t WAKE_MSK:1;
ram54288 0:a7a43371b306 434 uint8_t PB_ERR_MSK:1;
ram54288 0:a7a43371b306 435 uint8_t ASM_MSK:1;
ram54288 0:a7a43371b306 436 uint8_t RESERVED:1;
ram54288 0:a7a43371b306 437 uint8_t TMR1CMP_EN:1;
ram54288 0:a7a43371b306 438 uint8_t TMR2CMP_EN:1;
ram54288 0:a7a43371b306 439 uint8_t TMR3CMP_EN:1;
ram54288 0:a7a43371b306 440 uint8_t TMR4CMP_EN:1;
ram54288 0:a7a43371b306 441 }bit;
ram54288 0:a7a43371b306 442 } regPHY_CTRL3_t;
ram54288 0:a7a43371b306 443
ram54288 0:a7a43371b306 444 // RX_FRM_LEN bits
ram54288 0:a7a43371b306 445 #define cRX_FRAME_LENGTH (0x7F)
ram54288 0:a7a43371b306 446
ram54288 0:a7a43371b306 447 // PHY_CTRL4 bits
ram54288 0:a7a43371b306 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
ram54288 0:a7a43371b306 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
ram54288 0:a7a43371b306 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
ram54288 0:a7a43371b306 451 #define cPHY_CTRL4_CCATYPE (3<<0)
ram54288 0:a7a43371b306 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
ram54288 0:a7a43371b306 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
ram54288 0:a7a43371b306 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
ram54288 0:a7a43371b306 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
ram54288 0:a7a43371b306 456
ram54288 0:a7a43371b306 457 typedef union regPHY_CTRL4_tag{
ram54288 0:a7a43371b306 458 uint8_t byte;
ram54288 0:a7a43371b306 459 struct{
ram54288 0:a7a43371b306 460 uint8_t TC2PRIME_EN:1;
ram54288 0:a7a43371b306 461 uint8_t PROMISCUOUS:1;
ram54288 0:a7a43371b306 462 uint8_t TMRLOAD:1;
ram54288 0:a7a43371b306 463 uint8_t CCATYPE:2;
ram54288 0:a7a43371b306 464 uint8_t PANCORDNTR0:1;
ram54288 0:a7a43371b306 465 uint8_t TC3TMOUT:1;
ram54288 0:a7a43371b306 466 uint8_t TRCV_MSK:1;
ram54288 0:a7a43371b306 467 }bit;
ram54288 0:a7a43371b306 468 } regPHY_CTRL4_t;
ram54288 0:a7a43371b306 469
ram54288 0:a7a43371b306 470 // SRC_CTRL bits
ram54288 0:a7a43371b306 471 #define cSRC_CTRL_INDEX (0x0F)
ram54288 0:a7a43371b306 472 #define cSRC_CTRL_INDEX_Shift_c (4)
ram54288 0:a7a43371b306 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
ram54288 0:a7a43371b306 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
ram54288 0:a7a43371b306 475 #define cSRC_CTRL_INDEX_EN (1<<1)
ram54288 0:a7a43371b306 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
ram54288 0:a7a43371b306 477
ram54288 0:a7a43371b306 478 typedef union regSRC_CTRL_tag{
ram54288 0:a7a43371b306 479 uint8_t byte;
ram54288 0:a7a43371b306 480 struct{
ram54288 0:a7a43371b306 481 uint8_t INDEX_DISABLE:1;
ram54288 0:a7a43371b306 482 uint8_t INDEX_EN:1;
ram54288 0:a7a43371b306 483 uint8_t SRCADDR_EN:1;
ram54288 0:a7a43371b306 484 uint8_t ACK_FRM_PND:1;
ram54288 0:a7a43371b306 485 uint8_t INDEX:4;
ram54288 0:a7a43371b306 486 }bit;
ram54288 0:a7a43371b306 487 } regSRC_CTRL_t;
ram54288 0:a7a43371b306 488
ram54288 0:a7a43371b306 489 // ASM_CTRL1 bits
ram54288 0:a7a43371b306 490 #define cASM_CTRL1_CLEAR (1<<7)
ram54288 0:a7a43371b306 491 #define cASM_CTRL1_START (1<<6)
ram54288 0:a7a43371b306 492 #define cASM_CTRL1_SELFTST (1<<5)
ram54288 0:a7a43371b306 493 #define cASM_CTRL1_CTR (1<<4)
ram54288 0:a7a43371b306 494 #define cASM_CTRL1_CBC (1<<3)
ram54288 0:a7a43371b306 495 #define cASM_CTRL1_AES (1<<2)
ram54288 0:a7a43371b306 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
ram54288 0:a7a43371b306 497
ram54288 0:a7a43371b306 498 // ASM_CTRL2 bits
ram54288 0:a7a43371b306 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
ram54288 0:a7a43371b306 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
ram54288 0:a7a43371b306 501 #define cASM_CTRL2_TSTPAS (1<<1)
ram54288 0:a7a43371b306 502
ram54288 0:a7a43371b306 503 // CLK_OUT_CTRL bits
ram54288 0:a7a43371b306 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
ram54288 0:a7a43371b306 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
ram54288 0:a7a43371b306 506 #define cCLK_OUT_CTRL_SR (1<<5)
ram54288 0:a7a43371b306 507 #define cCLK_OUT_CTRL_DS (1<<4)
ram54288 0:a7a43371b306 508 #define cCLK_OUT_CTRL_EN (1<<3)
ram54288 0:a7a43371b306 509 #define cCLK_OUT_CTRL_DIV (7)
ram54288 0:a7a43371b306 510
ram54288 0:a7a43371b306 511 // PWR_MODES bits
ram54288 0:a7a43371b306 512 #define cPWR_MODES_XTAL_READY (1<<5)
ram54288 0:a7a43371b306 513 #define cPWR_MODES_XTALEN (1<<4)
ram54288 0:a7a43371b306 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
ram54288 0:a7a43371b306 515 #define cPWR_MODES_AUTODOZE (1<<1)
ram54288 0:a7a43371b306 516 #define cPWR_MODES_PMC_MODE (1<<0)
ram54288 0:a7a43371b306 517
ram54288 0:a7a43371b306 518 // RX_FRAME_FILTER bits
ram54288 0:a7a43371b306 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
ram54288 0:a7a43371b306 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
ram54288 0:a7a43371b306 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
ram54288 0:a7a43371b306 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
ram54288 0:a7a43371b306 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
ram54288 0:a7a43371b306 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
ram54288 0:a7a43371b306 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
ram54288 0:a7a43371b306 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
ram54288 0:a7a43371b306 527
ram54288 0:a7a43371b306 528 typedef union regRX_FRAME_FILTER_tag{
ram54288 0:a7a43371b306 529 uint8_t byte;
ram54288 0:a7a43371b306 530 struct{
ram54288 0:a7a43371b306 531 uint8_t FRAME_FLT_BEACON_FT:1;
ram54288 0:a7a43371b306 532 uint8_t FRAME_FLT_DATA_FT:1;
ram54288 0:a7a43371b306 533 uint8_t FRAME_FLT_ACK_FT:1;
ram54288 0:a7a43371b306 534 uint8_t FRAME_FLT_CMD_FT:1;
ram54288 0:a7a43371b306 535 uint8_t FRAME_FLT_NS_FT:1;
ram54288 0:a7a43371b306 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
ram54288 0:a7a43371b306 537 uint8_t FRAME_FLT_FRM_VER:2;
ram54288 0:a7a43371b306 538 }bit;
ram54288 0:a7a43371b306 539 } regRX_FRAME_FILTER_t;
ram54288 0:a7a43371b306 540
ram54288 0:a7a43371b306 541 // DUAL_PAN_CTRL bits
ram54288 0:a7a43371b306 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
ram54288 0:a7a43371b306 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
ram54288 0:a7a43371b306 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
ram54288 0:a7a43371b306 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
ram54288 0:a7a43371b306 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
ram54288 0:a7a43371b306 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
ram54288 0:a7a43371b306 548
ram54288 0:a7a43371b306 549 // DUAL_PAN_STS bits
ram54288 0:a7a43371b306 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
ram54288 0:a7a43371b306 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
ram54288 0:a7a43371b306 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
ram54288 0:a7a43371b306 553
ram54288 0:a7a43371b306 554 // CCA_CTRL bits
ram54288 0:a7a43371b306 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
ram54288 0:a7a43371b306 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
ram54288 0:a7a43371b306 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
ram54288 0:a7a43371b306 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
ram54288 0:a7a43371b306 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
ram54288 0:a7a43371b306 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
ram54288 0:a7a43371b306 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
ram54288 0:a7a43371b306 562
ram54288 0:a7a43371b306 563 // GPIO_DATA bits
ram54288 0:a7a43371b306 564 #define cGPIO_DATA_7 (1<<7)
ram54288 0:a7a43371b306 565 #define cGPIO_DATA_6 (1<<6)
ram54288 0:a7a43371b306 566 #define cGPIO_DATA_5 (1<<5)
ram54288 0:a7a43371b306 567 #define cGPIO_DATA_4 (1<<4)
ram54288 0:a7a43371b306 568 #define cGPIO_DATA_3 (1<<3)
ram54288 0:a7a43371b306 569 #define cGPIO_DATA_2 (1<<2)
ram54288 0:a7a43371b306 570 #define cGPIO_DATA_1 (1<<1)
ram54288 0:a7a43371b306 571 #define cGPIO_DATA_0 (1<<0)
ram54288 0:a7a43371b306 572
ram54288 0:a7a43371b306 573 // GPIO_DIR bits
ram54288 0:a7a43371b306 574 #define cGPIO_DIR_7 (1<<7)
ram54288 0:a7a43371b306 575 #define cGPIO_DIR_6 (1<<6)
ram54288 0:a7a43371b306 576 #define cGPIO_DIR_5 (1<<5)
ram54288 0:a7a43371b306 577 #define cGPIO_DIR_4 (1<<4)
ram54288 0:a7a43371b306 578 #define cGPIO_DIR_3 (1<<3)
ram54288 0:a7a43371b306 579 #define cGPIO_DIR_2 (1<<2)
ram54288 0:a7a43371b306 580 #define cGPIO_DIR_1 (1<<1)
ram54288 0:a7a43371b306 581 #define cGPIO_DIR_0 (1<<0)
ram54288 0:a7a43371b306 582
ram54288 0:a7a43371b306 583 // GPIO_PUL_EN bits
ram54288 0:a7a43371b306 584 #define cGPIO_PUL_EN_7 (1<<7)
ram54288 0:a7a43371b306 585 #define cGPIO_PUL_EN_6 (1<<6)
ram54288 0:a7a43371b306 586 #define cGPIO_PUL_EN_5 (1<<5)
ram54288 0:a7a43371b306 587 #define cGPIO_PUL_EN_4 (1<<4)
ram54288 0:a7a43371b306 588 #define cGPIO_PUL_EN_3 (1<<3)
ram54288 0:a7a43371b306 589 #define cGPIO_PUL_EN_2 (1<<2)
ram54288 0:a7a43371b306 590 #define cGPIO_PUL_EN_1 (1<<1)
ram54288 0:a7a43371b306 591 #define cGPIO_PUL_EN_0 (1<<0)
ram54288 0:a7a43371b306 592
ram54288 0:a7a43371b306 593 // GPIO_PUL_SEL bits
ram54288 0:a7a43371b306 594 #define cGPIO_PUL_SEL_7 (1<<7)
ram54288 0:a7a43371b306 595 #define cGPIO_PUL_SEL_6 (1<<6)
ram54288 0:a7a43371b306 596 #define cGPIO_PUL_SEL_5 (1<<5)
ram54288 0:a7a43371b306 597 #define cGPIO_PUL_SEL_4 (1<<4)
ram54288 0:a7a43371b306 598 #define cGPIO_PUL_SEL_3 (1<<3)
ram54288 0:a7a43371b306 599 #define cGPIO_PUL_SEL_2 (1<<2)
ram54288 0:a7a43371b306 600 #define cGPIO_PUL_SEL_1 (1<<1)
ram54288 0:a7a43371b306 601 #define cGPIO_PUL_SEL_0 (1<<0)
ram54288 0:a7a43371b306 602
ram54288 0:a7a43371b306 603 // GPIO_DS bits
ram54288 0:a7a43371b306 604 #define cGPIO_DS_7 (1<<7)
ram54288 0:a7a43371b306 605 #define cGPIO_DS_6 (1<<6)
ram54288 0:a7a43371b306 606 #define cGPIO_DS_5 (1<<5)
ram54288 0:a7a43371b306 607 #define cGPIO_DS_4 (1<<4)
ram54288 0:a7a43371b306 608 #define cGPIO_DS_3 (1<<3)
ram54288 0:a7a43371b306 609 #define cGPIO_DS_2 (1<<2)
ram54288 0:a7a43371b306 610 #define cGPIO_DS_1 (1<<1)
ram54288 0:a7a43371b306 611 #define cGPIO_DS_0 (1<<0)
ram54288 0:a7a43371b306 612
ram54288 0:a7a43371b306 613 // SPI_CTRL bits
ram54288 0:a7a43371b306 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
ram54288 0:a7a43371b306 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
ram54288 0:a7a43371b306 616
ram54288 0:a7a43371b306 617 // ANT_PAD_CTRL bits
ram54288 0:a7a43371b306 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
ram54288 0:a7a43371b306 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
ram54288 0:a7a43371b306 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
ram54288 0:a7a43371b306 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
ram54288 0:a7a43371b306 622 #define cANT_PAD_CTRL_ANTX_EN (3)
ram54288 0:a7a43371b306 623
ram54288 0:a7a43371b306 624 // MISC_PAD_CTRL bits
ram54288 0:a7a43371b306 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
ram54288 0:a7a43371b306 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
ram54288 0:a7a43371b306 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
ram54288 0:a7a43371b306 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
ram54288 0:a7a43371b306 629
ram54288 0:a7a43371b306 630 // ANT_AGC_CTRL bits
ram54288 0:a7a43371b306 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
ram54288 0:a7a43371b306 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
ram54288 0:a7a43371b306 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
ram54288 0:a7a43371b306 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
ram54288 0:a7a43371b306 635
ram54288 0:a7a43371b306 636 // BSM_CTRL bits
ram54288 0:a7a43371b306 637 #define cBSM_CTRL_BSM_EN (1<<0)
ram54288 0:a7a43371b306 638
ram54288 0:a7a43371b306 639 // SOFT_RESET bits
ram54288 0:a7a43371b306 640 #define cSOFT_RESET_SOG_RST (1<<7)
ram54288 0:a7a43371b306 641 #define cSOFT_RESET_REGS_RST (1<<4)
ram54288 0:a7a43371b306 642 #define cSOFT_RESET_PLL_RST (1<<3)
ram54288 0:a7a43371b306 643 #define cSOFT_RESET_TX_RST (1<<2)
ram54288 0:a7a43371b306 644 #define cSOFT_RESET_RX_RST (1<<1)
ram54288 0:a7a43371b306 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
ram54288 0:a7a43371b306 646
ram54288 0:a7a43371b306 647 // SEQ_MGR_CTRL bits
ram54288 0:a7a43371b306 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
ram54288 0:a7a43371b306 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
ram54288 0:a7a43371b306 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
ram54288 0:a7a43371b306 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
ram54288 0:a7a43371b306 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
ram54288 0:a7a43371b306 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
ram54288 0:a7a43371b306 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
ram54288 0:a7a43371b306 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
ram54288 0:a7a43371b306 656
ram54288 0:a7a43371b306 657 // SEQ_MGR_STS bits
ram54288 0:a7a43371b306 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
ram54288 0:a7a43371b306 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
ram54288 0:a7a43371b306 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
ram54288 0:a7a43371b306 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
ram54288 0:a7a43371b306 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
ram54288 0:a7a43371b306 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
ram54288 0:a7a43371b306 664
ram54288 0:a7a43371b306 665 // ABORT_STS bits
ram54288 0:a7a43371b306 666 #define cABORT_STS_PLL_ABORTED (1<<2)
ram54288 0:a7a43371b306 667 #define cABORT_STS_TC3_ABORTED (1<<1)
ram54288 0:a7a43371b306 668 #define cABORT_STS_SW_ABORTED (1<<0)
ram54288 0:a7a43371b306 669
ram54288 0:a7a43371b306 670 // FILTERFAIL_CODE2 bits
ram54288 0:a7a43371b306 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
ram54288 0:a7a43371b306 672 #define cFILTERFAIL_CODE2_9_8 (3)
ram54288 0:a7a43371b306 673
ram54288 0:a7a43371b306 674 // PHY_STS bits
ram54288 0:a7a43371b306 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
ram54288 0:a7a43371b306 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
ram54288 0:a7a43371b306 677 #define cPHY_STS_PLL_LOCK (1<<5)
ram54288 0:a7a43371b306 678 #define cPHY_STS_CRCVALID (1<<3)
ram54288 0:a7a43371b306 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
ram54288 0:a7a43371b306 680 #define cPHY_STS_SFD_DET (1<<1)
ram54288 0:a7a43371b306 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
ram54288 0:a7a43371b306 682
ram54288 0:a7a43371b306 683 // TESTMODE_CTRL bits
ram54288 0:a7a43371b306 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
ram54288 0:a7a43371b306 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
ram54288 0:a7a43371b306 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
ram54288 0:a7a43371b306 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
ram54288 0:a7a43371b306 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
ram54288 0:a7a43371b306 689
ram54288 0:a7a43371b306 690 // DTM_CTRL1 bits
ram54288 0:a7a43371b306 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
ram54288 0:a7a43371b306 692 #define cDTM_CTRL1_DTM_EN (1<<6)
ram54288 0:a7a43371b306 693 #define cDTM_CTRL1_PAGE5 (1<<5)
ram54288 0:a7a43371b306 694 #define cDTM_CTRL1_PAGE4 (1<<4)
ram54288 0:a7a43371b306 695 #define cDTM_CTRL1_PAGE3 (1<<3)
ram54288 0:a7a43371b306 696 #define cDTM_CTRL1_PAGE2 (1<<2)
ram54288 0:a7a43371b306 697 #define cDTM_CTRL1_PAGE1 (1<<1)
ram54288 0:a7a43371b306 698 #define cDTM_CTRL1_PAGE0 (1<<0)
ram54288 0:a7a43371b306 699
ram54288 0:a7a43371b306 700 // TX_MODE_CTRL
ram54288 0:a7a43371b306 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
ram54288 0:a7a43371b306 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
ram54288 0:a7a43371b306 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
ram54288 0:a7a43371b306 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
ram54288 0:a7a43371b306 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
ram54288 0:a7a43371b306 706
ram54288 0:a7a43371b306 707 #define cTX_MODE_CTRL_DTS_MASK (7)
ram54288 0:a7a43371b306 708
ram54288 0:a7a43371b306 709 // CLK_OUT_CTRL bits
ram54288 0:a7a43371b306 710 #define cCLK_OUT_EXTEND (1<<7)
ram54288 0:a7a43371b306 711 #define cCLK_OUT_HIZ (1<<6)
ram54288 0:a7a43371b306 712 #define cCLK_OUT_SR (1<<5)
ram54288 0:a7a43371b306 713 #define cCLK_OUT_DS (1<<4)
ram54288 0:a7a43371b306 714 #define cCLK_OUT_EN (1<<3)
ram54288 0:a7a43371b306 715 #define cCLK_OUT_DIV_Mask (7<<0)
ram54288 0:a7a43371b306 716
ram54288 0:a7a43371b306 717 #define gCLK_OUT_FREQ_32_MHz (0)
ram54288 0:a7a43371b306 718 #define gCLK_OUT_FREQ_16_MHz (1)
ram54288 0:a7a43371b306 719 #define gCLK_OUT_FREQ_8_MHz (2)
ram54288 0:a7a43371b306 720 #define gCLK_OUT_FREQ_4_MHz (3)
ram54288 0:a7a43371b306 721 #define gCLK_OUT_FREQ_1_MHz (4)
ram54288 0:a7a43371b306 722 #define gCLK_OUT_FREQ_250_KHz (5)
ram54288 0:a7a43371b306 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
ram54288 0:a7a43371b306 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
ram54288 0:a7a43371b306 725 #define gCLK_OUT_FREQ_DISABLE (8)
ram54288 0:a7a43371b306 726
ram54288 0:a7a43371b306 727
ram54288 0:a7a43371b306 728
ram54288 0:a7a43371b306 729
ram54288 0:a7a43371b306 730 #endif /* __MCR20_REG_H__ */