Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

easy-connect/mcr20a-rf-driver/source/MCR20Overwrites.h@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /*!
ram54288 0:a7a43371b306 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:a7a43371b306 3 * All rights reserved.
ram54288 0:a7a43371b306 4 *
ram54288 0:a7a43371b306 5 * \file MCR20Overwrites.h
ram54288 0:a7a43371b306 6 * Description: Overwrites header file for MCR20 Register values
ram54288 0:a7a43371b306 7 *
ram54288 0:a7a43371b306 8 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:a7a43371b306 9 * are permitted provided that the following conditions are met:
ram54288 0:a7a43371b306 10 *
ram54288 0:a7a43371b306 11 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:a7a43371b306 12 * of conditions and the following disclaimer.
ram54288 0:a7a43371b306 13 *
ram54288 0:a7a43371b306 14 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:a7a43371b306 15 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:a7a43371b306 16 * other materials provided with the distribution.
ram54288 0:a7a43371b306 17 *
ram54288 0:a7a43371b306 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:a7a43371b306 19 * contributors may be used to endorse or promote products derived from this
ram54288 0:a7a43371b306 20 * software without specific prior written permission.
ram54288 0:a7a43371b306 21 *
ram54288 0:a7a43371b306 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:a7a43371b306 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:a7a43371b306 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:a7a43371b306 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:a7a43371b306 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:a7a43371b306 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:a7a43371b306 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:a7a43371b306 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:a7a43371b306 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:a7a43371b306 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:a7a43371b306 32 */
ram54288 0:a7a43371b306 33
ram54288 0:a7a43371b306 34 #ifndef OVERWRITES_H_
ram54288 0:a7a43371b306 35 #define OVERWRITES_H_
ram54288 0:a7a43371b306 36
ram54288 0:a7a43371b306 37 typedef struct overwrites_tag {
ram54288 0:a7a43371b306 38 char address;
ram54288 0:a7a43371b306 39 char data;
ram54288 0:a7a43371b306 40 }overwrites_t;
ram54288 0:a7a43371b306 41
ram54288 0:a7a43371b306 42
ram54288 0:a7a43371b306 43 /*****************************************************************************************************************/
ram54288 0:a7a43371b306 44 // This file is created exclusively for use with the transceiver 2.0 silicon
ram54288 0:a7a43371b306 45 // and is provided for the world to use. It contains a list of all
ram54288 0:a7a43371b306 46 // known overwrite values. Overwrite values are non-default register
ram54288 0:a7a43371b306 47 // values that configure the transceiver device to a more optimally performing
ram54288 0:a7a43371b306 48 // posture. It is expected that low level software (i.e. PHY) will
ram54288 0:a7a43371b306 49 // consume this file as a #include, and transfer the contents to the
ram54288 0:a7a43371b306 50 // the indicated addresses in the transceiver's memory space. This file has
ram54288 0:a7a43371b306 51 // at least one required entry, that being its own version current version
ram54288 0:a7a43371b306 52 // number, to be stored at transceiver's location 0x3B the
ram54288 0:a7a43371b306 53 // OVERWRITES_VERSION_NUMBER register. The RAM register is provided in
ram54288 0:a7a43371b306 54 // the transceiver address space to assist in future debug efforts. The
ram54288 0:a7a43371b306 55 // analyst may read this location (once device has been booted with
ram54288 0:a7a43371b306 56 // mysterious software) and have a good indication of what register
ram54288 0:a7a43371b306 57 // overwrites were performed (with all versions of the overwrites.h file
ram54288 0:a7a43371b306 58 // being archived forever at the Compass location shown above.
ram54288 0:a7a43371b306 59 //
ram54288 0:a7a43371b306 60 // The transceiver has an indirect register (IAR) space. Write access to this space
ram54288 0:a7a43371b306 61 // requires 3 or more writes:
ram54288 0:a7a43371b306 62 // 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E
ram54288 0:a7a43371b306 63 // 2nd) IAR Register #0x00 - 0xFF.
ram54288 0:a7a43371b306 64 // 3rd) The data to write
ram54288 0:a7a43371b306 65 // nth) Burst mode additional data if required.
ram54288 0:a7a43371b306 66 //
ram54288 0:a7a43371b306 67 // Write access to direct space requires only a single address, data pair.
ram54288 0:a7a43371b306 68
ram54288 0:a7a43371b306 69 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 70 {0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak)
ram54288 0:a7a43371b306 71 {0x23, 0x17} //PA_PWR new default Power Step is "23"
ram54288 0:a7a43371b306 72 };
ram54288 0:a7a43371b306 73
ram54288 0:a7a43371b306 74 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 75 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 76 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 77 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 78 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 79 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 80 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 81 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 82 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 83 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 84 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 85 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 86 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 87 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 88 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 89 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 90 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
ram54288 0:a7a43371b306 91 {0x52, 0x55}, //AGC_THR1 RSSI tune up
ram54288 0:a7a43371b306 92 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
ram54288 0:a7a43371b306 93 {0x66, 0x5F}, //ATT_RSSI1 tune up
ram54288 0:a7a43371b306 94 {0x67, 0x8F}, //ATT_RSSI2 tune up
ram54288 0:a7a43371b306 95 {0x68, 0x61}, //RSSI_OFFSET
ram54288 0:a7a43371b306 96 {0x78, 0x03}, //CHF_PMAGAIN
ram54288 0:a7a43371b306 97 {0x22, 0x50}, //CCA1_THRESH
ram54288 0:a7a43371b306 98 {0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity
ram54288 0:a7a43371b306 99 {0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak)
ram54288 0:a7a43371b306 100 };
ram54288 0:a7a43371b306 101
ram54288 0:a7a43371b306 102
ram54288 0:a7a43371b306 103 /* begin of deprecated versions
ram54288 0:a7a43371b306 104
ram54288 0:a7a43371b306 105 ==VERSION 1==
ram54288 0:a7a43371b306 106 (version 1 is empty)
ram54288 0:a7a43371b306 107
ram54288 0:a7a43371b306 108 ==VERSION 2==
ram54288 0:a7a43371b306 109 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 110 {0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 111 };
ram54288 0:a7a43371b306 112
ram54288 0:a7a43371b306 113 ==VERSION 3==
ram54288 0:a7a43371b306 114 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 115 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 116 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 117 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 118 };
ram54288 0:a7a43371b306 119
ram54288 0:a7a43371b306 120 ==VERSION 4==
ram54288 0:a7a43371b306 121 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 122 {0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default
ram54288 0:a7a43371b306 123 };
ram54288 0:a7a43371b306 124
ram54288 0:a7a43371b306 125 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 126 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 127 {0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 128 {0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 129 {0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 130 };
ram54288 0:a7a43371b306 131
ram54288 0:a7a43371b306 132 ==VERSION 5==
ram54288 0:a7a43371b306 133 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 134 {0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 135 };
ram54288 0:a7a43371b306 136
ram54288 0:a7a43371b306 137 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 138 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 139 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 140 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 141 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 142 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 143 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 144 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 145 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 146 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 147 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 148 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 149 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 150 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 151 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 152 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 153 };
ram54288 0:a7a43371b306 154
ram54288 0:a7a43371b306 155 ==VERSION 6==
ram54288 0:a7a43371b306 156 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 157 {0x3B, 0x06} //version 06: disable PA calibration
ram54288 0:a7a43371b306 158 };
ram54288 0:a7a43371b306 159
ram54288 0:a7a43371b306 160 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 161 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 162 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 163 {0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 164 {0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 165 {0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 166 {0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 167 {0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 168 {0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 169 {0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 170 {0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 171 {0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 172 {0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 173 {0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 174 {0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 175 {0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 176 {0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration
ram54288 0:a7a43371b306 177 };
ram54288 0:a7a43371b306 178
ram54288 0:a7a43371b306 179 ==VERSION 7==
ram54288 0:a7a43371b306 180 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 181 {0x3B, 0x07} //version 07: updated registers for ED/RSSI
ram54288 0:a7a43371b306 182 };
ram54288 0:a7a43371b306 183
ram54288 0:a7a43371b306 184 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 185 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 186 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 187 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 188 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 189 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 190 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 191 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 192 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 193 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 194 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 195 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 196 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 197 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 198 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 199 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 200 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
ram54288 0:a7a43371b306 201 {0x52, 0x73}, //AGC_THR1 RSSI tune up
ram54288 0:a7a43371b306 202 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
ram54288 0:a7a43371b306 203 {0x66, 0x5F}, //ATT_RSSI1 tune up
ram54288 0:a7a43371b306 204 {0x67, 0x8F}, //ATT_RSSI2 tune up
ram54288 0:a7a43371b306 205 {0x68, 0x60}, //RSSI_OFFSET
ram54288 0:a7a43371b306 206 {0x69, 0x65} //RSSI_SLOPE
ram54288 0:a7a43371b306 207 };
ram54288 0:a7a43371b306 208
ram54288 0:a7a43371b306 209
ram54288 0:a7a43371b306 210 ==VERSION 8==
ram54288 0:a7a43371b306 211 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 212 {0x3B, 0x08} //version 08: updated registers for ED/RSSI
ram54288 0:a7a43371b306 213 };
ram54288 0:a7a43371b306 214
ram54288 0:a7a43371b306 215 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 216 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 217 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 218 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 219 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 220 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 221 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 222 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 223 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 224 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 225 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 226 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 227 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 228 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 229 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 230 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 231 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
ram54288 0:a7a43371b306 232 {0x52, 0x73}, //AGC_THR1 RSSI tune up
ram54288 0:a7a43371b306 233 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
ram54288 0:a7a43371b306 234 {0x66, 0x5F}, //ATT_RSSI1 tune up
ram54288 0:a7a43371b306 235 {0x67, 0x8F}, //ATT_RSSI2 tune up
ram54288 0:a7a43371b306 236 {0x69, 0x65} //RSSI_SLOPE
ram54288 0:a7a43371b306 237 {0x68, 0x61}, //RSSI_OFFSET
ram54288 0:a7a43371b306 238 {0x78, 0x03} //CHF_PMAGAIN
ram54288 0:a7a43371b306 239 };
ram54288 0:a7a43371b306 240
ram54288 0:a7a43371b306 241
ram54288 0:a7a43371b306 242 ==VERSION 9==
ram54288 0:a7a43371b306 243 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 244 {0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep
ram54288 0:a7a43371b306 245 {0x23, 0x17} //PA_PWR new default value
ram54288 0:a7a43371b306 246 };
ram54288 0:a7a43371b306 247
ram54288 0:a7a43371b306 248 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 249 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 250 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 251 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 252 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 253 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 254 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 255 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 256 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 257 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 258 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 259 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 260 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 261 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 262 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 263 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 264 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
ram54288 0:a7a43371b306 265 {0x52, 0x55}, //AGC_THR1 RSSI tune up
ram54288 0:a7a43371b306 266 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
ram54288 0:a7a43371b306 267 {0x66, 0x5F}, //ATT_RSSI1 tune up
ram54288 0:a7a43371b306 268 {0x67, 0x8F}, //ATT_RSSI2 tune up
ram54288 0:a7a43371b306 269 {0x68, 0x61}, //RSSI_OFFSET
ram54288 0:a7a43371b306 270 {0x78, 0x03} //CHF_PMAGAIN
ram54288 0:a7a43371b306 271 };
ram54288 0:a7a43371b306 272
ram54288 0:a7a43371b306 273 ==VERSION A==
ram54288 0:a7a43371b306 274 overwrites_t const overwrites_direct[] ={
ram54288 0:a7a43371b306 275 {0x3B, 0x0A} //version 0A: updated registers for CCA
ram54288 0:a7a43371b306 276 {0x23, 0x17} //PA_PWR new default Power Step is "23"
ram54288 0:a7a43371b306 277 };
ram54288 0:a7a43371b306 278
ram54288 0:a7a43371b306 279 overwrites_t const overwrites_indirect[] ={
ram54288 0:a7a43371b306 280 {0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents)
ram54288 0:a7a43371b306 281 {0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3
ram54288 0:a7a43371b306 282 {0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1
ram54288 0:a7a43371b306 283 {0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid)
ram54288 0:a7a43371b306 284 {0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 285 {0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 286 {0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 287 {0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 288 {0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 289 {0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 290 {0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 291 {0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 292 {0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 293 {0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 294 {0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca)
ram54288 0:a7a43371b306 295 {0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration
ram54288 0:a7a43371b306 296 {0x52, 0x55}, //AGC_THR1 RSSI tune up
ram54288 0:a7a43371b306 297 {0x53, 0x2D}, //AGC_THR2 RSSI tune up
ram54288 0:a7a43371b306 298 {0x66, 0x5F}, //ATT_RSSI1 tune up
ram54288 0:a7a43371b306 299 {0x67, 0x8F}, //ATT_RSSI2 tune up
ram54288 0:a7a43371b306 300 {0x68, 0x61}, //RSSI_OFFSET
ram54288 0:a7a43371b306 301 {0x78, 0x03} //CHF_PMAGAIN
ram54288 0:a7a43371b306 302 {0x22, 0x50} //CCA1_THRESH
ram54288 0:a7a43371b306 303 };
ram54288 0:a7a43371b306 304
ram54288 0:a7a43371b306 305 end of deprecated versions */
ram54288 0:a7a43371b306 306
ram54288 0:a7a43371b306 307
ram54288 0:a7a43371b306 308 #endif //OVERWRITES_H_
ram54288 0:a7a43371b306 309