Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

easy-connect/mcr20a-rf-driver/source/MCR20Drv.h@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /*!
ram54288 0:a7a43371b306 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:a7a43371b306 3 * All rights reserved.
ram54288 0:a7a43371b306 4 *
ram54288 0:a7a43371b306 5 * \file MCR20Drv.h
ram54288 0:a7a43371b306 6 *
ram54288 0:a7a43371b306 7 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:a7a43371b306 8 * are permitted provided that the following conditions are met:
ram54288 0:a7a43371b306 9 *
ram54288 0:a7a43371b306 10 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:a7a43371b306 11 * of conditions and the following disclaimer.
ram54288 0:a7a43371b306 12 *
ram54288 0:a7a43371b306 13 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:a7a43371b306 14 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:a7a43371b306 15 * other materials provided with the distribution.
ram54288 0:a7a43371b306 16 *
ram54288 0:a7a43371b306 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:a7a43371b306 18 * contributors may be used to endorse or promote products derived from this
ram54288 0:a7a43371b306 19 * software without specific prior written permission.
ram54288 0:a7a43371b306 20 *
ram54288 0:a7a43371b306 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:a7a43371b306 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:a7a43371b306 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:a7a43371b306 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:a7a43371b306 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:a7a43371b306 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:a7a43371b306 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:a7a43371b306 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:a7a43371b306 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:a7a43371b306 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:a7a43371b306 31 */
ram54288 0:a7a43371b306 32
ram54288 0:a7a43371b306 33 #ifndef __MCR20_DRV_H__
ram54288 0:a7a43371b306 34 #define __MCR20_DRV_H__
ram54288 0:a7a43371b306 35
ram54288 0:a7a43371b306 36
ram54288 0:a7a43371b306 37 /*****************************************************************************
ram54288 0:a7a43371b306 38 * INCLUDED HEADERS *
ram54288 0:a7a43371b306 39 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 40 * Add to this section all the headers that this module needs to include. *
ram54288 0:a7a43371b306 41 * Note that it is not a good practice to include header files into header *
ram54288 0:a7a43371b306 42 * files, so use this section only if there is no other better solution. *
ram54288 0:a7a43371b306 43 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 44 *****************************************************************************/
ram54288 0:a7a43371b306 45
ram54288 0:a7a43371b306 46 /*****************************************************************************
ram54288 0:a7a43371b306 47 * PRIVATE MACROS *
ram54288 0:a7a43371b306 48 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 49 * Add to this section all the access macros, registers mappings, bit access *
ram54288 0:a7a43371b306 50 * macros, masks, flags etc ...
ram54288 0:a7a43371b306 51 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 52 *****************************************************************************/
ram54288 0:a7a43371b306 53
ram54288 0:a7a43371b306 54 /* Disable XCVR clock output by default, to reduce power consumption */
ram54288 0:a7a43371b306 55 #ifndef gMCR20_ClkOutFreq_d
ram54288 0:a7a43371b306 56 #define gMCR20_ClkOutFreq_d gCLK_OUT_FREQ_DISABLE
ram54288 0:a7a43371b306 57 #endif
ram54288 0:a7a43371b306 58
ram54288 0:a7a43371b306 59 /*****************************************************************************
ram54288 0:a7a43371b306 60 * PUBLIC FUNCTIONS *
ram54288 0:a7a43371b306 61 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 62 * Add to this section all the global functions prototype preceded (as a *
ram54288 0:a7a43371b306 63 * good practice) by the keyword 'extern' *
ram54288 0:a7a43371b306 64 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 65 *****************************************************************************/
ram54288 0:a7a43371b306 66
ram54288 0:a7a43371b306 67 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 68 * Name: MCR20Drv_Init
ram54288 0:a7a43371b306 69 * Description: -
ram54288 0:a7a43371b306 70 * Parameters: -
ram54288 0:a7a43371b306 71 * Return: -
ram54288 0:a7a43371b306 72 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 73 extern void MCR20Drv_Init
ram54288 0:a7a43371b306 74 (
ram54288 0:a7a43371b306 75 void
ram54288 0:a7a43371b306 76 );
ram54288 0:a7a43371b306 77
ram54288 0:a7a43371b306 78 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 79 * Name: MCR20Drv_SPI_DMA_Init
ram54288 0:a7a43371b306 80 * Description: -
ram54288 0:a7a43371b306 81 * Parameters: -
ram54288 0:a7a43371b306 82 * Return: -
ram54288 0:a7a43371b306 83 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 84 void MCR20Drv_SPI_DMA_Init
ram54288 0:a7a43371b306 85 (
ram54288 0:a7a43371b306 86 void
ram54288 0:a7a43371b306 87 );
ram54288 0:a7a43371b306 88
ram54288 0:a7a43371b306 89 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 90 * Name: MCR20Drv_Start_PB_DMA_SPI_Write
ram54288 0:a7a43371b306 91 * Description: -
ram54288 0:a7a43371b306 92 * Parameters: -
ram54288 0:a7a43371b306 93 * Return: -
ram54288 0:a7a43371b306 94 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 95 void MCR20Drv_Start_PB_DMA_SPI_Write
ram54288 0:a7a43371b306 96 (
ram54288 0:a7a43371b306 97 uint8_t * srcAddress,
ram54288 0:a7a43371b306 98 uint8_t numOfBytes
ram54288 0:a7a43371b306 99 );
ram54288 0:a7a43371b306 100
ram54288 0:a7a43371b306 101 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 102 * Name: MCR20Drv_Start_PB_DMA_SPI_Read
ram54288 0:a7a43371b306 103 * Description: -
ram54288 0:a7a43371b306 104 * Parameters: -
ram54288 0:a7a43371b306 105 * Return: -
ram54288 0:a7a43371b306 106 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 107 void MCR20Drv_Start_PB_DMA_SPI_Read
ram54288 0:a7a43371b306 108 (
ram54288 0:a7a43371b306 109 uint8_t * dstAddress,
ram54288 0:a7a43371b306 110 uint8_t numOfBytes
ram54288 0:a7a43371b306 111 );
ram54288 0:a7a43371b306 112
ram54288 0:a7a43371b306 113 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 114 * Name: MCR20Drv_DirectAccessSPIWrite
ram54288 0:a7a43371b306 115 * Description: -
ram54288 0:a7a43371b306 116 * Parameters: -
ram54288 0:a7a43371b306 117 * Return: -
ram54288 0:a7a43371b306 118 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 119 void MCR20Drv_DirectAccessSPIWrite
ram54288 0:a7a43371b306 120 (
ram54288 0:a7a43371b306 121 uint8_t address,
ram54288 0:a7a43371b306 122 uint8_t value
ram54288 0:a7a43371b306 123 );
ram54288 0:a7a43371b306 124
ram54288 0:a7a43371b306 125 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 126 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 127 * Description: -
ram54288 0:a7a43371b306 128 * Parameters: -
ram54288 0:a7a43371b306 129 * Return: -
ram54288 0:a7a43371b306 130 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 131 void MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 132 (
ram54288 0:a7a43371b306 133 uint8_t startAddress,
ram54288 0:a7a43371b306 134 uint8_t * byteArray,
ram54288 0:a7a43371b306 135 uint8_t numOfBytes
ram54288 0:a7a43371b306 136 );
ram54288 0:a7a43371b306 137
ram54288 0:a7a43371b306 138 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 139 * Name: MCR20Drv_PB_SPIBurstWrite
ram54288 0:a7a43371b306 140 * Description: -
ram54288 0:a7a43371b306 141 * Parameters: -
ram54288 0:a7a43371b306 142 * Return: -
ram54288 0:a7a43371b306 143 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 144 void MCR20Drv_PB_SPIBurstWrite
ram54288 0:a7a43371b306 145 (
ram54288 0:a7a43371b306 146 uint8_t * byteArray,
ram54288 0:a7a43371b306 147 uint8_t numOfBytes
ram54288 0:a7a43371b306 148 );
ram54288 0:a7a43371b306 149
ram54288 0:a7a43371b306 150 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 151 * Name: MCR20Drv_DirectAccessSPIRead
ram54288 0:a7a43371b306 152 * Description: -
ram54288 0:a7a43371b306 153 * Parameters: -
ram54288 0:a7a43371b306 154 * Return: -
ram54288 0:a7a43371b306 155 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 156 uint8_t MCR20Drv_DirectAccessSPIRead
ram54288 0:a7a43371b306 157 (
ram54288 0:a7a43371b306 158 uint8_t address
ram54288 0:a7a43371b306 159 );
ram54288 0:a7a43371b306 160
ram54288 0:a7a43371b306 161 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 162 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
ram54288 0:a7a43371b306 163 * Description: -
ram54288 0:a7a43371b306 164 * Parameters: -
ram54288 0:a7a43371b306 165 * Return: -
ram54288 0:a7a43371b306 166 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 167
ram54288 0:a7a43371b306 168 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
ram54288 0:a7a43371b306 169 (
ram54288 0:a7a43371b306 170 uint8_t startAddress,
ram54288 0:a7a43371b306 171 uint8_t * byteArray,
ram54288 0:a7a43371b306 172 uint8_t numOfBytes
ram54288 0:a7a43371b306 173 );
ram54288 0:a7a43371b306 174
ram54288 0:a7a43371b306 175 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 176 * Name: MCR20Drv_PB_SPIByteWrite
ram54288 0:a7a43371b306 177 * Description: -
ram54288 0:a7a43371b306 178 * Parameters: -
ram54288 0:a7a43371b306 179 * Return: -
ram54288 0:a7a43371b306 180 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 181 void MCR20Drv_PB_SPIByteWrite
ram54288 0:a7a43371b306 182 (
ram54288 0:a7a43371b306 183 uint8_t address,
ram54288 0:a7a43371b306 184 uint8_t value
ram54288 0:a7a43371b306 185 );
ram54288 0:a7a43371b306 186
ram54288 0:a7a43371b306 187 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 188 * Name: MCR20Drv_PB_SPIBurstRead
ram54288 0:a7a43371b306 189 * Description: -
ram54288 0:a7a43371b306 190 * Parameters: -
ram54288 0:a7a43371b306 191 * Return: -
ram54288 0:a7a43371b306 192 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 193 uint8_t MCR20Drv_PB_SPIBurstRead
ram54288 0:a7a43371b306 194 (
ram54288 0:a7a43371b306 195 uint8_t * byteArray,
ram54288 0:a7a43371b306 196 uint8_t numOfBytes
ram54288 0:a7a43371b306 197 );
ram54288 0:a7a43371b306 198
ram54288 0:a7a43371b306 199 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 200 * Name: MCR20Drv_IndirectAccessSPIWrite
ram54288 0:a7a43371b306 201 * Description: -
ram54288 0:a7a43371b306 202 * Parameters: -
ram54288 0:a7a43371b306 203 * Return: -
ram54288 0:a7a43371b306 204 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 205 void MCR20Drv_IndirectAccessSPIWrite
ram54288 0:a7a43371b306 206 (
ram54288 0:a7a43371b306 207 uint8_t address,
ram54288 0:a7a43371b306 208 uint8_t value
ram54288 0:a7a43371b306 209 );
ram54288 0:a7a43371b306 210
ram54288 0:a7a43371b306 211 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 212 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 213 * Description: -
ram54288 0:a7a43371b306 214 * Parameters: -
ram54288 0:a7a43371b306 215 * Return: -
ram54288 0:a7a43371b306 216 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 217 void MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 218 (
ram54288 0:a7a43371b306 219 uint8_t startAddress,
ram54288 0:a7a43371b306 220 uint8_t * byteArray,
ram54288 0:a7a43371b306 221 uint8_t numOfBytes
ram54288 0:a7a43371b306 222 );
ram54288 0:a7a43371b306 223
ram54288 0:a7a43371b306 224 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 225 * Name: MCR20Drv_IndirectAccessSPIRead
ram54288 0:a7a43371b306 226 * Description: -
ram54288 0:a7a43371b306 227 * Parameters: -
ram54288 0:a7a43371b306 228 * Return: -
ram54288 0:a7a43371b306 229 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 230 uint8_t MCR20Drv_IndirectAccessSPIRead
ram54288 0:a7a43371b306 231 (
ram54288 0:a7a43371b306 232 uint8_t address
ram54288 0:a7a43371b306 233 );
ram54288 0:a7a43371b306 234 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 235 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:a7a43371b306 236 * Description: -
ram54288 0:a7a43371b306 237 * Parameters: -
ram54288 0:a7a43371b306 238 * Return: -
ram54288 0:a7a43371b306 239 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 240 void MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:a7a43371b306 241 (
ram54288 0:a7a43371b306 242 uint8_t startAddress,
ram54288 0:a7a43371b306 243 uint8_t * byteArray,
ram54288 0:a7a43371b306 244 uint8_t numOfBytes
ram54288 0:a7a43371b306 245 );
ram54288 0:a7a43371b306 246
ram54288 0:a7a43371b306 247 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 248 * Name: MCR20Drv_IsIrqPending
ram54288 0:a7a43371b306 249 * Description: -
ram54288 0:a7a43371b306 250 * Parameters: -
ram54288 0:a7a43371b306 251 * Return: -
ram54288 0:a7a43371b306 252 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 253 uint32_t MCR20Drv_IsIrqPending
ram54288 0:a7a43371b306 254 (
ram54288 0:a7a43371b306 255 void
ram54288 0:a7a43371b306 256 );
ram54288 0:a7a43371b306 257
ram54288 0:a7a43371b306 258 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 259 * Name: MCR20Drv_IRQ_Disable
ram54288 0:a7a43371b306 260 * Description: -
ram54288 0:a7a43371b306 261 * Parameters: -
ram54288 0:a7a43371b306 262 * Return: -
ram54288 0:a7a43371b306 263 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 264 void MCR20Drv_IRQ_Disable
ram54288 0:a7a43371b306 265 (
ram54288 0:a7a43371b306 266 void
ram54288 0:a7a43371b306 267 );
ram54288 0:a7a43371b306 268
ram54288 0:a7a43371b306 269 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 270 * Name: MCR20Drv_IRQ_Enable
ram54288 0:a7a43371b306 271 * Description: -
ram54288 0:a7a43371b306 272 * Parameters: -
ram54288 0:a7a43371b306 273 * Return: -
ram54288 0:a7a43371b306 274 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 275 void MCR20Drv_IRQ_Enable
ram54288 0:a7a43371b306 276 (
ram54288 0:a7a43371b306 277 void
ram54288 0:a7a43371b306 278 );
ram54288 0:a7a43371b306 279
ram54288 0:a7a43371b306 280 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 281 * Name: MCR20Drv_RST_PortConfig
ram54288 0:a7a43371b306 282 * Description: -
ram54288 0:a7a43371b306 283 * Parameters: -
ram54288 0:a7a43371b306 284 * Return: -
ram54288 0:a7a43371b306 285 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 286 void MCR20Drv_RST_B_PortConfig
ram54288 0:a7a43371b306 287 (
ram54288 0:a7a43371b306 288 void
ram54288 0:a7a43371b306 289 );
ram54288 0:a7a43371b306 290
ram54288 0:a7a43371b306 291 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 292 * Name: MCR20Drv_RST_Assert
ram54288 0:a7a43371b306 293 * Description: -
ram54288 0:a7a43371b306 294 * Parameters: -
ram54288 0:a7a43371b306 295 * Return: -
ram54288 0:a7a43371b306 296 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 297 void MCR20Drv_RST_B_Assert
ram54288 0:a7a43371b306 298 (
ram54288 0:a7a43371b306 299 void
ram54288 0:a7a43371b306 300 );
ram54288 0:a7a43371b306 301
ram54288 0:a7a43371b306 302 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 303 * Name: MCR20Drv_RST_Deassert
ram54288 0:a7a43371b306 304 * Description: -
ram54288 0:a7a43371b306 305 * Parameters: -
ram54288 0:a7a43371b306 306 * Return: -
ram54288 0:a7a43371b306 307 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 308 void MCR20Drv_RST_B_Deassert
ram54288 0:a7a43371b306 309 (
ram54288 0:a7a43371b306 310 void
ram54288 0:a7a43371b306 311 );
ram54288 0:a7a43371b306 312
ram54288 0:a7a43371b306 313 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 314 * Name: MCR20Drv_SoftRST_Assert
ram54288 0:a7a43371b306 315 * Description: -
ram54288 0:a7a43371b306 316 * Parameters: -
ram54288 0:a7a43371b306 317 * Return: -
ram54288 0:a7a43371b306 318 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 319 void MCR20Drv_SoftRST_Assert
ram54288 0:a7a43371b306 320 (
ram54288 0:a7a43371b306 321 void
ram54288 0:a7a43371b306 322 );
ram54288 0:a7a43371b306 323
ram54288 0:a7a43371b306 324 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 325 * Name: MCR20Drv_SoftRST_Deassert
ram54288 0:a7a43371b306 326 * Description: -
ram54288 0:a7a43371b306 327 * Parameters: -
ram54288 0:a7a43371b306 328 * Return: -
ram54288 0:a7a43371b306 329 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 330 void MCR20Drv_SoftRST_Deassert
ram54288 0:a7a43371b306 331 (
ram54288 0:a7a43371b306 332 void
ram54288 0:a7a43371b306 333 );
ram54288 0:a7a43371b306 334
ram54288 0:a7a43371b306 335
ram54288 0:a7a43371b306 336 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 337 * Name: MCR20Drv_RESET
ram54288 0:a7a43371b306 338 * Description: -
ram54288 0:a7a43371b306 339 * Parameters: -
ram54288 0:a7a43371b306 340 * Return: -
ram54288 0:a7a43371b306 341 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 342 void MCR20Drv_RESET
ram54288 0:a7a43371b306 343 (
ram54288 0:a7a43371b306 344 void
ram54288 0:a7a43371b306 345 );
ram54288 0:a7a43371b306 346
ram54288 0:a7a43371b306 347 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 348 * Name: MCR20Drv_Soft_RESET
ram54288 0:a7a43371b306 349 * Description: -
ram54288 0:a7a43371b306 350 * Parameters: -
ram54288 0:a7a43371b306 351 * Return: -
ram54288 0:a7a43371b306 352 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 353 void MCR20Drv_Soft_RESET
ram54288 0:a7a43371b306 354 (
ram54288 0:a7a43371b306 355 void
ram54288 0:a7a43371b306 356 );
ram54288 0:a7a43371b306 357
ram54288 0:a7a43371b306 358 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 359 * Name: MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:a7a43371b306 360 * Description: -
ram54288 0:a7a43371b306 361 * Parameters: -
ram54288 0:a7a43371b306 362 * Return: -
ram54288 0:a7a43371b306 363 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 364 void MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:a7a43371b306 365 (
ram54288 0:a7a43371b306 366 uint8_t freqDiv
ram54288 0:a7a43371b306 367 );
ram54288 0:a7a43371b306 368
ram54288 0:a7a43371b306 369 #define ProtectFromMCR20Interrupt() MCR20Drv_IRQ_Disable()
ram54288 0:a7a43371b306 370 #define UnprotectFromMCR20Interrupt() MCR20Drv_IRQ_Enable()
ram54288 0:a7a43371b306 371
ram54288 0:a7a43371b306 372 #endif /* __MCR20_DRV_H__ */