Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

easy-connect/mcr20a-rf-driver/source/MCR20Drv.c@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /*!
ram54288 0:a7a43371b306 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
ram54288 0:a7a43371b306 3 * All rights reserved.
ram54288 0:a7a43371b306 4 *
ram54288 0:a7a43371b306 5 * \file MCR20Drv.c
ram54288 0:a7a43371b306 6 *
ram54288 0:a7a43371b306 7 * Redistribution and use in source and binary forms, with or without modification,
ram54288 0:a7a43371b306 8 * are permitted provided that the following conditions are met:
ram54288 0:a7a43371b306 9 *
ram54288 0:a7a43371b306 10 * o Redistributions of source code must retain the above copyright notice, this list
ram54288 0:a7a43371b306 11 * of conditions and the following disclaimer.
ram54288 0:a7a43371b306 12 *
ram54288 0:a7a43371b306 13 * o Redistributions in binary form must reproduce the above copyright notice, this
ram54288 0:a7a43371b306 14 * list of conditions and the following disclaimer in the documentation and/or
ram54288 0:a7a43371b306 15 * other materials provided with the distribution.
ram54288 0:a7a43371b306 16 *
ram54288 0:a7a43371b306 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
ram54288 0:a7a43371b306 18 * contributors may be used to endorse or promote products derived from this
ram54288 0:a7a43371b306 19 * software without specific prior written permission.
ram54288 0:a7a43371b306 20 *
ram54288 0:a7a43371b306 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ram54288 0:a7a43371b306 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
ram54288 0:a7a43371b306 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ram54288 0:a7a43371b306 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ram54288 0:a7a43371b306 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
ram54288 0:a7a43371b306 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ram54288 0:a7a43371b306 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ram54288 0:a7a43371b306 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
ram54288 0:a7a43371b306 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
ram54288 0:a7a43371b306 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ram54288 0:a7a43371b306 31 */
ram54288 0:a7a43371b306 32
ram54288 0:a7a43371b306 33
ram54288 0:a7a43371b306 34 /*****************************************************************************
ram54288 0:a7a43371b306 35 * INCLUDED HEADERS *
ram54288 0:a7a43371b306 36 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 37 * Add to this section all the headers that this module needs to include. *
ram54288 0:a7a43371b306 38 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 39 *****************************************************************************/
ram54288 0:a7a43371b306 40
ram54288 0:a7a43371b306 41 #include "platform/arm_hal_interrupt.h"
ram54288 0:a7a43371b306 42 #include "MCR20Drv.h"
ram54288 0:a7a43371b306 43 #include "MCR20Reg.h"
ram54288 0:a7a43371b306 44 #include "XcvrSpi.h"
ram54288 0:a7a43371b306 45
ram54288 0:a7a43371b306 46
ram54288 0:a7a43371b306 47 /*****************************************************************************
ram54288 0:a7a43371b306 48 * PRIVATE VARIABLES *
ram54288 0:a7a43371b306 49 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 50 * Add to this section all the variables and constants that have local *
ram54288 0:a7a43371b306 51 * (file) scope. *
ram54288 0:a7a43371b306 52 * Each of this declarations shall be preceded by the 'static' keyword. *
ram54288 0:a7a43371b306 53 * These variables / constants cannot be accessed outside this module. *
ram54288 0:a7a43371b306 54 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 55 *****************************************************************************/
ram54288 0:a7a43371b306 56 uint32_t mPhyIrqDisableCnt = 1;
ram54288 0:a7a43371b306 57
ram54288 0:a7a43371b306 58 /*****************************************************************************
ram54288 0:a7a43371b306 59 * PUBLIC VARIABLES *
ram54288 0:a7a43371b306 60 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 61 * Add to this section all the variables and constants that have global *
ram54288 0:a7a43371b306 62 * (project) scope. *
ram54288 0:a7a43371b306 63 * These variables / constants can be accessed outside this module. *
ram54288 0:a7a43371b306 64 * These variables / constants shall be preceded by the 'extern' keyword in *
ram54288 0:a7a43371b306 65 * the interface header. *
ram54288 0:a7a43371b306 66 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 67 *****************************************************************************/
ram54288 0:a7a43371b306 68
ram54288 0:a7a43371b306 69 /*****************************************************************************
ram54288 0:a7a43371b306 70 * PRIVATE FUNCTIONS PROTOTYPES *
ram54288 0:a7a43371b306 71 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 72 * Add to this section all the functions prototypes that have local (file) *
ram54288 0:a7a43371b306 73 * scope. *
ram54288 0:a7a43371b306 74 * These functions cannot be accessed outside this module. *
ram54288 0:a7a43371b306 75 * These declarations shall be preceded by the 'static' keyword. *
ram54288 0:a7a43371b306 76 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 77 *****************************************************************************/
ram54288 0:a7a43371b306 78
ram54288 0:a7a43371b306 79 /*****************************************************************************
ram54288 0:a7a43371b306 80 * PRIVATE FUNCTIONS *
ram54288 0:a7a43371b306 81 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 82 * Add to this section all the functions that have local (file) scope. *
ram54288 0:a7a43371b306 83 * These functions cannot be accessed outside this module. *
ram54288 0:a7a43371b306 84 * These definitions shall be preceded by the 'static' keyword. *
ram54288 0:a7a43371b306 85 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 86 *****************************************************************************/
ram54288 0:a7a43371b306 87
ram54288 0:a7a43371b306 88
ram54288 0:a7a43371b306 89 /*****************************************************************************
ram54288 0:a7a43371b306 90 * PUBLIC FUNCTIONS *
ram54288 0:a7a43371b306 91 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 92 * Add to this section all the functions that have global (project) scope. *
ram54288 0:a7a43371b306 93 * These functions can be accessed outside this module. *
ram54288 0:a7a43371b306 94 * These functions shall have their declarations (prototypes) within the *
ram54288 0:a7a43371b306 95 * interface header file and shall be preceded by the 'extern' keyword. *
ram54288 0:a7a43371b306 96 *---------------------------------------------------------------------------*
ram54288 0:a7a43371b306 97 *****************************************************************************/
ram54288 0:a7a43371b306 98
ram54288 0:a7a43371b306 99 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 100 * Name: MCR20Drv_Init
ram54288 0:a7a43371b306 101 * Description: -
ram54288 0:a7a43371b306 102 * Parameters: -
ram54288 0:a7a43371b306 103 * Return: -
ram54288 0:a7a43371b306 104 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 105 void MCR20Drv_Init
ram54288 0:a7a43371b306 106 (
ram54288 0:a7a43371b306 107 void
ram54288 0:a7a43371b306 108 )
ram54288 0:a7a43371b306 109 {
ram54288 0:a7a43371b306 110 xcvr_spi_init(gXcvrSpiInstance_c);
ram54288 0:a7a43371b306 111 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:a7a43371b306 112
ram54288 0:a7a43371b306 113 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 114 MCR20Drv_RST_B_Deassert();
ram54288 0:a7a43371b306 115 RF_IRQ_Init();
ram54288 0:a7a43371b306 116 RF_IRQ_Disable();
ram54288 0:a7a43371b306 117 mPhyIrqDisableCnt = 1;
ram54288 0:a7a43371b306 118 }
ram54288 0:a7a43371b306 119
ram54288 0:a7a43371b306 120 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 121 * Name: MCR20Drv_DirectAccessSPIWrite
ram54288 0:a7a43371b306 122 * Description: -
ram54288 0:a7a43371b306 123 * Parameters: -
ram54288 0:a7a43371b306 124 * Return: -
ram54288 0:a7a43371b306 125 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 126 void MCR20Drv_DirectAccessSPIWrite
ram54288 0:a7a43371b306 127 (
ram54288 0:a7a43371b306 128 uint8_t address,
ram54288 0:a7a43371b306 129 uint8_t value
ram54288 0:a7a43371b306 130 )
ram54288 0:a7a43371b306 131 {
ram54288 0:a7a43371b306 132 uint16_t txData;
ram54288 0:a7a43371b306 133
ram54288 0:a7a43371b306 134 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 135
ram54288 0:a7a43371b306 136 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:a7a43371b306 137
ram54288 0:a7a43371b306 138 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 139
ram54288 0:a7a43371b306 140 txData = (address & TransceiverSPI_DirectRegisterAddressMask);
ram54288 0:a7a43371b306 141 txData |= value << 8;
ram54288 0:a7a43371b306 142
ram54288 0:a7a43371b306 143 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t *)&txData, 0, sizeof(txData));
ram54288 0:a7a43371b306 144
ram54288 0:a7a43371b306 145 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 146 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 147 }
ram54288 0:a7a43371b306 148
ram54288 0:a7a43371b306 149 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 150 * Name: MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 151 * Description: -
ram54288 0:a7a43371b306 152 * Parameters: -
ram54288 0:a7a43371b306 153 * Return: -
ram54288 0:a7a43371b306 154 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 155 void MCR20Drv_DirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 156 (
ram54288 0:a7a43371b306 157 uint8_t startAddress,
ram54288 0:a7a43371b306 158 uint8_t * byteArray,
ram54288 0:a7a43371b306 159 uint8_t numOfBytes
ram54288 0:a7a43371b306 160 )
ram54288 0:a7a43371b306 161 {
ram54288 0:a7a43371b306 162 uint8_t txData;
ram54288 0:a7a43371b306 163
ram54288 0:a7a43371b306 164 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:a7a43371b306 165 {
ram54288 0:a7a43371b306 166 return;
ram54288 0:a7a43371b306 167 }
ram54288 0:a7a43371b306 168
ram54288 0:a7a43371b306 169 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 170
ram54288 0:a7a43371b306 171 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:a7a43371b306 172
ram54288 0:a7a43371b306 173 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 174
ram54288 0:a7a43371b306 175 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask);
ram54288 0:a7a43371b306 176
ram54288 0:a7a43371b306 177 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
ram54288 0:a7a43371b306 178 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
ram54288 0:a7a43371b306 179
ram54288 0:a7a43371b306 180 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 181 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 182 }
ram54288 0:a7a43371b306 183
ram54288 0:a7a43371b306 184 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 185 * Name: MCR20Drv_PB_SPIByteWrite
ram54288 0:a7a43371b306 186 * Description: -
ram54288 0:a7a43371b306 187 * Parameters: -
ram54288 0:a7a43371b306 188 * Return: -
ram54288 0:a7a43371b306 189 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 190 void MCR20Drv_PB_SPIByteWrite
ram54288 0:a7a43371b306 191 (
ram54288 0:a7a43371b306 192 uint8_t address,
ram54288 0:a7a43371b306 193 uint8_t value
ram54288 0:a7a43371b306 194 )
ram54288 0:a7a43371b306 195 {
ram54288 0:a7a43371b306 196 uint32_t txData;
ram54288 0:a7a43371b306 197
ram54288 0:a7a43371b306 198 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 199
ram54288 0:a7a43371b306 200 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:a7a43371b306 201
ram54288 0:a7a43371b306 202 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 203
ram54288 0:a7a43371b306 204 txData = TransceiverSPI_WriteSelect |
ram54288 0:a7a43371b306 205 TransceiverSPI_PacketBuffAccessSelect |
ram54288 0:a7a43371b306 206 TransceiverSPI_PacketBuffByteModeSelect;
ram54288 0:a7a43371b306 207 txData |= (address) << 8;
ram54288 0:a7a43371b306 208 txData |= (value) << 16;
ram54288 0:a7a43371b306 209
ram54288 0:a7a43371b306 210 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
ram54288 0:a7a43371b306 211
ram54288 0:a7a43371b306 212 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 213 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 214 }
ram54288 0:a7a43371b306 215
ram54288 0:a7a43371b306 216 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 217 * Name: MCR20Drv_PB_SPIBurstWrite
ram54288 0:a7a43371b306 218 * Description: -
ram54288 0:a7a43371b306 219 * Parameters: -
ram54288 0:a7a43371b306 220 * Return: -
ram54288 0:a7a43371b306 221 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 222 void MCR20Drv_PB_SPIBurstWrite
ram54288 0:a7a43371b306 223 (
ram54288 0:a7a43371b306 224 uint8_t * byteArray,
ram54288 0:a7a43371b306 225 uint8_t numOfBytes
ram54288 0:a7a43371b306 226 )
ram54288 0:a7a43371b306 227 {
ram54288 0:a7a43371b306 228 uint8_t txData;
ram54288 0:a7a43371b306 229
ram54288 0:a7a43371b306 230 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:a7a43371b306 231 {
ram54288 0:a7a43371b306 232 return;
ram54288 0:a7a43371b306 233 }
ram54288 0:a7a43371b306 234
ram54288 0:a7a43371b306 235 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 236
ram54288 0:a7a43371b306 237 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:a7a43371b306 238
ram54288 0:a7a43371b306 239 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 240
ram54288 0:a7a43371b306 241 txData = TransceiverSPI_WriteSelect |
ram54288 0:a7a43371b306 242 TransceiverSPI_PacketBuffAccessSelect |
ram54288 0:a7a43371b306 243 TransceiverSPI_PacketBuffBurstModeSelect;
ram54288 0:a7a43371b306 244
ram54288 0:a7a43371b306 245 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, 1);
ram54288 0:a7a43371b306 246 xcvr_spi_transfer(gXcvrSpiInstance_c, byteArray, 0, numOfBytes);
ram54288 0:a7a43371b306 247
ram54288 0:a7a43371b306 248 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 249 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 250 }
ram54288 0:a7a43371b306 251
ram54288 0:a7a43371b306 252 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 253 * Name: MCR20Drv_DirectAccessSPIRead
ram54288 0:a7a43371b306 254 * Description: -
ram54288 0:a7a43371b306 255 * Parameters: -
ram54288 0:a7a43371b306 256 * Return: -
ram54288 0:a7a43371b306 257 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 258
ram54288 0:a7a43371b306 259 uint8_t MCR20Drv_DirectAccessSPIRead
ram54288 0:a7a43371b306 260 (
ram54288 0:a7a43371b306 261 uint8_t address
ram54288 0:a7a43371b306 262 )
ram54288 0:a7a43371b306 263 {
ram54288 0:a7a43371b306 264 uint8_t txData;
ram54288 0:a7a43371b306 265 uint8_t rxData;
ram54288 0:a7a43371b306 266
ram54288 0:a7a43371b306 267 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 268
ram54288 0:a7a43371b306 269 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:a7a43371b306 270
ram54288 0:a7a43371b306 271 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 272
ram54288 0:a7a43371b306 273 txData = (address & TransceiverSPI_DirectRegisterAddressMask) |
ram54288 0:a7a43371b306 274 TransceiverSPI_ReadSelect;
ram54288 0:a7a43371b306 275
ram54288 0:a7a43371b306 276 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, 0, sizeof(txData));
ram54288 0:a7a43371b306 277 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
ram54288 0:a7a43371b306 278
ram54288 0:a7a43371b306 279 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 280 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 281
ram54288 0:a7a43371b306 282 return rxData;
ram54288 0:a7a43371b306 283
ram54288 0:a7a43371b306 284 }
ram54288 0:a7a43371b306 285
ram54288 0:a7a43371b306 286 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 287 * Name: MCR20Drv_DirectAccessSPIMultyByteRead
ram54288 0:a7a43371b306 288 * Description: -
ram54288 0:a7a43371b306 289 * Parameters: -
ram54288 0:a7a43371b306 290 * Return: -
ram54288 0:a7a43371b306 291 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 292 uint8_t MCR20Drv_DirectAccessSPIMultiByteRead
ram54288 0:a7a43371b306 293 (
ram54288 0:a7a43371b306 294 uint8_t startAddress,
ram54288 0:a7a43371b306 295 uint8_t * byteArray,
ram54288 0:a7a43371b306 296 uint8_t numOfBytes
ram54288 0:a7a43371b306 297 )
ram54288 0:a7a43371b306 298 {
ram54288 0:a7a43371b306 299 uint8_t txData;
ram54288 0:a7a43371b306 300 uint8_t phyIRQSTS1;
ram54288 0:a7a43371b306 301
ram54288 0:a7a43371b306 302 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:a7a43371b306 303 {
ram54288 0:a7a43371b306 304 return 0;
ram54288 0:a7a43371b306 305 }
ram54288 0:a7a43371b306 306
ram54288 0:a7a43371b306 307 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 308
ram54288 0:a7a43371b306 309 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:a7a43371b306 310
ram54288 0:a7a43371b306 311 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 312
ram54288 0:a7a43371b306 313 txData = (startAddress & TransceiverSPI_DirectRegisterAddressMask) |
ram54288 0:a7a43371b306 314 TransceiverSPI_ReadSelect;
ram54288 0:a7a43371b306 315
ram54288 0:a7a43371b306 316 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
ram54288 0:a7a43371b306 317 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
ram54288 0:a7a43371b306 318
ram54288 0:a7a43371b306 319 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 320 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 321
ram54288 0:a7a43371b306 322 return phyIRQSTS1;
ram54288 0:a7a43371b306 323 }
ram54288 0:a7a43371b306 324
ram54288 0:a7a43371b306 325 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 326 * Name: MCR20Drv_PB_SPIBurstRead
ram54288 0:a7a43371b306 327 * Description: -
ram54288 0:a7a43371b306 328 * Parameters: -
ram54288 0:a7a43371b306 329 * Return: -
ram54288 0:a7a43371b306 330 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 331 uint8_t MCR20Drv_PB_SPIBurstRead
ram54288 0:a7a43371b306 332 (
ram54288 0:a7a43371b306 333 uint8_t * byteArray,
ram54288 0:a7a43371b306 334 uint8_t numOfBytes
ram54288 0:a7a43371b306 335 )
ram54288 0:a7a43371b306 336 {
ram54288 0:a7a43371b306 337 uint8_t txData;
ram54288 0:a7a43371b306 338 uint8_t phyIRQSTS1;
ram54288 0:a7a43371b306 339
ram54288 0:a7a43371b306 340 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:a7a43371b306 341 {
ram54288 0:a7a43371b306 342 return 0;
ram54288 0:a7a43371b306 343 }
ram54288 0:a7a43371b306 344
ram54288 0:a7a43371b306 345 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 346
ram54288 0:a7a43371b306 347 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:a7a43371b306 348
ram54288 0:a7a43371b306 349 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 350
ram54288 0:a7a43371b306 351 txData = TransceiverSPI_ReadSelect |
ram54288 0:a7a43371b306 352 TransceiverSPI_PacketBuffAccessSelect |
ram54288 0:a7a43371b306 353 TransceiverSPI_PacketBuffBurstModeSelect;
ram54288 0:a7a43371b306 354
ram54288 0:a7a43371b306 355 xcvr_spi_transfer(gXcvrSpiInstance_c, &txData, &phyIRQSTS1, sizeof(txData));
ram54288 0:a7a43371b306 356 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
ram54288 0:a7a43371b306 357
ram54288 0:a7a43371b306 358 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 359 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 360
ram54288 0:a7a43371b306 361 return phyIRQSTS1;
ram54288 0:a7a43371b306 362 }
ram54288 0:a7a43371b306 363
ram54288 0:a7a43371b306 364 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 365 * Name: MCR20Drv_IndirectAccessSPIWrite
ram54288 0:a7a43371b306 366 * Description: -
ram54288 0:a7a43371b306 367 * Parameters: -
ram54288 0:a7a43371b306 368 * Return: -
ram54288 0:a7a43371b306 369 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 370 void MCR20Drv_IndirectAccessSPIWrite
ram54288 0:a7a43371b306 371 (
ram54288 0:a7a43371b306 372 uint8_t address,
ram54288 0:a7a43371b306 373 uint8_t value
ram54288 0:a7a43371b306 374 )
ram54288 0:a7a43371b306 375 {
ram54288 0:a7a43371b306 376 uint32_t txData;
ram54288 0:a7a43371b306 377
ram54288 0:a7a43371b306 378 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 379
ram54288 0:a7a43371b306 380 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:a7a43371b306 381
ram54288 0:a7a43371b306 382 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 383
ram54288 0:a7a43371b306 384 txData = TransceiverSPI_IARIndexReg;
ram54288 0:a7a43371b306 385 txData |= (address) << 8;
ram54288 0:a7a43371b306 386 txData |= (value) << 16;
ram54288 0:a7a43371b306 387
ram54288 0:a7a43371b306 388 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, 3);
ram54288 0:a7a43371b306 389
ram54288 0:a7a43371b306 390 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 391 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 392 }
ram54288 0:a7a43371b306 393
ram54288 0:a7a43371b306 394 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 395 * Name: MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 396 * Description: -
ram54288 0:a7a43371b306 397 * Parameters: -
ram54288 0:a7a43371b306 398 * Return: -
ram54288 0:a7a43371b306 399 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 400 void MCR20Drv_IndirectAccessSPIMultiByteWrite
ram54288 0:a7a43371b306 401 (
ram54288 0:a7a43371b306 402 uint8_t startAddress,
ram54288 0:a7a43371b306 403 uint8_t * byteArray,
ram54288 0:a7a43371b306 404 uint8_t numOfBytes
ram54288 0:a7a43371b306 405 )
ram54288 0:a7a43371b306 406 {
ram54288 0:a7a43371b306 407 uint16_t txData;
ram54288 0:a7a43371b306 408
ram54288 0:a7a43371b306 409 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:a7a43371b306 410 {
ram54288 0:a7a43371b306 411 return;
ram54288 0:a7a43371b306 412 }
ram54288 0:a7a43371b306 413
ram54288 0:a7a43371b306 414 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 415
ram54288 0:a7a43371b306 416 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 16000000);
ram54288 0:a7a43371b306 417
ram54288 0:a7a43371b306 418 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 419
ram54288 0:a7a43371b306 420 txData = TransceiverSPI_IARIndexReg;
ram54288 0:a7a43371b306 421 txData |= (startAddress) << 8;
ram54288 0:a7a43371b306 422
ram54288 0:a7a43371b306 423 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
ram54288 0:a7a43371b306 424 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)byteArray, 0, numOfBytes);
ram54288 0:a7a43371b306 425
ram54288 0:a7a43371b306 426 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 427 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 428 }
ram54288 0:a7a43371b306 429
ram54288 0:a7a43371b306 430 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 431 * Name: MCR20Drv_IndirectAccessSPIRead
ram54288 0:a7a43371b306 432 * Description: -
ram54288 0:a7a43371b306 433 * Parameters: -
ram54288 0:a7a43371b306 434 * Return: -
ram54288 0:a7a43371b306 435 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 436 uint8_t MCR20Drv_IndirectAccessSPIRead
ram54288 0:a7a43371b306 437 (
ram54288 0:a7a43371b306 438 uint8_t address
ram54288 0:a7a43371b306 439 )
ram54288 0:a7a43371b306 440 {
ram54288 0:a7a43371b306 441 uint16_t txData;
ram54288 0:a7a43371b306 442 uint8_t rxData;
ram54288 0:a7a43371b306 443
ram54288 0:a7a43371b306 444 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 445
ram54288 0:a7a43371b306 446 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:a7a43371b306 447
ram54288 0:a7a43371b306 448 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 449
ram54288 0:a7a43371b306 450 txData = TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect;
ram54288 0:a7a43371b306 451 txData |= (address) << 8;
ram54288 0:a7a43371b306 452
ram54288 0:a7a43371b306 453 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
ram54288 0:a7a43371b306 454 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, &rxData, sizeof(rxData));
ram54288 0:a7a43371b306 455
ram54288 0:a7a43371b306 456 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 457 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 458
ram54288 0:a7a43371b306 459 return rxData;
ram54288 0:a7a43371b306 460 }
ram54288 0:a7a43371b306 461
ram54288 0:a7a43371b306 462 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 463 * Name: MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:a7a43371b306 464 * Description: -
ram54288 0:a7a43371b306 465 * Parameters: -
ram54288 0:a7a43371b306 466 * Return: -
ram54288 0:a7a43371b306 467 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 468 void MCR20Drv_IndirectAccessSPIMultiByteRead
ram54288 0:a7a43371b306 469 (
ram54288 0:a7a43371b306 470 uint8_t startAddress,
ram54288 0:a7a43371b306 471 uint8_t * byteArray,
ram54288 0:a7a43371b306 472 uint8_t numOfBytes
ram54288 0:a7a43371b306 473 )
ram54288 0:a7a43371b306 474 {
ram54288 0:a7a43371b306 475 uint16_t txData;
ram54288 0:a7a43371b306 476
ram54288 0:a7a43371b306 477 if( (numOfBytes == 0) || (byteArray == 0) )
ram54288 0:a7a43371b306 478 {
ram54288 0:a7a43371b306 479 return;
ram54288 0:a7a43371b306 480 }
ram54288 0:a7a43371b306 481
ram54288 0:a7a43371b306 482 ProtectFromMCR20Interrupt();
ram54288 0:a7a43371b306 483
ram54288 0:a7a43371b306 484 xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);
ram54288 0:a7a43371b306 485
ram54288 0:a7a43371b306 486 gXcvrAssertCS_d();
ram54288 0:a7a43371b306 487
ram54288 0:a7a43371b306 488 txData = (TransceiverSPI_IARIndexReg | TransceiverSPI_ReadSelect);
ram54288 0:a7a43371b306 489 txData |= (startAddress) << 8;
ram54288 0:a7a43371b306 490
ram54288 0:a7a43371b306 491 xcvr_spi_transfer(gXcvrSpiInstance_c, (uint8_t*)&txData, 0, sizeof(txData));
ram54288 0:a7a43371b306 492 xcvr_spi_transfer(gXcvrSpiInstance_c, 0, byteArray, numOfBytes);
ram54288 0:a7a43371b306 493
ram54288 0:a7a43371b306 494 gXcvrDeassertCS_d();
ram54288 0:a7a43371b306 495 UnprotectFromMCR20Interrupt();
ram54288 0:a7a43371b306 496 }
ram54288 0:a7a43371b306 497
ram54288 0:a7a43371b306 498 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 499 * Name: MCR20Drv_IsIrqPending
ram54288 0:a7a43371b306 500 * Description: -
ram54288 0:a7a43371b306 501 * Parameters: -
ram54288 0:a7a43371b306 502 * Return: -
ram54288 0:a7a43371b306 503 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 504 uint32_t MCR20Drv_IsIrqPending
ram54288 0:a7a43371b306 505 (
ram54288 0:a7a43371b306 506 void
ram54288 0:a7a43371b306 507 )
ram54288 0:a7a43371b306 508 {
ram54288 0:a7a43371b306 509 return RF_isIRQ_Pending();
ram54288 0:a7a43371b306 510 }
ram54288 0:a7a43371b306 511
ram54288 0:a7a43371b306 512 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 513 * Name: MCR20Drv_IRQ_Disable
ram54288 0:a7a43371b306 514 * Description: -
ram54288 0:a7a43371b306 515 * Parameters: -
ram54288 0:a7a43371b306 516 * Return: -
ram54288 0:a7a43371b306 517 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 518 void MCR20Drv_IRQ_Disable
ram54288 0:a7a43371b306 519 (
ram54288 0:a7a43371b306 520 void
ram54288 0:a7a43371b306 521 )
ram54288 0:a7a43371b306 522 {
ram54288 0:a7a43371b306 523 platform_enter_critical();
ram54288 0:a7a43371b306 524
ram54288 0:a7a43371b306 525 if( mPhyIrqDisableCnt == 0 )
ram54288 0:a7a43371b306 526 {
ram54288 0:a7a43371b306 527 RF_IRQ_Disable();
ram54288 0:a7a43371b306 528 }
ram54288 0:a7a43371b306 529
ram54288 0:a7a43371b306 530 mPhyIrqDisableCnt++;
ram54288 0:a7a43371b306 531
ram54288 0:a7a43371b306 532 platform_exit_critical();
ram54288 0:a7a43371b306 533 }
ram54288 0:a7a43371b306 534
ram54288 0:a7a43371b306 535 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 536 * Name: MCR20Drv_IRQ_Enable
ram54288 0:a7a43371b306 537 * Description: -
ram54288 0:a7a43371b306 538 * Parameters: -
ram54288 0:a7a43371b306 539 * Return: -
ram54288 0:a7a43371b306 540 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 541 void MCR20Drv_IRQ_Enable
ram54288 0:a7a43371b306 542 (
ram54288 0:a7a43371b306 543 void
ram54288 0:a7a43371b306 544 )
ram54288 0:a7a43371b306 545 {
ram54288 0:a7a43371b306 546 platform_enter_critical();
ram54288 0:a7a43371b306 547
ram54288 0:a7a43371b306 548 if( mPhyIrqDisableCnt )
ram54288 0:a7a43371b306 549 {
ram54288 0:a7a43371b306 550 mPhyIrqDisableCnt--;
ram54288 0:a7a43371b306 551
ram54288 0:a7a43371b306 552 if( mPhyIrqDisableCnt == 0 )
ram54288 0:a7a43371b306 553 {
ram54288 0:a7a43371b306 554 RF_IRQ_Enable();
ram54288 0:a7a43371b306 555 }
ram54288 0:a7a43371b306 556 }
ram54288 0:a7a43371b306 557
ram54288 0:a7a43371b306 558 platform_exit_critical();
ram54288 0:a7a43371b306 559 }
ram54288 0:a7a43371b306 560
ram54288 0:a7a43371b306 561 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 562 * Name: MCR20Drv_RST_Assert
ram54288 0:a7a43371b306 563 * Description: -
ram54288 0:a7a43371b306 564 * Parameters: -
ram54288 0:a7a43371b306 565 * Return: -
ram54288 0:a7a43371b306 566 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 567 void MCR20Drv_RST_B_Assert
ram54288 0:a7a43371b306 568 (
ram54288 0:a7a43371b306 569 void
ram54288 0:a7a43371b306 570 )
ram54288 0:a7a43371b306 571 {
ram54288 0:a7a43371b306 572 RF_RST_Set(0);
ram54288 0:a7a43371b306 573 }
ram54288 0:a7a43371b306 574
ram54288 0:a7a43371b306 575 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 576 * Name: MCR20Drv_RST_Deassert
ram54288 0:a7a43371b306 577 * Description: -
ram54288 0:a7a43371b306 578 * Parameters: -
ram54288 0:a7a43371b306 579 * Return: -
ram54288 0:a7a43371b306 580 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 581 void MCR20Drv_RST_B_Deassert
ram54288 0:a7a43371b306 582 (
ram54288 0:a7a43371b306 583 void
ram54288 0:a7a43371b306 584 )
ram54288 0:a7a43371b306 585 {
ram54288 0:a7a43371b306 586 RF_RST_Set(1);
ram54288 0:a7a43371b306 587 }
ram54288 0:a7a43371b306 588
ram54288 0:a7a43371b306 589 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 590 * Name: MCR20Drv_SoftRST_Assert
ram54288 0:a7a43371b306 591 * Description: -
ram54288 0:a7a43371b306 592 * Parameters: -
ram54288 0:a7a43371b306 593 * Return: -
ram54288 0:a7a43371b306 594 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 595 void MCR20Drv_SoftRST_Assert
ram54288 0:a7a43371b306 596 (
ram54288 0:a7a43371b306 597 void
ram54288 0:a7a43371b306 598 )
ram54288 0:a7a43371b306 599 {
ram54288 0:a7a43371b306 600 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
ram54288 0:a7a43371b306 601 }
ram54288 0:a7a43371b306 602
ram54288 0:a7a43371b306 603 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 604 * Name: MCR20Drv_SoftRST_Deassert
ram54288 0:a7a43371b306 605 * Description: -
ram54288 0:a7a43371b306 606 * Parameters: -
ram54288 0:a7a43371b306 607 * Return: -
ram54288 0:a7a43371b306 608 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 609 void MCR20Drv_SoftRST_Deassert
ram54288 0:a7a43371b306 610 (
ram54288 0:a7a43371b306 611 void
ram54288 0:a7a43371b306 612 )
ram54288 0:a7a43371b306 613 {
ram54288 0:a7a43371b306 614 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
ram54288 0:a7a43371b306 615 }
ram54288 0:a7a43371b306 616
ram54288 0:a7a43371b306 617 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 618 * Name: MCR20Drv_Soft_RESET
ram54288 0:a7a43371b306 619 * Description: -
ram54288 0:a7a43371b306 620 * Parameters: -
ram54288 0:a7a43371b306 621 * Return: -
ram54288 0:a7a43371b306 622 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 623 void MCR20Drv_Soft_RESET
ram54288 0:a7a43371b306 624 (
ram54288 0:a7a43371b306 625 void
ram54288 0:a7a43371b306 626 )
ram54288 0:a7a43371b306 627 {
ram54288 0:a7a43371b306 628 //assert SOG_RST
ram54288 0:a7a43371b306 629 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x80));
ram54288 0:a7a43371b306 630
ram54288 0:a7a43371b306 631 //deassert SOG_RST
ram54288 0:a7a43371b306 632 MCR20Drv_IndirectAccessSPIWrite(SOFT_RESET, (0x00));
ram54288 0:a7a43371b306 633 }
ram54288 0:a7a43371b306 634
ram54288 0:a7a43371b306 635 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 636 * Name: MCR20Drv_RESET
ram54288 0:a7a43371b306 637 * Description: -
ram54288 0:a7a43371b306 638 * Parameters: -
ram54288 0:a7a43371b306 639 * Return: -
ram54288 0:a7a43371b306 640 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 641 void MCR20Drv_RESET
ram54288 0:a7a43371b306 642 (
ram54288 0:a7a43371b306 643 void
ram54288 0:a7a43371b306 644 )
ram54288 0:a7a43371b306 645 {
ram54288 0:a7a43371b306 646 volatile uint32_t delay = 1000;
ram54288 0:a7a43371b306 647 //assert RST_B
ram54288 0:a7a43371b306 648 MCR20Drv_RST_B_Assert();
ram54288 0:a7a43371b306 649
ram54288 0:a7a43371b306 650 while(delay--);
ram54288 0:a7a43371b306 651
ram54288 0:a7a43371b306 652 //deassert RST_B
ram54288 0:a7a43371b306 653 MCR20Drv_RST_B_Deassert();
ram54288 0:a7a43371b306 654 }
ram54288 0:a7a43371b306 655
ram54288 0:a7a43371b306 656 /*---------------------------------------------------------------------------
ram54288 0:a7a43371b306 657 * Name: MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:a7a43371b306 658 * Description: -
ram54288 0:a7a43371b306 659 * Parameters: -
ram54288 0:a7a43371b306 660 * Return: -
ram54288 0:a7a43371b306 661 *---------------------------------------------------------------------------*/
ram54288 0:a7a43371b306 662 void MCR20Drv_Set_CLK_OUT_Freq
ram54288 0:a7a43371b306 663 (
ram54288 0:a7a43371b306 664 uint8_t freqDiv
ram54288 0:a7a43371b306 665 )
ram54288 0:a7a43371b306 666 {
ram54288 0:a7a43371b306 667 uint8_t clkOutCtrlReg = (freqDiv & cCLK_OUT_DIV_Mask) | cCLK_OUT_EN | cCLK_OUT_EXTEND;
ram54288 0:a7a43371b306 668
ram54288 0:a7a43371b306 669 if(freqDiv == gCLK_OUT_FREQ_DISABLE)
ram54288 0:a7a43371b306 670 {
ram54288 0:a7a43371b306 671 clkOutCtrlReg = (cCLK_OUT_EXTEND | gCLK_OUT_FREQ_4_MHz); //reset value with clock out disabled
ram54288 0:a7a43371b306 672 }
ram54288 0:a7a43371b306 673
ram54288 0:a7a43371b306 674 MCR20Drv_DirectAccessSPIWrite((uint8_t) CLK_OUT_CTRL, clkOutCtrlReg);
ram54288 0:a7a43371b306 675 }