ABCD - A metronome using the FRDM K64F board

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A metronome using the FRDM K64F board

easy-connect/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp@0:a7a43371b306, 2017-05-14 (annotated)

Committer:: ram54288
Date:: Sun May 14 18:40:18 2017 +0000
Revision:: 0:a7a43371b306

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
ram54288	0:a7a43371b306	1	/*
ram54288	0:a7a43371b306	2	* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
ram54288	0:a7a43371b306	3	* SPDX-License-Identifier: Apache-2.0
ram54288	0:a7a43371b306	4	* Licensed under the Apache License, Version 2.0 (the License); you may
ram54288	0:a7a43371b306	5	* not use this file except in compliance with the License.
ram54288	0:a7a43371b306	6	* You may obtain a copy of the License at
ram54288	0:a7a43371b306	7	*
ram54288	0:a7a43371b306	8	* http://www.apache.org/licenses/LICENSE-2.0
ram54288	0:a7a43371b306	9	*
ram54288	0:a7a43371b306	10	* Unless required by applicable law or agreed to in writing, software
ram54288	0:a7a43371b306	11	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
ram54288	0:a7a43371b306	12	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ram54288	0:a7a43371b306	13	* See the License for the specific language governing permissions and
ram54288	0:a7a43371b306	14	* limitations under the License.
ram54288	0:a7a43371b306	15	*/
ram54288	0:a7a43371b306	16	#include <string.h>
ram54288	0:a7a43371b306	17	#include "platform/arm_hal_interrupt.h"
ram54288	0:a7a43371b306	18	#include "nanostack/platform/arm_hal_phy.h"
ram54288	0:a7a43371b306	19	#include "ns_types.h"
ram54288	0:a7a43371b306	20	#include "NanostackRfPhyAtmel.h"
ram54288	0:a7a43371b306	21	#include "randLIB.h"
ram54288	0:a7a43371b306	22	#include "AT86RFReg.h"
ram54288	0:a7a43371b306	23	#include "nanostack/platform/arm_hal_phy.h"
ram54288	0:a7a43371b306	24	#include "toolchain.h"
ram54288	0:a7a43371b306	25
ram54288	0:a7a43371b306	26	/Worst case sensitivity/
ram54288	0:a7a43371b306	27	#define RF_DEFAULT_SENSITIVITY -88
ram54288	0:a7a43371b306	28	/Run calibration every 5 minutes/
ram54288	0:a7a43371b306	29	#define RF_CALIBRATION_INTERVAL 6000000
ram54288	0:a7a43371b306	30	/Wait ACK for 2.5ms/
ram54288	0:a7a43371b306	31	#define RF_ACK_WAIT_DEFAULT_TIMEOUT 50
ram54288	0:a7a43371b306	32	/Base CCA backoff (50us units) - substitutes for Inter-Frame Spacing/
ram54288	0:a7a43371b306	33	#define RF_CCA_BASE_BACKOFF 13 /* 650us */
ram54288	0:a7a43371b306	34	/CCA random backoff (50us units)/
ram54288	0:a7a43371b306	35	#define RF_CCA_RANDOM_BACKOFF 51 /* 2550us */
ram54288	0:a7a43371b306	36
ram54288	0:a7a43371b306	37	#define RF_MTU 127
ram54288	0:a7a43371b306	38
ram54288	0:a7a43371b306	39	#define RF_PHY_MODE OQPSK_SIN_250
ram54288	0:a7a43371b306	40
ram54288	0:a7a43371b306	41	/Radio RX and TX state definitions/
ram54288	0:a7a43371b306	42	#define RFF_ON 0x01
ram54288	0:a7a43371b306	43	#define RFF_RX 0x02
ram54288	0:a7a43371b306	44	#define RFF_TX 0x04
ram54288	0:a7a43371b306	45	#define RFF_CCA 0x08
ram54288	0:a7a43371b306	46	#define RFF_PROT 0x10
ram54288	0:a7a43371b306	47
ram54288	0:a7a43371b306	48	typedef enum
ram54288	0:a7a43371b306	49	{
ram54288	0:a7a43371b306	50	RF_MODE_NORMAL = 0,
ram54288	0:a7a43371b306	51	RF_MODE_SNIFFER = 1,
ram54288	0:a7a43371b306	52	RF_MODE_ED = 2
ram54288	0:a7a43371b306	53	}rf_mode_t;
ram54288	0:a7a43371b306	54
ram54288	0:a7a43371b306	55	/Atmel RF Part Type/
ram54288	0:a7a43371b306	56	typedef enum
ram54288	0:a7a43371b306	57	{
ram54288	0:a7a43371b306	58	ATMEL_UNKNOW_DEV = 0,
ram54288	0:a7a43371b306	59	ATMEL_AT86RF212,
ram54288	0:a7a43371b306	60	ATMEL_AT86RF231, // No longer supported (doesn't give ED+status on frame read)
ram54288	0:a7a43371b306	61	ATMEL_AT86RF233
ram54288	0:a7a43371b306	62	}rf_trx_part_e;
ram54288	0:a7a43371b306	63
ram54288	0:a7a43371b306	64	/Atmel RF states/
ram54288	0:a7a43371b306	65	typedef enum
ram54288	0:a7a43371b306	66	{
ram54288	0:a7a43371b306	67	NOP = 0x00,
ram54288	0:a7a43371b306	68	BUSY_RX = 0x01,
ram54288	0:a7a43371b306	69	RF_TX_START = 0x02,
ram54288	0:a7a43371b306	70	FORCE_TRX_OFF = 0x03,
ram54288	0:a7a43371b306	71	FORCE_PLL_ON = 0x04,
ram54288	0:a7a43371b306	72	RX_ON = 0x06,
ram54288	0:a7a43371b306	73	TRX_OFF = 0x08,
ram54288	0:a7a43371b306	74	PLL_ON = 0x09,
ram54288	0:a7a43371b306	75	BUSY_RX_AACK = 0x11,
ram54288	0:a7a43371b306	76	SLEEP = 0x0F,
ram54288	0:a7a43371b306	77	RX_AACK_ON = 0x16,
ram54288	0:a7a43371b306	78	TX_ARET_ON = 0x19
ram54288	0:a7a43371b306	79	}rf_trx_states_t;
ram54288	0:a7a43371b306	80
ram54288	0:a7a43371b306	81	static const uint8_t *rf_tx_data; // Points to Nanostack's buffer
ram54288	0:a7a43371b306	82	static uint8_t rf_tx_length;
ram54288	0:a7a43371b306	83	/ACK wait duration changes depending on data rate/
ram54288	0:a7a43371b306	84	static uint16_t rf_ack_wait_duration = RF_ACK_WAIT_DEFAULT_TIMEOUT;
ram54288	0:a7a43371b306	85
ram54288	0:a7a43371b306	86	static int8_t rf_sensitivity = RF_DEFAULT_SENSITIVITY;
ram54288	0:a7a43371b306	87	static rf_mode_t rf_mode = RF_MODE_NORMAL;
ram54288	0:a7a43371b306	88	static uint8_t radio_tx_power = 0x00; // Default to +4dBm
ram54288	0:a7a43371b306	89	static uint8_t rf_phy_channel = 12;
ram54288	0:a7a43371b306	90	static uint8_t rf_tuned = 1;
ram54288	0:a7a43371b306	91	static uint8_t rf_use_antenna_diversity = 0;
ram54288	0:a7a43371b306	92	static int16_t expected_ack_sequence = -1;
ram54288	0:a7a43371b306	93	static uint8_t rf_rx_mode = 0;
ram54288	0:a7a43371b306	94	static uint8_t rf_flags = 0;
ram54288	0:a7a43371b306	95	static int8_t rf_radio_driver_id = -1;
ram54288	0:a7a43371b306	96	static phy_device_driver_s device_driver;
ram54288	0:a7a43371b306	97	static uint8_t mac_tx_handle = 0;
ram54288	0:a7a43371b306	98
ram54288	0:a7a43371b306	99	/* Channel configurations for 2.4 and sub-GHz */
ram54288	0:a7a43371b306	100	static const phy_rf_channel_configuration_s phy_24ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK};
ram54288	0:a7a43371b306	101	static const phy_rf_channel_configuration_s phy_subghz = {868300000U, 2000000U, 250000U, 11U, M_OQPSK};
ram54288	0:a7a43371b306	102
ram54288	0:a7a43371b306	103	static const phy_device_channel_page_s phy_channel_pages[] = {
ram54288	0:a7a43371b306	104	{ CHANNEL_PAGE_0, &phy_24ghz},
ram54288	0:a7a43371b306	105	{ CHANNEL_PAGE_2, &phy_subghz},
ram54288	0:a7a43371b306	106	{ CHANNEL_PAGE_0, NULL}
ram54288	0:a7a43371b306	107	};
ram54288	0:a7a43371b306	108
ram54288	0:a7a43371b306	109	/**
ram54288	0:a7a43371b306	110	* RF output power write
ram54288	0:a7a43371b306	111	*
ram54288	0:a7a43371b306	112	* \brief TX power has to be set before network start.
ram54288	0:a7a43371b306	113	*
ram54288	0:a7a43371b306	114	* \param power
ram54288	0:a7a43371b306	115	* AT86RF233
ram54288	0:a7a43371b306	116	* 0 = 4 dBm
ram54288	0:a7a43371b306	117	* 1 = 3.7 dBm
ram54288	0:a7a43371b306	118	* 2 = 3.4 dBm
ram54288	0:a7a43371b306	119	* 3 = 3 dBm
ram54288	0:a7a43371b306	120	* 4 = 2.5 dBm
ram54288	0:a7a43371b306	121	* 5 = 2 dBm
ram54288	0:a7a43371b306	122	* 6 = 1 dBm
ram54288	0:a7a43371b306	123	* 7 = 0 dBm
ram54288	0:a7a43371b306	124	* 8 = -1 dBm
ram54288	0:a7a43371b306	125	* 9 = -2 dBm
ram54288	0:a7a43371b306	126	* 10 = -3 dBm
ram54288	0:a7a43371b306	127	* 11 = -4 dBm
ram54288	0:a7a43371b306	128	* 12 = -6 dBm
ram54288	0:a7a43371b306	129	* 13 = -8 dBm
ram54288	0:a7a43371b306	130	* 14 = -12 dBm
ram54288	0:a7a43371b306	131	* 15 = -17 dBm
ram54288	0:a7a43371b306	132	*
ram54288	0:a7a43371b306	133	* AT86RF212B
ram54288	0:a7a43371b306	134	* See datasheet for TX power settings
ram54288	0:a7a43371b306	135	*
ram54288	0:a7a43371b306	136	* \return 0, Supported Value
ram54288	0:a7a43371b306	137	* \return -1, Not Supported Value
ram54288	0:a7a43371b306	138	*/
ram54288	0:a7a43371b306	139	static int8_t rf_tx_power_set(uint8_t power);
ram54288	0:a7a43371b306	140	static rf_trx_part_e rf_radio_type_read(void);
ram54288	0:a7a43371b306	141	static void rf_ack_wait_timer_start(uint16_t slots);
ram54288	0:a7a43371b306	142	static void rf_ack_wait_timer_stop(void);
ram54288	0:a7a43371b306	143	static void rf_handle_cca_ed_done(void);
ram54288	0:a7a43371b306	144	static void rf_handle_tx_end(void);
ram54288	0:a7a43371b306	145	static void rf_handle_rx_end(void);
ram54288	0:a7a43371b306	146	static void rf_on(void);
ram54288	0:a7a43371b306	147	static void rf_receive(void);
ram54288	0:a7a43371b306	148	static void rf_poll_trx_state_change(rf_trx_states_t trx_state);
ram54288	0:a7a43371b306	149	static void rf_init(void);
ram54288	0:a7a43371b306	150	static int8_t rf_device_register(const uint8_t *mac_addr);
ram54288	0:a7a43371b306	151	static void rf_device_unregister(void);
ram54288	0:a7a43371b306	152	static void rf_enable_static_frame_buffer_protection(void);
ram54288	0:a7a43371b306	153	static void rf_disable_static_frame_buffer_protection(void);
ram54288	0:a7a43371b306	154	static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol );
ram54288	0:a7a43371b306	155	static void rf_cca_abort(void);
ram54288	0:a7a43371b306	156	static void rf_calibration_cb(void);
ram54288	0:a7a43371b306	157	static void rf_init_phy_mode(void);
ram54288	0:a7a43371b306	158	static void rf_ack_wait_timer_interrupt(void);
ram54288	0:a7a43371b306	159	static void rf_calibration_timer_interrupt(void);
ram54288	0:a7a43371b306	160	static void rf_calibration_timer_start(uint32_t slots);
ram54288	0:a7a43371b306	161	static void rf_cca_timer_interrupt(void);
ram54288	0:a7a43371b306	162	static void rf_cca_timer_start(uint32_t slots);
ram54288	0:a7a43371b306	163	static uint8_t rf_scale_lqi(int8_t rssi);
ram54288	0:a7a43371b306	164
ram54288	0:a7a43371b306	165	static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel);
ram54288	0:a7a43371b306	166	static int8_t rf_extension(phy_extension_type_e extension_type,uint8_t *data_ptr);
ram54288	0:a7a43371b306	167	static int8_t rf_address_write(phy_address_type_e address_type,uint8_t *address_ptr);
ram54288	0:a7a43371b306	168
ram54288	0:a7a43371b306	169	static void rf_if_cca_timer_start(uint32_t slots);
ram54288	0:a7a43371b306	170	static void rf_if_enable_promiscuous_mode(void);
ram54288	0:a7a43371b306	171	static void rf_if_lock(void);
ram54288	0:a7a43371b306	172	static void rf_if_unlock(void);
ram54288	0:a7a43371b306	173	static uint8_t rf_if_read_rnd(void);
ram54288	0:a7a43371b306	174	static void rf_if_calibration_timer_start(uint32_t slots);
ram54288	0:a7a43371b306	175	static void rf_if_interrupt_handler(void);
ram54288	0:a7a43371b306	176	static void rf_if_ack_wait_timer_start(uint16_t slots);
ram54288	0:a7a43371b306	177	static void rf_if_ack_wait_timer_stop(void);
ram54288	0:a7a43371b306	178	static void rf_if_ack_pending_ctrl(uint8_t state);
ram54288	0:a7a43371b306	179	static void rf_if_calibration(void);
ram54288	0:a7a43371b306	180	static uint8_t rf_if_read_register(uint8_t addr);
ram54288	0:a7a43371b306	181	static void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask);
ram54288	0:a7a43371b306	182	static void rf_if_clear_bit(uint8_t addr, uint8_t bit);
ram54288	0:a7a43371b306	183	static void rf_if_write_register(uint8_t addr, uint8_t data);
ram54288	0:a7a43371b306	184	static void rf_if_reset_radio(void);
ram54288	0:a7a43371b306	185	static void rf_if_enable_ant_div(void);
ram54288	0:a7a43371b306	186	static void rf_if_disable_ant_div(void);
ram54288	0:a7a43371b306	187	static void rf_if_enable_slptr(void);
ram54288	0:a7a43371b306	188	static void rf_if_disable_slptr(void);
ram54288	0:a7a43371b306	189	static void rf_if_write_antenna_diversity_settings(void);
ram54288	0:a7a43371b306	190	static void rf_if_write_set_tx_power_register(uint8_t value);
ram54288	0:a7a43371b306	191	static void rf_if_write_rf_settings(void);
ram54288	0:a7a43371b306	192	static uint8_t rf_if_check_cca(void);
ram54288	0:a7a43371b306	193	static uint8_t rf_if_read_trx_state(void);
ram54288	0:a7a43371b306	194	static uint16_t rf_if_read_packet(uint8_t data[RF_MTU], uint8_t lqi_out, uint8_t ed_out, bool *crc_good);
ram54288	0:a7a43371b306	195	static void rf_if_write_short_addr_registers(uint8_t *short_address);
ram54288	0:a7a43371b306	196	static uint8_t rf_if_last_acked_pending(void);
ram54288	0:a7a43371b306	197	static void rf_if_write_pan_id_registers(uint8_t *pan_id);
ram54288	0:a7a43371b306	198	static void rf_if_write_ieee_addr_registers(uint8_t *address);
ram54288	0:a7a43371b306	199	static void rf_if_write_frame_buffer(const uint8_t *ptr, uint8_t length);
ram54288	0:a7a43371b306	200	static void rf_if_change_trx_state(rf_trx_states_t trx_state);
ram54288	0:a7a43371b306	201	static void rf_if_enable_tx_end_interrupt(void);
ram54288	0:a7a43371b306	202	static void rf_if_enable_rx_end_interrupt(void);
ram54288	0:a7a43371b306	203	static void rf_if_enable_cca_ed_done_interrupt(void);
ram54288	0:a7a43371b306	204	static void rf_if_start_cca_process(void);
ram54288	0:a7a43371b306	205	static int8_t rf_if_scale_rssi(uint8_t ed_level);
ram54288	0:a7a43371b306	206	static void rf_if_set_channel_register(uint8_t channel);
ram54288	0:a7a43371b306	207	static void rf_if_enable_promiscuous_mode(void);
ram54288	0:a7a43371b306	208	static void rf_if_disable_promiscuous_mode(void);
ram54288	0:a7a43371b306	209	static uint8_t rf_if_read_part_num(void);
ram54288	0:a7a43371b306	210	static void rf_if_enable_irq(void);
ram54288	0:a7a43371b306	211	static void rf_if_disable_irq(void);
ram54288	0:a7a43371b306	212
ram54288	0:a7a43371b306	213	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	214	#include "mbed.h"
ram54288	0:a7a43371b306	215	#include "rtos.h"
ram54288	0:a7a43371b306	216
ram54288	0:a7a43371b306	217	static void rf_if_irq_task_process_irq();
ram54288	0:a7a43371b306	218
ram54288	0:a7a43371b306	219	#define SIG_RADIO 1
ram54288	0:a7a43371b306	220	#define SIG_TIMER_ACK 2
ram54288	0:a7a43371b306	221	#define SIG_TIMER_CAL 4
ram54288	0:a7a43371b306	222	#define SIG_TIMER_CCA 8
ram54288	0:a7a43371b306	223
ram54288	0:a7a43371b306	224	#define SIG_TIMERS (SIG_TIMER_ACK\|SIG_TIMER_CAL\|SIG_TIMER_CCA)
ram54288	0:a7a43371b306	225	#define SIG_ALL (SIG_RADIO\|SIG_TIMERS)
ram54288	0:a7a43371b306	226	#endif
ram54288	0:a7a43371b306	227
ram54288	0:a7a43371b306	228	// HW pins to RF chip
ram54288	0:a7a43371b306	229	#define SPI_SPEED 7500000
ram54288	0:a7a43371b306	230
ram54288	0:a7a43371b306	231	class UnlockedSPI : public SPI {
ram54288	0:a7a43371b306	232	public:
ram54288	0:a7a43371b306	233	UnlockedSPI(PinName mosi, PinName miso, PinName sclk) :
ram54288	0:a7a43371b306	234	SPI(mosi, miso, sclk) { }
ram54288	0:a7a43371b306	235	virtual void lock() { }
ram54288	0:a7a43371b306	236	virtual void unlock() { }
ram54288	0:a7a43371b306	237	};
ram54288	0:a7a43371b306	238
ram54288	0:a7a43371b306	239	class RFBits {
ram54288	0:a7a43371b306	240	public:
ram54288	0:a7a43371b306	241	RFBits(PinName spi_mosi, PinName spi_miso,
ram54288	0:a7a43371b306	242	PinName spi_sclk, PinName spi_cs,
ram54288	0:a7a43371b306	243	PinName spi_rst, PinName spi_slp, PinName spi_irq);
ram54288	0:a7a43371b306	244	UnlockedSPI spi;
ram54288	0:a7a43371b306	245	DigitalOut CS;
ram54288	0:a7a43371b306	246	DigitalOut RST;
ram54288	0:a7a43371b306	247	DigitalOut SLP_TR;
ram54288	0:a7a43371b306	248	InterruptIn IRQ;
ram54288	0:a7a43371b306	249	Timeout ack_timer;
ram54288	0:a7a43371b306	250	Timeout cal_timer;
ram54288	0:a7a43371b306	251	Timeout cca_timer;
ram54288	0:a7a43371b306	252	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	253	Thread irq_thread;
ram54288	0:a7a43371b306	254	Mutex mutex;
ram54288	0:a7a43371b306	255	void rf_if_irq_task();
ram54288	0:a7a43371b306	256	#endif
ram54288	0:a7a43371b306	257	};
ram54288	0:a7a43371b306	258
ram54288	0:a7a43371b306	259	RFBits::RFBits(PinName spi_mosi, PinName spi_miso,
ram54288	0:a7a43371b306	260	PinName spi_sclk, PinName spi_cs,
ram54288	0:a7a43371b306	261	PinName spi_rst, PinName spi_slp, PinName spi_irq)
ram54288	0:a7a43371b306	262	: spi(spi_mosi, spi_miso, spi_sclk),
ram54288	0:a7a43371b306	263	CS(spi_cs),
ram54288	0:a7a43371b306	264	RST(spi_rst),
ram54288	0:a7a43371b306	265	SLP_TR(spi_slp),
ram54288	0:a7a43371b306	266	IRQ(spi_irq)
ram54288	0:a7a43371b306	267	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	268	,irq_thread(osPriorityRealtime, 1024)
ram54288	0:a7a43371b306	269	#endif
ram54288	0:a7a43371b306	270	{
ram54288	0:a7a43371b306	271	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	272	irq_thread.start(mbed::callback(this, &RFBits::rf_if_irq_task));
ram54288	0:a7a43371b306	273	#endif
ram54288	0:a7a43371b306	274	}
ram54288	0:a7a43371b306	275
ram54288	0:a7a43371b306	276	static RFBits *rf;
ram54288	0:a7a43371b306	277	static uint8_t rf_part_num = 0;
ram54288	0:a7a43371b306	278	/TODO: RSSI Base value setting/
ram54288	0:a7a43371b306	279	static int8_t rf_rssi_base_val = -91;
ram54288	0:a7a43371b306	280
ram54288	0:a7a43371b306	281	static uint8_t rf_if_spi_exchange(uint8_t out);
ram54288	0:a7a43371b306	282
ram54288	0:a7a43371b306	283	static void rf_if_lock(void)
ram54288	0:a7a43371b306	284	{
ram54288	0:a7a43371b306	285	platform_enter_critical();
ram54288	0:a7a43371b306	286	}
ram54288	0:a7a43371b306	287
ram54288	0:a7a43371b306	288	static void rf_if_unlock(void)
ram54288	0:a7a43371b306	289	{
ram54288	0:a7a43371b306	290	platform_exit_critical();
ram54288	0:a7a43371b306	291	}
ram54288	0:a7a43371b306	292
ram54288	0:a7a43371b306	293	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	294	static void rf_if_cca_timer_signal(void)
ram54288	0:a7a43371b306	295	{
ram54288	0:a7a43371b306	296	rf->irq_thread.signal_set(SIG_TIMER_CCA);
ram54288	0:a7a43371b306	297	}
ram54288	0:a7a43371b306	298
ram54288	0:a7a43371b306	299	static void rf_if_cal_timer_signal(void)
ram54288	0:a7a43371b306	300	{
ram54288	0:a7a43371b306	301	rf->irq_thread.signal_set(SIG_TIMER_CAL);
ram54288	0:a7a43371b306	302	}
ram54288	0:a7a43371b306	303
ram54288	0:a7a43371b306	304	static void rf_if_ack_timer_signal(void)
ram54288	0:a7a43371b306	305	{
ram54288	0:a7a43371b306	306	rf->irq_thread.signal_set(SIG_TIMER_ACK);
ram54288	0:a7a43371b306	307	}
ram54288	0:a7a43371b306	308	#endif
ram54288	0:a7a43371b306	309
ram54288	0:a7a43371b306	310
ram54288	0:a7a43371b306	311	/* Delay functions for RF Chip SPI access */
ram54288	0:a7a43371b306	312	#ifdef __CC_ARM
ram54288	0:a7a43371b306	313	__asm static void delay_loop(uint32_t count)
ram54288	0:a7a43371b306	314	{
ram54288	0:a7a43371b306	315	1
ram54288	0:a7a43371b306	316	SUBS a1, a1, #1
ram54288	0:a7a43371b306	317	BCS %BT1
ram54288	0:a7a43371b306	318	BX lr
ram54288	0:a7a43371b306	319	}
ram54288	0:a7a43371b306	320	#elif defined (__ICCARM__)
ram54288	0:a7a43371b306	321	static void delay_loop(uint32_t count)
ram54288	0:a7a43371b306	322	{
ram54288	0:a7a43371b306	323	__asm volatile(
ram54288	0:a7a43371b306	324	"loop: \n"
ram54288	0:a7a43371b306	325	" SUBS %0, %0, #1 \n"
ram54288	0:a7a43371b306	326	" BCS.n loop\n"
ram54288	0:a7a43371b306	327	: "+r" (count)
ram54288	0:a7a43371b306	328	:
ram54288	0:a7a43371b306	329	: "cc"
ram54288	0:a7a43371b306	330	);
ram54288	0:a7a43371b306	331	}
ram54288	0:a7a43371b306	332	#else // GCC
ram54288	0:a7a43371b306	333	static void delay_loop(uint32_t count)
ram54288	0:a7a43371b306	334	{
ram54288	0:a7a43371b306	335	__asm__ volatile (
ram54288	0:a7a43371b306	336	"%=:\n\t"
ram54288	0:a7a43371b306	337	#if defined(__thumb__) && !defined(__thumb2__)
ram54288	0:a7a43371b306	338	"SUB %0, #1\n\t"
ram54288	0:a7a43371b306	339	#else
ram54288	0:a7a43371b306	340	"SUBS %0, %0, #1\n\t"
ram54288	0:a7a43371b306	341	#endif
ram54288	0:a7a43371b306	342	"BCS %=b\n\t"
ram54288	0:a7a43371b306	343	: "+l" (count)
ram54288	0:a7a43371b306	344	:
ram54288	0:a7a43371b306	345	: "cc"
ram54288	0:a7a43371b306	346	);
ram54288	0:a7a43371b306	347	}
ram54288	0:a7a43371b306	348	#endif
ram54288	0:a7a43371b306	349
ram54288	0:a7a43371b306	350	static void delay_ns(uint32_t ns)
ram54288	0:a7a43371b306	351	{
ram54288	0:a7a43371b306	352	uint32_t cycles_per_us = SystemCoreClock / 1000000;
ram54288	0:a7a43371b306	353	// Cortex-M0 takes 4 cycles per loop (SUB=1, BCS=3)
ram54288	0:a7a43371b306	354	// Cortex-M3 and M4 takes 3 cycles per loop (SUB=1, BCS=2)
ram54288	0:a7a43371b306	355	// Cortex-M7 - who knows?
ram54288	0:a7a43371b306	356	// Cortex M3-M7 have "CYCCNT" - would be better than a software loop, but M0 doesn't
ram54288	0:a7a43371b306	357	// Assume 3 cycles per loop for now - will be 33% slow on M0. No biggie,
ram54288	0:a7a43371b306	358	// as original version of code was 300% slow on M4.
ram54288	0:a7a43371b306	359	// [Note that this very calculation, plus call overhead, will take multiple
ram54288	0:a7a43371b306	360	// cycles. Could well be 100ns on its own... So round down here, startup is
ram54288	0:a7a43371b306	361	// worth at least one loop iteration.]
ram54288	0:a7a43371b306	362	uint32_t count = (cycles_per_us * ns) / 3000;
ram54288	0:a7a43371b306	363
ram54288	0:a7a43371b306	364	delay_loop(count);
ram54288	0:a7a43371b306	365	}
ram54288	0:a7a43371b306	366
ram54288	0:a7a43371b306	367	// t1 = 180ns, SEL falling edge to MISO active [SPI setup assumed slow enough to not need manual delay]
ram54288	0:a7a43371b306	368	#define CS_SELECT() {rf->CS = 0; /* delay_ns(180); */}
ram54288	0:a7a43371b306	369	// t9 = 250ns, last clock to SEL rising edge, t8 = 250ns, SPI idle time between consecutive access
ram54288	0:a7a43371b306	370	#define CS_RELEASE() {delay_ns(250); rf->CS = 1; delay_ns(250);}
ram54288	0:a7a43371b306	371
ram54288	0:a7a43371b306	372	/*
ram54288	0:a7a43371b306	373	* \brief Function sets the TX power variable.
ram54288	0:a7a43371b306	374	*
ram54288	0:a7a43371b306	375	* \param power TX power setting
ram54288	0:a7a43371b306	376	*
ram54288	0:a7a43371b306	377	* \return 0 Success
ram54288	0:a7a43371b306	378	* \return -1 Fail
ram54288	0:a7a43371b306	379	*/
ram54288	0:a7a43371b306	380	MBED_UNUSED static int8_t rf_tx_power_set(uint8_t power)
ram54288	0:a7a43371b306	381	{
ram54288	0:a7a43371b306	382	int8_t ret_val = -1;
ram54288	0:a7a43371b306	383
ram54288	0:a7a43371b306	384	radio_tx_power = power;
ram54288	0:a7a43371b306	385	rf_if_lock();
ram54288	0:a7a43371b306	386	rf_if_write_set_tx_power_register(radio_tx_power);
ram54288	0:a7a43371b306	387	rf_if_unlock();
ram54288	0:a7a43371b306	388	ret_val = 0;
ram54288	0:a7a43371b306	389
ram54288	0:a7a43371b306	390	return ret_val;
ram54288	0:a7a43371b306	391	}
ram54288	0:a7a43371b306	392
ram54288	0:a7a43371b306	393	/*
ram54288	0:a7a43371b306	394	* \brief Read connected radio part.
ram54288	0:a7a43371b306	395	*
ram54288	0:a7a43371b306	396	* This function only return valid information when rf_init() is called
ram54288	0:a7a43371b306	397	*
ram54288	0:a7a43371b306	398	* \return
ram54288	0:a7a43371b306	399	*/
ram54288	0:a7a43371b306	400	static rf_trx_part_e rf_radio_type_read(void)
ram54288	0:a7a43371b306	401	{
ram54288	0:a7a43371b306	402	rf_trx_part_e ret_val = ATMEL_UNKNOW_DEV;
ram54288	0:a7a43371b306	403
ram54288	0:a7a43371b306	404	switch (rf_part_num)
ram54288	0:a7a43371b306	405	{
ram54288	0:a7a43371b306	406	case PART_AT86RF212:
ram54288	0:a7a43371b306	407	ret_val = ATMEL_AT86RF212;
ram54288	0:a7a43371b306	408	break;
ram54288	0:a7a43371b306	409	case PART_AT86RF233:
ram54288	0:a7a43371b306	410	ret_val = ATMEL_AT86RF233;
ram54288	0:a7a43371b306	411	break;
ram54288	0:a7a43371b306	412	default:
ram54288	0:a7a43371b306	413	break;
ram54288	0:a7a43371b306	414	}
ram54288	0:a7a43371b306	415
ram54288	0:a7a43371b306	416	return ret_val;
ram54288	0:a7a43371b306	417	}
ram54288	0:a7a43371b306	418
ram54288	0:a7a43371b306	419
ram54288	0:a7a43371b306	420	/*
ram54288	0:a7a43371b306	421	* \brief Function starts the ACK wait timeout.
ram54288	0:a7a43371b306	422	*
ram54288	0:a7a43371b306	423	* \param slots Given slots, resolution 50us
ram54288	0:a7a43371b306	424	*
ram54288	0:a7a43371b306	425	* \return none
ram54288	0:a7a43371b306	426	*/
ram54288	0:a7a43371b306	427	static void rf_if_ack_wait_timer_start(uint16_t slots)
ram54288	0:a7a43371b306	428	{
ram54288	0:a7a43371b306	429	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	430	rf->ack_timer.attach_us(rf_if_ack_timer_signal, slots*50);
ram54288	0:a7a43371b306	431	#else
ram54288	0:a7a43371b306	432	rf->ack_timer.attach_us(rf_ack_wait_timer_interrupt, slots*50);
ram54288	0:a7a43371b306	433	#endif
ram54288	0:a7a43371b306	434	}
ram54288	0:a7a43371b306	435
ram54288	0:a7a43371b306	436	/*
ram54288	0:a7a43371b306	437	* \brief Function starts the calibration interval.
ram54288	0:a7a43371b306	438	*
ram54288	0:a7a43371b306	439	* \param slots Given slots, resolution 50us
ram54288	0:a7a43371b306	440	*
ram54288	0:a7a43371b306	441	* \return none
ram54288	0:a7a43371b306	442	*/
ram54288	0:a7a43371b306	443	static void rf_if_calibration_timer_start(uint32_t slots)
ram54288	0:a7a43371b306	444	{
ram54288	0:a7a43371b306	445	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	446	rf->cal_timer.attach_us(rf_if_cal_timer_signal, slots*50);
ram54288	0:a7a43371b306	447	#else
ram54288	0:a7a43371b306	448	rf->cal_timer.attach_us(rf_calibration_timer_interrupt, slots*50);
ram54288	0:a7a43371b306	449	#endif
ram54288	0:a7a43371b306	450	}
ram54288	0:a7a43371b306	451
ram54288	0:a7a43371b306	452	/*
ram54288	0:a7a43371b306	453	* \brief Function starts the CCA interval.
ram54288	0:a7a43371b306	454	*
ram54288	0:a7a43371b306	455	* \param slots Given slots, resolution 50us
ram54288	0:a7a43371b306	456	*
ram54288	0:a7a43371b306	457	* \return none
ram54288	0:a7a43371b306	458	*/
ram54288	0:a7a43371b306	459	static void rf_if_cca_timer_start(uint32_t slots)
ram54288	0:a7a43371b306	460	{
ram54288	0:a7a43371b306	461	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	462	rf->cca_timer.attach_us(rf_if_cca_timer_signal, slots*50);
ram54288	0:a7a43371b306	463	#else
ram54288	0:a7a43371b306	464	rf->cca_timer.attach_us(rf_cca_timer_interrupt, slots*50);
ram54288	0:a7a43371b306	465	#endif
ram54288	0:a7a43371b306	466	}
ram54288	0:a7a43371b306	467
ram54288	0:a7a43371b306	468	/*
ram54288	0:a7a43371b306	469	* \brief Function stops the CCA interval.
ram54288	0:a7a43371b306	470	*
ram54288	0:a7a43371b306	471	* \return none
ram54288	0:a7a43371b306	472	*/
ram54288	0:a7a43371b306	473	static void rf_if_cca_timer_stop(void)
ram54288	0:a7a43371b306	474	{
ram54288	0:a7a43371b306	475	rf->cca_timer.detach();
ram54288	0:a7a43371b306	476	}
ram54288	0:a7a43371b306	477
ram54288	0:a7a43371b306	478	/*
ram54288	0:a7a43371b306	479	* \brief Function stops the ACK wait timeout.
ram54288	0:a7a43371b306	480	*
ram54288	0:a7a43371b306	481	* \param none
ram54288	0:a7a43371b306	482	*
ram54288	0:a7a43371b306	483	* \return none
ram54288	0:a7a43371b306	484	*/
ram54288	0:a7a43371b306	485	static void rf_if_ack_wait_timer_stop(void)
ram54288	0:a7a43371b306	486	{
ram54288	0:a7a43371b306	487	rf->ack_timer.detach();
ram54288	0:a7a43371b306	488	}
ram54288	0:a7a43371b306	489
ram54288	0:a7a43371b306	490	/*
ram54288	0:a7a43371b306	491	* \brief Function sets bit(s) in given RF register.
ram54288	0:a7a43371b306	492	*
ram54288	0:a7a43371b306	493	* \param addr Address of the register to set
ram54288	0:a7a43371b306	494	* \param bit Bit(s) to set
ram54288	0:a7a43371b306	495	* \param bit_mask Masks the field inside the register
ram54288	0:a7a43371b306	496	*
ram54288	0:a7a43371b306	497	* \return none
ram54288	0:a7a43371b306	498	*/
ram54288	0:a7a43371b306	499	static void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask)
ram54288	0:a7a43371b306	500	{
ram54288	0:a7a43371b306	501	uint8_t reg = rf_if_read_register(addr);
ram54288	0:a7a43371b306	502	reg &= ~bit_mask;
ram54288	0:a7a43371b306	503	reg \|= bit;
ram54288	0:a7a43371b306	504	rf_if_write_register(addr, reg);
ram54288	0:a7a43371b306	505	}
ram54288	0:a7a43371b306	506
ram54288	0:a7a43371b306	507	/*
ram54288	0:a7a43371b306	508	* \brief Function clears bit(s) in given RF register.
ram54288	0:a7a43371b306	509	*
ram54288	0:a7a43371b306	510	* \param addr Address of the register to clear
ram54288	0:a7a43371b306	511	* \param bit Bit(s) to clear
ram54288	0:a7a43371b306	512	*
ram54288	0:a7a43371b306	513	* \return none
ram54288	0:a7a43371b306	514	*/
ram54288	0:a7a43371b306	515	static void rf_if_clear_bit(uint8_t addr, uint8_t bit)
ram54288	0:a7a43371b306	516	{
ram54288	0:a7a43371b306	517	rf_if_set_bit(addr, 0, bit);
ram54288	0:a7a43371b306	518	}
ram54288	0:a7a43371b306	519
ram54288	0:a7a43371b306	520	/*
ram54288	0:a7a43371b306	521	* \brief Function writes register in RF.
ram54288	0:a7a43371b306	522	*
ram54288	0:a7a43371b306	523	* \param addr Address on the RF
ram54288	0:a7a43371b306	524	* \param data Written data
ram54288	0:a7a43371b306	525	*
ram54288	0:a7a43371b306	526	* \return none
ram54288	0:a7a43371b306	527	*/
ram54288	0:a7a43371b306	528	static void rf_if_write_register(uint8_t addr, uint8_t data)
ram54288	0:a7a43371b306	529	{
ram54288	0:a7a43371b306	530	uint8_t cmd = 0xC0;
ram54288	0:a7a43371b306	531	CS_SELECT();
ram54288	0:a7a43371b306	532	rf_if_spi_exchange(cmd \| addr);
ram54288	0:a7a43371b306	533	rf_if_spi_exchange(data);
ram54288	0:a7a43371b306	534	CS_RELEASE();
ram54288	0:a7a43371b306	535	}
ram54288	0:a7a43371b306	536
ram54288	0:a7a43371b306	537	/*
ram54288	0:a7a43371b306	538	* \brief Function reads RF register.
ram54288	0:a7a43371b306	539	*
ram54288	0:a7a43371b306	540	* \param addr Address on the RF
ram54288	0:a7a43371b306	541	*
ram54288	0:a7a43371b306	542	* \return Read data
ram54288	0:a7a43371b306	543	*/
ram54288	0:a7a43371b306	544	static uint8_t rf_if_read_register(uint8_t addr)
ram54288	0:a7a43371b306	545	{
ram54288	0:a7a43371b306	546	uint8_t cmd = 0x80;
ram54288	0:a7a43371b306	547	uint8_t data;
ram54288	0:a7a43371b306	548	CS_SELECT();
ram54288	0:a7a43371b306	549	rf_if_spi_exchange(cmd \| addr);
ram54288	0:a7a43371b306	550	data = rf_if_spi_exchange(0);
ram54288	0:a7a43371b306	551	CS_RELEASE();
ram54288	0:a7a43371b306	552	return data;
ram54288	0:a7a43371b306	553	}
ram54288	0:a7a43371b306	554
ram54288	0:a7a43371b306	555	/*
ram54288	0:a7a43371b306	556	* \brief Function resets the RF.
ram54288	0:a7a43371b306	557	*
ram54288	0:a7a43371b306	558	* \param none
ram54288	0:a7a43371b306	559	*
ram54288	0:a7a43371b306	560	* \return none
ram54288	0:a7a43371b306	561	*/
ram54288	0:a7a43371b306	562	static void rf_if_reset_radio(void)
ram54288	0:a7a43371b306	563	{
ram54288	0:a7a43371b306	564	rf->spi.frequency(SPI_SPEED);
ram54288	0:a7a43371b306	565	rf->IRQ.rise(0);
ram54288	0:a7a43371b306	566	rf->RST = 1;
ram54288	0:a7a43371b306	567	wait_ms(1);
ram54288	0:a7a43371b306	568	rf->RST = 0;
ram54288	0:a7a43371b306	569	wait_ms(10);
ram54288	0:a7a43371b306	570	CS_RELEASE();
ram54288	0:a7a43371b306	571	rf->SLP_TR = 0;
ram54288	0:a7a43371b306	572	wait_ms(10);
ram54288	0:a7a43371b306	573	rf->RST = 1;
ram54288	0:a7a43371b306	574	wait_ms(10);
ram54288	0:a7a43371b306	575
ram54288	0:a7a43371b306	576	rf->IRQ.rise(&rf_if_interrupt_handler);
ram54288	0:a7a43371b306	577	}
ram54288	0:a7a43371b306	578
ram54288	0:a7a43371b306	579	/*
ram54288	0:a7a43371b306	580	* \brief Function enables the promiscuous mode.
ram54288	0:a7a43371b306	581	*
ram54288	0:a7a43371b306	582	* \param none
ram54288	0:a7a43371b306	583	*
ram54288	0:a7a43371b306	584	* \return none
ram54288	0:a7a43371b306	585	*/
ram54288	0:a7a43371b306	586	static void rf_if_enable_promiscuous_mode(void)
ram54288	0:a7a43371b306	587	{
ram54288	0:a7a43371b306	588	/Set AACK_PROM_MODE to enable the promiscuous mode/
ram54288	0:a7a43371b306	589	rf_if_set_bit(XAH_CTRL_1, AACK_PROM_MODE, AACK_PROM_MODE);
ram54288	0:a7a43371b306	590	}
ram54288	0:a7a43371b306	591
ram54288	0:a7a43371b306	592	/*
ram54288	0:a7a43371b306	593	* \brief Function enables the promiscuous mode.
ram54288	0:a7a43371b306	594	*
ram54288	0:a7a43371b306	595	* \param none
ram54288	0:a7a43371b306	596	*
ram54288	0:a7a43371b306	597	* \return none
ram54288	0:a7a43371b306	598	*/
ram54288	0:a7a43371b306	599	static void rf_if_disable_promiscuous_mode(void)
ram54288	0:a7a43371b306	600	{
ram54288	0:a7a43371b306	601	/Set AACK_PROM_MODE to enable the promiscuous mode/
ram54288	0:a7a43371b306	602	rf_if_clear_bit(XAH_CTRL_1, AACK_PROM_MODE);
ram54288	0:a7a43371b306	603	}
ram54288	0:a7a43371b306	604
ram54288	0:a7a43371b306	605	/*
ram54288	0:a7a43371b306	606	* \brief Function enables the Antenna diversity usage.
ram54288	0:a7a43371b306	607	*
ram54288	0:a7a43371b306	608	* \param none
ram54288	0:a7a43371b306	609	*
ram54288	0:a7a43371b306	610	* \return none
ram54288	0:a7a43371b306	611	*/
ram54288	0:a7a43371b306	612	static void rf_if_enable_ant_div(void)
ram54288	0:a7a43371b306	613	{
ram54288	0:a7a43371b306	614	/Set ANT_EXT_SW_EN to enable controlling of antenna diversity/
ram54288	0:a7a43371b306	615	rf_if_set_bit(ANT_DIV, ANT_EXT_SW_EN, ANT_EXT_SW_EN);
ram54288	0:a7a43371b306	616	}
ram54288	0:a7a43371b306	617
ram54288	0:a7a43371b306	618	/*
ram54288	0:a7a43371b306	619	* \brief Function disables the Antenna diversity usage.
ram54288	0:a7a43371b306	620	*
ram54288	0:a7a43371b306	621	* \param none
ram54288	0:a7a43371b306	622	*
ram54288	0:a7a43371b306	623	* \return none
ram54288	0:a7a43371b306	624	*/
ram54288	0:a7a43371b306	625	static void rf_if_disable_ant_div(void)
ram54288	0:a7a43371b306	626	{
ram54288	0:a7a43371b306	627	rf_if_clear_bit(ANT_DIV, ANT_EXT_SW_EN);
ram54288	0:a7a43371b306	628	}
ram54288	0:a7a43371b306	629
ram54288	0:a7a43371b306	630	/*
ram54288	0:a7a43371b306	631	* \brief Function sets the SLP TR pin.
ram54288	0:a7a43371b306	632	*
ram54288	0:a7a43371b306	633	* \param none
ram54288	0:a7a43371b306	634	*
ram54288	0:a7a43371b306	635	* \return none
ram54288	0:a7a43371b306	636	*/
ram54288	0:a7a43371b306	637	static void rf_if_enable_slptr(void)
ram54288	0:a7a43371b306	638	{
ram54288	0:a7a43371b306	639	rf->SLP_TR = 1;
ram54288	0:a7a43371b306	640	}
ram54288	0:a7a43371b306	641
ram54288	0:a7a43371b306	642	/*
ram54288	0:a7a43371b306	643	* \brief Function clears the SLP TR pin.
ram54288	0:a7a43371b306	644	*
ram54288	0:a7a43371b306	645	* \param none
ram54288	0:a7a43371b306	646	*
ram54288	0:a7a43371b306	647	* \return none
ram54288	0:a7a43371b306	648	*/
ram54288	0:a7a43371b306	649	static void rf_if_disable_slptr(void)
ram54288	0:a7a43371b306	650	{
ram54288	0:a7a43371b306	651	rf->SLP_TR = 0;
ram54288	0:a7a43371b306	652	}
ram54288	0:a7a43371b306	653
ram54288	0:a7a43371b306	654	/*
ram54288	0:a7a43371b306	655	* \brief Function writes the antenna diversity settings.
ram54288	0:a7a43371b306	656	*
ram54288	0:a7a43371b306	657	* \param none
ram54288	0:a7a43371b306	658	*
ram54288	0:a7a43371b306	659	* \return none
ram54288	0:a7a43371b306	660	*/
ram54288	0:a7a43371b306	661	static void rf_if_write_antenna_diversity_settings(void)
ram54288	0:a7a43371b306	662	{
ram54288	0:a7a43371b306	663	/Recommended setting of PDT_THRES is 3 when antenna diversity is used/
ram54288	0:a7a43371b306	664	rf_if_set_bit(RX_CTRL, 0x03, 0x0f);
ram54288	0:a7a43371b306	665	rf_if_write_register(ANT_DIV, ANT_DIV_EN \| ANT_EXT_SW_EN \| ANT_CTRL_DEFAULT);
ram54288	0:a7a43371b306	666	}
ram54288	0:a7a43371b306	667
ram54288	0:a7a43371b306	668	/*
ram54288	0:a7a43371b306	669	* \brief Function writes the TX output power register.
ram54288	0:a7a43371b306	670	*
ram54288	0:a7a43371b306	671	* \param value Given register value
ram54288	0:a7a43371b306	672	*
ram54288	0:a7a43371b306	673	* \return none
ram54288	0:a7a43371b306	674	*/
ram54288	0:a7a43371b306	675	static void rf_if_write_set_tx_power_register(uint8_t value)
ram54288	0:a7a43371b306	676	{
ram54288	0:a7a43371b306	677	rf_if_write_register(PHY_TX_PWR, value);
ram54288	0:a7a43371b306	678	}
ram54288	0:a7a43371b306	679
ram54288	0:a7a43371b306	680	/*
ram54288	0:a7a43371b306	681	* \brief Function returns the RF part number.
ram54288	0:a7a43371b306	682	*
ram54288	0:a7a43371b306	683	* \param none
ram54288	0:a7a43371b306	684	*
ram54288	0:a7a43371b306	685	* \return part number
ram54288	0:a7a43371b306	686	*/
ram54288	0:a7a43371b306	687	static uint8_t rf_if_read_part_num(void)
ram54288	0:a7a43371b306	688	{
ram54288	0:a7a43371b306	689	return rf_if_read_register(PART_NUM);
ram54288	0:a7a43371b306	690	}
ram54288	0:a7a43371b306	691
ram54288	0:a7a43371b306	692	/*
ram54288	0:a7a43371b306	693	* \brief Function writes the RF settings and initialises SPI interface.
ram54288	0:a7a43371b306	694	*
ram54288	0:a7a43371b306	695	* \param none
ram54288	0:a7a43371b306	696	*
ram54288	0:a7a43371b306	697	* \return none
ram54288	0:a7a43371b306	698	*/
ram54288	0:a7a43371b306	699	static void rf_if_write_rf_settings(void)
ram54288	0:a7a43371b306	700	{
ram54288	0:a7a43371b306	701	/Reset RF module/
ram54288	0:a7a43371b306	702	rf_if_reset_radio();
ram54288	0:a7a43371b306	703
ram54288	0:a7a43371b306	704	rf_part_num = rf_if_read_part_num();
ram54288	0:a7a43371b306	705
ram54288	0:a7a43371b306	706	rf_if_write_register(XAH_CTRL_0,0);
ram54288	0:a7a43371b306	707	rf_if_write_register(TRX_CTRL_1, 0x20);
ram54288	0:a7a43371b306	708
ram54288	0:a7a43371b306	709	/CCA Mode - Carrier sense OR energy above threshold. Channel list is set separately/
ram54288	0:a7a43371b306	710	rf_if_write_register(PHY_CC_CCA, 0x05);
ram54288	0:a7a43371b306	711
ram54288	0:a7a43371b306	712	/Read transceiver PART_NUM/
ram54288	0:a7a43371b306	713	rf_part_num = rf_if_read_register(PART_NUM);
ram54288	0:a7a43371b306	714
ram54288	0:a7a43371b306	715	/Sub-GHz RF settings/
ram54288	0:a7a43371b306	716	if(rf_part_num == PART_AT86RF212)
ram54288	0:a7a43371b306	717	{
ram54288	0:a7a43371b306	718	/GC_TX_OFFS mode-dependent setting - OQPSK/
ram54288	0:a7a43371b306	719	rf_if_write_register(RF_CTRL_0, 0x32);
ram54288	0:a7a43371b306	720
ram54288	0:a7a43371b306	721	if(rf_if_read_register(VERSION_NUM) == VERSION_AT86RF212B)
ram54288	0:a7a43371b306	722	{
ram54288	0:a7a43371b306	723	/TX Output Power setting - 0 dBm North American Band/
ram54288	0:a7a43371b306	724	rf_if_write_register(PHY_TX_PWR, 0x03);
ram54288	0:a7a43371b306	725	}
ram54288	0:a7a43371b306	726	else
ram54288	0:a7a43371b306	727	{
ram54288	0:a7a43371b306	728	/TX Output Power setting - 0 dBm North American Band/
ram54288	0:a7a43371b306	729	rf_if_write_register(PHY_TX_PWR, 0x24);
ram54288	0:a7a43371b306	730	}
ram54288	0:a7a43371b306	731
ram54288	0:a7a43371b306	732	/PHY Mode: IEEE 802.15.4-2006/2011 - OQPSK-SIN-250/
ram54288	0:a7a43371b306	733	rf_if_write_register(TRX_CTRL_2, RF_PHY_MODE);
ram54288	0:a7a43371b306	734	/Based on receiver Characteristics. See AT86RF212B Datasheet where RSSI BASE VALUE in range -97 - -100 dBm/
ram54288	0:a7a43371b306	735	rf_rssi_base_val = -98;
ram54288	0:a7a43371b306	736	}
ram54288	0:a7a43371b306	737	/2.4GHz RF settings/
ram54288	0:a7a43371b306	738	else
ram54288	0:a7a43371b306	739	{
ram54288	0:a7a43371b306	740	#if 0
ram54288	0:a7a43371b306	741	/* Disable power saving functions for now - can only impact reliability,
ram54288	0:a7a43371b306	742	* and don't have any users demanding it. */
ram54288	0:a7a43371b306	743	/Set RPC register/
ram54288	0:a7a43371b306	744	rf_if_write_register(TRX_RPC, RX_RPC_CTRL\|RX_RPC_EN\|PLL_RPC_EN\|XAH_TX_RPC_EN\|IPAN_RPC_EN\|TRX_RPC_RSVD_1);
ram54288	0:a7a43371b306	745	#endif
ram54288	0:a7a43371b306	746	/PHY Mode: IEEE 802.15.4 - Data Rate 250 kb/s/
ram54288	0:a7a43371b306	747	rf_if_write_register(TRX_CTRL_2, 0);
ram54288	0:a7a43371b306	748	rf_rssi_base_val = -91;
ram54288	0:a7a43371b306	749	}
ram54288	0:a7a43371b306	750	}
ram54288	0:a7a43371b306	751
ram54288	0:a7a43371b306	752	/*
ram54288	0:a7a43371b306	753	* \brief Function checks the channel availability
ram54288	0:a7a43371b306	754	*
ram54288	0:a7a43371b306	755	* \param none
ram54288	0:a7a43371b306	756	*
ram54288	0:a7a43371b306	757	* \return 1 Channel clear
ram54288	0:a7a43371b306	758	* \return 0 Channel not clear
ram54288	0:a7a43371b306	759	*/
ram54288	0:a7a43371b306	760	static uint8_t rf_if_check_cca(void)
ram54288	0:a7a43371b306	761	{
ram54288	0:a7a43371b306	762	uint8_t retval = 0;
ram54288	0:a7a43371b306	763	if(rf_if_read_register(TRX_STATUS) & CCA_STATUS)
ram54288	0:a7a43371b306	764	{
ram54288	0:a7a43371b306	765	retval = 1;
ram54288	0:a7a43371b306	766	}
ram54288	0:a7a43371b306	767	return retval;
ram54288	0:a7a43371b306	768	}
ram54288	0:a7a43371b306	769
ram54288	0:a7a43371b306	770	/*
ram54288	0:a7a43371b306	771	* \brief Function returns the RF state
ram54288	0:a7a43371b306	772	*
ram54288	0:a7a43371b306	773	* \param none
ram54288	0:a7a43371b306	774	*
ram54288	0:a7a43371b306	775	* \return RF state
ram54288	0:a7a43371b306	776	*/
ram54288	0:a7a43371b306	777	static uint8_t rf_if_read_trx_state(void)
ram54288	0:a7a43371b306	778	{
ram54288	0:a7a43371b306	779	return rf_if_read_register(TRX_STATUS) & 0x1F;
ram54288	0:a7a43371b306	780	}
ram54288	0:a7a43371b306	781
ram54288	0:a7a43371b306	782	/*
ram54288	0:a7a43371b306	783	* \brief Function reads packet buffer.
ram54288	0:a7a43371b306	784	*
ram54288	0:a7a43371b306	785	* \param data_out Output buffer
ram54288	0:a7a43371b306	786	* \param lqi_out LQI output
ram54288	0:a7a43371b306	787	* \param ed_out ED output
ram54288	0:a7a43371b306	788	* \param crc_good CRC good indication
ram54288	0:a7a43371b306	789	*
ram54288	0:a7a43371b306	790	* \return PSDU length [0..RF_MTU]
ram54288	0:a7a43371b306	791	*/
ram54288	0:a7a43371b306	792	static uint16_t rf_if_read_packet(uint8_t data_out[RF_MTU], uint8_t lqi_out, uint8_t ed_out, bool *crc_good)
ram54288	0:a7a43371b306	793	{
ram54288	0:a7a43371b306	794	CS_SELECT();
ram54288	0:a7a43371b306	795	rf_if_spi_exchange(0x20);
ram54288	0:a7a43371b306	796	uint8_t len = rf_if_spi_exchange(0) & 0x7F;
ram54288	0:a7a43371b306	797	uint8_t *ptr = data_out;
ram54288	0:a7a43371b306	798	for (uint_fast8_t i = 0; i < len; i++) {
ram54288	0:a7a43371b306	799	*ptr++ = rf_if_spi_exchange(0);
ram54288	0:a7a43371b306	800	}
ram54288	0:a7a43371b306	801
ram54288	0:a7a43371b306	802	*lqi_out = rf_if_spi_exchange(0);
ram54288	0:a7a43371b306	803	*ed_out = rf_if_spi_exchange(0);
ram54288	0:a7a43371b306	804	*crc_good = rf_if_spi_exchange(0) & 0x80;
ram54288	0:a7a43371b306	805	CS_RELEASE();
ram54288	0:a7a43371b306	806
ram54288	0:a7a43371b306	807	return len;
ram54288	0:a7a43371b306	808	}
ram54288	0:a7a43371b306	809
ram54288	0:a7a43371b306	810	/*
ram54288	0:a7a43371b306	811	* \brief Function writes RF short address registers
ram54288	0:a7a43371b306	812	*
ram54288	0:a7a43371b306	813	* \param short_address Given short address
ram54288	0:a7a43371b306	814	*
ram54288	0:a7a43371b306	815	* \return none
ram54288	0:a7a43371b306	816	*/
ram54288	0:a7a43371b306	817	static void rf_if_write_short_addr_registers(uint8_t *short_address)
ram54288	0:a7a43371b306	818	{
ram54288	0:a7a43371b306	819	rf_if_write_register(SHORT_ADDR_1, *short_address++);
ram54288	0:a7a43371b306	820	rf_if_write_register(SHORT_ADDR_0, *short_address);
ram54288	0:a7a43371b306	821	}
ram54288	0:a7a43371b306	822
ram54288	0:a7a43371b306	823	/*
ram54288	0:a7a43371b306	824	* \brief Function sets the frame pending in ACK message
ram54288	0:a7a43371b306	825	*
ram54288	0:a7a43371b306	826	* \param state Given frame pending state
ram54288	0:a7a43371b306	827	*
ram54288	0:a7a43371b306	828	* \return none
ram54288	0:a7a43371b306	829	*/
ram54288	0:a7a43371b306	830	static void rf_if_ack_pending_ctrl(uint8_t state)
ram54288	0:a7a43371b306	831	{
ram54288	0:a7a43371b306	832	rf_if_lock();
ram54288	0:a7a43371b306	833	if(state)
ram54288	0:a7a43371b306	834	{
ram54288	0:a7a43371b306	835	rf_if_set_bit(CSMA_SEED_1, (1 << AACK_SET_PD), (1 << AACK_SET_PD));
ram54288	0:a7a43371b306	836	}
ram54288	0:a7a43371b306	837	else
ram54288	0:a7a43371b306	838	{
ram54288	0:a7a43371b306	839	rf_if_clear_bit(CSMA_SEED_1, (1 << AACK_SET_PD));
ram54288	0:a7a43371b306	840	}
ram54288	0:a7a43371b306	841	rf_if_unlock();
ram54288	0:a7a43371b306	842	}
ram54288	0:a7a43371b306	843
ram54288	0:a7a43371b306	844	/*
ram54288	0:a7a43371b306	845	* \brief Function returns the state of frame pending control
ram54288	0:a7a43371b306	846	*
ram54288	0:a7a43371b306	847	* \param none
ram54288	0:a7a43371b306	848	*
ram54288	0:a7a43371b306	849	* \return Frame pending state
ram54288	0:a7a43371b306	850	*/
ram54288	0:a7a43371b306	851	static uint8_t rf_if_last_acked_pending(void)
ram54288	0:a7a43371b306	852	{
ram54288	0:a7a43371b306	853	uint8_t last_acked_data_pending;
ram54288	0:a7a43371b306	854
ram54288	0:a7a43371b306	855	rf_if_lock();
ram54288	0:a7a43371b306	856	if(rf_if_read_register(CSMA_SEED_1) & 0x20)
ram54288	0:a7a43371b306	857	last_acked_data_pending = 1;
ram54288	0:a7a43371b306	858	else
ram54288	0:a7a43371b306	859	last_acked_data_pending = 0;
ram54288	0:a7a43371b306	860	rf_if_unlock();
ram54288	0:a7a43371b306	861
ram54288	0:a7a43371b306	862	return last_acked_data_pending;
ram54288	0:a7a43371b306	863	}
ram54288	0:a7a43371b306	864
ram54288	0:a7a43371b306	865	/*
ram54288	0:a7a43371b306	866	* \brief Function calibrates the RF part.
ram54288	0:a7a43371b306	867	*
ram54288	0:a7a43371b306	868	* \param none
ram54288	0:a7a43371b306	869	*
ram54288	0:a7a43371b306	870	* \return none
ram54288	0:a7a43371b306	871	*/
ram54288	0:a7a43371b306	872	static void rf_if_calibration(void)
ram54288	0:a7a43371b306	873	{
ram54288	0:a7a43371b306	874	rf_if_set_bit(FTN_CTRL, FTN_START, FTN_START);
ram54288	0:a7a43371b306	875	/Wait while calibration is running/
ram54288	0:a7a43371b306	876	while(rf_if_read_register(FTN_CTRL) & FTN_START);
ram54288	0:a7a43371b306	877	}
ram54288	0:a7a43371b306	878
ram54288	0:a7a43371b306	879	/*
ram54288	0:a7a43371b306	880	* \brief Function writes RF PAN Id registers
ram54288	0:a7a43371b306	881	*
ram54288	0:a7a43371b306	882	* \param pan_id Given PAN Id
ram54288	0:a7a43371b306	883	*
ram54288	0:a7a43371b306	884	* \return none
ram54288	0:a7a43371b306	885	*/
ram54288	0:a7a43371b306	886	static void rf_if_write_pan_id_registers(uint8_t *pan_id)
ram54288	0:a7a43371b306	887	{
ram54288	0:a7a43371b306	888	rf_if_write_register(PAN_ID_1, *pan_id++);
ram54288	0:a7a43371b306	889	rf_if_write_register(PAN_ID_0, *pan_id);
ram54288	0:a7a43371b306	890	}
ram54288	0:a7a43371b306	891
ram54288	0:a7a43371b306	892	/*
ram54288	0:a7a43371b306	893	* \brief Function writes RF IEEE Address registers
ram54288	0:a7a43371b306	894	*
ram54288	0:a7a43371b306	895	* \param address Given IEEE Address
ram54288	0:a7a43371b306	896	*
ram54288	0:a7a43371b306	897	* \return none
ram54288	0:a7a43371b306	898	*/
ram54288	0:a7a43371b306	899	static void rf_if_write_ieee_addr_registers(uint8_t *address)
ram54288	0:a7a43371b306	900	{
ram54288	0:a7a43371b306	901	uint8_t i;
ram54288	0:a7a43371b306	902	uint8_t temp = IEEE_ADDR_0;
ram54288	0:a7a43371b306	903
ram54288	0:a7a43371b306	904	for(i=0; i<8; i++)
ram54288	0:a7a43371b306	905	rf_if_write_register(temp++, address[7-i]);
ram54288	0:a7a43371b306	906	}
ram54288	0:a7a43371b306	907
ram54288	0:a7a43371b306	908	/*
ram54288	0:a7a43371b306	909	* \brief Function writes data in RF frame buffer.
ram54288	0:a7a43371b306	910	*
ram54288	0:a7a43371b306	911	* \param ptr Pointer to data (PSDU, except FCS)
ram54288	0:a7a43371b306	912	* \param length Pointer to length (PSDU length, minus 2 for FCS)
ram54288	0:a7a43371b306	913	*
ram54288	0:a7a43371b306	914	* \return none
ram54288	0:a7a43371b306	915	*/
ram54288	0:a7a43371b306	916	static void rf_if_write_frame_buffer(const uint8_t *ptr, uint8_t length)
ram54288	0:a7a43371b306	917	{
ram54288	0:a7a43371b306	918	uint8_t i;
ram54288	0:a7a43371b306	919	uint8_t cmd = 0x60;
ram54288	0:a7a43371b306	920
ram54288	0:a7a43371b306	921	CS_SELECT();
ram54288	0:a7a43371b306	922	rf_if_spi_exchange(cmd);
ram54288	0:a7a43371b306	923	rf_if_spi_exchange(length + 2);
ram54288	0:a7a43371b306	924	for(i=0; i<length; i++)
ram54288	0:a7a43371b306	925	rf_if_spi_exchange(*ptr++);
ram54288	0:a7a43371b306	926
ram54288	0:a7a43371b306	927	CS_RELEASE();
ram54288	0:a7a43371b306	928	}
ram54288	0:a7a43371b306	929
ram54288	0:a7a43371b306	930	/*
ram54288	0:a7a43371b306	931	* \brief Function returns 8-bit random value.
ram54288	0:a7a43371b306	932	*
ram54288	0:a7a43371b306	933	* \param none
ram54288	0:a7a43371b306	934	*
ram54288	0:a7a43371b306	935	* \return random value
ram54288	0:a7a43371b306	936	*/
ram54288	0:a7a43371b306	937	static uint8_t rf_if_read_rnd(void)
ram54288	0:a7a43371b306	938	{
ram54288	0:a7a43371b306	939	uint8_t temp;
ram54288	0:a7a43371b306	940	uint8_t tmp_rpc_val = 0;
ram54288	0:a7a43371b306	941	/RPC must be disabled while reading the random number/
ram54288	0:a7a43371b306	942	if(rf_part_num == PART_AT86RF233)
ram54288	0:a7a43371b306	943	{
ram54288	0:a7a43371b306	944	tmp_rpc_val = rf_if_read_register(TRX_RPC);
ram54288	0:a7a43371b306	945	rf_if_write_register(TRX_RPC, RX_RPC_CTRL\|TRX_RPC_RSVD_1);
ram54288	0:a7a43371b306	946	}
ram54288	0:a7a43371b306	947
ram54288	0:a7a43371b306	948	wait_ms(1);
ram54288	0:a7a43371b306	949	temp = ((rf_if_read_register(PHY_RSSI)>>5) << 6);
ram54288	0:a7a43371b306	950	wait_ms(1);
ram54288	0:a7a43371b306	951	temp \|= ((rf_if_read_register(PHY_RSSI)>>5) << 4);
ram54288	0:a7a43371b306	952	wait_ms(1);
ram54288	0:a7a43371b306	953	temp \|= ((rf_if_read_register(PHY_RSSI)>>5) << 2);
ram54288	0:a7a43371b306	954	wait_ms(1);
ram54288	0:a7a43371b306	955	temp \|= ((rf_if_read_register(PHY_RSSI)>>5));
ram54288	0:a7a43371b306	956	wait_ms(1);
ram54288	0:a7a43371b306	957	if(rf_part_num == PART_AT86RF233)
ram54288	0:a7a43371b306	958	rf_if_write_register(TRX_RPC, tmp_rpc_val);
ram54288	0:a7a43371b306	959	return temp;
ram54288	0:a7a43371b306	960	}
ram54288	0:a7a43371b306	961
ram54288	0:a7a43371b306	962	/*
ram54288	0:a7a43371b306	963	* \brief Function changes the state of the RF.
ram54288	0:a7a43371b306	964	*
ram54288	0:a7a43371b306	965	* \param trx_state Given RF state
ram54288	0:a7a43371b306	966	*
ram54288	0:a7a43371b306	967	* \return none
ram54288	0:a7a43371b306	968	*/
ram54288	0:a7a43371b306	969	static void rf_if_change_trx_state(rf_trx_states_t trx_state)
ram54288	0:a7a43371b306	970	{
ram54288	0:a7a43371b306	971	// XXX Lock claim apparently not required
ram54288	0:a7a43371b306	972	rf_if_lock();
ram54288	0:a7a43371b306	973	rf_if_write_register(TRX_STATE, trx_state);
ram54288	0:a7a43371b306	974	/Wait while not in desired state/
ram54288	0:a7a43371b306	975	rf_poll_trx_state_change(trx_state);
ram54288	0:a7a43371b306	976	rf_if_unlock();
ram54288	0:a7a43371b306	977	}
ram54288	0:a7a43371b306	978
ram54288	0:a7a43371b306	979	/*
ram54288	0:a7a43371b306	980	* \brief Function enables the TX END interrupt
ram54288	0:a7a43371b306	981	*
ram54288	0:a7a43371b306	982	* \param none
ram54288	0:a7a43371b306	983	*
ram54288	0:a7a43371b306	984	* \return none
ram54288	0:a7a43371b306	985	*/
ram54288	0:a7a43371b306	986	static void rf_if_enable_tx_end_interrupt(void)
ram54288	0:a7a43371b306	987	{
ram54288	0:a7a43371b306	988	rf_if_set_bit(IRQ_MASK, TRX_END, TRX_END);
ram54288	0:a7a43371b306	989	}
ram54288	0:a7a43371b306	990
ram54288	0:a7a43371b306	991	/*
ram54288	0:a7a43371b306	992	* \brief Function enables the RX END interrupt
ram54288	0:a7a43371b306	993	*
ram54288	0:a7a43371b306	994	* \param none
ram54288	0:a7a43371b306	995	*
ram54288	0:a7a43371b306	996	* \return none
ram54288	0:a7a43371b306	997	*/
ram54288	0:a7a43371b306	998	static void rf_if_enable_rx_end_interrupt(void)
ram54288	0:a7a43371b306	999	{
ram54288	0:a7a43371b306	1000	rf_if_set_bit(IRQ_MASK, TRX_END, TRX_END);
ram54288	0:a7a43371b306	1001	}
ram54288	0:a7a43371b306	1002
ram54288	0:a7a43371b306	1003	/*
ram54288	0:a7a43371b306	1004	* \brief Function enables the CCA ED interrupt
ram54288	0:a7a43371b306	1005	*
ram54288	0:a7a43371b306	1006	* \param none
ram54288	0:a7a43371b306	1007	*
ram54288	0:a7a43371b306	1008	* \return none
ram54288	0:a7a43371b306	1009	*/
ram54288	0:a7a43371b306	1010	static void rf_if_enable_cca_ed_done_interrupt(void)
ram54288	0:a7a43371b306	1011	{
ram54288	0:a7a43371b306	1012	rf_if_set_bit(IRQ_MASK, CCA_ED_DONE, CCA_ED_DONE);
ram54288	0:a7a43371b306	1013	}
ram54288	0:a7a43371b306	1014
ram54288	0:a7a43371b306	1015	/*
ram54288	0:a7a43371b306	1016	* \brief Function starts the CCA process
ram54288	0:a7a43371b306	1017	*
ram54288	0:a7a43371b306	1018	* \param none
ram54288	0:a7a43371b306	1019	*
ram54288	0:a7a43371b306	1020	* \return none
ram54288	0:a7a43371b306	1021	*/
ram54288	0:a7a43371b306	1022	static void rf_if_start_cca_process(void)
ram54288	0:a7a43371b306	1023	{
ram54288	0:a7a43371b306	1024	rf_if_set_bit(PHY_CC_CCA, CCA_REQUEST, CCA_REQUEST);
ram54288	0:a7a43371b306	1025	}
ram54288	0:a7a43371b306	1026
ram54288	0:a7a43371b306	1027	/*
ram54288	0:a7a43371b306	1028	* \brief Function scales RSSI
ram54288	0:a7a43371b306	1029	*
ram54288	0:a7a43371b306	1030	* \param ed_level ED level read from chip
ram54288	0:a7a43371b306	1031	*
ram54288	0:a7a43371b306	1032	* \return appropriately scaled RSSI dBm
ram54288	0:a7a43371b306	1033	*/
ram54288	0:a7a43371b306	1034	static int8_t rf_if_scale_rssi(uint8_t ed_level)
ram54288	0:a7a43371b306	1035	{
ram54288	0:a7a43371b306	1036	if (rf_part_num == PART_AT86RF212) {
ram54288	0:a7a43371b306	1037	/* Data sheet says to multiply by 1.03 - this is 1.03125, rounding down */
ram54288	0:a7a43371b306	1038	ed_level += ed_level >> 5;
ram54288	0:a7a43371b306	1039	}
ram54288	0:a7a43371b306	1040	return rf_rssi_base_val + ed_level;
ram54288	0:a7a43371b306	1041	}
ram54288	0:a7a43371b306	1042
ram54288	0:a7a43371b306	1043	/*
ram54288	0:a7a43371b306	1044	* \brief Function sets the RF channel field
ram54288	0:a7a43371b306	1045	*
ram54288	0:a7a43371b306	1046	* \param Given channel
ram54288	0:a7a43371b306	1047	*
ram54288	0:a7a43371b306	1048	* \return none
ram54288	0:a7a43371b306	1049	*/
ram54288	0:a7a43371b306	1050	static void rf_if_set_channel_register(uint8_t channel)
ram54288	0:a7a43371b306	1051	{
ram54288	0:a7a43371b306	1052	rf_if_set_bit(PHY_CC_CCA, channel, 0x1f);
ram54288	0:a7a43371b306	1053	}
ram54288	0:a7a43371b306	1054
ram54288	0:a7a43371b306	1055	/*
ram54288	0:a7a43371b306	1056	* \brief Function enables RF irq pin interrupts in RF interface.
ram54288	0:a7a43371b306	1057	*
ram54288	0:a7a43371b306	1058	* \param none
ram54288	0:a7a43371b306	1059	*
ram54288	0:a7a43371b306	1060	* \return none
ram54288	0:a7a43371b306	1061	*/
ram54288	0:a7a43371b306	1062	static void rf_if_enable_irq(void)
ram54288	0:a7a43371b306	1063	{
ram54288	0:a7a43371b306	1064	rf->IRQ.enable_irq();
ram54288	0:a7a43371b306	1065	}
ram54288	0:a7a43371b306	1066
ram54288	0:a7a43371b306	1067	/*
ram54288	0:a7a43371b306	1068	* \brief Function disables RF irq pin interrupts in RF interface.
ram54288	0:a7a43371b306	1069	*
ram54288	0:a7a43371b306	1070	* \param none
ram54288	0:a7a43371b306	1071	*
ram54288	0:a7a43371b306	1072	* \return none
ram54288	0:a7a43371b306	1073	*/
ram54288	0:a7a43371b306	1074	static void rf_if_disable_irq(void)
ram54288	0:a7a43371b306	1075	{
ram54288	0:a7a43371b306	1076	rf->IRQ.disable_irq();
ram54288	0:a7a43371b306	1077	}
ram54288	0:a7a43371b306	1078
ram54288	0:a7a43371b306	1079	#ifdef MBED_CONF_RTOS_PRESENT
ram54288	0:a7a43371b306	1080	static void rf_if_interrupt_handler(void)
ram54288	0:a7a43371b306	1081	{
ram54288	0:a7a43371b306	1082	rf->irq_thread.signal_set(SIG_RADIO);
ram54288	0:a7a43371b306	1083	}
ram54288	0:a7a43371b306	1084
ram54288	0:a7a43371b306	1085	// Started during construction of rf, so variable
ram54288	0:a7a43371b306	1086	// rf isn't set at the start. Uses 'this' instead.
ram54288	0:a7a43371b306	1087	void RFBits::rf_if_irq_task(void)
ram54288	0:a7a43371b306	1088	{
ram54288	0:a7a43371b306	1089	for (;;) {
ram54288	0:a7a43371b306	1090	osEvent event = irq_thread.signal_wait(0);
ram54288	0:a7a43371b306	1091	if (event.status != osEventSignal) {
ram54288	0:a7a43371b306	1092	continue;
ram54288	0:a7a43371b306	1093	}
ram54288	0:a7a43371b306	1094	rf_if_lock();
ram54288	0:a7a43371b306	1095	if (event.value.signals & SIG_RADIO) {
ram54288	0:a7a43371b306	1096	rf_if_irq_task_process_irq();
ram54288	0:a7a43371b306	1097	}
ram54288	0:a7a43371b306	1098	if (event.value.signals & SIG_TIMER_ACK) {
ram54288	0:a7a43371b306	1099	rf_ack_wait_timer_interrupt();
ram54288	0:a7a43371b306	1100	}
ram54288	0:a7a43371b306	1101	if (event.value.signals & SIG_TIMER_CCA) {
ram54288	0:a7a43371b306	1102	rf_cca_timer_interrupt();
ram54288	0:a7a43371b306	1103	}
ram54288	0:a7a43371b306	1104	if (event.value.signals & SIG_TIMER_CAL) {
ram54288	0:a7a43371b306	1105	rf_calibration_timer_interrupt();
ram54288	0:a7a43371b306	1106	}
ram54288	0:a7a43371b306	1107	rf_if_unlock();
ram54288	0:a7a43371b306	1108	}
ram54288	0:a7a43371b306	1109	}
ram54288	0:a7a43371b306	1110
ram54288	0:a7a43371b306	1111	static void rf_if_irq_task_process_irq(void)
ram54288	0:a7a43371b306	1112	#else
ram54288	0:a7a43371b306	1113	/*
ram54288	0:a7a43371b306	1114	* \brief Function is a RF interrupt vector. End of frame in RX and TX are handled here as well as CCA process interrupt.
ram54288	0:a7a43371b306	1115	*
ram54288	0:a7a43371b306	1116	* \param none
ram54288	0:a7a43371b306	1117	*
ram54288	0:a7a43371b306	1118	* \return none
ram54288	0:a7a43371b306	1119	*/
ram54288	0:a7a43371b306	1120	static void rf_if_interrupt_handler(void)
ram54288	0:a7a43371b306	1121	#endif
ram54288	0:a7a43371b306	1122	{
ram54288	0:a7a43371b306	1123	uint8_t irq_status;
ram54288	0:a7a43371b306	1124
ram54288	0:a7a43371b306	1125	/Read interrupt flag/
ram54288	0:a7a43371b306	1126	irq_status = rf_if_read_register(IRQ_STATUS);
ram54288	0:a7a43371b306	1127
ram54288	0:a7a43371b306	1128	/Disable interrupt on RF/
ram54288	0:a7a43371b306	1129	rf_if_clear_bit(IRQ_MASK, irq_status);
ram54288	0:a7a43371b306	1130	/RX start interrupt/
ram54288	0:a7a43371b306	1131	if(irq_status & RX_START)
ram54288	0:a7a43371b306	1132	{
ram54288	0:a7a43371b306	1133	}
ram54288	0:a7a43371b306	1134	/Address matching interrupt/
ram54288	0:a7a43371b306	1135	if(irq_status & AMI)
ram54288	0:a7a43371b306	1136	{
ram54288	0:a7a43371b306	1137	}
ram54288	0:a7a43371b306	1138	if(irq_status & TRX_UR)
ram54288	0:a7a43371b306	1139	{
ram54288	0:a7a43371b306	1140	}
ram54288	0:a7a43371b306	1141	/Frame end interrupt (RX and TX)/
ram54288	0:a7a43371b306	1142	if(irq_status & TRX_END)
ram54288	0:a7a43371b306	1143	{
ram54288	0:a7a43371b306	1144	/TX done interrupt/
ram54288	0:a7a43371b306	1145	if(rf_if_read_trx_state() == PLL_ON \|\| rf_if_read_trx_state() == TX_ARET_ON)
ram54288	0:a7a43371b306	1146	{
ram54288	0:a7a43371b306	1147	rf_handle_tx_end();
ram54288	0:a7a43371b306	1148	}
ram54288	0:a7a43371b306	1149	/Frame received interrupt/
ram54288	0:a7a43371b306	1150	else
ram54288	0:a7a43371b306	1151	{
ram54288	0:a7a43371b306	1152	rf_handle_rx_end();
ram54288	0:a7a43371b306	1153	}
ram54288	0:a7a43371b306	1154	}
ram54288	0:a7a43371b306	1155	if(irq_status & CCA_ED_DONE)
ram54288	0:a7a43371b306	1156	{
ram54288	0:a7a43371b306	1157	rf_handle_cca_ed_done();
ram54288	0:a7a43371b306	1158	}
ram54288	0:a7a43371b306	1159	}
ram54288	0:a7a43371b306	1160
ram54288	0:a7a43371b306	1161	/*
ram54288	0:a7a43371b306	1162	* \brief Function writes/read data in SPI interface
ram54288	0:a7a43371b306	1163	*
ram54288	0:a7a43371b306	1164	* \param out Output data
ram54288	0:a7a43371b306	1165	*
ram54288	0:a7a43371b306	1166	* \return Input data
ram54288	0:a7a43371b306	1167	*/
ram54288	0:a7a43371b306	1168	static uint8_t rf_if_spi_exchange(uint8_t out)
ram54288	0:a7a43371b306	1169	{
ram54288	0:a7a43371b306	1170	uint8_t v;
ram54288	0:a7a43371b306	1171	v = rf->spi.write(out);
ram54288	0:a7a43371b306	1172	// t9 = t5 = 250ns, delay between LSB of last byte to next MSB or delay between LSB & SEL rising
ram54288	0:a7a43371b306	1173	// [SPI setup assumed slow enough to not need manual delay]
ram54288	0:a7a43371b306	1174	// delay_ns(250);
ram54288	0:a7a43371b306	1175	return v;
ram54288	0:a7a43371b306	1176	}
ram54288	0:a7a43371b306	1177
ram54288	0:a7a43371b306	1178	/*
ram54288	0:a7a43371b306	1179	* \brief Function sets given RF flag on.
ram54288	0:a7a43371b306	1180	*
ram54288	0:a7a43371b306	1181	* \param x Given RF flag
ram54288	0:a7a43371b306	1182	*
ram54288	0:a7a43371b306	1183	* \return none
ram54288	0:a7a43371b306	1184	*/
ram54288	0:a7a43371b306	1185	static void rf_flags_set(uint8_t x)
ram54288	0:a7a43371b306	1186	{
ram54288	0:a7a43371b306	1187	rf_flags \|= x;
ram54288	0:a7a43371b306	1188	}
ram54288	0:a7a43371b306	1189
ram54288	0:a7a43371b306	1190	/*
ram54288	0:a7a43371b306	1191	* \brief Function clears given RF flag on.
ram54288	0:a7a43371b306	1192	*
ram54288	0:a7a43371b306	1193	* \param x Given RF flag
ram54288	0:a7a43371b306	1194	*
ram54288	0:a7a43371b306	1195	* \return none
ram54288	0:a7a43371b306	1196	*/
ram54288	0:a7a43371b306	1197	static void rf_flags_clear(uint8_t x)
ram54288	0:a7a43371b306	1198	{
ram54288	0:a7a43371b306	1199	rf_flags &= ~x;
ram54288	0:a7a43371b306	1200	}
ram54288	0:a7a43371b306	1201
ram54288	0:a7a43371b306	1202	/*
ram54288	0:a7a43371b306	1203	* \brief Function checks if given RF flag is on.
ram54288	0:a7a43371b306	1204	*
ram54288	0:a7a43371b306	1205	* \param x Given RF flag
ram54288	0:a7a43371b306	1206	*
ram54288	0:a7a43371b306	1207	* \return states of the given flags
ram54288	0:a7a43371b306	1208	*/
ram54288	0:a7a43371b306	1209	static uint8_t rf_flags_check(uint8_t x)
ram54288	0:a7a43371b306	1210	{
ram54288	0:a7a43371b306	1211	return (rf_flags & x);
ram54288	0:a7a43371b306	1212	}
ram54288	0:a7a43371b306	1213
ram54288	0:a7a43371b306	1214	/*
ram54288	0:a7a43371b306	1215	* \brief Function clears all RF flags.
ram54288	0:a7a43371b306	1216	*
ram54288	0:a7a43371b306	1217	* \param none
ram54288	0:a7a43371b306	1218	*
ram54288	0:a7a43371b306	1219	* \return none
ram54288	0:a7a43371b306	1220	*/
ram54288	0:a7a43371b306	1221	static void rf_flags_reset(void)
ram54288	0:a7a43371b306	1222	{
ram54288	0:a7a43371b306	1223	rf_flags = 0;
ram54288	0:a7a43371b306	1224	}
ram54288	0:a7a43371b306	1225
ram54288	0:a7a43371b306	1226	/*
ram54288	0:a7a43371b306	1227	* \brief Function initialises and registers the RF driver.
ram54288	0:a7a43371b306	1228	*
ram54288	0:a7a43371b306	1229	* \param none
ram54288	0:a7a43371b306	1230	*
ram54288	0:a7a43371b306	1231	* \return rf_radio_driver_id Driver ID given by NET library
ram54288	0:a7a43371b306	1232	*/
ram54288	0:a7a43371b306	1233	static int8_t rf_device_register(const uint8_t *mac_addr)
ram54288	0:a7a43371b306	1234	{
ram54288	0:a7a43371b306	1235	rf_trx_part_e radio_type;
ram54288	0:a7a43371b306	1236
ram54288	0:a7a43371b306	1237	rf_init();
ram54288	0:a7a43371b306	1238
ram54288	0:a7a43371b306	1239	radio_type = rf_radio_type_read();
ram54288	0:a7a43371b306	1240	if(radio_type != ATMEL_UNKNOW_DEV)
ram54288	0:a7a43371b306	1241	{
ram54288	0:a7a43371b306	1242	/Set pointer to MAC address/
ram54288	0:a7a43371b306	1243	device_driver.PHY_MAC = (uint8_t *)mac_addr;
ram54288	0:a7a43371b306	1244	device_driver.driver_description = (char*)"ATMEL_MAC";
ram54288	0:a7a43371b306	1245	//Create setup Used Radio chips
ram54288	0:a7a43371b306	1246	if(radio_type == ATMEL_AT86RF212)
ram54288	0:a7a43371b306	1247	{
ram54288	0:a7a43371b306	1248	device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
ram54288	0:a7a43371b306	1249	}
ram54288	0:a7a43371b306	1250	else
ram54288	0:a7a43371b306	1251	{
ram54288	0:a7a43371b306	1252	device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
ram54288	0:a7a43371b306	1253	}
ram54288	0:a7a43371b306	1254	device_driver.phy_channel_pages = phy_channel_pages;
ram54288	0:a7a43371b306	1255	/Maximum size of payload is 127/
ram54288	0:a7a43371b306	1256	device_driver.phy_MTU = 127;
ram54288	0:a7a43371b306	1257	/No header in PHY/
ram54288	0:a7a43371b306	1258	device_driver.phy_header_length = 0;
ram54288	0:a7a43371b306	1259	/No tail in PHY/
ram54288	0:a7a43371b306	1260	device_driver.phy_tail_length = 0;
ram54288	0:a7a43371b306	1261	/Set address write function/
ram54288	0:a7a43371b306	1262	device_driver.address_write = &rf_address_write;
ram54288	0:a7a43371b306	1263	/Set RF extension function/
ram54288	0:a7a43371b306	1264	device_driver.extension = &rf_extension;
ram54288	0:a7a43371b306	1265	/Set RF state control function/
ram54288	0:a7a43371b306	1266	device_driver.state_control = &rf_interface_state_control;
ram54288	0:a7a43371b306	1267	/Set transmit function/
ram54288	0:a7a43371b306	1268	device_driver.tx = &rf_start_cca;
ram54288	0:a7a43371b306	1269	/NULLIFY rx and tx_done callbacks/
ram54288	0:a7a43371b306	1270	device_driver.phy_rx_cb = NULL;
ram54288	0:a7a43371b306	1271	device_driver.phy_tx_done_cb = NULL;
ram54288	0:a7a43371b306	1272	/Register device driver/
ram54288	0:a7a43371b306	1273	rf_radio_driver_id = arm_net_phy_register(&device_driver);
ram54288	0:a7a43371b306	1274	}
ram54288	0:a7a43371b306	1275	return rf_radio_driver_id;
ram54288	0:a7a43371b306	1276	}
ram54288	0:a7a43371b306	1277
ram54288	0:a7a43371b306	1278	/*
ram54288	0:a7a43371b306	1279	* \brief Function unregisters the RF driver.
ram54288	0:a7a43371b306	1280	*
ram54288	0:a7a43371b306	1281	* \param none
ram54288	0:a7a43371b306	1282	*
ram54288	0:a7a43371b306	1283	* \return none
ram54288	0:a7a43371b306	1284	*/
ram54288	0:a7a43371b306	1285	static void rf_device_unregister()
ram54288	0:a7a43371b306	1286	{
ram54288	0:a7a43371b306	1287	if (rf_radio_driver_id >= 0) {
ram54288	0:a7a43371b306	1288	arm_net_phy_unregister(rf_radio_driver_id);
ram54288	0:a7a43371b306	1289	rf_radio_driver_id = -1;
ram54288	0:a7a43371b306	1290	}
ram54288	0:a7a43371b306	1291	}
ram54288	0:a7a43371b306	1292
ram54288	0:a7a43371b306	1293	/*
ram54288	0:a7a43371b306	1294	* \brief Enable frame buffer protection
ram54288	0:a7a43371b306	1295	*
ram54288	0:a7a43371b306	1296	* If protection is enabled, reception cannot start - the radio will
ram54288	0:a7a43371b306	1297	* not go into RX_BUSY or write into the frame buffer if in receive mode.
ram54288	0:a7a43371b306	1298	* Setting this won't abort an already-started reception.
ram54288	0:a7a43371b306	1299	* We can still write the frame buffer ourselves.
ram54288	0:a7a43371b306	1300	*/
ram54288	0:a7a43371b306	1301	static void rf_enable_static_frame_buffer_protection(void)
ram54288	0:a7a43371b306	1302	{
ram54288	0:a7a43371b306	1303	if (!rf_flags_check(RFF_PROT)) {
ram54288	0:a7a43371b306	1304	/* This also writes RX_PDT_LEVEL to 0 - maximum RX sensitivity */
ram54288	0:a7a43371b306	1305	/* Would need to modify this function if messing with that */
ram54288	0:a7a43371b306	1306	rf_if_write_register(RX_SYN, RX_PDT_DIS);
ram54288	0:a7a43371b306	1307	rf_flags_set(RFF_PROT);
ram54288	0:a7a43371b306	1308	}
ram54288	0:a7a43371b306	1309	}
ram54288	0:a7a43371b306	1310
ram54288	0:a7a43371b306	1311	/*
ram54288	0:a7a43371b306	1312	* \brief Disable frame buffer protection
ram54288	0:a7a43371b306	1313	*/
ram54288	0:a7a43371b306	1314	static void rf_disable_static_frame_buffer_protection(void)
ram54288	0:a7a43371b306	1315	{
ram54288	0:a7a43371b306	1316	if (rf_flags_check(RFF_PROT)) {
ram54288	0:a7a43371b306	1317	/* This also writes RX_PDT_LEVEL to 0 - maximum RX sensitivity */
ram54288	0:a7a43371b306	1318	/* Would need to modify this function if messing with that */
ram54288	0:a7a43371b306	1319	rf_if_write_register(RX_SYN, 0);
ram54288	0:a7a43371b306	1320	rf_flags_clear(RFF_PROT);
ram54288	0:a7a43371b306	1321	}
ram54288	0:a7a43371b306	1322	}
ram54288	0:a7a43371b306	1323
ram54288	0:a7a43371b306	1324
ram54288	0:a7a43371b306	1325	/*
ram54288	0:a7a43371b306	1326	* \brief Function is a call back for ACK wait timeout.
ram54288	0:a7a43371b306	1327	*
ram54288	0:a7a43371b306	1328	* \param none
ram54288	0:a7a43371b306	1329	*
ram54288	0:a7a43371b306	1330	* \return none
ram54288	0:a7a43371b306	1331	*/
ram54288	0:a7a43371b306	1332	static void rf_ack_wait_timer_interrupt(void)
ram54288	0:a7a43371b306	1333	{
ram54288	0:a7a43371b306	1334	rf_if_lock();
ram54288	0:a7a43371b306	1335	expected_ack_sequence = -1;
ram54288	0:a7a43371b306	1336	/Force PLL state/
ram54288	0:a7a43371b306	1337	rf_if_change_trx_state(FORCE_PLL_ON);
ram54288	0:a7a43371b306	1338	rf_poll_trx_state_change(PLL_ON);
ram54288	0:a7a43371b306	1339	/Start receiver in RX_AACK_ON state/
ram54288	0:a7a43371b306	1340	rf_rx_mode = 0;
ram54288	0:a7a43371b306	1341	rf_flags_clear(RFF_RX);
ram54288	0:a7a43371b306	1342	rf_receive();
ram54288	0:a7a43371b306	1343	rf_if_unlock();
ram54288	0:a7a43371b306	1344	}
ram54288	0:a7a43371b306	1345
ram54288	0:a7a43371b306	1346	/*
ram54288	0:a7a43371b306	1347	* \brief Function is a call back for calibration interval timer.
ram54288	0:a7a43371b306	1348	*
ram54288	0:a7a43371b306	1349	* \param none
ram54288	0:a7a43371b306	1350	*
ram54288	0:a7a43371b306	1351	* \return none
ram54288	0:a7a43371b306	1352	*/
ram54288	0:a7a43371b306	1353	static void rf_calibration_timer_interrupt(void)
ram54288	0:a7a43371b306	1354	{
ram54288	0:a7a43371b306	1355	/Calibrate RF/
ram54288	0:a7a43371b306	1356	rf_calibration_cb();
ram54288	0:a7a43371b306	1357	/Start new calibration timeout/
ram54288	0:a7a43371b306	1358	rf_calibration_timer_start(RF_CALIBRATION_INTERVAL);
ram54288	0:a7a43371b306	1359	}
ram54288	0:a7a43371b306	1360
ram54288	0:a7a43371b306	1361	/*
ram54288	0:a7a43371b306	1362	* \brief Function is a call back for cca interval timer.
ram54288	0:a7a43371b306	1363	*
ram54288	0:a7a43371b306	1364	* \param none
ram54288	0:a7a43371b306	1365	*
ram54288	0:a7a43371b306	1366	* \return none
ram54288	0:a7a43371b306	1367	*/
ram54288	0:a7a43371b306	1368	static void rf_cca_timer_interrupt(void)
ram54288	0:a7a43371b306	1369	{
ram54288	0:a7a43371b306	1370	/Disable reception - locks against entering BUSY_RX and overwriting frame buffer/
ram54288	0:a7a43371b306	1371	rf_enable_static_frame_buffer_protection();
ram54288	0:a7a43371b306	1372
ram54288	0:a7a43371b306	1373	if(rf_if_read_trx_state() == BUSY_RX_AACK)
ram54288	0:a7a43371b306	1374	{
ram54288	0:a7a43371b306	1375	/Reception already started - re-enable reception and say CCA fail/
ram54288	0:a7a43371b306	1376	rf_disable_static_frame_buffer_protection();
ram54288	0:a7a43371b306	1377	if(device_driver.phy_tx_done_cb){
ram54288	0:a7a43371b306	1378	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
ram54288	0:a7a43371b306	1379	}
ram54288	0:a7a43371b306	1380	}
ram54288	0:a7a43371b306	1381	else
ram54288	0:a7a43371b306	1382	{
ram54288	0:a7a43371b306	1383	/Load the frame buffer with frame to transmit /
ram54288	0:a7a43371b306	1384	rf_if_write_frame_buffer(rf_tx_data, rf_tx_length);
ram54288	0:a7a43371b306	1385	/Make sure we're in RX state to read channel (any way we could not be?)/
ram54288	0:a7a43371b306	1386	rf_receive();
ram54288	0:a7a43371b306	1387	rf_flags_set(RFF_CCA);
ram54288	0:a7a43371b306	1388	/Start CCA process/
ram54288	0:a7a43371b306	1389	rf_if_enable_cca_ed_done_interrupt();
ram54288	0:a7a43371b306	1390	rf_if_start_cca_process();
ram54288	0:a7a43371b306	1391	}
ram54288	0:a7a43371b306	1392	}
ram54288	0:a7a43371b306	1393
ram54288	0:a7a43371b306	1394	/*
ram54288	0:a7a43371b306	1395	* \brief Function starts the ACK wait timeout.
ram54288	0:a7a43371b306	1396	*
ram54288	0:a7a43371b306	1397	* \param slots Given slots, resolution 50us
ram54288	0:a7a43371b306	1398	*
ram54288	0:a7a43371b306	1399	* \return none
ram54288	0:a7a43371b306	1400	*/
ram54288	0:a7a43371b306	1401	static void rf_ack_wait_timer_start(uint16_t slots)
ram54288	0:a7a43371b306	1402	{
ram54288	0:a7a43371b306	1403	rf_if_ack_wait_timer_start(slots);
ram54288	0:a7a43371b306	1404	}
ram54288	0:a7a43371b306	1405
ram54288	0:a7a43371b306	1406	/*
ram54288	0:a7a43371b306	1407	* \brief Function starts the calibration interval.
ram54288	0:a7a43371b306	1408	*
ram54288	0:a7a43371b306	1409	* \param slots Given slots, resolution 50us
ram54288	0:a7a43371b306	1410	*
ram54288	0:a7a43371b306	1411	* \return none
ram54288	0:a7a43371b306	1412	*/
ram54288	0:a7a43371b306	1413	static void rf_calibration_timer_start(uint32_t slots)
ram54288	0:a7a43371b306	1414	{
ram54288	0:a7a43371b306	1415	rf_if_calibration_timer_start(slots);
ram54288	0:a7a43371b306	1416	}
ram54288	0:a7a43371b306	1417
ram54288	0:a7a43371b306	1418	/*
ram54288	0:a7a43371b306	1419	* \brief Function starts the CCA backoff.
ram54288	0:a7a43371b306	1420	*
ram54288	0:a7a43371b306	1421	* \param slots Given slots, resolution 50us
ram54288	0:a7a43371b306	1422	*
ram54288	0:a7a43371b306	1423	* \return none
ram54288	0:a7a43371b306	1424	*/
ram54288	0:a7a43371b306	1425	static void rf_cca_timer_start(uint32_t slots)
ram54288	0:a7a43371b306	1426	{
ram54288	0:a7a43371b306	1427	rf_if_cca_timer_start(slots);
ram54288	0:a7a43371b306	1428	}
ram54288	0:a7a43371b306	1429
ram54288	0:a7a43371b306	1430	/*
ram54288	0:a7a43371b306	1431	* \brief Function stops the CCA backoff.
ram54288	0:a7a43371b306	1432	*
ram54288	0:a7a43371b306	1433	* \return none
ram54288	0:a7a43371b306	1434	*/
ram54288	0:a7a43371b306	1435	static void rf_cca_timer_stop(void)
ram54288	0:a7a43371b306	1436	{
ram54288	0:a7a43371b306	1437	rf_if_cca_timer_stop();
ram54288	0:a7a43371b306	1438	}
ram54288	0:a7a43371b306	1439
ram54288	0:a7a43371b306	1440	/*
ram54288	0:a7a43371b306	1441	* \brief Function stops the ACK wait timeout.
ram54288	0:a7a43371b306	1442	*
ram54288	0:a7a43371b306	1443	* \param none
ram54288	0:a7a43371b306	1444	*
ram54288	0:a7a43371b306	1445	* \return none
ram54288	0:a7a43371b306	1446	*/
ram54288	0:a7a43371b306	1447	static void rf_ack_wait_timer_stop(void)
ram54288	0:a7a43371b306	1448	{
ram54288	0:a7a43371b306	1449	rf_if_ack_wait_timer_stop();
ram54288	0:a7a43371b306	1450	}
ram54288	0:a7a43371b306	1451
ram54288	0:a7a43371b306	1452	/*
ram54288	0:a7a43371b306	1453	* \brief Function writes various RF settings in startup.
ram54288	0:a7a43371b306	1454	*
ram54288	0:a7a43371b306	1455	* \param none
ram54288	0:a7a43371b306	1456	*
ram54288	0:a7a43371b306	1457	* \return none
ram54288	0:a7a43371b306	1458	*/
ram54288	0:a7a43371b306	1459	static void rf_write_settings(void)
ram54288	0:a7a43371b306	1460	{
ram54288	0:a7a43371b306	1461	rf_if_lock();
ram54288	0:a7a43371b306	1462	rf_if_write_rf_settings();
ram54288	0:a7a43371b306	1463	/Set output power/
ram54288	0:a7a43371b306	1464	rf_if_write_set_tx_power_register(radio_tx_power);
ram54288	0:a7a43371b306	1465	/Initialise Antenna Diversity/
ram54288	0:a7a43371b306	1466	if(rf_use_antenna_diversity)
ram54288	0:a7a43371b306	1467	rf_if_write_antenna_diversity_settings();
ram54288	0:a7a43371b306	1468	rf_if_unlock();
ram54288	0:a7a43371b306	1469	}
ram54288	0:a7a43371b306	1470
ram54288	0:a7a43371b306	1471	/*
ram54288	0:a7a43371b306	1472	* \brief Function writes 16-bit address in RF address filter.
ram54288	0:a7a43371b306	1473	*
ram54288	0:a7a43371b306	1474	* \param short_address Given short address
ram54288	0:a7a43371b306	1475	*
ram54288	0:a7a43371b306	1476	* \return none
ram54288	0:a7a43371b306	1477	*/
ram54288	0:a7a43371b306	1478	static void rf_set_short_adr(uint8_t * short_address)
ram54288	0:a7a43371b306	1479	{
ram54288	0:a7a43371b306	1480	rf_if_lock();
ram54288	0:a7a43371b306	1481	/Wake up RF if sleeping/
ram54288	0:a7a43371b306	1482	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1483	{
ram54288	0:a7a43371b306	1484	rf_if_disable_slptr();
ram54288	0:a7a43371b306	1485	rf_poll_trx_state_change(TRX_OFF);
ram54288	0:a7a43371b306	1486	}
ram54288	0:a7a43371b306	1487	/Write address filter registers/
ram54288	0:a7a43371b306	1488	rf_if_write_short_addr_registers(short_address);
ram54288	0:a7a43371b306	1489	/RF back to sleep/
ram54288	0:a7a43371b306	1490	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1491	{
ram54288	0:a7a43371b306	1492	rf_if_enable_slptr();
ram54288	0:a7a43371b306	1493	}
ram54288	0:a7a43371b306	1494	rf_if_unlock();
ram54288	0:a7a43371b306	1495	}
ram54288	0:a7a43371b306	1496
ram54288	0:a7a43371b306	1497	/*
ram54288	0:a7a43371b306	1498	* \brief Function writes PAN Id in RF PAN Id filter.
ram54288	0:a7a43371b306	1499	*
ram54288	0:a7a43371b306	1500	* \param pan_id Given PAN Id
ram54288	0:a7a43371b306	1501	*
ram54288	0:a7a43371b306	1502	* \return none
ram54288	0:a7a43371b306	1503	*/
ram54288	0:a7a43371b306	1504	static void rf_set_pan_id(uint8_t *pan_id)
ram54288	0:a7a43371b306	1505	{
ram54288	0:a7a43371b306	1506	rf_if_lock();
ram54288	0:a7a43371b306	1507	/Wake up RF if sleeping/
ram54288	0:a7a43371b306	1508	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1509	{
ram54288	0:a7a43371b306	1510	rf_if_disable_slptr();
ram54288	0:a7a43371b306	1511	rf_poll_trx_state_change(TRX_OFF);
ram54288	0:a7a43371b306	1512	}
ram54288	0:a7a43371b306	1513	/Write address filter registers/
ram54288	0:a7a43371b306	1514	rf_if_write_pan_id_registers(pan_id);
ram54288	0:a7a43371b306	1515	/RF back to sleep/
ram54288	0:a7a43371b306	1516	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1517	{
ram54288	0:a7a43371b306	1518	rf_if_enable_slptr();
ram54288	0:a7a43371b306	1519	}
ram54288	0:a7a43371b306	1520	rf_if_unlock();
ram54288	0:a7a43371b306	1521	}
ram54288	0:a7a43371b306	1522
ram54288	0:a7a43371b306	1523	/*
ram54288	0:a7a43371b306	1524	* \brief Function writes 64-bit address in RF address filter.
ram54288	0:a7a43371b306	1525	*
ram54288	0:a7a43371b306	1526	* \param address Given 64-bit address
ram54288	0:a7a43371b306	1527	*
ram54288	0:a7a43371b306	1528	* \return none
ram54288	0:a7a43371b306	1529	*/
ram54288	0:a7a43371b306	1530	static void rf_set_address(uint8_t *address)
ram54288	0:a7a43371b306	1531	{
ram54288	0:a7a43371b306	1532	rf_if_lock();
ram54288	0:a7a43371b306	1533	/Wake up RF if sleeping/
ram54288	0:a7a43371b306	1534	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1535	{
ram54288	0:a7a43371b306	1536	rf_if_disable_slptr();
ram54288	0:a7a43371b306	1537	rf_poll_trx_state_change(TRX_OFF);
ram54288	0:a7a43371b306	1538	}
ram54288	0:a7a43371b306	1539	/Write address filter registers/
ram54288	0:a7a43371b306	1540	rf_if_write_ieee_addr_registers(address);
ram54288	0:a7a43371b306	1541	/RF back to sleep/
ram54288	0:a7a43371b306	1542	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1543	{
ram54288	0:a7a43371b306	1544	rf_if_enable_slptr();
ram54288	0:a7a43371b306	1545	}
ram54288	0:a7a43371b306	1546	rf_if_unlock();
ram54288	0:a7a43371b306	1547	}
ram54288	0:a7a43371b306	1548
ram54288	0:a7a43371b306	1549	/*
ram54288	0:a7a43371b306	1550	* \brief Function sets the RF channel.
ram54288	0:a7a43371b306	1551	*
ram54288	0:a7a43371b306	1552	* \param ch New channel
ram54288	0:a7a43371b306	1553	*
ram54288	0:a7a43371b306	1554	* \return none
ram54288	0:a7a43371b306	1555	*/
ram54288	0:a7a43371b306	1556	static void rf_channel_set(uint8_t ch)
ram54288	0:a7a43371b306	1557	{
ram54288	0:a7a43371b306	1558	rf_if_lock();
ram54288	0:a7a43371b306	1559	rf_phy_channel = ch;
ram54288	0:a7a43371b306	1560	if(ch < 0x1f)
ram54288	0:a7a43371b306	1561	rf_if_set_channel_register(ch);
ram54288	0:a7a43371b306	1562	rf_if_unlock();
ram54288	0:a7a43371b306	1563	}
ram54288	0:a7a43371b306	1564
ram54288	0:a7a43371b306	1565
ram54288	0:a7a43371b306	1566	/*
ram54288	0:a7a43371b306	1567	* \brief Function initialises the radio driver and resets the radio.
ram54288	0:a7a43371b306	1568	*
ram54288	0:a7a43371b306	1569	* \param none
ram54288	0:a7a43371b306	1570	*
ram54288	0:a7a43371b306	1571	* \return none
ram54288	0:a7a43371b306	1572	*/
ram54288	0:a7a43371b306	1573	static void rf_init(void)
ram54288	0:a7a43371b306	1574	{
ram54288	0:a7a43371b306	1575	/Reset RF module/
ram54288	0:a7a43371b306	1576	rf_if_reset_radio();
ram54288	0:a7a43371b306	1577
ram54288	0:a7a43371b306	1578	rf_if_lock();
ram54288	0:a7a43371b306	1579
ram54288	0:a7a43371b306	1580	/Write RF settings/
ram54288	0:a7a43371b306	1581	rf_write_settings();
ram54288	0:a7a43371b306	1582	/Initialise PHY mode/
ram54288	0:a7a43371b306	1583	rf_init_phy_mode();
ram54288	0:a7a43371b306	1584	/Clear RF flags/
ram54288	0:a7a43371b306	1585	rf_flags_reset();
ram54288	0:a7a43371b306	1586	/Set RF in TRX OFF state/
ram54288	0:a7a43371b306	1587	rf_if_change_trx_state(TRX_OFF);
ram54288	0:a7a43371b306	1588	/Set RF in PLL_ON state/
ram54288	0:a7a43371b306	1589	rf_if_change_trx_state(PLL_ON);
ram54288	0:a7a43371b306	1590	/Start receiver/
ram54288	0:a7a43371b306	1591	rf_receive();
ram54288	0:a7a43371b306	1592	/Read randomness, and add to seed/
ram54288	0:a7a43371b306	1593	randLIB_add_seed(rf_if_read_rnd());
ram54288	0:a7a43371b306	1594	/Start RF calibration timer/
ram54288	0:a7a43371b306	1595	rf_calibration_timer_start(RF_CALIBRATION_INTERVAL);
ram54288	0:a7a43371b306	1596
ram54288	0:a7a43371b306	1597	rf_if_unlock();
ram54288	0:a7a43371b306	1598	}
ram54288	0:a7a43371b306	1599
ram54288	0:a7a43371b306	1600	/**
ram54288	0:a7a43371b306	1601	* \brief Function gets called when MAC is setting radio off.
ram54288	0:a7a43371b306	1602	*
ram54288	0:a7a43371b306	1603	* \param none
ram54288	0:a7a43371b306	1604	*
ram54288	0:a7a43371b306	1605	* \return none
ram54288	0:a7a43371b306	1606	*/
ram54288	0:a7a43371b306	1607	static void rf_off(void)
ram54288	0:a7a43371b306	1608	{
ram54288	0:a7a43371b306	1609	if(rf_flags_check(RFF_ON))
ram54288	0:a7a43371b306	1610	{
ram54288	0:a7a43371b306	1611	rf_if_lock();
ram54288	0:a7a43371b306	1612	rf_cca_abort();
ram54288	0:a7a43371b306	1613	uint16_t while_counter = 0;
ram54288	0:a7a43371b306	1614	/Wait while receiving/
ram54288	0:a7a43371b306	1615	while(rf_if_read_trx_state() == BUSY_RX_AACK)
ram54288	0:a7a43371b306	1616	{
ram54288	0:a7a43371b306	1617	while_counter++;
ram54288	0:a7a43371b306	1618	if(while_counter == 0xffff)
ram54288	0:a7a43371b306	1619	break;
ram54288	0:a7a43371b306	1620	}
ram54288	0:a7a43371b306	1621	/RF state change: RX_AACK_ON->PLL_ON->TRX_OFF->SLEEP/
ram54288	0:a7a43371b306	1622	if(rf_if_read_trx_state() == RX_AACK_ON)
ram54288	0:a7a43371b306	1623	{
ram54288	0:a7a43371b306	1624	rf_if_change_trx_state(PLL_ON);
ram54288	0:a7a43371b306	1625	}
ram54288	0:a7a43371b306	1626	rf_if_change_trx_state(TRX_OFF);
ram54288	0:a7a43371b306	1627	rf_if_enable_slptr();
ram54288	0:a7a43371b306	1628
ram54288	0:a7a43371b306	1629	/Disable Antenna Diversity/
ram54288	0:a7a43371b306	1630	if(rf_use_antenna_diversity)
ram54288	0:a7a43371b306	1631	rf_if_disable_ant_div();
ram54288	0:a7a43371b306	1632	rf_if_unlock();
ram54288	0:a7a43371b306	1633	}
ram54288	0:a7a43371b306	1634
ram54288	0:a7a43371b306	1635	/Clears all flags/
ram54288	0:a7a43371b306	1636	rf_flags_reset();
ram54288	0:a7a43371b306	1637	}
ram54288	0:a7a43371b306	1638
ram54288	0:a7a43371b306	1639	/*
ram54288	0:a7a43371b306	1640	* \brief Function polls the RF state until it has changed to desired state.
ram54288	0:a7a43371b306	1641	*
ram54288	0:a7a43371b306	1642	* \param trx_state RF state
ram54288	0:a7a43371b306	1643	*
ram54288	0:a7a43371b306	1644	* \return none
ram54288	0:a7a43371b306	1645	*/
ram54288	0:a7a43371b306	1646	static void rf_poll_trx_state_change(rf_trx_states_t trx_state)
ram54288	0:a7a43371b306	1647	{
ram54288	0:a7a43371b306	1648	uint16_t while_counter = 0;
ram54288	0:a7a43371b306	1649	// XXX lock apparently not needed
ram54288	0:a7a43371b306	1650	rf_if_lock();
ram54288	0:a7a43371b306	1651
ram54288	0:a7a43371b306	1652	if(trx_state != RF_TX_START)
ram54288	0:a7a43371b306	1653	{
ram54288	0:a7a43371b306	1654	if(trx_state == FORCE_PLL_ON)
ram54288	0:a7a43371b306	1655	trx_state = PLL_ON;
ram54288	0:a7a43371b306	1656	else if(trx_state == FORCE_TRX_OFF)
ram54288	0:a7a43371b306	1657	trx_state = TRX_OFF;
ram54288	0:a7a43371b306	1658
ram54288	0:a7a43371b306	1659	while(rf_if_read_trx_state() != trx_state)
ram54288	0:a7a43371b306	1660	{
ram54288	0:a7a43371b306	1661	while_counter++;
ram54288	0:a7a43371b306	1662	if(while_counter == 0x1ff)
ram54288	0:a7a43371b306	1663	break;
ram54288	0:a7a43371b306	1664	}
ram54288	0:a7a43371b306	1665	}
ram54288	0:a7a43371b306	1666	rf_if_unlock();
ram54288	0:a7a43371b306	1667	}
ram54288	0:a7a43371b306	1668
ram54288	0:a7a43371b306	1669	/*
ram54288	0:a7a43371b306	1670	* \brief Function starts the CCA process before starting data transmission and copies the data to RF TX FIFO.
ram54288	0:a7a43371b306	1671	*
ram54288	0:a7a43371b306	1672	* \param data_ptr Pointer to TX data (excluding FCS)
ram54288	0:a7a43371b306	1673	* \param data_length Length of the TX data (excluding FCS)
ram54288	0:a7a43371b306	1674	* \param tx_handle Handle to transmission
ram54288	0:a7a43371b306	1675	* \return 0 Success
ram54288	0:a7a43371b306	1676	* \return -1 Busy
ram54288	0:a7a43371b306	1677	*/
ram54288	0:a7a43371b306	1678	static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol )
ram54288	0:a7a43371b306	1679	{
ram54288	0:a7a43371b306	1680	(void)data_protocol;
ram54288	0:a7a43371b306	1681	rf_if_lock();
ram54288	0:a7a43371b306	1682	/Check if transmitter is busy/
ram54288	0:a7a43371b306	1683	if(rf_if_read_trx_state() == BUSY_RX_AACK \|\| data_length > RF_MTU - 2)
ram54288	0:a7a43371b306	1684	{
ram54288	0:a7a43371b306	1685	rf_if_unlock();
ram54288	0:a7a43371b306	1686	/Return busy/
ram54288	0:a7a43371b306	1687	return -1;
ram54288	0:a7a43371b306	1688	}
ram54288	0:a7a43371b306	1689	else
ram54288	0:a7a43371b306	1690	{
ram54288	0:a7a43371b306	1691	expected_ack_sequence = -1;
ram54288	0:a7a43371b306	1692
ram54288	0:a7a43371b306	1693	/Nanostack has a static TX buffer, which will remain valid until we/
ram54288	0:a7a43371b306	1694	/generate a callback, so we just note the pointer for reading later./
ram54288	0:a7a43371b306	1695	rf_tx_data = data_ptr;
ram54288	0:a7a43371b306	1696	rf_tx_length = data_length;
ram54288	0:a7a43371b306	1697	/Start CCA timeout/
ram54288	0:a7a43371b306	1698	rf_cca_timer_start(RF_CCA_BASE_BACKOFF + randLIB_get_random_in_range(0, RF_CCA_RANDOM_BACKOFF));
ram54288	0:a7a43371b306	1699	/Store TX handle/
ram54288	0:a7a43371b306	1700	mac_tx_handle = tx_handle;
ram54288	0:a7a43371b306	1701	rf_if_unlock();
ram54288	0:a7a43371b306	1702	}
ram54288	0:a7a43371b306	1703
ram54288	0:a7a43371b306	1704	/Return success/
ram54288	0:a7a43371b306	1705	return 0;
ram54288	0:a7a43371b306	1706	}
ram54288	0:a7a43371b306	1707
ram54288	0:a7a43371b306	1708	/*
ram54288	0:a7a43371b306	1709	* \brief Function aborts CCA process.
ram54288	0:a7a43371b306	1710	*
ram54288	0:a7a43371b306	1711	* \param none
ram54288	0:a7a43371b306	1712	*
ram54288	0:a7a43371b306	1713	* \return none
ram54288	0:a7a43371b306	1714	*/
ram54288	0:a7a43371b306	1715	static void rf_cca_abort(void)
ram54288	0:a7a43371b306	1716	{
ram54288	0:a7a43371b306	1717	rf_cca_timer_stop();
ram54288	0:a7a43371b306	1718	rf_flags_clear(RFF_CCA);
ram54288	0:a7a43371b306	1719	rf_disable_static_frame_buffer_protection();
ram54288	0:a7a43371b306	1720	}
ram54288	0:a7a43371b306	1721
ram54288	0:a7a43371b306	1722	/*
ram54288	0:a7a43371b306	1723	* \brief Function starts the transmission of the frame.
ram54288	0:a7a43371b306	1724	*
ram54288	0:a7a43371b306	1725	* \param none
ram54288	0:a7a43371b306	1726	*
ram54288	0:a7a43371b306	1727	* \return none
ram54288	0:a7a43371b306	1728	*/
ram54288	0:a7a43371b306	1729	static void rf_start_tx(void)
ram54288	0:a7a43371b306	1730	{
ram54288	0:a7a43371b306	1731	/Only start transmitting from RX state/
ram54288	0:a7a43371b306	1732	uint8_t trx_state = rf_if_read_trx_state();
ram54288	0:a7a43371b306	1733	if(trx_state != RX_AACK_ON)
ram54288	0:a7a43371b306	1734	{
ram54288	0:a7a43371b306	1735	rf_disable_static_frame_buffer_protection();
ram54288	0:a7a43371b306	1736	if(device_driver.phy_tx_done_cb){
ram54288	0:a7a43371b306	1737	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
ram54288	0:a7a43371b306	1738	}
ram54288	0:a7a43371b306	1739	}
ram54288	0:a7a43371b306	1740	else
ram54288	0:a7a43371b306	1741	{
ram54288	0:a7a43371b306	1742	/RF state change: ->PLL_ON->RF_TX_START/
ram54288	0:a7a43371b306	1743	rf_if_change_trx_state(FORCE_PLL_ON);
ram54288	0:a7a43371b306	1744	rf_flags_clear(RFF_RX);
ram54288	0:a7a43371b306	1745	/Now we're out of receive mode, can release protection/
ram54288	0:a7a43371b306	1746	rf_disable_static_frame_buffer_protection();
ram54288	0:a7a43371b306	1747	rf_if_enable_tx_end_interrupt();
ram54288	0:a7a43371b306	1748	rf_flags_set(RFF_TX);
ram54288	0:a7a43371b306	1749	rf_if_change_trx_state(RF_TX_START);
ram54288	0:a7a43371b306	1750	}
ram54288	0:a7a43371b306	1751	}
ram54288	0:a7a43371b306	1752
ram54288	0:a7a43371b306	1753	/*
ram54288	0:a7a43371b306	1754	* \brief Function sets the RF in RX state.
ram54288	0:a7a43371b306	1755	*
ram54288	0:a7a43371b306	1756	* \param none
ram54288	0:a7a43371b306	1757	*
ram54288	0:a7a43371b306	1758	* \return none
ram54288	0:a7a43371b306	1759	*/
ram54288	0:a7a43371b306	1760	static void rf_receive(void)
ram54288	0:a7a43371b306	1761	{
ram54288	0:a7a43371b306	1762	uint16_t while_counter = 0;
ram54288	0:a7a43371b306	1763	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1764	{
ram54288	0:a7a43371b306	1765	rf_on();
ram54288	0:a7a43371b306	1766	}
ram54288	0:a7a43371b306	1767	/If not yet in RX state set it/
ram54288	0:a7a43371b306	1768	if(rf_flags_check(RFF_RX) == 0)
ram54288	0:a7a43371b306	1769	{
ram54288	0:a7a43371b306	1770	rf_if_lock();
ram54288	0:a7a43371b306	1771	/Wait while receiving data/
ram54288	0:a7a43371b306	1772	while(rf_if_read_trx_state() == BUSY_RX_AACK)
ram54288	0:a7a43371b306	1773	{
ram54288	0:a7a43371b306	1774	while_counter++;
ram54288	0:a7a43371b306	1775	if(while_counter == 0xffff)
ram54288	0:a7a43371b306	1776	{
ram54288	0:a7a43371b306	1777	break;
ram54288	0:a7a43371b306	1778	}
ram54288	0:a7a43371b306	1779	}
ram54288	0:a7a43371b306	1780
ram54288	0:a7a43371b306	1781	rf_if_change_trx_state(PLL_ON);
ram54288	0:a7a43371b306	1782
ram54288	0:a7a43371b306	1783	if((rf_mode == RF_MODE_SNIFFER) \|\| (rf_mode == RF_MODE_ED))
ram54288	0:a7a43371b306	1784	{
ram54288	0:a7a43371b306	1785	rf_if_change_trx_state(RX_ON);
ram54288	0:a7a43371b306	1786	}
ram54288	0:a7a43371b306	1787	else
ram54288	0:a7a43371b306	1788	{
ram54288	0:a7a43371b306	1789	/ACK is always received in promiscuous mode to bypass address filters/
ram54288	0:a7a43371b306	1790	if(rf_rx_mode)
ram54288	0:a7a43371b306	1791	{
ram54288	0:a7a43371b306	1792	rf_rx_mode = 0;
ram54288	0:a7a43371b306	1793	rf_if_enable_promiscuous_mode();
ram54288	0:a7a43371b306	1794	}
ram54288	0:a7a43371b306	1795	else
ram54288	0:a7a43371b306	1796	{
ram54288	0:a7a43371b306	1797	rf_if_disable_promiscuous_mode();
ram54288	0:a7a43371b306	1798	}
ram54288	0:a7a43371b306	1799	rf_if_change_trx_state(RX_AACK_ON);
ram54288	0:a7a43371b306	1800	}
ram54288	0:a7a43371b306	1801	/If calibration timer was unable to calibrate the RF, run calibration now/
ram54288	0:a7a43371b306	1802	if(!rf_tuned)
ram54288	0:a7a43371b306	1803	{
ram54288	0:a7a43371b306	1804	/Start calibration. This can be done in states TRX_OFF, PLL_ON or in any receive state/
ram54288	0:a7a43371b306	1805	rf_if_calibration();
ram54288	0:a7a43371b306	1806	/RF is tuned now/
ram54288	0:a7a43371b306	1807	rf_tuned = 1;
ram54288	0:a7a43371b306	1808	}
ram54288	0:a7a43371b306	1809
ram54288	0:a7a43371b306	1810	rf_channel_set(rf_phy_channel);
ram54288	0:a7a43371b306	1811	rf_flags_set(RFF_RX);
ram54288	0:a7a43371b306	1812	// Don't receive packets when ED mode enabled
ram54288	0:a7a43371b306	1813	if (rf_mode != RF_MODE_ED)
ram54288	0:a7a43371b306	1814	{
ram54288	0:a7a43371b306	1815	rf_if_enable_rx_end_interrupt();
ram54288	0:a7a43371b306	1816	}
ram54288	0:a7a43371b306	1817	rf_if_unlock();
ram54288	0:a7a43371b306	1818	}
ram54288	0:a7a43371b306	1819	}
ram54288	0:a7a43371b306	1820
ram54288	0:a7a43371b306	1821	/*
ram54288	0:a7a43371b306	1822	* \brief Function calibrates the radio.
ram54288	0:a7a43371b306	1823	*
ram54288	0:a7a43371b306	1824	* \param none
ram54288	0:a7a43371b306	1825	*
ram54288	0:a7a43371b306	1826	* \return none
ram54288	0:a7a43371b306	1827	*/
ram54288	0:a7a43371b306	1828	static void rf_calibration_cb(void)
ram54288	0:a7a43371b306	1829	{
ram54288	0:a7a43371b306	1830	/clear tuned flag to start tuning in rf_receive/
ram54288	0:a7a43371b306	1831	rf_tuned = 0;
ram54288	0:a7a43371b306	1832	/If RF is in default receive state, start calibration/
ram54288	0:a7a43371b306	1833	if(rf_if_read_trx_state() == RX_AACK_ON)
ram54288	0:a7a43371b306	1834	{
ram54288	0:a7a43371b306	1835	rf_if_lock();
ram54288	0:a7a43371b306	1836	/Set RF in PLL_ON state/
ram54288	0:a7a43371b306	1837	rf_if_change_trx_state(PLL_ON);
ram54288	0:a7a43371b306	1838	/Set RF in TRX_OFF state to start PLL tuning/
ram54288	0:a7a43371b306	1839	rf_if_change_trx_state(TRX_OFF);
ram54288	0:a7a43371b306	1840	/Set RF in RX_ON state to calibrate/
ram54288	0:a7a43371b306	1841	rf_if_change_trx_state(RX_ON);
ram54288	0:a7a43371b306	1842	/Calibrate FTN/
ram54288	0:a7a43371b306	1843	rf_if_calibration();
ram54288	0:a7a43371b306	1844	/RF is tuned now/
ram54288	0:a7a43371b306	1845	rf_tuned = 1;
ram54288	0:a7a43371b306	1846	/Back to default receive state/
ram54288	0:a7a43371b306	1847	rf_flags_clear(RFF_RX);
ram54288	0:a7a43371b306	1848	rf_receive();
ram54288	0:a7a43371b306	1849	rf_if_unlock();
ram54288	0:a7a43371b306	1850	}
ram54288	0:a7a43371b306	1851	}
ram54288	0:a7a43371b306	1852
ram54288	0:a7a43371b306	1853	/*
ram54288	0:a7a43371b306	1854	* \brief Function sets RF_ON flag when radio is powered.
ram54288	0:a7a43371b306	1855	*
ram54288	0:a7a43371b306	1856	* \param none
ram54288	0:a7a43371b306	1857	*
ram54288	0:a7a43371b306	1858	* \return none
ram54288	0:a7a43371b306	1859	*/
ram54288	0:a7a43371b306	1860	static void rf_on(void)
ram54288	0:a7a43371b306	1861	{
ram54288	0:a7a43371b306	1862	/Set RFF_ON flag/
ram54288	0:a7a43371b306	1863	if(rf_flags_check(RFF_ON) == 0)
ram54288	0:a7a43371b306	1864	{
ram54288	0:a7a43371b306	1865	rf_if_lock();
ram54288	0:a7a43371b306	1866	rf_flags_set(RFF_ON);
ram54288	0:a7a43371b306	1867	/Enable Antenna diversity/
ram54288	0:a7a43371b306	1868	if(rf_use_antenna_diversity)
ram54288	0:a7a43371b306	1869	/Set ANT_EXT_SW_EN to enable controlling of antenna diversity/
ram54288	0:a7a43371b306	1870	rf_if_enable_ant_div();
ram54288	0:a7a43371b306	1871
ram54288	0:a7a43371b306	1872	/Wake up from sleep state/
ram54288	0:a7a43371b306	1873	rf_if_disable_slptr();
ram54288	0:a7a43371b306	1874	rf_poll_trx_state_change(TRX_OFF);
ram54288	0:a7a43371b306	1875	rf_if_unlock();
ram54288	0:a7a43371b306	1876	}
ram54288	0:a7a43371b306	1877	}
ram54288	0:a7a43371b306	1878
ram54288	0:a7a43371b306	1879	/*
ram54288	0:a7a43371b306	1880	* \brief Function handles the received ACK frame.
ram54288	0:a7a43371b306	1881	*
ram54288	0:a7a43371b306	1882	* \param seq_number Sequence number of received ACK
ram54288	0:a7a43371b306	1883	* \param data_pending Pending bit state in received ACK
ram54288	0:a7a43371b306	1884	*
ram54288	0:a7a43371b306	1885	* \return none
ram54288	0:a7a43371b306	1886	*/
ram54288	0:a7a43371b306	1887	static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending)
ram54288	0:a7a43371b306	1888	{
ram54288	0:a7a43371b306	1889	phy_link_tx_status_e phy_status;
ram54288	0:a7a43371b306	1890	rf_if_lock();
ram54288	0:a7a43371b306	1891	/Received ACK sequence must be equal with transmitted packet sequence/
ram54288	0:a7a43371b306	1892	if(expected_ack_sequence == seq_number)
ram54288	0:a7a43371b306	1893	{
ram54288	0:a7a43371b306	1894	rf_ack_wait_timer_stop();
ram54288	0:a7a43371b306	1895	expected_ack_sequence = -1;
ram54288	0:a7a43371b306	1896	/When data pending bit in ACK frame is set, inform NET library/
ram54288	0:a7a43371b306	1897	if(data_pending)
ram54288	0:a7a43371b306	1898	phy_status = PHY_LINK_TX_DONE_PENDING;
ram54288	0:a7a43371b306	1899	else
ram54288	0:a7a43371b306	1900	phy_status = PHY_LINK_TX_DONE;
ram54288	0:a7a43371b306	1901	/Call PHY TX Done API/
ram54288	0:a7a43371b306	1902	if(device_driver.phy_tx_done_cb){
ram54288	0:a7a43371b306	1903	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle,phy_status, 0, 0);
ram54288	0:a7a43371b306	1904	}
ram54288	0:a7a43371b306	1905	}
ram54288	0:a7a43371b306	1906	rf_if_unlock();
ram54288	0:a7a43371b306	1907	}
ram54288	0:a7a43371b306	1908
ram54288	0:a7a43371b306	1909	/*
ram54288	0:a7a43371b306	1910	* \brief Function is a call back for RX end interrupt.
ram54288	0:a7a43371b306	1911	*
ram54288	0:a7a43371b306	1912	* \param none
ram54288	0:a7a43371b306	1913	*
ram54288	0:a7a43371b306	1914	* \return none
ram54288	0:a7a43371b306	1915	*/
ram54288	0:a7a43371b306	1916	static void rf_handle_rx_end(void)
ram54288	0:a7a43371b306	1917	{
ram54288	0:a7a43371b306	1918	/Start receiver/
ram54288	0:a7a43371b306	1919	rf_flags_clear(RFF_RX);
ram54288	0:a7a43371b306	1920	rf_receive();
ram54288	0:a7a43371b306	1921
ram54288	0:a7a43371b306	1922	/Frame received interrupt/
ram54288	0:a7a43371b306	1923	if(!rf_flags_check(RFF_RX)) {
ram54288	0:a7a43371b306	1924	return;
ram54288	0:a7a43371b306	1925	}
ram54288	0:a7a43371b306	1926
ram54288	0:a7a43371b306	1927	static uint8_t rf_buffer[RF_MTU];
ram54288	0:a7a43371b306	1928	uint8_t rf_lqi, rf_ed;
ram54288	0:a7a43371b306	1929	int8_t rf_rssi;
ram54288	0:a7a43371b306	1930	bool crc_good;
ram54288	0:a7a43371b306	1931
ram54288	0:a7a43371b306	1932	/Read received packet/
ram54288	0:a7a43371b306	1933	uint8_t len = rf_if_read_packet(rf_buffer, &rf_lqi, &rf_ed, &crc_good);
ram54288	0:a7a43371b306	1934	if (len < 5 \|\| !crc_good) {
ram54288	0:a7a43371b306	1935	return;
ram54288	0:a7a43371b306	1936	}
ram54288	0:a7a43371b306	1937
ram54288	0:a7a43371b306	1938	/* Convert raw ED to dBm value (chip-dependent) */
ram54288	0:a7a43371b306	1939	rf_rssi = rf_if_scale_rssi(rf_ed);
ram54288	0:a7a43371b306	1940
ram54288	0:a7a43371b306	1941	/* Create a virtual LQI using received RSSI, forgetting actual HW LQI */
ram54288	0:a7a43371b306	1942	/* (should be done through PHY_EXTENSION_CONVERT_SIGNAL_INFO) */
ram54288	0:a7a43371b306	1943	rf_lqi = rf_scale_lqi(rf_rssi);
ram54288	0:a7a43371b306	1944
ram54288	0:a7a43371b306	1945	/Handle received ACK/
ram54288	0:a7a43371b306	1946	if((rf_buffer[0] & 0x07) == 0x02 && rf_mode != RF_MODE_SNIFFER)
ram54288	0:a7a43371b306	1947	{
ram54288	0:a7a43371b306	1948	/Check if data is pending/
ram54288	0:a7a43371b306	1949	bool pending = (rf_buffer[0] & 0x10);
ram54288	0:a7a43371b306	1950
ram54288	0:a7a43371b306	1951	/Send sequence number in ACK handler/
ram54288	0:a7a43371b306	1952	rf_handle_ack(rf_buffer[2], pending);
ram54288	0:a7a43371b306	1953	} else {
ram54288	0:a7a43371b306	1954	if( device_driver.phy_rx_cb ){
ram54288	0:a7a43371b306	1955	device_driver.phy_rx_cb(rf_buffer, len - 2, rf_lqi, rf_rssi, rf_radio_driver_id);
ram54288	0:a7a43371b306	1956	}
ram54288	0:a7a43371b306	1957	}
ram54288	0:a7a43371b306	1958	}
ram54288	0:a7a43371b306	1959
ram54288	0:a7a43371b306	1960	/*
ram54288	0:a7a43371b306	1961	* \brief Function is called when MAC is shutting down the radio.
ram54288	0:a7a43371b306	1962	*
ram54288	0:a7a43371b306	1963	* \param none
ram54288	0:a7a43371b306	1964	*
ram54288	0:a7a43371b306	1965	* \return none
ram54288	0:a7a43371b306	1966	*/
ram54288	0:a7a43371b306	1967	static void rf_shutdown(void)
ram54288	0:a7a43371b306	1968	{
ram54288	0:a7a43371b306	1969	/Call RF OFF/
ram54288	0:a7a43371b306	1970	rf_off();
ram54288	0:a7a43371b306	1971	}
ram54288	0:a7a43371b306	1972
ram54288	0:a7a43371b306	1973	/*
ram54288	0:a7a43371b306	1974	* \brief Function is a call back for TX end interrupt.
ram54288	0:a7a43371b306	1975	*
ram54288	0:a7a43371b306	1976	* \param none
ram54288	0:a7a43371b306	1977	*
ram54288	0:a7a43371b306	1978	* \return none
ram54288	0:a7a43371b306	1979	*/
ram54288	0:a7a43371b306	1980	static void rf_handle_tx_end(void)
ram54288	0:a7a43371b306	1981	{
ram54288	0:a7a43371b306	1982	rf_rx_mode = 0;
ram54288	0:a7a43371b306	1983	/If ACK is needed for this transmission/
ram54288	0:a7a43371b306	1984	if((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX))
ram54288	0:a7a43371b306	1985	{
ram54288	0:a7a43371b306	1986	expected_ack_sequence = rf_tx_data[2];
ram54288	0:a7a43371b306	1987	rf_ack_wait_timer_start(rf_ack_wait_duration);
ram54288	0:a7a43371b306	1988	rf_rx_mode = 1;
ram54288	0:a7a43371b306	1989	}
ram54288	0:a7a43371b306	1990	rf_flags_clear(RFF_RX);
ram54288	0:a7a43371b306	1991	/Start receiver/
ram54288	0:a7a43371b306	1992	rf_receive();
ram54288	0:a7a43371b306	1993
ram54288	0:a7a43371b306	1994	/Call PHY TX Done API/
ram54288	0:a7a43371b306	1995	if(device_driver.phy_tx_done_cb){
ram54288	0:a7a43371b306	1996	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0);
ram54288	0:a7a43371b306	1997	}
ram54288	0:a7a43371b306	1998	}
ram54288	0:a7a43371b306	1999
ram54288	0:a7a43371b306	2000	/*
ram54288	0:a7a43371b306	2001	* \brief Function is a call back for CCA ED done interrupt.
ram54288	0:a7a43371b306	2002	*
ram54288	0:a7a43371b306	2003	* \param none
ram54288	0:a7a43371b306	2004	*
ram54288	0:a7a43371b306	2005	* \return none
ram54288	0:a7a43371b306	2006	*/
ram54288	0:a7a43371b306	2007	static void rf_handle_cca_ed_done(void)
ram54288	0:a7a43371b306	2008	{
ram54288	0:a7a43371b306	2009	if (!rf_flags_check(RFF_CCA)) {
ram54288	0:a7a43371b306	2010	return;
ram54288	0:a7a43371b306	2011	}
ram54288	0:a7a43371b306	2012	rf_flags_clear(RFF_CCA);
ram54288	0:a7a43371b306	2013	/Check the result of CCA process/
ram54288	0:a7a43371b306	2014	if(rf_if_check_cca())
ram54288	0:a7a43371b306	2015	{
ram54288	0:a7a43371b306	2016	rf_start_tx();
ram54288	0:a7a43371b306	2017	}
ram54288	0:a7a43371b306	2018	else
ram54288	0:a7a43371b306	2019	{
ram54288	0:a7a43371b306	2020	/Re-enable reception/
ram54288	0:a7a43371b306	2021	rf_disable_static_frame_buffer_protection();
ram54288	0:a7a43371b306	2022	/Send CCA fail notification/
ram54288	0:a7a43371b306	2023	if(device_driver.phy_tx_done_cb){
ram54288	0:a7a43371b306	2024	device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0);
ram54288	0:a7a43371b306	2025	}
ram54288	0:a7a43371b306	2026	}
ram54288	0:a7a43371b306	2027	}
ram54288	0:a7a43371b306	2028
ram54288	0:a7a43371b306	2029	/*
ram54288	0:a7a43371b306	2030	* \brief Function returns the TX power variable.
ram54288	0:a7a43371b306	2031	*
ram54288	0:a7a43371b306	2032	* \param none
ram54288	0:a7a43371b306	2033	*
ram54288	0:a7a43371b306	2034	* \return radio_tx_power TX power variable
ram54288	0:a7a43371b306	2035	*/
ram54288	0:a7a43371b306	2036	MBED_UNUSED static uint8_t rf_tx_power_get(void)
ram54288	0:a7a43371b306	2037	{
ram54288	0:a7a43371b306	2038	return radio_tx_power;
ram54288	0:a7a43371b306	2039	}
ram54288	0:a7a43371b306	2040
ram54288	0:a7a43371b306	2041	/*
ram54288	0:a7a43371b306	2042	* \brief Function enables the usage of Antenna diversity.
ram54288	0:a7a43371b306	2043	*
ram54288	0:a7a43371b306	2044	* \param none
ram54288	0:a7a43371b306	2045	*
ram54288	0:a7a43371b306	2046	* \return 0 Success
ram54288	0:a7a43371b306	2047	*/
ram54288	0:a7a43371b306	2048	MBED_UNUSED static int8_t rf_enable_antenna_diversity(void)
ram54288	0:a7a43371b306	2049	{
ram54288	0:a7a43371b306	2050	int8_t ret_val = 0;
ram54288	0:a7a43371b306	2051	rf_use_antenna_diversity = 1;
ram54288	0:a7a43371b306	2052	return ret_val;
ram54288	0:a7a43371b306	2053	}
ram54288	0:a7a43371b306	2054
ram54288	0:a7a43371b306	2055	/*
ram54288	0:a7a43371b306	2056	* \brief Function gives the control of RF states to MAC.
ram54288	0:a7a43371b306	2057	*
ram54288	0:a7a43371b306	2058	* \param new_state RF state
ram54288	0:a7a43371b306	2059	* \param rf_channel RF channel
ram54288	0:a7a43371b306	2060	*
ram54288	0:a7a43371b306	2061	* \return 0 Success
ram54288	0:a7a43371b306	2062	*/
ram54288	0:a7a43371b306	2063	static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel)
ram54288	0:a7a43371b306	2064	{
ram54288	0:a7a43371b306	2065	int8_t ret_val = 0;
ram54288	0:a7a43371b306	2066	switch (new_state)
ram54288	0:a7a43371b306	2067	{
ram54288	0:a7a43371b306	2068	/Reset PHY driver and set to idle/
ram54288	0:a7a43371b306	2069	case PHY_INTERFACE_RESET:
ram54288	0:a7a43371b306	2070	break;
ram54288	0:a7a43371b306	2071	/Disable PHY Interface driver/
ram54288	0:a7a43371b306	2072	case PHY_INTERFACE_DOWN:
ram54288	0:a7a43371b306	2073	rf_shutdown();
ram54288	0:a7a43371b306	2074	break;
ram54288	0:a7a43371b306	2075	/Enable PHY Interface driver/
ram54288	0:a7a43371b306	2076	case PHY_INTERFACE_UP:
ram54288	0:a7a43371b306	2077	rf_mode = RF_MODE_NORMAL;
ram54288	0:a7a43371b306	2078	rf_channel_set(rf_channel);
ram54288	0:a7a43371b306	2079	rf_receive();
ram54288	0:a7a43371b306	2080	rf_if_enable_irq();
ram54288	0:a7a43371b306	2081	break;
ram54288	0:a7a43371b306	2082	/Enable wireless interface ED scan mode/
ram54288	0:a7a43371b306	2083	case PHY_INTERFACE_RX_ENERGY_STATE:
ram54288	0:a7a43371b306	2084	rf_mode = RF_MODE_ED;
ram54288	0:a7a43371b306	2085	rf_channel_set(rf_channel);
ram54288	0:a7a43371b306	2086	rf_receive();
ram54288	0:a7a43371b306	2087	rf_if_disable_irq();
ram54288	0:a7a43371b306	2088	// Read status to clear pending flags.
ram54288	0:a7a43371b306	2089	rf_if_read_register(IRQ_STATUS);
ram54288	0:a7a43371b306	2090	// Must set interrupt mask to be able to read IRQ status. GPIO interrupt is disabled.
ram54288	0:a7a43371b306	2091	rf_if_enable_cca_ed_done_interrupt();
ram54288	0:a7a43371b306	2092	// ED can be initiated by writing arbitrary value to PHY_ED_LEVEL
ram54288	0:a7a43371b306	2093	rf_if_write_register(PHY_ED_LEVEL, 0xff);
ram54288	0:a7a43371b306	2094	break;
ram54288	0:a7a43371b306	2095	case PHY_INTERFACE_SNIFFER_STATE: /*< Enable Sniffer state /
ram54288	0:a7a43371b306	2096	rf_mode = RF_MODE_SNIFFER;
ram54288	0:a7a43371b306	2097	rf_channel_set(rf_channel);
ram54288	0:a7a43371b306	2098	rf_flags_clear(RFF_RX);
ram54288	0:a7a43371b306	2099	rf_receive();
ram54288	0:a7a43371b306	2100	rf_if_enable_irq();
ram54288	0:a7a43371b306	2101	break;
ram54288	0:a7a43371b306	2102	}
ram54288	0:a7a43371b306	2103	return ret_val;
ram54288	0:a7a43371b306	2104	}
ram54288	0:a7a43371b306	2105
ram54288	0:a7a43371b306	2106	/*
ram54288	0:a7a43371b306	2107	* \brief Function controls the ACK pending, channel setting and energy detection.
ram54288	0:a7a43371b306	2108	*
ram54288	0:a7a43371b306	2109	* \param extension_type Type of control
ram54288	0:a7a43371b306	2110	* \param data_ptr Data from NET library
ram54288	0:a7a43371b306	2111	*
ram54288	0:a7a43371b306	2112	* \return 0 Success
ram54288	0:a7a43371b306	2113	*/
ram54288	0:a7a43371b306	2114	static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr)
ram54288	0:a7a43371b306	2115	{
ram54288	0:a7a43371b306	2116	switch (extension_type)
ram54288	0:a7a43371b306	2117	{
ram54288	0:a7a43371b306	2118	/Control MAC pending bit for Indirect data transmission/
ram54288	0:a7a43371b306	2119	case PHY_EXTENSION_CTRL_PENDING_BIT:
ram54288	0:a7a43371b306	2120	if(*data_ptr)
ram54288	0:a7a43371b306	2121	{
ram54288	0:a7a43371b306	2122	rf_if_ack_pending_ctrl(1);
ram54288	0:a7a43371b306	2123	}
ram54288	0:a7a43371b306	2124	else
ram54288	0:a7a43371b306	2125	{
ram54288	0:a7a43371b306	2126	rf_if_ack_pending_ctrl(0);
ram54288	0:a7a43371b306	2127	}
ram54288	0:a7a43371b306	2128	break;
ram54288	0:a7a43371b306	2129	/Return frame pending status/
ram54288	0:a7a43371b306	2130	case PHY_EXTENSION_READ_LAST_ACK_PENDING_STATUS:
ram54288	0:a7a43371b306	2131	*data_ptr = rf_if_last_acked_pending();
ram54288	0:a7a43371b306	2132	break;
ram54288	0:a7a43371b306	2133	/Set channel/
ram54288	0:a7a43371b306	2134	case PHY_EXTENSION_SET_CHANNEL:
ram54288	0:a7a43371b306	2135	break;
ram54288	0:a7a43371b306	2136	/Read energy on the channel/
ram54288	0:a7a43371b306	2137	case PHY_EXTENSION_READ_CHANNEL_ENERGY:
ram54288	0:a7a43371b306	2138	// End of the ED measurement is indicated by CCA_ED_DONE
ram54288	0:a7a43371b306	2139	while (!(rf_if_read_register(IRQ_STATUS) & CCA_ED_DONE));
ram54288	0:a7a43371b306	2140	// RF input power: RSSI base level + 1[db] * PHY_ED_LEVEL
ram54288	0:a7a43371b306	2141	*data_ptr = rf_sensitivity + rf_if_read_register(PHY_ED_LEVEL);
ram54288	0:a7a43371b306	2142	// Read status to clear pending flags.
ram54288	0:a7a43371b306	2143	rf_if_read_register(IRQ_STATUS);
ram54288	0:a7a43371b306	2144	// Next ED measurement is started, next PHY_EXTENSION_READ_CHANNEL_ENERGY call will return the result.
ram54288	0:a7a43371b306	2145	rf_if_write_register(PHY_ED_LEVEL, 0xff);
ram54288	0:a7a43371b306	2146	break;
ram54288	0:a7a43371b306	2147	/Read status of the link/
ram54288	0:a7a43371b306	2148	case PHY_EXTENSION_READ_LINK_STATUS:
ram54288	0:a7a43371b306	2149	break;
ram54288	0:a7a43371b306	2150	default:
ram54288	0:a7a43371b306	2151	break;
ram54288	0:a7a43371b306	2152	}
ram54288	0:a7a43371b306	2153	return 0;
ram54288	0:a7a43371b306	2154	}
ram54288	0:a7a43371b306	2155
ram54288	0:a7a43371b306	2156	/*
ram54288	0:a7a43371b306	2157	* \brief Function sets the addresses to RF address filters.
ram54288	0:a7a43371b306	2158	*
ram54288	0:a7a43371b306	2159	* \param address_type Type of address
ram54288	0:a7a43371b306	2160	* \param address_ptr Pointer to given address
ram54288	0:a7a43371b306	2161	*
ram54288	0:a7a43371b306	2162	* \return 0 Success
ram54288	0:a7a43371b306	2163	*/
ram54288	0:a7a43371b306	2164	static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr)
ram54288	0:a7a43371b306	2165	{
ram54288	0:a7a43371b306	2166	int8_t ret_val = 0;
ram54288	0:a7a43371b306	2167	switch (address_type)
ram54288	0:a7a43371b306	2168	{
ram54288	0:a7a43371b306	2169	/Set 48-bit address/
ram54288	0:a7a43371b306	2170	case PHY_MAC_48BIT:
ram54288	0:a7a43371b306	2171	break;
ram54288	0:a7a43371b306	2172	/Set 64-bit address/
ram54288	0:a7a43371b306	2173	case PHY_MAC_64BIT:
ram54288	0:a7a43371b306	2174	rf_set_address(address_ptr);
ram54288	0:a7a43371b306	2175	break;
ram54288	0:a7a43371b306	2176	/Set 16-bit address/
ram54288	0:a7a43371b306	2177	case PHY_MAC_16BIT:
ram54288	0:a7a43371b306	2178	rf_set_short_adr(address_ptr);
ram54288	0:a7a43371b306	2179	break;
ram54288	0:a7a43371b306	2180	/Set PAN Id/
ram54288	0:a7a43371b306	2181	case PHY_MAC_PANID:
ram54288	0:a7a43371b306	2182	rf_set_pan_id(address_ptr);
ram54288	0:a7a43371b306	2183	break;
ram54288	0:a7a43371b306	2184	}
ram54288	0:a7a43371b306	2185	return ret_val;
ram54288	0:a7a43371b306	2186	}
ram54288	0:a7a43371b306	2187
ram54288	0:a7a43371b306	2188	/*
ram54288	0:a7a43371b306	2189	* \brief Function initialises the ACK wait time and returns the used PHY mode.
ram54288	0:a7a43371b306	2190	*
ram54288	0:a7a43371b306	2191	* \param none
ram54288	0:a7a43371b306	2192	*
ram54288	0:a7a43371b306	2193	* \return tmp Used PHY mode
ram54288	0:a7a43371b306	2194	*/
ram54288	0:a7a43371b306	2195	static void rf_init_phy_mode(void)
ram54288	0:a7a43371b306	2196	{
ram54288	0:a7a43371b306	2197	uint8_t tmp = 0;
ram54288	0:a7a43371b306	2198	uint8_t part = rf_if_read_part_num();
ram54288	0:a7a43371b306	2199	/Read used PHY Mode/
ram54288	0:a7a43371b306	2200	tmp = rf_if_read_register(TRX_CTRL_2);
ram54288	0:a7a43371b306	2201	/Set ACK wait time for used data rate/
ram54288	0:a7a43371b306	2202	if(part == PART_AT86RF212)
ram54288	0:a7a43371b306	2203	{
ram54288	0:a7a43371b306	2204	if((tmp & 0x1f) == 0x00)
ram54288	0:a7a43371b306	2205	{
ram54288	0:a7a43371b306	2206	rf_sensitivity = -110;
ram54288	0:a7a43371b306	2207	rf_ack_wait_duration = 938;
ram54288	0:a7a43371b306	2208	tmp = BPSK_20;
ram54288	0:a7a43371b306	2209	}
ram54288	0:a7a43371b306	2210	else if((tmp & 0x1f) == 0x04)
ram54288	0:a7a43371b306	2211	{
ram54288	0:a7a43371b306	2212	rf_sensitivity = -108;
ram54288	0:a7a43371b306	2213	rf_ack_wait_duration = 469;
ram54288	0:a7a43371b306	2214	tmp = BPSK_40;
ram54288	0:a7a43371b306	2215	}
ram54288	0:a7a43371b306	2216	else if((tmp & 0x1f) == 0x14)
ram54288	0:a7a43371b306	2217	{
ram54288	0:a7a43371b306	2218	rf_sensitivity = -108;
ram54288	0:a7a43371b306	2219	rf_ack_wait_duration = 469;
ram54288	0:a7a43371b306	2220	tmp = BPSK_40_ALT;
ram54288	0:a7a43371b306	2221	}
ram54288	0:a7a43371b306	2222	else if((tmp & 0x1f) == 0x08)
ram54288	0:a7a43371b306	2223	{
ram54288	0:a7a43371b306	2224	rf_sensitivity = -101;
ram54288	0:a7a43371b306	2225	rf_ack_wait_duration = 50;
ram54288	0:a7a43371b306	2226	tmp = OQPSK_SIN_RC_100;
ram54288	0:a7a43371b306	2227	}
ram54288	0:a7a43371b306	2228	else if((tmp & 0x1f) == 0x09)
ram54288	0:a7a43371b306	2229	{
ram54288	0:a7a43371b306	2230	rf_sensitivity = -99;
ram54288	0:a7a43371b306	2231	rf_ack_wait_duration = 30;
ram54288	0:a7a43371b306	2232	tmp = OQPSK_SIN_RC_200;
ram54288	0:a7a43371b306	2233	}
ram54288	0:a7a43371b306	2234	else if((tmp & 0x1f) == 0x18)
ram54288	0:a7a43371b306	2235	{
ram54288	0:a7a43371b306	2236	rf_sensitivity = -102;
ram54288	0:a7a43371b306	2237	rf_ack_wait_duration = 50;
ram54288	0:a7a43371b306	2238	tmp = OQPSK_RC_100;
ram54288	0:a7a43371b306	2239	}
ram54288	0:a7a43371b306	2240	else if((tmp & 0x1f) == 0x19)
ram54288	0:a7a43371b306	2241	{
ram54288	0:a7a43371b306	2242	rf_sensitivity = -100;
ram54288	0:a7a43371b306	2243	rf_ack_wait_duration = 30;
ram54288	0:a7a43371b306	2244	tmp = OQPSK_RC_200;
ram54288	0:a7a43371b306	2245	}
ram54288	0:a7a43371b306	2246	else if((tmp & 0x1f) == 0x0c)
ram54288	0:a7a43371b306	2247	{
ram54288	0:a7a43371b306	2248	rf_sensitivity = -100;
ram54288	0:a7a43371b306	2249	rf_ack_wait_duration = 20;
ram54288	0:a7a43371b306	2250	tmp = OQPSK_SIN_250;
ram54288	0:a7a43371b306	2251	}
ram54288	0:a7a43371b306	2252	else if((tmp & 0x1f) == 0x0d)
ram54288	0:a7a43371b306	2253	{
ram54288	0:a7a43371b306	2254	rf_sensitivity = -98;
ram54288	0:a7a43371b306	2255	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2256	tmp = OQPSK_SIN_500;
ram54288	0:a7a43371b306	2257	}
ram54288	0:a7a43371b306	2258	else if((tmp & 0x1f) == 0x0f)
ram54288	0:a7a43371b306	2259	{
ram54288	0:a7a43371b306	2260	rf_sensitivity = -98;
ram54288	0:a7a43371b306	2261	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2262	tmp = OQPSK_SIN_500_ALT;
ram54288	0:a7a43371b306	2263	}
ram54288	0:a7a43371b306	2264	else if((tmp & 0x1f) == 0x1c)
ram54288	0:a7a43371b306	2265	{
ram54288	0:a7a43371b306	2266	rf_sensitivity = -101;
ram54288	0:a7a43371b306	2267	rf_ack_wait_duration = 20;
ram54288	0:a7a43371b306	2268	tmp = OQPSK_RC_250;
ram54288	0:a7a43371b306	2269	}
ram54288	0:a7a43371b306	2270	else if((tmp & 0x1f) == 0x1d)
ram54288	0:a7a43371b306	2271	{
ram54288	0:a7a43371b306	2272	rf_sensitivity = -99;
ram54288	0:a7a43371b306	2273	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2274	tmp = OQPSK_RC_500;
ram54288	0:a7a43371b306	2275	}
ram54288	0:a7a43371b306	2276	else if((tmp & 0x1f) == 0x1f)
ram54288	0:a7a43371b306	2277	{
ram54288	0:a7a43371b306	2278	rf_sensitivity = -99;
ram54288	0:a7a43371b306	2279	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2280	tmp = OQPSK_RC_500_ALT;
ram54288	0:a7a43371b306	2281	}
ram54288	0:a7a43371b306	2282	else if((tmp & 0x3f) == 0x2A)
ram54288	0:a7a43371b306	2283	{
ram54288	0:a7a43371b306	2284	rf_sensitivity = -91;
ram54288	0:a7a43371b306	2285	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2286	tmp = OQPSK_SIN_RC_400_SCR_ON;
ram54288	0:a7a43371b306	2287	}
ram54288	0:a7a43371b306	2288	else if((tmp & 0x3f) == 0x0A)
ram54288	0:a7a43371b306	2289	{
ram54288	0:a7a43371b306	2290	rf_sensitivity = -91;
ram54288	0:a7a43371b306	2291	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2292	tmp = OQPSK_SIN_RC_400_SCR_OFF;
ram54288	0:a7a43371b306	2293	}
ram54288	0:a7a43371b306	2294	else if((tmp & 0x3f) == 0x3A)
ram54288	0:a7a43371b306	2295	{
ram54288	0:a7a43371b306	2296	rf_sensitivity = -97;
ram54288	0:a7a43371b306	2297	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2298	tmp = OQPSK_RC_400_SCR_ON;
ram54288	0:a7a43371b306	2299	}
ram54288	0:a7a43371b306	2300	else if((tmp & 0x3f) == 0x1A)
ram54288	0:a7a43371b306	2301	{
ram54288	0:a7a43371b306	2302	rf_sensitivity = -97;
ram54288	0:a7a43371b306	2303	rf_ack_wait_duration = 25;
ram54288	0:a7a43371b306	2304	tmp = OQPSK_RC_400_SCR_OFF;
ram54288	0:a7a43371b306	2305	}
ram54288	0:a7a43371b306	2306	else if((tmp & 0x3f) == 0x2E)
ram54288	0:a7a43371b306	2307	{
ram54288	0:a7a43371b306	2308	rf_sensitivity = -93;
ram54288	0:a7a43371b306	2309	rf_ack_wait_duration = 13;
ram54288	0:a7a43371b306	2310	tmp = OQPSK_SIN_1000_SCR_ON;
ram54288	0:a7a43371b306	2311	}
ram54288	0:a7a43371b306	2312	else if((tmp & 0x3f) == 0x0E)
ram54288	0:a7a43371b306	2313	{
ram54288	0:a7a43371b306	2314	rf_sensitivity = -93;
ram54288	0:a7a43371b306	2315	rf_ack_wait_duration = 13;
ram54288	0:a7a43371b306	2316	tmp = OQPSK_SIN_1000_SCR_OFF;
ram54288	0:a7a43371b306	2317	}
ram54288	0:a7a43371b306	2318	else if((tmp & 0x3f) == 0x3E)
ram54288	0:a7a43371b306	2319	{
ram54288	0:a7a43371b306	2320	rf_sensitivity = -95;
ram54288	0:a7a43371b306	2321	rf_ack_wait_duration = 13;
ram54288	0:a7a43371b306	2322	tmp = OQPSK_RC_1000_SCR_ON;
ram54288	0:a7a43371b306	2323	}
ram54288	0:a7a43371b306	2324	else if((tmp & 0x3f) == 0x1E)
ram54288	0:a7a43371b306	2325	{
ram54288	0:a7a43371b306	2326	rf_sensitivity = -95;
ram54288	0:a7a43371b306	2327	rf_ack_wait_duration = 13;
ram54288	0:a7a43371b306	2328	tmp = OQPSK_RC_1000_SCR_OFF;
ram54288	0:a7a43371b306	2329	}
ram54288	0:a7a43371b306	2330	}
ram54288	0:a7a43371b306	2331	else
ram54288	0:a7a43371b306	2332	{
ram54288	0:a7a43371b306	2333	rf_sensitivity = -101;
ram54288	0:a7a43371b306	2334	rf_ack_wait_duration = 20;
ram54288	0:a7a43371b306	2335	}
ram54288	0:a7a43371b306	2336	/Board design might reduces the sensitivity/
ram54288	0:a7a43371b306	2337	//rf_sensitivity += RF_SENSITIVITY_CALIBRATION;
ram54288	0:a7a43371b306	2338	}
ram54288	0:a7a43371b306	2339
ram54288	0:a7a43371b306	2340
ram54288	0:a7a43371b306	2341	static uint8_t rf_scale_lqi(int8_t rssi)
ram54288	0:a7a43371b306	2342	{
ram54288	0:a7a43371b306	2343	uint8_t scaled_lqi;
ram54288	0:a7a43371b306	2344
ram54288	0:a7a43371b306	2345	/rssi < RF sensitivity/
ram54288	0:a7a43371b306	2346	if(rssi < rf_sensitivity)
ram54288	0:a7a43371b306	2347	scaled_lqi=0;
ram54288	0:a7a43371b306	2348	/-91 dBm < rssi < -81 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2349	/-90 dBm < rssi < -80 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2350	else if(rssi < (rf_sensitivity + 10))
ram54288	0:a7a43371b306	2351	scaled_lqi=31;
ram54288	0:a7a43371b306	2352	/-81 dBm < rssi < -71 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2353	/-80 dBm < rssi < -70 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2354	else if(rssi < (rf_sensitivity + 20))
ram54288	0:a7a43371b306	2355	scaled_lqi=207;
ram54288	0:a7a43371b306	2356	/-71 dBm < rssi < -61 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2357	/-70 dBm < rssi < -60 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2358	else if(rssi < (rf_sensitivity + 30))
ram54288	0:a7a43371b306	2359	scaled_lqi=255;
ram54288	0:a7a43371b306	2360	/-61 dBm < rssi < -51 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2361	/-60 dBm < rssi < -50 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2362	else if(rssi < (rf_sensitivity + 40))
ram54288	0:a7a43371b306	2363	scaled_lqi=255;
ram54288	0:a7a43371b306	2364	/-51 dBm < rssi < -41 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2365	/-50 dBm < rssi < -40 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2366	else if(rssi < (rf_sensitivity + 50))
ram54288	0:a7a43371b306	2367	scaled_lqi=255;
ram54288	0:a7a43371b306	2368	/-41 dBm < rssi < -31 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2369	/-40 dBm < rssi < -30 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2370	else if(rssi < (rf_sensitivity + 60))
ram54288	0:a7a43371b306	2371	scaled_lqi=255;
ram54288	0:a7a43371b306	2372	/-31 dBm < rssi < -21 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2373	/-30 dBm < rssi < -20 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2374	else if(rssi < (rf_sensitivity + 70))
ram54288	0:a7a43371b306	2375	scaled_lqi=255;
ram54288	0:a7a43371b306	2376	/rssi > RF saturation/
ram54288	0:a7a43371b306	2377	else if(rssi > (rf_sensitivity + 80))
ram54288	0:a7a43371b306	2378	scaled_lqi=111;
ram54288	0:a7a43371b306	2379	/-21 dBm < rssi < -11 dBm (AT86RF233 XPro)/
ram54288	0:a7a43371b306	2380	/-20 dBm < rssi < -10 dBm (AT86RF212B XPro)/
ram54288	0:a7a43371b306	2381	else
ram54288	0:a7a43371b306	2382	scaled_lqi=255;
ram54288	0:a7a43371b306	2383
ram54288	0:a7a43371b306	2384	return scaled_lqi;
ram54288	0:a7a43371b306	2385	}
ram54288	0:a7a43371b306	2386
ram54288	0:a7a43371b306	2387	NanostackRfPhyAtmel::NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso,
ram54288	0:a7a43371b306	2388	PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq,
ram54288	0:a7a43371b306	2389	PinName i2c_sda, PinName i2c_scl)
ram54288	0:a7a43371b306	2390	: _mac(i2c_sda, i2c_scl), _mac_addr(), _rf(NULL), _mac_set(false),
ram54288	0:a7a43371b306	2391	_spi_mosi(spi_mosi), _spi_miso(spi_miso), _spi_sclk(spi_sclk),
ram54288	0:a7a43371b306	2392	_spi_cs(spi_cs), _spi_rst(spi_rst), _spi_slp(spi_slp), _spi_irq(spi_irq)
ram54288	0:a7a43371b306	2393	{
ram54288	0:a7a43371b306	2394	_rf = new RFBits(_spi_mosi, _spi_miso, _spi_sclk, _spi_cs, _spi_rst, _spi_slp, _spi_irq);
ram54288	0:a7a43371b306	2395	}
ram54288	0:a7a43371b306	2396
ram54288	0:a7a43371b306	2397	NanostackRfPhyAtmel::~NanostackRfPhyAtmel()
ram54288	0:a7a43371b306	2398	{
ram54288	0:a7a43371b306	2399	delete _rf;
ram54288	0:a7a43371b306	2400	}
ram54288	0:a7a43371b306	2401
ram54288	0:a7a43371b306	2402	int8_t NanostackRfPhyAtmel::rf_register()
ram54288	0:a7a43371b306	2403	{
ram54288	0:a7a43371b306	2404	if (NULL == _rf) {
ram54288	0:a7a43371b306	2405	return -1;
ram54288	0:a7a43371b306	2406	}
ram54288	0:a7a43371b306	2407
ram54288	0:a7a43371b306	2408	rf_if_lock();
ram54288	0:a7a43371b306	2409
ram54288	0:a7a43371b306	2410	if (rf != NULL) {
ram54288	0:a7a43371b306	2411	rf_if_unlock();
ram54288	0:a7a43371b306	2412	error("Multiple registrations of NanostackRfPhyAtmel not supported");
ram54288	0:a7a43371b306	2413	return -1;
ram54288	0:a7a43371b306	2414	}
ram54288	0:a7a43371b306	2415
ram54288	0:a7a43371b306	2416	// Read the mac address if it hasn't been set by a user
ram54288	0:a7a43371b306	2417	rf = _rf;
ram54288	0:a7a43371b306	2418	if (!_mac_set) {
ram54288	0:a7a43371b306	2419	int ret = _mac.read_eui64((void*)_mac_addr);
ram54288	0:a7a43371b306	2420	if (ret < 0) {
ram54288	0:a7a43371b306	2421	rf = NULL;
ram54288	0:a7a43371b306	2422	rf_if_unlock();
ram54288	0:a7a43371b306	2423	return -1;
ram54288	0:a7a43371b306	2424	}
ram54288	0:a7a43371b306	2425	}
ram54288	0:a7a43371b306	2426
ram54288	0:a7a43371b306	2427	int8_t radio_id = rf_device_register(_mac_addr);
ram54288	0:a7a43371b306	2428	if (radio_id < 0) {
ram54288	0:a7a43371b306	2429	rf = NULL;
ram54288	0:a7a43371b306	2430	}
ram54288	0:a7a43371b306	2431
ram54288	0:a7a43371b306	2432	rf_if_unlock();
ram54288	0:a7a43371b306	2433	return radio_id;
ram54288	0:a7a43371b306	2434	}
ram54288	0:a7a43371b306	2435
ram54288	0:a7a43371b306	2436	void NanostackRfPhyAtmel::rf_unregister()
ram54288	0:a7a43371b306	2437	{
ram54288	0:a7a43371b306	2438	rf_if_lock();
ram54288	0:a7a43371b306	2439
ram54288	0:a7a43371b306	2440	if (NULL == rf) {
ram54288	0:a7a43371b306	2441	rf_if_unlock();
ram54288	0:a7a43371b306	2442	return;
ram54288	0:a7a43371b306	2443	}
ram54288	0:a7a43371b306	2444
ram54288	0:a7a43371b306	2445	rf_device_unregister();
ram54288	0:a7a43371b306	2446	rf = NULL;
ram54288	0:a7a43371b306	2447
ram54288	0:a7a43371b306	2448	rf_if_unlock();
ram54288	0:a7a43371b306	2449	}
ram54288	0:a7a43371b306	2450
ram54288	0:a7a43371b306	2451	void NanostackRfPhyAtmel::get_mac_address(uint8_t *mac)
ram54288	0:a7a43371b306	2452	{
ram54288	0:a7a43371b306	2453	rf_if_lock();
ram54288	0:a7a43371b306	2454
ram54288	0:a7a43371b306	2455	if (NULL == rf) {
ram54288	0:a7a43371b306	2456	error("NanostackRfPhyAtmel Must be registered to read mac address");
ram54288	0:a7a43371b306	2457	rf_if_unlock();
ram54288	0:a7a43371b306	2458	return;
ram54288	0:a7a43371b306	2459	}
ram54288	0:a7a43371b306	2460	memcpy((void)mac, (void)_mac_addr, sizeof(_mac_addr));
ram54288	0:a7a43371b306	2461
ram54288	0:a7a43371b306	2462	rf_if_unlock();
ram54288	0:a7a43371b306	2463	}
ram54288	0:a7a43371b306	2464
ram54288	0:a7a43371b306	2465	void NanostackRfPhyAtmel::set_mac_address(uint8_t *mac)
ram54288	0:a7a43371b306	2466	{
ram54288	0:a7a43371b306	2467	rf_if_lock();
ram54288	0:a7a43371b306	2468
ram54288	0:a7a43371b306	2469	if (NULL != rf) {
ram54288	0:a7a43371b306	2470	error("NanostackRfPhyAtmel cannot change mac address when running");
ram54288	0:a7a43371b306	2471	rf_if_unlock();
ram54288	0:a7a43371b306	2472	return;
ram54288	0:a7a43371b306	2473	}
ram54288	0:a7a43371b306	2474	memcpy((void)_mac_addr, (void)mac, sizeof(_mac_addr));
ram54288	0:a7a43371b306	2475	_mac_set = true;
ram54288	0:a7a43371b306	2476
ram54288	0:a7a43371b306	2477	rf_if_unlock();
ram54288	0:a7a43371b306	2478	}
ram54288	0:a7a43371b306	2479

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Type:	Program
Mbed OS support:	Mbed OS
Created:	14 May 2017
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

easy-connect/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp@0:a7a43371b306, 2017-05-14 (annotated)

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