Ram Gandikota / Mbed OS ABCD

A metronome using the FRDM K64F board

easy-connect/atmel-rf-driver/source/AT86RFReg.h@0:a7a43371b306, 2017-05-14 (annotated)

Committer:
ram54288
Date:
Sun May 14 18:40:18 2017 +0000
Revision:
0:a7a43371b306
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ram54288 0:a7a43371b306 1 /*
ram54288 0:a7a43371b306 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
ram54288 0:a7a43371b306 3 * SPDX-License-Identifier: Apache-2.0
ram54288 0:a7a43371b306 4 * Licensed under the Apache License, Version 2.0 (the License); you may
ram54288 0:a7a43371b306 5 * not use this file except in compliance with the License.
ram54288 0:a7a43371b306 6 * You may obtain a copy of the License at
ram54288 0:a7a43371b306 7 *
ram54288 0:a7a43371b306 8 * http://www.apache.org/licenses/LICENSE-2.0
ram54288 0:a7a43371b306 9 *
ram54288 0:a7a43371b306 10 * Unless required by applicable law or agreed to in writing, software
ram54288 0:a7a43371b306 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ram54288 0:a7a43371b306 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ram54288 0:a7a43371b306 13 * See the License for the specific language governing permissions and
ram54288 0:a7a43371b306 14 * limitations under the License.
ram54288 0:a7a43371b306 15 */
ram54288 0:a7a43371b306 16
ram54288 0:a7a43371b306 17 #ifndef AT86RFREG_H_
ram54288 0:a7a43371b306 18 #define AT86RFREG_H_
ram54288 0:a7a43371b306 19 #ifdef __cplusplus
ram54288 0:a7a43371b306 20 extern "C" {
ram54288 0:a7a43371b306 21 #endif
ram54288 0:a7a43371b306 22
ram54288 0:a7a43371b306 23 /*AT86RF212 PHY Modes*/
ram54288 0:a7a43371b306 24 #define BPSK_20 0x00
ram54288 0:a7a43371b306 25 #define BPSK_40 0x04
ram54288 0:a7a43371b306 26 #define BPSK_40_ALT 0x14
ram54288 0:a7a43371b306 27 #define OQPSK_SIN_RC_100 0x08
ram54288 0:a7a43371b306 28 #define OQPSK_SIN_RC_200 0x09
ram54288 0:a7a43371b306 29 #define OQPSK_RC_100 0x18
ram54288 0:a7a43371b306 30 #define OQPSK_RC_200 0x19
ram54288 0:a7a43371b306 31 #define OQPSK_SIN_250 0x0c
ram54288 0:a7a43371b306 32 #define OQPSK_SIN_500 0x0d
ram54288 0:a7a43371b306 33 #define OQPSK_SIN_500_ALT 0x0f
ram54288 0:a7a43371b306 34 #define OQPSK_RC_250 0x1c
ram54288 0:a7a43371b306 35 #define OQPSK_RC_500 0x1d
ram54288 0:a7a43371b306 36 #define OQPSK_RC_500_ALT 0x1f
ram54288 0:a7a43371b306 37 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
ram54288 0:a7a43371b306 38 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
ram54288 0:a7a43371b306 39 #define OQPSK_RC_400_SCR_ON 0x3A
ram54288 0:a7a43371b306 40 #define OQPSK_RC_400_SCR_OFF 0x1A
ram54288 0:a7a43371b306 41 #define OQPSK_SIN_1000_SCR_ON 0x2E
ram54288 0:a7a43371b306 42 #define OQPSK_SIN_1000_SCR_OFF 0x0E
ram54288 0:a7a43371b306 43 #define OQPSK_RC_1000_SCR_ON 0x3E
ram54288 0:a7a43371b306 44 #define OQPSK_RC_1000_SCR_OFF 0x1E
ram54288 0:a7a43371b306 45
ram54288 0:a7a43371b306 46 /*Supported transceivers*/
ram54288 0:a7a43371b306 47 #define PART_AT86RF231 0x03
ram54288 0:a7a43371b306 48 #define PART_AT86RF212 0x07
ram54288 0:a7a43371b306 49 #define PART_AT86RF233 0x0B
ram54288 0:a7a43371b306 50 #define VERSION_AT86RF212 0x01
ram54288 0:a7a43371b306 51 #define VERSION_AT86RF212B 0x03
ram54288 0:a7a43371b306 52
ram54288 0:a7a43371b306 53 /*RF Configuration Registers*/
ram54288 0:a7a43371b306 54 #define TRX_STATUS 0x01
ram54288 0:a7a43371b306 55 #define TRX_STATE 0x02
ram54288 0:a7a43371b306 56 #define TRX_CTRL_0 0x03
ram54288 0:a7a43371b306 57 #define TRX_CTRL_1 0x04
ram54288 0:a7a43371b306 58 #define PHY_TX_PWR 0x05
ram54288 0:a7a43371b306 59 #define PHY_RSSI 0x06
ram54288 0:a7a43371b306 60 #define PHY_ED_LEVEL 0x07
ram54288 0:a7a43371b306 61 #define PHY_CC_CCA 0x08
ram54288 0:a7a43371b306 62 #define RX_CTRL 0x0A
ram54288 0:a7a43371b306 63 #define SFD_VALUE 0x0B
ram54288 0:a7a43371b306 64 #define TRX_CTRL_2 0x0C
ram54288 0:a7a43371b306 65 #define ANT_DIV 0x0D
ram54288 0:a7a43371b306 66 #define IRQ_MASK 0x0E
ram54288 0:a7a43371b306 67 #define IRQ_STATUS 0x0F
ram54288 0:a7a43371b306 68 #define VREG_CTRL 0x10
ram54288 0:a7a43371b306 69 #define BATMON 0x11
ram54288 0:a7a43371b306 70 #define XOSC_CTRL 0x12
ram54288 0:a7a43371b306 71 #define CC_CTRL_0 0x13
ram54288 0:a7a43371b306 72 #define CC_CTRL_1 0x14
ram54288 0:a7a43371b306 73 #define RX_SYN 0x15
ram54288 0:a7a43371b306 74 #define TRX_RPC 0x16
ram54288 0:a7a43371b306 75 #define RF_CTRL_0 0x16
ram54288 0:a7a43371b306 76 #define XAH_CTRL_1 0x17
ram54288 0:a7a43371b306 77 #define FTN_CTRL 0x18
ram54288 0:a7a43371b306 78 #define PLL_CF 0x1A
ram54288 0:a7a43371b306 79 #define PLL_DCU 0x1B
ram54288 0:a7a43371b306 80 #define PART_NUM 0x1C
ram54288 0:a7a43371b306 81 #define VERSION_NUM 0x1D
ram54288 0:a7a43371b306 82 #define MAN_ID_0 0x1E
ram54288 0:a7a43371b306 83 #define MAN_ID_1 0x1F
ram54288 0:a7a43371b306 84 #define SHORT_ADDR_0 0x20
ram54288 0:a7a43371b306 85 #define SHORT_ADDR_1 0x21
ram54288 0:a7a43371b306 86 #define PAN_ID_0 0x22
ram54288 0:a7a43371b306 87 #define PAN_ID_1 0x23
ram54288 0:a7a43371b306 88 #define IEEE_ADDR_0 0x24
ram54288 0:a7a43371b306 89 #define IEEE_ADDR_1 0x25
ram54288 0:a7a43371b306 90 #define IEEE_ADDR_2 0x26
ram54288 0:a7a43371b306 91 #define IEEE_ADDR_3 0x27
ram54288 0:a7a43371b306 92 #define IEEE_ADDR_4 0x28
ram54288 0:a7a43371b306 93 #define IEEE_ADDR_5 0x29
ram54288 0:a7a43371b306 94 #define IEEE_ADDR_6 0x2A
ram54288 0:a7a43371b306 95 #define IEEE_ADDR_7 0x2B
ram54288 0:a7a43371b306 96 #define XAH_CTRL_0 0x2C
ram54288 0:a7a43371b306 97 #define CSMA_SEED_0 0x2D
ram54288 0:a7a43371b306 98 #define CSMA_SEED_1 0x2E
ram54288 0:a7a43371b306 99 #define CSMA_BE 0x2F
ram54288 0:a7a43371b306 100
ram54288 0:a7a43371b306 101 /* CSMA_SEED_1*/
ram54288 0:a7a43371b306 102 #define AACK_FVN_MODE1 7
ram54288 0:a7a43371b306 103 #define AACK_FVN_MODE0 6
ram54288 0:a7a43371b306 104 #define AACK_SET_PD 5
ram54288 0:a7a43371b306 105 #define AACK_DIS_ACK 4
ram54288 0:a7a43371b306 106 #define AACK_I_AM_COORD 3
ram54288 0:a7a43371b306 107 #define CSMA_SEED_12 2
ram54288 0:a7a43371b306 108 #define CSMA_SEED_11 1
ram54288 0:a7a43371b306 109 #define CSMA_SEED_10 0
ram54288 0:a7a43371b306 110
ram54288 0:a7a43371b306 111 /*TRX_STATUS bits*/
ram54288 0:a7a43371b306 112 #define CCA_STATUS 0x40
ram54288 0:a7a43371b306 113 #define CCA_DONE 0x80
ram54288 0:a7a43371b306 114
ram54288 0:a7a43371b306 115 /*PHY_CC_CCA bits*/
ram54288 0:a7a43371b306 116 #define CCA_REQUEST 0x80
ram54288 0:a7a43371b306 117 #define CCA_MODE_1 0x20
ram54288 0:a7a43371b306 118 #define CCA_MODE_3 0x60
ram54288 0:a7a43371b306 119
ram54288 0:a7a43371b306 120 /*IRQ_MASK bits*/
ram54288 0:a7a43371b306 121 #define RX_START 0x04
ram54288 0:a7a43371b306 122 #define TRX_END 0x08
ram54288 0:a7a43371b306 123 #define CCA_ED_DONE 0x10
ram54288 0:a7a43371b306 124 #define AMI 0x20
ram54288 0:a7a43371b306 125 #define TRX_UR 0x40
ram54288 0:a7a43371b306 126
ram54288 0:a7a43371b306 127 /*ANT_DIV bits*/
ram54288 0:a7a43371b306 128 #define ANT_DIV_EN 0x08
ram54288 0:a7a43371b306 129 #define ANT_EXT_SW_EN 0x04
ram54288 0:a7a43371b306 130 #define ANT_CTRL_DEFAULT 0x03
ram54288 0:a7a43371b306 131
ram54288 0:a7a43371b306 132 /*TRX_CTRL_1 bits*/
ram54288 0:a7a43371b306 133 #define PA_EXT_EN 0x80
ram54288 0:a7a43371b306 134
ram54288 0:a7a43371b306 135 /*FTN_CTRL bits*/
ram54288 0:a7a43371b306 136 #define FTN_START 0x80
ram54288 0:a7a43371b306 137
ram54288 0:a7a43371b306 138 /*PHY_RSSI bits*/
ram54288 0:a7a43371b306 139 #define CRC_VALID 0x80
ram54288 0:a7a43371b306 140
ram54288 0:a7a43371b306 141 /*RX_SYN bits*/
ram54288 0:a7a43371b306 142 #define RX_PDT_DIS 0x80
ram54288 0:a7a43371b306 143
ram54288 0:a7a43371b306 144 /*TRX_RPC bits */
ram54288 0:a7a43371b306 145 #define RX_RPC_CTRL 0xC0
ram54288 0:a7a43371b306 146 #define RX_RPC_EN 0x20
ram54288 0:a7a43371b306 147 #define PDT_RPC_EN 0x10
ram54288 0:a7a43371b306 148 #define PLL_RPC_EN 0x08
ram54288 0:a7a43371b306 149 #define XAH_TX_RPC_EN 0x04
ram54288 0:a7a43371b306 150 #define IPAN_RPC_EN 0x02
ram54288 0:a7a43371b306 151 #define TRX_RPC_RSVD_1 0x01
ram54288 0:a7a43371b306 152
ram54288 0:a7a43371b306 153 /*XAH_CTRL_1 bits*/
ram54288 0:a7a43371b306 154 #define AACK_PROM_MODE 0x02
ram54288 0:a7a43371b306 155
ram54288 0:a7a43371b306 156
ram54288 0:a7a43371b306 157 #ifdef __cplusplus
ram54288 0:a7a43371b306 158 }
ram54288 0:a7a43371b306 159 #endif
ram54288 0:a7a43371b306 160
ram54288 0:a7a43371b306 161 #endif /* AT86RFREG_H_ */