Rajath Ravi
/
ravi_blinkycode
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
stm32f4xx_tim_mort.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_tim.c 00004 * @author MCD Application Team 00005 * @version V1.8.0 00006 * @date 04-November-2016 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the TIM peripheral: 00009 * + TimeBase management 00010 * + Output Compare management 00011 * + Input Capture management 00012 * + Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features 00013 * + Interrupts, DMA and flags management 00014 * + Clocks management 00015 * + Synchronization management 00016 * + Specific interface management 00017 * + Specific remapping management 00018 * 00019 @verbatim 00020 =============================================================================== 00021 ##### How to use this driver ##### 00022 =============================================================================== 00023 [..] 00024 This driver provides functions to configure and program the TIM 00025 of all STM32F4xx devices. 00026 These functions are split in 9 groups: 00027 00028 (#) TIM TimeBase management: this group includes all needed functions 00029 to configure the TM Timebase unit: 00030 (++) Set/Get Prescaler 00031 (++) Set/Get Autoreload 00032 (++) Counter modes configuration 00033 (++) Set Clock division 00034 (++) Select the One Pulse mode 00035 (++) Update Request Configuration 00036 (++) Update Disable Configuration 00037 (++) Auto-Preload Configuration 00038 (++) Enable/Disable the counter 00039 00040 (#) TIM Output Compare management: this group includes all needed 00041 functions to configure the Capture/Compare unit used in Output 00042 compare mode: 00043 (++) Configure each channel, independently, in Output Compare mode 00044 (++) Select the output compare modes 00045 (++) Select the Polarities of each channel 00046 (++) Set/Get the Capture/Compare register values 00047 (++) Select the Output Compare Fast mode 00048 (++) Select the Output Compare Forced mode 00049 (++) Output Compare-Preload Configuration 00050 (++) Clear Output Compare Reference 00051 (++) Select the OCREF Clear signal 00052 (++) Enable/Disable the Capture/Compare Channels 00053 00054 (#) TIM Input Capture management: this group includes all needed 00055 functions to configure the Capture/Compare unit used in 00056 Input Capture mode: 00057 (++) Configure each channel in input capture mode 00058 (++) Configure Channel1/2 in PWM Input mode 00059 (++) Set the Input Capture Prescaler 00060 (++) Get the Capture/Compare values 00061 00062 (#) Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features 00063 (++) Configures the Break input, dead time, Lock level, the OSSI, 00064 the OSSR State and the AOE(automatic output enable) 00065 (++) Enable/Disable the TIM peripheral Main Outputs 00066 (++) Select the Commutation event 00067 (++) Set/Reset the Capture Compare Preload Control bit 00068 00069 (#) TIM interrupts, DMA and flags management 00070 (++) Enable/Disable interrupt sources 00071 (++) Get flags status 00072 (++) Clear flags/ Pending bits 00073 (++) Enable/Disable DMA requests 00074 (++) Configure DMA burst mode 00075 (++) Select CaptureCompare DMA request 00076 00077 (#) TIM clocks management: this group includes all needed functions 00078 to configure the clock controller unit: 00079 (++) Select internal/External clock 00080 (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx 00081 00082 (#) TIM synchronization management: this group includes all needed 00083 functions to configure the Synchronization unit: 00084 (++) Select Input Trigger 00085 (++) Select Output Trigger 00086 (++) Select Master Slave Mode 00087 (++) ETR Configuration when used as external trigger 00088 00089 (#) TIM specific interface management, this group includes all 00090 needed functions to use the specific TIM interface: 00091 (++) Encoder Interface Configuration 00092 (++) Select Hall Sensor 00093 00094 (#) TIM specific remapping management includes the Remapping 00095 configuration of specific timers 00096 00097 @endverbatim 00098 ****************************************************************************** 00099 * @attention 00100 * 00101 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00102 * 00103 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00104 * You may not use this file except in compliance with the License. 00105 * You may obtain a copy of the License at: 00106 * 00107 * http://www.st.com/software_license_agreement_liberty_v2 00108 * 00109 * Unless required by applicable law or agreed to in writing, software 00110 * distributed under the License is distributed on an "AS IS" BASIS, 00111 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00112 * See the License for the specific language governing permissions and 00113 * limitations under the License. 00114 * 00115 ****************************************************************************** 00116 */ 00117 00118 /* Includes ------------------------------------------------------------------*/ 00119 #include "stm32f4xx_tim_mort.h" 00120 #include "stm32f4xx_rcc_mort.h" 00121 00122 /** @addtogroup STM32F4xx_StdPeriph_Driver 00123 * @{ 00124 */ 00125 00126 /** @defgroup TIM 00127 * @brief TIM driver modules 00128 * @{ 00129 */ 00130 00131 /* Private typedef -----------------------------------------------------------*/ 00132 /* Private define ------------------------------------------------------------*/ 00133 00134 /* ---------------------- TIM registers bit mask ------------------------ */ 00135 #define SMCR_ETR_MASK_MORT ((uint16_t)0x00FF) 00136 #define CCMR_OFFSET_MORT ((uint16_t)0x0018) 00137 #define CCER_CCE_SET_MORT ((uint16_t)0x0001) 00138 #define CCER_CCNE_SET_MORT ((uint16_t)0x0004) 00139 #define CCMR_OC13M_MASK_MORT ((uint16_t)0xFF8F) 00140 #define CCMR_OC24M_MASK_MORT ((uint16_t)0x8FFF) 00141 00142 /* Private macro -------------------------------------------------------------*/ 00143 /* Private variables ---------------------------------------------------------*/ 00144 /* Private function prototypes -----------------------------------------------*/ 00145 static void TI1_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00146 uint16_t TIM_ICFilter); 00147 static void TI2_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00148 uint16_t TIM_ICFilter); 00149 static void TI3_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00150 uint16_t TIM_ICFilter); 00151 static void TI4_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00152 uint16_t TIM_ICFilter); 00153 00154 /* Private functions ---------------------------------------------------------*/ 00155 00156 /** @defgroup TIM_Private_Functions 00157 * @{ 00158 */ 00159 00160 /** @defgroup TIM_Group1 TimeBase management functions 00161 * @brief TimeBase management functions 00162 * 00163 @verbatim 00164 =============================================================================== 00165 ##### TimeBase management functions ##### 00166 =============================================================================== 00167 00168 00169 ##### TIM Driver: how to use it in Timing(Time base) Mode ##### 00170 =============================================================================== 00171 [..] 00172 To use the Timer in Timing(Time base) mode, the following steps are mandatory: 00173 00174 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 00175 00176 (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. 00177 00178 (#) Call TIM_TimeBaseInit_mort(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit 00179 with the corresponding configuration 00180 00181 (#) Enable the NVIC if you need to generate the update interrupt. 00182 00183 (#) Enable the corresponding interrupt using the function TIM_ITConfig_mort(TIMx, TIM_IT_Update_MORT) 00184 00185 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 00186 00187 -@- All other functions can be used separately to modify, if needed, 00188 a specific feature of the Timer. 00189 00190 @endverbatim 00191 * @{ 00192 */ 00193 00194 /** 00195 * @brief Deinitializes the TIMx peripheral registers to their default reset values. 00196 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00197 * @retval None 00198 00199 */ 00200 void TIM_DeInit_mort(TIM_TypeDef_mort* TIMx) 00201 { 00202 /* Check the parameters */ 00203 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00204 00205 if (TIMx == TIM1_MORT) 00206 { 00207 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); 00208 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); 00209 } 00210 else if (TIMx == TIM2_MORT) 00211 { 00212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); 00213 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); 00214 } 00215 else if (TIMx == TIM3_MORT) 00216 { 00217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); 00218 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); 00219 } 00220 else if (TIMx == TIM4_MORT) 00221 { 00222 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); 00223 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); 00224 } 00225 else if (TIMx == TIM5_MORT) 00226 { 00227 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); 00228 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); 00229 } 00230 else if (TIMx == TIM6_MORT) 00231 { 00232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); 00233 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); 00234 } 00235 else if (TIMx == TIM7_MORT) 00236 { 00237 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); 00238 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); 00239 } 00240 else if (TIMx == TIM8_MORT) 00241 { 00242 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); 00243 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); 00244 } 00245 else if (TIMx == TIM9_MORT) 00246 { 00247 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); 00248 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); 00249 } 00250 else if (TIMx == TIM10_MORT) 00251 { 00252 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); 00253 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); 00254 } 00255 else if (TIMx == TIM11_MORT) 00256 { 00257 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); 00258 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); 00259 } 00260 else if (TIMx == TIM12_MORT) 00261 { 00262 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); 00263 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); 00264 } 00265 else if (TIMx == TIM13_MORT) 00266 { 00267 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); 00268 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); 00269 } 00270 else 00271 { 00272 if (TIMx == TIM14_MORT) 00273 { 00274 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); 00275 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 00276 } 00277 } 00278 } 00279 00280 /** 00281 * @brief Initializes the TIMx Time Base Unit peripheral according to 00282 * the specified parameters in the TIM_TimeBaseInitStruct. 00283 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00284 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef_mort structure 00285 * that contains the configuration information for the specified TIM peripheral. 00286 * @retval None 00287 */ 00288 void TIM_TimeBaseInit_mort(TIM_TypeDef_mort* TIMx, TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct) 00289 { 00290 uint16_t tmpcr1 = 0; 00291 00292 /* Check the parameters */ 00293 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00294 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); 00295 assert_param(IS_TIM_CKD_DIV_MORT(TIM_TimeBaseInitStruct->TIM_ClockDivision)); 00296 00297 tmpcr1 = TIMx->CR1; 00298 00299 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)|| 00300 (TIMx == TIM2_MORT) || (TIMx == TIM3_MORT)|| 00301 (TIMx == TIM4_MORT) || (TIMx == TIM5_MORT)) 00302 { 00303 /* Select the Counter Mode */ 00304 tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR_MORT | TIM_CR1_CMS_MORT)); 00305 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; 00306 } 00307 00308 if((TIMx != TIM6_MORT) && (TIMx != TIM7_MORT)) 00309 { 00310 /* Set the clock division */ 00311 tmpcr1 &= (uint16_t)(~TIM_CR1_CKD_MORT); 00312 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; 00313 } 00314 00315 TIMx->CR1 = tmpcr1; 00316 00317 /* Set the Autoreload value */ 00318 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; 00319 00320 /* Set the Prescaler value */ 00321 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; 00322 00323 if ((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)) 00324 { 00325 /* Set the Repetition Counter value */ 00326 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; 00327 } 00328 00329 /* Generate an update event to reload the Prescaler 00330 and the repetition counter(only for TIM1_MORT and TIM8_MORT) value immediately */ 00331 TIMx->EGR = TIM_PSCReloadMode_Immediate_MORT; 00332 } 00333 00334 /** 00335 * @brief Fills each TIM_TimeBaseInitStruct member with its default value. 00336 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef_mort 00337 * structure which will be initialized. 00338 * @retval None 00339 */ 00340 void TIM_TimeBaseStructInit_mort(TIM_TimeBaseInitTypeDef_mort* TIM_TimeBaseInitStruct) 00341 { 00342 /* Set the default configuration */ 00343 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; 00344 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; 00345 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1_MORT; 00346 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up_MORT; 00347 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; 00348 } 00349 00350 /** 00351 * @brief Configures the TIMx Prescaler. 00352 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00353 * @param Prescaler: specifies the Prescaler Register value 00354 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode 00355 * This parameter can be one of the following values: 00356 * @arg TIM_PSCReloadMode_Update_MORT: The Prescaler is loaded at the update event. 00357 * @arg TIM_PSCReloadMode_Immediate_MORT: The Prescaler is loaded immediately. 00358 * @retval None 00359 */ 00360 void TIM_PrescalerConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) 00361 { 00362 /* Check the parameters */ 00363 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00364 assert_param(IS_TIM_PRESCALER_RELOAD_MORT(TIM_PSCReloadMode)); 00365 /* Set the Prescaler value */ 00366 TIMx->PSC = Prescaler; 00367 /* Set or reset the UG Bit */ 00368 TIMx->EGR = TIM_PSCReloadMode; 00369 } 00370 00371 /** 00372 * @brief Specifies the TIMx Counter Mode to be used. 00373 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 00374 * @param TIM_CounterMode: specifies the Counter Mode to be used 00375 * This parameter can be one of the following values: 00376 * @arg TIM_CounterMode_Up_MORT: TIM Up Counting Mode 00377 * @arg TIM_CounterMode_Down_MORT: TIM Down Counting Mode 00378 * @arg TIM_CounterMode_CenterAligned1_MORT: TIM Center Aligned Mode1 00379 * @arg TIM_CounterMode_CenterAligned2_MORT: TIM Center Aligned Mode2 00380 * @arg TIM_CounterMode_CenterAligned3_MORT: TIM Center Aligned Mode3 00381 * @retval None 00382 */ 00383 void TIM_CounterModeConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CounterMode) 00384 { 00385 uint16_t tmpcr1 = 0; 00386 00387 /* Check the parameters */ 00388 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 00389 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); 00390 00391 tmpcr1 = TIMx->CR1; 00392 00393 /* Reset the CMS and DIR Bits */ 00394 tmpcr1 &= (uint16_t)~(TIM_CR1_DIR_MORT | TIM_CR1_CMS_MORT); 00395 00396 /* Set the Counter Mode */ 00397 tmpcr1 |= TIM_CounterMode; 00398 00399 /* Write to TIMx CR1 register */ 00400 TIMx->CR1 = tmpcr1; 00401 } 00402 00403 /** 00404 * @brief Sets the TIMx Counter Register value 00405 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00406 * @param Counter: specifies the Counter register new value. 00407 * @retval None 00408 */ 00409 void TIM_SetCounter_mort(TIM_TypeDef_mort* TIMx, uint32_t Counter) 00410 { 00411 /* Check the parameters */ 00412 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00413 00414 /* Set the Counter Register value */ 00415 TIMx->CNT = Counter; 00416 } 00417 00418 /** 00419 * @brief Sets the TIMx Autoreload Register value 00420 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00421 * @param Autoreload: specifies the Autoreload register new value. 00422 * @retval None 00423 */ 00424 void TIM_SetAutoreload_mort(TIM_TypeDef_mort* TIMx, uint32_t Autoreload) 00425 { 00426 /* Check the parameters */ 00427 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00428 00429 /* Set the Autoreload Register value */ 00430 TIMx->ARR = Autoreload; 00431 } 00432 00433 /** 00434 * @brief Gets the TIMx Counter value. 00435 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00436 * @retval Counter Register value 00437 */ 00438 uint32_t TIM_GetCounter_mort(TIM_TypeDef_mort* TIMx) 00439 { 00440 /* Check the parameters */ 00441 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00442 00443 /* Get the Counter Register value */ 00444 return TIMx->CNT; 00445 } 00446 00447 /** 00448 * @brief Gets the TIMx Prescaler value. 00449 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00450 * @retval Prescaler Register value. 00451 */ 00452 uint16_t TIM_GetPrescaler_mort(TIM_TypeDef_mort* TIMx) 00453 { 00454 /* Check the parameters */ 00455 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00456 00457 /* Get the Prescaler Register value */ 00458 return TIMx->PSC; 00459 } 00460 00461 /** 00462 * @brief Enables or Disables the TIMx Update event. 00463 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00464 * @param NewState: new state of the TIMx UDIS bit 00465 * This parameter can be: ENABLE or DISABLE. 00466 * @retval None 00467 */ 00468 void TIM_UpdateDisableConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 00469 { 00470 /* Check the parameters */ 00471 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00472 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00473 00474 if (NewState != DISABLE) 00475 { 00476 /* Set the Update Disable Bit */ 00477 TIMx->CR1 |= TIM_CR1_UDIS_MORT; 00478 } 00479 else 00480 { 00481 /* Reset the Update Disable Bit */ 00482 TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS_MORT; 00483 } 00484 } 00485 00486 /** 00487 * @brief Configures the TIMx Update Request Interrupt source. 00488 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00489 * @param TIM_UpdateSource: specifies the Update source. 00490 * This parameter can be one of the following values: 00491 * @arg TIM_UpdateSource_Global_MORT: Source of update is the counter 00492 * overflow/underflow or the setting of UG bit, or an update 00493 * generation through the slave mode controller. 00494 * @arg TIM_UpdateSource_Regular_MORT: Source of update is counter overflow/underflow. 00495 * @retval None 00496 */ 00497 void TIM_UpdateRequestConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_UpdateSource) 00498 { 00499 /* Check the parameters */ 00500 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00501 assert_param(IS_TIM_UPDATE_SOURCE_MORT(TIM_UpdateSource)); 00502 00503 if (TIM_UpdateSource != TIM_UpdateSource_Global_MORT) 00504 { 00505 /* Set the URS Bit */ 00506 TIMx->CR1 |= TIM_CR1_URS_MORT; 00507 } 00508 else 00509 { 00510 /* Reset the URS Bit */ 00511 TIMx->CR1 &= (uint16_t)~TIM_CR1_URS_MORT; 00512 } 00513 } 00514 00515 /** 00516 * @brief Enables or disables TIMx peripheral Preload register on ARR. 00517 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00518 * @param NewState: new state of the TIMx peripheral Preload register 00519 * This parameter can be: ENABLE or DISABLE. 00520 * @retval None 00521 */ 00522 void TIM_ARRPreloadConfig_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 00523 { 00524 /* Check the parameters */ 00525 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00526 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00527 00528 if (NewState != DISABLE) 00529 { 00530 /* Set the ARR Preload Bit */ 00531 TIMx->CR1 |= TIM_CR1_ARPE_MORT; 00532 } 00533 else 00534 { 00535 /* Reset the ARR Preload Bit */ 00536 TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE_MORT; 00537 } 00538 } 00539 00540 /** 00541 * @brief Selects the TIMx's One Pulse Mode. 00542 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 00543 * @param TIM_OPMode: specifies the OPM Mode to be used. 00544 * This parameter can be one of the following values: 00545 * @arg TIM_OPMode_Single_MORT 00546 * @arg TIM_OPMode_Repetitive_MORT 00547 * @retval None 00548 */ 00549 void TIM_SelectOnePulseMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OPMode) 00550 { 00551 /* Check the parameters */ 00552 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00553 assert_param(IS_TIM_OPM_MODE_MORT(TIM_OPMode)); 00554 00555 /* Reset the OPM Bit */ 00556 TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM_MORT; 00557 00558 /* Configure the OPM Mode */ 00559 TIMx->CR1 |= TIM_OPMode; 00560 } 00561 00562 /** 00563 * @brief Sets the TIMx Clock Division value. 00564 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 00565 * @param TIM_CKD: specifies the clock division value. 00566 * This parameter can be one of the following value: 00567 * @arg TIM_CKD_DIV1_MORT: TDTS = Tck_tim 00568 * @arg TIM_CKD_DIV2_MORT: TDTS = 2*Tck_tim 00569 * @arg TIM_CKD_DIV4_MORT: TDTS = 4*Tck_tim 00570 * @retval None 00571 */ 00572 void TIM_SetClockDivision_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_CKD) 00573 { 00574 /* Check the parameters */ 00575 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 00576 assert_param(IS_TIM_CKD_DIV_MORT(TIM_CKD)); 00577 00578 /* Reset the CKD Bits */ 00579 TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD_MORT); 00580 00581 /* Set the CKD value */ 00582 TIMx->CR1 |= TIM_CKD; 00583 } 00584 00585 /** 00586 * @brief Enables or disables the specified TIM peripheral. 00587 * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. 00588 * @param NewState: new state of the TIMx peripheral. 00589 * This parameter can be: ENABLE or DISABLE. 00590 * @retval None 00591 */ 00592 void TIM_Cmd_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 00593 { 00594 /* Check the parameters */ 00595 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 00596 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00597 00598 if (NewState != DISABLE) 00599 { 00600 /* Enable the TIM Counter */ 00601 TIMx->CR1 |= TIM_CR1_CEN_MORT; 00602 } 00603 else 00604 { 00605 /* Disable the TIM Counter */ 00606 TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN_MORT; 00607 } 00608 } 00609 /** 00610 * @} 00611 */ 00612 00613 /** @defgroup TIM_Group2 Output Compare management functions 00614 * @brief Output Compare management functions 00615 * 00616 @verbatim 00617 =============================================================================== 00618 ##### Output Compare management functions ##### 00619 =============================================================================== 00620 00621 00622 ##### TIM Driver: how to use it in Output Compare Mode ##### 00623 =============================================================================== 00624 [..] 00625 To use the Timer in Output Compare mode, the following steps are mandatory: 00626 00627 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) 00628 function 00629 00630 (#) Configure the TIM pins by configuring the corresponding GPIO pins 00631 00632 (#) Configure the Time base unit as described in the first part of this driver, 00633 (++) if needed, else the Timer will run with the default configuration: 00634 Autoreload value = 0xFFFF 00635 (++) Prescaler value = 0x0000 00636 (++) Counter mode = Up counting 00637 (++) Clock Division = TIM_CKD_DIV1_MORT 00638 00639 (#) Fill the TIM_OCInitStruct with the desired parameters including: 00640 (++) The TIM Output Compare mode: TIM_OCMode 00641 (++) TIM Output State: TIM_OutputState 00642 (++) TIM Pulse value: TIM_Pulse 00643 (++) TIM Output Compare Polarity : TIM_OCPolarity 00644 00645 (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired 00646 channel with the corresponding configuration 00647 00648 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 00649 00650 -@- All other functions can be used separately to modify, if needed, 00651 a specific feature of the Timer. 00652 00653 -@- In case of PWM mode, this function is mandatory: 00654 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_Enable_MORT); 00655 00656 -@- If the corresponding interrupt or DMA request are needed, the user should: 00657 (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 00658 (+@) Enable the corresponding interrupt (or DMA request) using the function 00659 TIM_ITConfig_mort(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 00660 00661 @endverbatim 00662 * @{ 00663 */ 00664 00665 /** 00666 * @brief Initializes the TIMx Channel1 according to the specified parameters in 00667 * the TIM_OCInitStruct. 00668 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 00669 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains 00670 * the configuration information for the specified TIM peripheral. 00671 * @retval None 00672 */ 00673 void TIM_OC1Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct) 00674 { 00675 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00676 00677 /* Check the parameters */ 00678 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 00679 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode)); 00680 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00681 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00682 00683 /* Disable the Channel 1: Reset the CC1E Bit */ 00684 TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E_MORT; 00685 00686 /* Get the TIMx CCER register value */ 00687 tmpccer = TIMx->CCER; 00688 /* Get the TIMx CR2 register value */ 00689 tmpcr2 = TIMx->CR2; 00690 00691 /* Get the TIMx CCMR1 register value */ 00692 tmpccmrx = TIMx->CCMR1; 00693 00694 /* Reset the Output Compare Mode Bits */ 00695 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M_MORT; 00696 tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S_MORT; 00697 /* Select the Output Compare Mode */ 00698 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 00699 00700 /* Reset the Output Polarity level */ 00701 tmpccer &= (uint16_t)~TIM_CCER_CC1P_MORT; 00702 /* Set the Output Compare Polarity */ 00703 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; 00704 00705 /* Set the Output State */ 00706 tmpccer |= TIM_OCInitStruct->TIM_OutputState; 00707 00708 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)) 00709 { 00710 assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState)); 00711 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity)); 00712 assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState)); 00713 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState)); 00714 00715 /* Reset the Output N Polarity level */ 00716 tmpccer &= (uint16_t)~TIM_CCER_CC1NP_MORT; 00717 /* Set the Output N Polarity */ 00718 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; 00719 /* Reset the Output N State */ 00720 tmpccer &= (uint16_t)~TIM_CCER_CC1NE_MORT; 00721 00722 /* Set the Output N State */ 00723 tmpccer |= TIM_OCInitStruct->TIM_OutputNState; 00724 /* Reset the Output Compare and Output Compare N IDLE State */ 00725 tmpcr2 &= (uint16_t)~TIM_CR2_OIS1_MORT; 00726 tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N_MORT; 00727 /* Set the Output Idle state */ 00728 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; 00729 /* Set the Output N Idle state */ 00730 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; 00731 } 00732 /* Write to TIMx CR2 */ 00733 TIMx->CR2 = tmpcr2; 00734 00735 /* Write to TIMx CCMR1 */ 00736 TIMx->CCMR1 = tmpccmrx; 00737 00738 /* Set the Capture Compare Register value */ 00739 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 00740 00741 /* Write to TIMx CCER */ 00742 TIMx->CCER = tmpccer; 00743 } 00744 00745 /** 00746 * @brief Initializes the TIMx Channel2 according to the specified parameters 00747 * in the TIM_OCInitStruct. 00748 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 00749 * peripheral. 00750 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains 00751 * the configuration information for the specified TIM peripheral. 00752 * @retval None 00753 */ 00754 void TIM_OC2Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct) 00755 { 00756 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00757 00758 /* Check the parameters */ 00759 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 00760 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode)); 00761 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00762 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00763 00764 /* Disable the Channel 2: Reset the CC2E Bit */ 00765 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E_MORT; 00766 00767 /* Get the TIMx CCER register value */ 00768 tmpccer = TIMx->CCER; 00769 /* Get the TIMx CR2 register value */ 00770 tmpcr2 = TIMx->CR2; 00771 00772 /* Get the TIMx CCMR1 register value */ 00773 tmpccmrx = TIMx->CCMR1; 00774 00775 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00776 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M_MORT; 00777 tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S_MORT; 00778 00779 /* Select the Output Compare Mode */ 00780 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 00781 00782 /* Reset the Output Polarity level */ 00783 tmpccer &= (uint16_t)~TIM_CCER_CC2P_MORT; 00784 /* Set the Output Compare Polarity */ 00785 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); 00786 00787 /* Set the Output State */ 00788 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); 00789 00790 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)) 00791 { 00792 assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState)); 00793 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity)); 00794 assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState)); 00795 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState)); 00796 00797 /* Reset the Output N Polarity level */ 00798 tmpccer &= (uint16_t)~TIM_CCER_CC2NP_MORT; 00799 /* Set the Output N Polarity */ 00800 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); 00801 /* Reset the Output N State */ 00802 tmpccer &= (uint16_t)~TIM_CCER_CC2NE_MORT; 00803 00804 /* Set the Output N State */ 00805 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); 00806 /* Reset the Output Compare and Output Compare N IDLE State */ 00807 tmpcr2 &= (uint16_t)~TIM_CR2_OIS2_MORT; 00808 tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N_MORT; 00809 /* Set the Output Idle state */ 00810 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); 00811 /* Set the Output N Idle state */ 00812 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); 00813 } 00814 /* Write to TIMx CR2 */ 00815 TIMx->CR2 = tmpcr2; 00816 00817 /* Write to TIMx CCMR1 */ 00818 TIMx->CCMR1 = tmpccmrx; 00819 00820 /* Set the Capture Compare Register value */ 00821 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; 00822 00823 /* Write to TIMx CCER */ 00824 TIMx->CCER = tmpccer; 00825 } 00826 00827 /** 00828 * @brief Initializes the TIMx Channel3 according to the specified parameters 00829 * in the TIM_OCInitStruct. 00830 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 00831 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains 00832 * the configuration information for the specified TIM peripheral. 00833 * @retval None 00834 */ 00835 void TIM_OC3Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct) 00836 { 00837 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00838 00839 /* Check the parameters */ 00840 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 00841 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode)); 00842 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00843 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00844 00845 /* Disable the Channel 3: Reset the CC2E Bit */ 00846 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E_MORT; 00847 00848 /* Get the TIMx CCER register value */ 00849 tmpccer = TIMx->CCER; 00850 /* Get the TIMx CR2 register value */ 00851 tmpcr2 = TIMx->CR2; 00852 00853 /* Get the TIMx CCMR2 register value */ 00854 tmpccmrx = TIMx->CCMR2; 00855 00856 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00857 tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M_MORT; 00858 tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S_MORT; 00859 /* Select the Output Compare Mode */ 00860 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 00861 00862 /* Reset the Output Polarity level */ 00863 tmpccer &= (uint16_t)~TIM_CCER_CC3P_MORT; 00864 /* Set the Output Compare Polarity */ 00865 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); 00866 00867 /* Set the Output State */ 00868 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); 00869 00870 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)) 00871 { 00872 assert_param(IS_TIM_OUTPUTN_STATE_MORT(TIM_OCInitStruct->TIM_OutputNState)); 00873 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCInitStruct->TIM_OCNPolarity)); 00874 assert_param(IS_TIM_OCNIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCNIdleState)); 00875 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState)); 00876 00877 /* Reset the Output N Polarity level */ 00878 tmpccer &= (uint16_t)~TIM_CCER_CC3NP_MORT; 00879 /* Set the Output N Polarity */ 00880 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); 00881 /* Reset the Output N State */ 00882 tmpccer &= (uint16_t)~TIM_CCER_CC3NE_MORT; 00883 00884 /* Set the Output N State */ 00885 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); 00886 /* Reset the Output Compare and Output Compare N IDLE State */ 00887 tmpcr2 &= (uint16_t)~TIM_CR2_OIS3_MORT; 00888 tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N_MORT; 00889 /* Set the Output Idle state */ 00890 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); 00891 /* Set the Output N Idle state */ 00892 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); 00893 } 00894 /* Write to TIMx CR2 */ 00895 TIMx->CR2 = tmpcr2; 00896 00897 /* Write to TIMx CCMR2 */ 00898 TIMx->CCMR2 = tmpccmrx; 00899 00900 /* Set the Capture Compare Register value */ 00901 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; 00902 00903 /* Write to TIMx CCER */ 00904 TIMx->CCER = tmpccer; 00905 } 00906 00907 /** 00908 * @brief Initializes the TIMx Channel4 according to the specified parameters 00909 * in the TIM_OCInitStruct. 00910 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 00911 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure that contains 00912 * the configuration information for the specified TIM peripheral. 00913 * @retval None 00914 */ 00915 void TIM_OC4Init_mort(TIM_TypeDef_mort* TIMx, TIM_OCInitTypeDef_mort* TIM_OCInitStruct) 00916 { 00917 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00918 00919 /* Check the parameters */ 00920 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 00921 assert_param(IS_TIM_OC_MODE_MORT(TIM_OCInitStruct->TIM_OCMode)); 00922 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00923 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00924 00925 /* Disable the Channel 4: Reset the CC4E Bit */ 00926 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E_MORT; 00927 00928 /* Get the TIMx CCER register value */ 00929 tmpccer = TIMx->CCER; 00930 /* Get the TIMx CR2 register value */ 00931 tmpcr2 = TIMx->CR2; 00932 00933 /* Get the TIMx CCMR2 register value */ 00934 tmpccmrx = TIMx->CCMR2; 00935 00936 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00937 tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M_MORT; 00938 tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S_MORT; 00939 00940 /* Select the Output Compare Mode */ 00941 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 00942 00943 /* Reset the Output Polarity level */ 00944 tmpccer &= (uint16_t)~TIM_CCER_CC4P_MORT; 00945 /* Set the Output Compare Polarity */ 00946 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); 00947 00948 /* Set the Output State */ 00949 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); 00950 00951 if((TIMx == TIM1_MORT) || (TIMx == TIM8_MORT)) 00952 { 00953 assert_param(IS_TIM_OCIDLE_STATE_MORT(TIM_OCInitStruct->TIM_OCIdleState)); 00954 /* Reset the Output Compare IDLE State */ 00955 tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4_MORT; 00956 /* Set the Output Idle state */ 00957 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); 00958 } 00959 /* Write to TIMx CR2 */ 00960 TIMx->CR2 = tmpcr2; 00961 00962 /* Write to TIMx CCMR2 */ 00963 TIMx->CCMR2 = tmpccmrx; 00964 00965 /* Set the Capture Compare Register value */ 00966 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; 00967 00968 /* Write to TIMx CCER */ 00969 TIMx->CCER = tmpccer; 00970 } 00971 00972 /** 00973 * @brief Fills each TIM_OCInitStruct member with its default value. 00974 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef_mort structure which will 00975 * be initialized. 00976 * @retval None 00977 */ 00978 void TIM_OCStructInit_mort(TIM_OCInitTypeDef_mort* TIM_OCInitStruct) 00979 { 00980 /* Set the default configuration */ 00981 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing_MORT; 00982 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable_MORT; 00983 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable_MORT; 00984 TIM_OCInitStruct->TIM_Pulse = 0x00000000; 00985 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High_MORT; 00986 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High_MORT; 00987 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset_MORT; 00988 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset_MORT; 00989 } 00990 00991 /** 00992 * @brief Selects the TIM Output Compare Mode. 00993 * @note This function disables the selected channel before changing the Output 00994 * Compare Mode. If needed, user has to enable this channel using 00995 * TIM_CCxCmd_mort() and TIM_CCxNCmd_mort() functions. 00996 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 00997 * @param TIM_Channel: specifies the TIM Channel 00998 * This parameter can be one of the following values: 00999 * @arg TIM_Channel_1_MORT: TIM Channel 1 01000 * @arg TIM_Channel_2_MORT: TIM Channel 2 01001 * @arg TIM_Channel_3_MORT: TIM Channel 3 01002 * @arg TIM_Channel_4_MORT: TIM Channel 4 01003 * @param TIM_OCMode: specifies the TIM Output Compare Mode. 01004 * This parameter can be one of the following values: 01005 * @arg TIM_OCMode_Timing_MORT 01006 * @arg TIM_OCMode_Active_MORT 01007 * @arg TIM_OCMode_Toggle 01008 * @arg TIM_OCMode_PWM1_MORT 01009 * @arg TIM_OCMode_PWM2_MORT 01010 * @arg TIM_ForcedAction_Active_MORT 01011 * @arg TIM_ForcedAction_InActive_MORT 01012 * @retval None 01013 */ 01014 void TIM_SelectOCxM_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) 01015 { 01016 uint32_t tmp = 0; 01017 uint16_t tmp1 = 0; 01018 01019 /* Check the parameters */ 01020 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01021 assert_param(IS_TIM_CHANNEL_MORT(TIM_Channel)); 01022 assert_param(IS_TIM_OCM_MORT(TIM_OCMode)); 01023 01024 tmp = (uint32_t) TIMx; 01025 tmp += CCMR_OFFSET_MORT; 01026 01027 tmp1 = CCER_CCE_SET_MORT << (uint16_t)TIM_Channel; 01028 01029 /* Disable the Channel: Reset the CCxE Bit */ 01030 TIMx->CCER &= (uint16_t) ~tmp1; 01031 01032 if((TIM_Channel == TIM_Channel_1_MORT) ||(TIM_Channel == TIM_Channel_3_MORT)) 01033 { 01034 tmp += (TIM_Channel>>1); 01035 01036 /* Reset the OCxM bits in the CCMRx register */ 01037 *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK_MORT; 01038 01039 /* Configure the OCxM bits in the CCMRx register */ 01040 *(__IO uint32_t *) tmp |= TIM_OCMode; 01041 } 01042 else 01043 { 01044 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; 01045 01046 /* Reset the OCxM bits in the CCMRx register */ 01047 *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK_MORT; 01048 01049 /* Configure the OCxM bits in the CCMRx register */ 01050 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); 01051 } 01052 } 01053 01054 /** 01055 * @brief Sets the TIMx Capture Compare1 Register value 01056 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01057 * @param Compare1: specifies the Capture Compare1 register new value. 01058 * @retval None 01059 */ 01060 void TIM_SetCompare1_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare1) 01061 { 01062 /* Check the parameters */ 01063 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01064 01065 /* Set the Capture Compare1 Register value */ 01066 TIMx->CCR1 = Compare1; 01067 } 01068 01069 /** 01070 * @brief Sets the TIMx Capture Compare2 Register value 01071 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 01072 * peripheral. 01073 * @param Compare2: specifies the Capture Compare2 register new value. 01074 * @retval None 01075 */ 01076 void TIM_SetCompare2_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare2) 01077 { 01078 /* Check the parameters */ 01079 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01080 01081 /* Set the Capture Compare2 Register value */ 01082 TIMx->CCR2 = Compare2; 01083 } 01084 01085 /** 01086 * @brief Sets the TIMx Capture Compare3 Register value 01087 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01088 * @param Compare3: specifies the Capture Compare3 register new value. 01089 * @retval None 01090 */ 01091 void TIM_SetCompare3_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare3) 01092 { 01093 /* Check the parameters */ 01094 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01095 01096 /* Set the Capture Compare3 Register value */ 01097 TIMx->CCR3 = Compare3; 01098 } 01099 01100 /** 01101 * @brief Sets the TIMx Capture Compare4 Register value 01102 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01103 * @param Compare4: specifies the Capture Compare4 register new value. 01104 * @retval None 01105 */ 01106 void TIM_SetCompare4_mort(TIM_TypeDef_mort* TIMx, uint32_t Compare4) 01107 { 01108 /* Check the parameters */ 01109 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01110 01111 /* Set the Capture Compare4 Register value */ 01112 TIMx->CCR4 = Compare4; 01113 } 01114 01115 /** 01116 * @brief Forces the TIMx output 1 waveform to active or inactive level. 01117 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01118 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01119 * This parameter can be one of the following values: 01120 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC1REF 01121 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC1REF. 01122 * @retval None 01123 */ 01124 void TIM_ForcedOC1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction) 01125 { 01126 uint16_t tmpccmr1 = 0; 01127 01128 /* Check the parameters */ 01129 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01130 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction)); 01131 tmpccmr1 = TIMx->CCMR1; 01132 01133 /* Reset the OC1M Bits */ 01134 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M_MORT; 01135 01136 /* Configure The Forced output Mode */ 01137 tmpccmr1 |= TIM_ForcedAction; 01138 01139 /* Write to TIMx CCMR1 register */ 01140 TIMx->CCMR1 = tmpccmr1; 01141 } 01142 01143 /** 01144 * @brief Forces the TIMx output 2 waveform to active or inactive level. 01145 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 01146 * peripheral. 01147 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01148 * This parameter can be one of the following values: 01149 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC2REF 01150 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC2REF. 01151 * @retval None 01152 */ 01153 void TIM_ForcedOC2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction) 01154 { 01155 uint16_t tmpccmr1 = 0; 01156 01157 /* Check the parameters */ 01158 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01159 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction)); 01160 tmpccmr1 = TIMx->CCMR1; 01161 01162 /* Reset the OC2M Bits */ 01163 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M_MORT; 01164 01165 /* Configure The Forced output Mode */ 01166 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); 01167 01168 /* Write to TIMx CCMR1 register */ 01169 TIMx->CCMR1 = tmpccmr1; 01170 } 01171 01172 /** 01173 * @brief Forces the TIMx output 3 waveform to active or inactive level. 01174 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01175 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01176 * This parameter can be one of the following values: 01177 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC3REF 01178 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC3REF. 01179 * @retval None 01180 */ 01181 void TIM_ForcedOC3Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction) 01182 { 01183 uint16_t tmpccmr2 = 0; 01184 01185 /* Check the parameters */ 01186 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01187 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction)); 01188 01189 tmpccmr2 = TIMx->CCMR2; 01190 01191 /* Reset the OC1M Bits */ 01192 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M_MORT; 01193 01194 /* Configure The Forced output Mode */ 01195 tmpccmr2 |= TIM_ForcedAction; 01196 01197 /* Write to TIMx CCMR2 register */ 01198 TIMx->CCMR2 = tmpccmr2; 01199 } 01200 01201 /** 01202 * @brief Forces the TIMx output 4 waveform to active or inactive level. 01203 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01204 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01205 * This parameter can be one of the following values: 01206 * @arg TIM_ForcedAction_Active_MORT: Force active level on OC4REF 01207 * @arg TIM_ForcedAction_InActive_MORT: Force inactive level on OC4REF. 01208 * @retval None 01209 */ 01210 void TIM_ForcedOC4Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ForcedAction) 01211 { 01212 uint16_t tmpccmr2 = 0; 01213 01214 /* Check the parameters */ 01215 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01216 assert_param(IS_TIM_FORCED_ACTION_MORT(TIM_ForcedAction)); 01217 tmpccmr2 = TIMx->CCMR2; 01218 01219 /* Reset the OC2M Bits */ 01220 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M_MORT; 01221 01222 /* Configure The Forced output Mode */ 01223 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); 01224 01225 /* Write to TIMx CCMR2 register */ 01226 TIMx->CCMR2 = tmpccmr2; 01227 } 01228 01229 /** 01230 * @brief Enables or disables the TIMx peripheral Preload register on CCR1. 01231 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01232 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01233 * This parameter can be one of the following values: 01234 * @arg TIM_OCPreload_Enable_MORT 01235 * @arg TIM_OCPreload_Disable_MORT 01236 * @retval None 01237 */ 01238 void TIM_OC1PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload) 01239 { 01240 uint16_t tmpccmr1 = 0; 01241 01242 /* Check the parameters */ 01243 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01244 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload)); 01245 01246 tmpccmr1 = TIMx->CCMR1; 01247 01248 /* Reset the OC1PE Bit */ 01249 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE_MORT); 01250 01251 /* Enable or Disable the Output Compare Preload feature */ 01252 tmpccmr1 |= TIM_OCPreload; 01253 01254 /* Write to TIMx CCMR1 register */ 01255 TIMx->CCMR1 = tmpccmr1; 01256 } 01257 01258 /** 01259 * @brief Enables or disables the TIMx peripheral Preload register on CCR2. 01260 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 01261 * peripheral. 01262 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01263 * This parameter can be one of the following values: 01264 * @arg TIM_OCPreload_Enable_MORT 01265 * @arg TIM_OCPreload_Disable_MORT 01266 * @retval None 01267 */ 01268 void TIM_OC2PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload) 01269 { 01270 uint16_t tmpccmr1 = 0; 01271 01272 /* Check the parameters */ 01273 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01274 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload)); 01275 01276 tmpccmr1 = TIMx->CCMR1; 01277 01278 /* Reset the OC2PE Bit */ 01279 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE_MORT); 01280 01281 /* Enable or Disable the Output Compare Preload feature */ 01282 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); 01283 01284 /* Write to TIMx CCMR1 register */ 01285 TIMx->CCMR1 = tmpccmr1; 01286 } 01287 01288 /** 01289 * @brief Enables or disables the TIMx peripheral Preload register on CCR3. 01290 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01291 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01292 * This parameter can be one of the following values: 01293 * @arg TIM_OCPreload_Enable_MORT 01294 * @arg TIM_OCPreload_Disable_MORT 01295 * @retval None 01296 */ 01297 void TIM_OC3PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload) 01298 { 01299 uint16_t tmpccmr2 = 0; 01300 01301 /* Check the parameters */ 01302 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01303 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload)); 01304 01305 tmpccmr2 = TIMx->CCMR2; 01306 01307 /* Reset the OC3PE Bit */ 01308 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE_MORT); 01309 01310 /* Enable or Disable the Output Compare Preload feature */ 01311 tmpccmr2 |= TIM_OCPreload; 01312 01313 /* Write to TIMx CCMR2 register */ 01314 TIMx->CCMR2 = tmpccmr2; 01315 } 01316 01317 /** 01318 * @brief Enables or disables the TIMx peripheral Preload register on CCR4. 01319 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01320 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01321 * This parameter can be one of the following values: 01322 * @arg TIM_OCPreload_Enable_MORT 01323 * @arg TIM_OCPreload_Disable_MORT 01324 * @retval None 01325 */ 01326 void TIM_OC4PreloadConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPreload) 01327 { 01328 uint16_t tmpccmr2 = 0; 01329 01330 /* Check the parameters */ 01331 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01332 assert_param(IS_TIM_OCPRELOAD_STATE_MORT(TIM_OCPreload)); 01333 01334 tmpccmr2 = TIMx->CCMR2; 01335 01336 /* Reset the OC4PE Bit */ 01337 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE_MORT); 01338 01339 /* Enable or Disable the Output Compare Preload feature */ 01340 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); 01341 01342 /* Write to TIMx CCMR2 register */ 01343 TIMx->CCMR2 = tmpccmr2; 01344 } 01345 01346 /** 01347 * @brief Configures the TIMx Output Compare 1 Fast feature. 01348 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01349 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01350 * This parameter can be one of the following values: 01351 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable 01352 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01353 * @retval None 01354 */ 01355 void TIM_OC1FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast) 01356 { 01357 uint16_t tmpccmr1 = 0; 01358 01359 /* Check the parameters */ 01360 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01361 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast)); 01362 01363 /* Get the TIMx CCMR1 register value */ 01364 tmpccmr1 = TIMx->CCMR1; 01365 01366 /* Reset the OC1FE Bit */ 01367 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE_MORT; 01368 01369 /* Enable or Disable the Output Compare Fast Bit */ 01370 tmpccmr1 |= TIM_OCFast; 01371 01372 /* Write to TIMx CCMR1 */ 01373 TIMx->CCMR1 = tmpccmr1; 01374 } 01375 01376 /** 01377 * @brief Configures the TIMx Output Compare 2 Fast feature. 01378 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 01379 * peripheral. 01380 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01381 * This parameter can be one of the following values: 01382 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable 01383 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01384 * @retval None 01385 */ 01386 void TIM_OC2FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast) 01387 { 01388 uint16_t tmpccmr1 = 0; 01389 01390 /* Check the parameters */ 01391 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01392 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast)); 01393 01394 /* Get the TIMx CCMR1 register value */ 01395 tmpccmr1 = TIMx->CCMR1; 01396 01397 /* Reset the OC2FE Bit */ 01398 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE_MORT); 01399 01400 /* Enable or Disable the Output Compare Fast Bit */ 01401 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); 01402 01403 /* Write to TIMx CCMR1 */ 01404 TIMx->CCMR1 = tmpccmr1; 01405 } 01406 01407 /** 01408 * @brief Configures the TIMx Output Compare 3 Fast feature. 01409 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01410 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01411 * This parameter can be one of the following values: 01412 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable 01413 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01414 * @retval None 01415 */ 01416 void TIM_OC3FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast) 01417 { 01418 uint16_t tmpccmr2 = 0; 01419 01420 /* Check the parameters */ 01421 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01422 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast)); 01423 01424 /* Get the TIMx CCMR2 register value */ 01425 tmpccmr2 = TIMx->CCMR2; 01426 01427 /* Reset the OC3FE Bit */ 01428 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE_MORT; 01429 01430 /* Enable or Disable the Output Compare Fast Bit */ 01431 tmpccmr2 |= TIM_OCFast; 01432 01433 /* Write to TIMx CCMR2 */ 01434 TIMx->CCMR2 = tmpccmr2; 01435 } 01436 01437 /** 01438 * @brief Configures the TIMx Output Compare 4 Fast feature. 01439 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01440 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01441 * This parameter can be one of the following values: 01442 * @arg TIM_OCFast_Enable_MORT: TIM output compare fast enable 01443 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01444 * @retval None 01445 */ 01446 void TIM_OC4FastConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCFast) 01447 { 01448 uint16_t tmpccmr2 = 0; 01449 01450 /* Check the parameters */ 01451 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01452 assert_param(IS_TIM_OCFAST_STATE_MORT(TIM_OCFast)); 01453 01454 /* Get the TIMx CCMR2 register value */ 01455 tmpccmr2 = TIMx->CCMR2; 01456 01457 /* Reset the OC4FE Bit */ 01458 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE_MORT); 01459 01460 /* Enable or Disable the Output Compare Fast Bit */ 01461 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); 01462 01463 /* Write to TIMx CCMR2 */ 01464 TIMx->CCMR2 = tmpccmr2; 01465 } 01466 01467 /** 01468 * @brief Clears or safeguards the OCREF1 signal on an external event 01469 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01470 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01471 * This parameter can be one of the following values: 01472 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable 01473 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable 01474 * @retval None 01475 */ 01476 void TIM_ClearOC1Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear) 01477 { 01478 uint16_t tmpccmr1 = 0; 01479 01480 /* Check the parameters */ 01481 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01482 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear)); 01483 01484 tmpccmr1 = TIMx->CCMR1; 01485 01486 /* Reset the OC1CE Bit */ 01487 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE_MORT; 01488 01489 /* Enable or Disable the Output Compare Clear Bit */ 01490 tmpccmr1 |= TIM_OCClear; 01491 01492 /* Write to TIMx CCMR1 register */ 01493 TIMx->CCMR1 = tmpccmr1; 01494 } 01495 01496 /** 01497 * @brief Clears or safeguards the OCREF2 signal on an external event 01498 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 01499 * peripheral. 01500 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01501 * This parameter can be one of the following values: 01502 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable 01503 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable 01504 * @retval None 01505 */ 01506 void TIM_ClearOC2Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear) 01507 { 01508 uint16_t tmpccmr1 = 0; 01509 01510 /* Check the parameters */ 01511 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01512 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear)); 01513 01514 tmpccmr1 = TIMx->CCMR1; 01515 01516 /* Reset the OC2CE Bit */ 01517 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE_MORT; 01518 01519 /* Enable or Disable the Output Compare Clear Bit */ 01520 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); 01521 01522 /* Write to TIMx CCMR1 register */ 01523 TIMx->CCMR1 = tmpccmr1; 01524 } 01525 01526 /** 01527 * @brief Clears or safeguards the OCREF3 signal on an external event 01528 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01529 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01530 * This parameter can be one of the following values: 01531 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable 01532 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable 01533 * @retval None 01534 */ 01535 void TIM_ClearOC3Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear) 01536 { 01537 uint16_t tmpccmr2 = 0; 01538 01539 /* Check the parameters */ 01540 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01541 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear)); 01542 01543 tmpccmr2 = TIMx->CCMR2; 01544 01545 /* Reset the OC3CE Bit */ 01546 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE_MORT; 01547 01548 /* Enable or Disable the Output Compare Clear Bit */ 01549 tmpccmr2 |= TIM_OCClear; 01550 01551 /* Write to TIMx CCMR2 register */ 01552 TIMx->CCMR2 = tmpccmr2; 01553 } 01554 01555 /** 01556 * @brief Clears or safeguards the OCREF4 signal on an external event 01557 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01558 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01559 * This parameter can be one of the following values: 01560 * @arg TIM_OCClear_Enable_MORT: TIM Output clear enable 01561 * @arg TIM_OCClear_Disable_MORT: TIM Output clear disable 01562 * @retval None 01563 */ 01564 void TIM_ClearOC4Ref_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCClear) 01565 { 01566 uint16_t tmpccmr2 = 0; 01567 01568 /* Check the parameters */ 01569 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01570 assert_param(IS_TIM_OCCLEAR_STATE_MORT(TIM_OCClear)); 01571 01572 tmpccmr2 = TIMx->CCMR2; 01573 01574 /* Reset the OC4CE Bit */ 01575 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE_MORT; 01576 01577 /* Enable or Disable the Output Compare Clear Bit */ 01578 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); 01579 01580 /* Write to TIMx CCMR2 register */ 01581 TIMx->CCMR2 = tmpccmr2; 01582 } 01583 01584 /** 01585 * @brief Configures the TIMx channel 1 polarity. 01586 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01587 * @param TIM_OCPolarity: specifies the OC1 Polarity 01588 * This parameter can be one of the following values: 01589 * @arg TIM_OCPolarity_High_MORT: Output Compare active high 01590 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low 01591 * @retval None 01592 */ 01593 void TIM_OC1PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity) 01594 { 01595 uint16_t tmpccer = 0; 01596 01597 /* Check the parameters */ 01598 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01599 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01600 01601 tmpccer = TIMx->CCER; 01602 01603 /* Set or Reset the CC1P Bit */ 01604 tmpccer &= (uint16_t)(~TIM_CCER_CC1P_MORT); 01605 tmpccer |= TIM_OCPolarity; 01606 01607 /* Write to TIMx CCER register */ 01608 TIMx->CCER = tmpccer; 01609 } 01610 01611 /** 01612 * @brief Configures the TIMx Channel 1N polarity. 01613 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01614 * @param TIM_OCNPolarity: specifies the OC1N Polarity 01615 * This parameter can be one of the following values: 01616 * @arg TIM_OCNPolarity_High_MORT: Output Compare active high 01617 * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low 01618 * @retval None 01619 */ 01620 void TIM_OC1NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity) 01621 { 01622 uint16_t tmpccer = 0; 01623 /* Check the parameters */ 01624 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 01625 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity)); 01626 01627 tmpccer = TIMx->CCER; 01628 01629 /* Set or Reset the CC1NP Bit */ 01630 tmpccer &= (uint16_t)~TIM_CCER_CC1NP_MORT; 01631 tmpccer |= TIM_OCNPolarity; 01632 01633 /* Write to TIMx CCER register */ 01634 TIMx->CCER = tmpccer; 01635 } 01636 01637 /** 01638 * @brief Configures the TIMx channel 2 polarity. 01639 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 01640 * peripheral. 01641 * @param TIM_OCPolarity: specifies the OC2 Polarity 01642 * This parameter can be one of the following values: 01643 * @arg TIM_OCPolarity_High_MORT: Output Compare active high 01644 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low 01645 * @retval None 01646 */ 01647 void TIM_OC2PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity) 01648 { 01649 uint16_t tmpccer = 0; 01650 01651 /* Check the parameters */ 01652 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01653 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01654 01655 tmpccer = TIMx->CCER; 01656 01657 /* Set or Reset the CC2P Bit */ 01658 tmpccer &= (uint16_t)(~TIM_CCER_CC2P_MORT); 01659 tmpccer |= (uint16_t)(TIM_OCPolarity << 4); 01660 01661 /* Write to TIMx CCER register */ 01662 TIMx->CCER = tmpccer; 01663 } 01664 01665 /** 01666 * @brief Configures the TIMx Channel 2N polarity. 01667 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01668 * @param TIM_OCNPolarity: specifies the OC2N Polarity 01669 * This parameter can be one of the following values: 01670 * @arg TIM_OCNPolarity_High_MORT: Output Compare active high 01671 * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low 01672 * @retval None 01673 */ 01674 void TIM_OC2NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity) 01675 { 01676 uint16_t tmpccer = 0; 01677 01678 /* Check the parameters */ 01679 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 01680 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity)); 01681 01682 tmpccer = TIMx->CCER; 01683 01684 /* Set or Reset the CC2NP Bit */ 01685 tmpccer &= (uint16_t)~TIM_CCER_CC2NP_MORT; 01686 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); 01687 01688 /* Write to TIMx CCER register */ 01689 TIMx->CCER = tmpccer; 01690 } 01691 01692 /** 01693 * @brief Configures the TIMx channel 3 polarity. 01694 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01695 * @param TIM_OCPolarity: specifies the OC3 Polarity 01696 * This parameter can be one of the following values: 01697 * @arg TIM_OCPolarity_High_MORT: Output Compare active high 01698 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low 01699 * @retval None 01700 */ 01701 void TIM_OC3PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity) 01702 { 01703 uint16_t tmpccer = 0; 01704 01705 /* Check the parameters */ 01706 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01707 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01708 01709 tmpccer = TIMx->CCER; 01710 01711 /* Set or Reset the CC3P Bit */ 01712 tmpccer &= (uint16_t)~TIM_CCER_CC3P_MORT; 01713 tmpccer |= (uint16_t)(TIM_OCPolarity << 8); 01714 01715 /* Write to TIMx CCER register */ 01716 TIMx->CCER = tmpccer; 01717 } 01718 01719 /** 01720 * @brief Configures the TIMx Channel 3N polarity. 01721 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01722 * @param TIM_OCNPolarity: specifies the OC3N Polarity 01723 * This parameter can be one of the following values: 01724 * @arg TIM_OCNPolarity_High_MORT: Output Compare active high 01725 * @arg TIM_OCNPolarity_Low_MORT: Output Compare active low 01726 * @retval None 01727 */ 01728 void TIM_OC3NPolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCNPolarity) 01729 { 01730 uint16_t tmpccer = 0; 01731 01732 /* Check the parameters */ 01733 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 01734 assert_param(IS_TIM_OCN_POLARITY_MORT(TIM_OCNPolarity)); 01735 01736 tmpccer = TIMx->CCER; 01737 01738 /* Set or Reset the CC3NP Bit */ 01739 tmpccer &= (uint16_t)~TIM_CCER_CC3NP_MORT; 01740 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); 01741 01742 /* Write to TIMx CCER register */ 01743 TIMx->CCER = tmpccer; 01744 } 01745 01746 /** 01747 * @brief Configures the TIMx channel 4 polarity. 01748 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01749 * @param TIM_OCPolarity: specifies the OC4 Polarity 01750 * This parameter can be one of the following values: 01751 * @arg TIM_OCPolarity_High_MORT: Output Compare active high 01752 * @arg TIM_OCPolarity_Low_MORT: Output Compare active low 01753 * @retval None 01754 */ 01755 void TIM_OC4PolarityConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_OCPolarity) 01756 { 01757 uint16_t tmpccer = 0; 01758 01759 /* Check the parameters */ 01760 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01761 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01762 01763 tmpccer = TIMx->CCER; 01764 01765 /* Set or Reset the CC4P Bit */ 01766 tmpccer &= (uint16_t)~TIM_CCER_CC4P_MORT; 01767 tmpccer |= (uint16_t)(TIM_OCPolarity << 12); 01768 01769 /* Write to TIMx CCER register */ 01770 TIMx->CCER = tmpccer; 01771 } 01772 01773 /** 01774 * @brief Enables or disables the TIM Capture Compare Channel x. 01775 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01776 * @param TIM_Channel: specifies the TIM Channel 01777 * This parameter can be one of the following values: 01778 * @arg TIM_Channel_1_MORT: TIM Channel 1 01779 * @arg TIM_Channel_2_MORT: TIM Channel 2 01780 * @arg TIM_Channel_3_MORT: TIM Channel 3 01781 * @arg TIM_Channel_4_MORT: TIM Channel 4 01782 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. 01783 * This parameter can be: TIM_CCx_Enable_MORT or TIM_CCx_Disable_MORT. 01784 * @retval None 01785 */ 01786 void TIM_CCxCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) 01787 { 01788 uint16_t tmp = 0; 01789 01790 /* Check the parameters */ 01791 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01792 assert_param(IS_TIM_CHANNEL_MORT(TIM_Channel)); 01793 assert_param(IS_TIM_CCX_MORT(TIM_CCx)); 01794 01795 tmp = CCER_CCE_SET_MORT << TIM_Channel; 01796 01797 /* Reset the CCxE Bit */ 01798 TIMx->CCER &= (uint16_t)~ tmp; 01799 01800 /* Set or reset the CCxE Bit */ 01801 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); 01802 } 01803 01804 /** 01805 * @brief Enables or disables the TIM Capture Compare Channel xN. 01806 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01807 * @param TIM_Channel: specifies the TIM Channel 01808 * This parameter can be one of the following values: 01809 * @arg TIM_Channel_1_MORT: TIM Channel 1 01810 * @arg TIM_Channel_2_MORT: TIM Channel 2 01811 * @arg TIM_Channel_3_MORT: TIM Channel 3 01812 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. 01813 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 01814 * @retval None 01815 */ 01816 void TIM_CCxNCmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) 01817 { 01818 uint16_t tmp = 0; 01819 01820 /* Check the parameters */ 01821 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 01822 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL_MORT(TIM_Channel)); 01823 assert_param(IS_TIM_CCXN_MORT(TIM_CCxN)); 01824 01825 tmp = CCER_CCNE_SET_MORT << TIM_Channel; 01826 01827 /* Reset the CCxNE Bit */ 01828 TIMx->CCER &= (uint16_t) ~tmp; 01829 01830 /* Set or reset the CCxNE Bit */ 01831 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); 01832 } 01833 /** 01834 * @} 01835 */ 01836 01837 /** @defgroup TIM_Group3 Input Capture management functions 01838 * @brief Input Capture management functions 01839 * 01840 @verbatim 01841 =============================================================================== 01842 ##### Input Capture management functions ##### 01843 =============================================================================== 01844 01845 ##### TIM Driver: how to use it in Input Capture Mode ##### 01846 =============================================================================== 01847 [..] 01848 To use the Timer in Input Capture mode, the following steps are mandatory: 01849 01850 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) 01851 function 01852 01853 (#) Configure the TIM pins by configuring the corresponding GPIO pins 01854 01855 (#) Configure the Time base unit as described in the first part of this driver, 01856 if needed, else the Timer will run with the default configuration: 01857 (++) Autoreload value = 0xFFFF 01858 (++) Prescaler value = 0x0000 01859 (++) Counter mode = Up counting 01860 (++) Clock Division = TIM_CKD_DIV1_MORT 01861 01862 (#) Fill the TIM_ICInitStruct with the desired parameters including: 01863 (++) TIM Channel: TIM_Channel 01864 (++) TIM Input Capture polarity: TIM_ICPolarity 01865 (++) TIM Input Capture selection: TIM_ICSelection 01866 (++) TIM Input Capture Prescaler: TIM_ICPrescaler 01867 (++) TIM Input Capture filter value: TIM_ICFilter 01868 01869 (#) Call TIM_ICInit_mort(TIMx, &TIM_ICInitStruct) to configure the desired channel 01870 with the corresponding configuration and to measure only frequency 01871 or duty cycle of the input signal, or, Call TIM_PWMIConfig_mort(TIMx, &TIM_ICInitStruct) 01872 to configure the desired channels with the corresponding configuration 01873 and to measure the frequency and the duty cycle of the input signal 01874 01875 (#) Enable the NVIC or the DMA to read the measured frequency. 01876 01877 (#) Enable the corresponding interrupt (or DMA request) to read the Captured 01878 value, using the function TIM_ITConfig_mort(TIMx, TIM_IT_CCx) 01879 (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 01880 01881 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 01882 01883 (#) Use TIM_GetCapturex(TIMx); to read the captured value. 01884 01885 -@- All other functions can be used separately to modify, if needed, 01886 a specific feature of the Timer. 01887 01888 @endverbatim 01889 * @{ 01890 */ 01891 01892 /** 01893 * @brief Initializes the TIM peripheral according to the specified parameters 01894 * in the TIM_ICInitStruct. 01895 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 01896 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure that contains 01897 * the configuration information for the specified TIM peripheral. 01898 * @retval None 01899 */ 01900 void TIM_ICInit_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct) 01901 { 01902 /* Check the parameters */ 01903 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 01904 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); 01905 assert_param(IS_TIM_IC_SELECTION_MORT(TIM_ICInitStruct->TIM_ICSelection)); 01906 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICInitStruct->TIM_ICPrescaler)); 01907 assert_param(IS_TIM_IC_FILTER_MORT(TIM_ICInitStruct->TIM_ICFilter)); 01908 01909 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1_MORT) 01910 { 01911 /* TI1 Configuration */ 01912 TI1_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 01913 TIM_ICInitStruct->TIM_ICSelection, 01914 TIM_ICInitStruct->TIM_ICFilter); 01915 /* Set the Input Capture Prescaler value */ 01916 TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 01917 } 01918 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2_MORT) 01919 { 01920 /* TI2 Configuration */ 01921 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01922 TI2_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 01923 TIM_ICInitStruct->TIM_ICSelection, 01924 TIM_ICInitStruct->TIM_ICFilter); 01925 /* Set the Input Capture Prescaler value */ 01926 TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 01927 } 01928 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3_MORT) 01929 { 01930 /* TI3 Configuration */ 01931 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01932 TI3_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 01933 TIM_ICInitStruct->TIM_ICSelection, 01934 TIM_ICInitStruct->TIM_ICFilter); 01935 /* Set the Input Capture Prescaler value */ 01936 TIM_SetIC3Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 01937 } 01938 else 01939 { 01940 /* TI4 Configuration */ 01941 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 01942 TI4_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 01943 TIM_ICInitStruct->TIM_ICSelection, 01944 TIM_ICInitStruct->TIM_ICFilter); 01945 /* Set the Input Capture Prescaler value */ 01946 TIM_SetIC4Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 01947 } 01948 } 01949 01950 /** 01951 * @brief Fills each TIM_ICInitStruct member with its default value. 01952 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure which will 01953 * be initialized. 01954 * @retval None 01955 */ 01956 void TIM_ICStructInit_mort(TIM_ICInitTypeDef_mort* TIM_ICInitStruct) 01957 { 01958 /* Set the default configuration */ 01959 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1_MORT; 01960 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising_MORT; 01961 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI_MORT; 01962 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1_MORT; 01963 TIM_ICInitStruct->TIM_ICFilter = 0x00; 01964 } 01965 01966 /** 01967 * @brief Configures the TIM peripheral according to the specified parameters 01968 * in the TIM_ICInitStruct to measure an external PWM signal. 01969 * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM 01970 * peripheral. 01971 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef_mort structure that contains 01972 * the configuration information for the specified TIM peripheral. 01973 * @retval None 01974 */ 01975 void TIM_PWMIConfig_mort(TIM_TypeDef_mort* TIMx, TIM_ICInitTypeDef_mort* TIM_ICInitStruct) 01976 { 01977 uint16_t icoppositepolarity = TIM_ICPolarity_Rising_MORT; 01978 uint16_t icoppositeselection = TIM_ICSelection_DirectTI_MORT; 01979 01980 /* Check the parameters */ 01981 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 01982 01983 /* Select the Opposite Input Polarity */ 01984 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising_MORT) 01985 { 01986 icoppositepolarity = TIM_ICPolarity_Falling_MORT; 01987 } 01988 else 01989 { 01990 icoppositepolarity = TIM_ICPolarity_Rising_MORT; 01991 } 01992 /* Select the Opposite Input */ 01993 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI_MORT) 01994 { 01995 icoppositeselection = TIM_ICSelection_IndirectTI_MORT; 01996 } 01997 else 01998 { 01999 icoppositeselection = TIM_ICSelection_DirectTI_MORT; 02000 } 02001 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1_MORT) 02002 { 02003 /* TI1 Configuration */ 02004 TI1_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 02005 TIM_ICInitStruct->TIM_ICFilter); 02006 /* Set the Input Capture Prescaler value */ 02007 TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02008 /* TI2 Configuration */ 02009 TI2_Config_mort(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 02010 /* Set the Input Capture Prescaler value */ 02011 TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02012 } 02013 else 02014 { 02015 /* TI2 Configuration */ 02016 TI2_Config_mort(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 02017 TIM_ICInitStruct->TIM_ICFilter); 02018 /* Set the Input Capture Prescaler value */ 02019 TIM_SetIC2Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02020 /* TI1 Configuration */ 02021 TI1_Config_mort(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 02022 /* Set the Input Capture Prescaler value */ 02023 TIM_SetIC1Prescaler_mort(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02024 } 02025 } 02026 02027 /** 02028 * @brief Gets the TIMx Input Capture 1 value. 02029 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 02030 * @retval Capture Compare 1 Register value. 02031 */ 02032 uint32_t TIM_GetCapture1_mort(TIM_TypeDef_mort* TIMx) 02033 { 02034 /* Check the parameters */ 02035 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 02036 02037 /* Get the Capture 1 Register value */ 02038 return TIMx->CCR1; 02039 } 02040 02041 /** 02042 * @brief Gets the TIMx Input Capture 2 value. 02043 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 02044 * peripheral. 02045 * @retval Capture Compare 2 Register value. 02046 */ 02047 uint32_t TIM_GetCapture2_mort(TIM_TypeDef_mort* TIMx) 02048 { 02049 /* Check the parameters */ 02050 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 02051 02052 /* Get the Capture 2 Register value */ 02053 return TIMx->CCR2; 02054 } 02055 02056 /** 02057 * @brief Gets the TIMx Input Capture 3 value. 02058 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02059 * @retval Capture Compare 3 Register value. 02060 */ 02061 uint32_t TIM_GetCapture3_mort(TIM_TypeDef_mort* TIMx) 02062 { 02063 /* Check the parameters */ 02064 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02065 02066 /* Get the Capture 3 Register value */ 02067 return TIMx->CCR3; 02068 } 02069 02070 /** 02071 * @brief Gets the TIMx Input Capture 4 value. 02072 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02073 * @retval Capture Compare 4 Register value. 02074 */ 02075 uint32_t TIM_GetCapture4_mort(TIM_TypeDef_mort* TIMx) 02076 { 02077 /* Check the parameters */ 02078 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02079 02080 /* Get the Capture 4 Register value */ 02081 return TIMx->CCR4; 02082 } 02083 02084 /** 02085 * @brief Sets the TIMx Input Capture 1 prescaler. 02086 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. 02087 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. 02088 * This parameter can be one of the following values: 02089 * @arg TIM_ICPSC_DIV1_MORT: no prescaler 02090 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events 02091 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events 02092 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events 02093 * @retval None 02094 */ 02095 void TIM_SetIC1Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC) 02096 { 02097 /* Check the parameters */ 02098 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 02099 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC)); 02100 02101 /* Reset the IC1PSC Bits */ 02102 TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC_MORT; 02103 02104 /* Set the IC1PSC value */ 02105 TIMx->CCMR1 |= TIM_ICPSC; 02106 } 02107 02108 /** 02109 * @brief Sets the TIMx Input Capture 2 prescaler. 02110 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 02111 * peripheral. 02112 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. 02113 * This parameter can be one of the following values: 02114 * @arg TIM_ICPSC_DIV1_MORT: no prescaler 02115 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events 02116 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events 02117 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events 02118 * @retval None 02119 */ 02120 void TIM_SetIC2Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC) 02121 { 02122 /* Check the parameters */ 02123 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 02124 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC)); 02125 02126 /* Reset the IC2PSC Bits */ 02127 TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC_MORT; 02128 02129 /* Set the IC2PSC value */ 02130 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); 02131 } 02132 02133 /** 02134 * @brief Sets the TIMx Input Capture 3 prescaler. 02135 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02136 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. 02137 * This parameter can be one of the following values: 02138 * @arg TIM_ICPSC_DIV1_MORT: no prescaler 02139 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events 02140 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events 02141 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events 02142 * @retval None 02143 */ 02144 void TIM_SetIC3Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC) 02145 { 02146 /* Check the parameters */ 02147 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02148 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC)); 02149 02150 /* Reset the IC3PSC Bits */ 02151 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC_MORT; 02152 02153 /* Set the IC3PSC value */ 02154 TIMx->CCMR2 |= TIM_ICPSC; 02155 } 02156 02157 /** 02158 * @brief Sets the TIMx Input Capture 4 prescaler. 02159 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02160 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. 02161 * This parameter can be one of the following values: 02162 * @arg TIM_ICPSC_DIV1_MORT: no prescaler 02163 * @arg TIM_ICPSC_DIV2_MORT: capture is done once every 2 events 02164 * @arg TIM_ICPSC_DIV4_MORT: capture is done once every 4 events 02165 * @arg TIM_ICPSC_DIV8_MORT: capture is done once every 8 events 02166 * @retval None 02167 */ 02168 void TIM_SetIC4Prescaler_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPSC) 02169 { 02170 /* Check the parameters */ 02171 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02172 assert_param(IS_TIM_IC_PRESCALER_MORT(TIM_ICPSC)); 02173 02174 /* Reset the IC4PSC Bits */ 02175 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC_MORT; 02176 02177 /* Set the IC4PSC value */ 02178 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); 02179 } 02180 /** 02181 * @} 02182 */ 02183 02184 /** @defgroup TIM_Group4 Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features 02185 * @brief Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features 02186 * 02187 @verbatim 02188 =============================================================================== 02189 ##### Advanced-control timers (TIM1_MORT and TIM8_MORT) specific features ##### 02190 =============================================================================== 02191 02192 ##### TIM Driver: how to use the Break feature ##### 02193 =============================================================================== 02194 [..] 02195 After configuring the Timer channel(s) in the appropriate Output Compare mode: 02196 02197 (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer 02198 Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 02199 AOE(automatic output enable). 02200 02201 (#) Call TIM_BDTRConfig_mort(TIMx, &TIM_BDTRInitStruct) to configure the Timer 02202 02203 (#) Enable the Main Output using TIM_CtrlPWMOutputs_mort(TIM1_MORT, ENABLE) 02204 02205 (#) Once the break even occurs, the Timer's output signals are put in reset 02206 state or in a known state (according to the configuration made in 02207 TIM_BDTRConfig_mort() function). 02208 02209 @endverbatim 02210 * @{ 02211 */ 02212 02213 /** 02214 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State 02215 * and the AOE(automatic output enable). 02216 * @param TIMx: where x can be 1 or 8 to select the TIM 02217 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef_mort structure that 02218 * contains the BDTR Register configuration information for the TIM peripheral. 02219 * @retval None 02220 */ 02221 void TIM_BDTRConfig_mort(TIM_TypeDef_mort* TIMx, TIM_BDTRInitTypeDef_mort *TIM_BDTRInitStruct) 02222 { 02223 /* Check the parameters */ 02224 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 02225 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); 02226 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); 02227 assert_param(IS_TIM_LOCK_LEVEL_MORT(TIM_BDTRInitStruct->TIM_LOCKLevel)); 02228 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); 02229 assert_param(IS_TIM_BREAK_POLARITY_MORT(TIM_BDTRInitStruct->TIM_BreakPolarity)); 02230 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE_MORT(TIM_BDTRInitStruct->TIM_AutomaticOutput)); 02231 02232 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, 02233 the OSSI State, the dead time value and the Automatic Output Enable Bit */ 02234 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 02235 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | 02236 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | 02237 TIM_BDTRInitStruct->TIM_AutomaticOutput; 02238 } 02239 02240 /** 02241 * @brief Fills each TIM_BDTRInitStruct member with its default value. 02242 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef_mort structure which 02243 * will be initialized. 02244 * @retval None 02245 */ 02246 void TIM_BDTRStructInit_mort(TIM_BDTRInitTypeDef_mort* TIM_BDTRInitStruct) 02247 { 02248 /* Set the default configuration */ 02249 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable_MORT; 02250 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable_MORT; 02251 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF_MORT; 02252 TIM_BDTRInitStruct->TIM_DeadTime = 0x00; 02253 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable_MORT; 02254 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low_MORT; 02255 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable_MORT; 02256 } 02257 02258 /** 02259 * @brief Enables or disables the TIM peripheral Main Outputs. 02260 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. 02261 * @param NewState: new state of the TIM peripheral Main Outputs. 02262 * This parameter can be: ENABLE or DISABLE. 02263 * @retval None 02264 */ 02265 void TIM_CtrlPWMOutputs_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 02266 { 02267 /* Check the parameters */ 02268 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 02269 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02270 02271 if (NewState != DISABLE) 02272 { 02273 /* Enable the TIM Main Output */ 02274 TIMx->BDTR |= TIM_BDTR_MOE_MORT; 02275 } 02276 else 02277 { 02278 /* Disable the TIM Main Output */ 02279 TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE_MORT; 02280 } 02281 } 02282 02283 /** 02284 * @brief Selects the TIM peripheral Commutation event. 02285 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral 02286 * @param NewState: new state of the Commutation event. 02287 * This parameter can be: ENABLE or DISABLE. 02288 * @retval None 02289 */ 02290 void TIM_SelectCOM_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 02291 { 02292 /* Check the parameters */ 02293 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 02294 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02295 02296 if (NewState != DISABLE) 02297 { 02298 /* Set the COM Bit */ 02299 TIMx->CR2 |= TIM_CR2_CCUS_MORT; 02300 } 02301 else 02302 { 02303 /* Reset the COM Bit */ 02304 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS_MORT; 02305 } 02306 } 02307 02308 /** 02309 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. 02310 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral 02311 * @param NewState: new state of the Capture Compare Preload Control bit 02312 * This parameter can be: ENABLE or DISABLE. 02313 * @retval None 02314 */ 02315 void TIM_CCPreloadControl_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 02316 { 02317 /* Check the parameters */ 02318 assert_param(IS_TIM_LIST4_PERIPH_MORT(TIMx)); 02319 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02320 if (NewState != DISABLE) 02321 { 02322 /* Set the CCPC Bit */ 02323 TIMx->CR2 |= TIM_CR2_CCPC_MORT; 02324 } 02325 else 02326 { 02327 /* Reset the CCPC Bit */ 02328 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC_MORT; 02329 } 02330 } 02331 /** 02332 * @} 02333 */ 02334 02335 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions 02336 * @brief Interrupts, DMA and flags management functions 02337 * 02338 @verbatim 02339 =============================================================================== 02340 ##### Interrupts, DMA and flags management functions ##### 02341 =============================================================================== 02342 02343 @endverbatim 02344 * @{ 02345 */ 02346 02347 /** 02348 * @brief Enables or disables the specified TIM interrupts. 02349 * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. 02350 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. 02351 * This parameter can be any combination of the following values: 02352 * @arg TIM_IT_Update_MORT: TIM update Interrupt source 02353 * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source 02354 * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source 02355 * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source 02356 * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source 02357 * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source 02358 * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source 02359 * @arg TIM_IT_Break_MORT: TIM Break Interrupt source 02360 * 02361 * @note For TIM6_MORT and TIM7_MORT only the parameter TIM_IT_Update_MORT can be used 02362 * @note For TIM9_MORT and TIM12_MORT only one of the following parameters can be used: TIM_IT_Update_MORT, 02363 * TIM_IT_CC1_MORT, TIM_IT_CC2_MORT or TIM_IT_Trigger_MORT. 02364 * @note For TIM10_MORT, TIM11_MORT, TIM13_MORT and TIM14_MORT only one of the following parameters can 02365 * be used: TIM_IT_Update_MORT or TIM_IT_CC1_MORT 02366 * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT can be used only with TIM1_MORT and TIM8_MORT 02367 * 02368 * @param NewState: new state of the TIM interrupts. 02369 * This parameter can be: ENABLE or DISABLE. 02370 * @retval None 02371 */ 02372 void TIM_ITConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT, FunctionalState NewState) 02373 { 02374 /* Check the parameters */ 02375 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 02376 assert_param(IS_TIM_IT_MORT(TIM_IT)); 02377 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02378 02379 if (NewState != DISABLE) 02380 { 02381 /* Enable the Interrupt sources */ 02382 TIMx->DIER |= TIM_IT; 02383 } 02384 else 02385 { 02386 /* Disable the Interrupt sources */ 02387 TIMx->DIER &= (uint16_t)~TIM_IT; 02388 } 02389 } 02390 02391 /** 02392 * @brief Configures the TIMx event to be generate by software. 02393 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 02394 * @param TIM_EventSource: specifies the event source. 02395 * This parameter can be one or more of the following values: 02396 * @arg TIM_EventSource_Update_MORT: Timer update Event source 02397 * @arg TIM_EventSource_CC1_MORT: Timer Capture Compare 1 Event source 02398 * @arg TIM_EventSource_CC2_MORT: Timer Capture Compare 2 Event source 02399 * @arg TIM_EventSource_CC3_MORT: Timer Capture Compare 3 Event source 02400 * @arg TIM_EventSource_CC4_MORT: Timer Capture Compare 4 Event source 02401 * @arg TIM_EventSource_COM_MORT: Timer COM event source 02402 * @arg TIM_EventSource_Trigger_MORT: Timer Trigger Event source 02403 * @arg TIM_EventSource_Break_MORT: Timer Break event source 02404 * 02405 * @note TIM6_MORT and TIM7_MORT can only generate an update event. 02406 * @note TIM_EventSource_COM_MORT and TIM_EventSource_Break_MORT are used only with TIM1_MORT and TIM8_MORT. 02407 * 02408 * @retval None 02409 */ 02410 void TIM_GenerateEvent_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EventSource) 02411 { 02412 /* Check the parameters */ 02413 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 02414 assert_param(IS_TIM_EVENT_SOURCE_MORT(TIM_EventSource)); 02415 02416 /* Set the event sources */ 02417 TIMx->EGR = TIM_EventSource; 02418 } 02419 02420 /** 02421 * @brief Checks whether the specified TIM flag is set or not. 02422 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 02423 * @param TIM_FLAG: specifies the flag to check. 02424 * This parameter can be one of the following values: 02425 * @arg TIM_FLAG_Update_MORT: TIM update Flag 02426 * @arg TIM_FLAG_CC1_MORT: TIM Capture Compare 1 Flag 02427 * @arg TIM_FLAG_CC2_MORT: TIM Capture Compare 2 Flag 02428 * @arg TIM_FLAG_CC3_MORT: TIM Capture Compare 3 Flag 02429 * @arg TIM_FLAG_CC4_MORT: TIM Capture Compare 4 Flag 02430 * @arg TIM_FLAG_COM_MORT: TIM Commutation Flag 02431 * @arg TIM_FLAG_Trigger_MORT: TIM Trigger Flag 02432 * @arg TIM_FLAG_Break_MORT: TIM Break Flag 02433 * @arg TIM_FLAG_CC1OF_MORT: TIM Capture Compare 1 over capture Flag 02434 * @arg TIM_FLAG_CC2OF_MORT: TIM Capture Compare 2 over capture Flag 02435 * @arg TIM_FLAG_CC3OF_MORT: TIM Capture Compare 3 over capture Flag 02436 * @arg TIM_FLAG_CC4OF_MORT: TIM Capture Compare 4 over capture Flag 02437 * 02438 * @note TIM6_MORT and TIM7_MORT can have only one update flag. 02439 * @note TIM_FLAG_COM_MORT and TIM_FLAG_Break_MORT are used only with TIM1_MORT and TIM8_MORT. 02440 * 02441 * @retval The new state of TIM_FLAG (SET or RESET). 02442 */ 02443 FlagStatus TIM_GetFlagStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG) 02444 { 02445 ITStatus bitstatus = RESET; 02446 /* Check the parameters */ 02447 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 02448 assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); 02449 02450 02451 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) 02452 { 02453 bitstatus = SET; 02454 } 02455 else 02456 { 02457 bitstatus = RESET; 02458 } 02459 return bitstatus; 02460 } 02461 02462 /** 02463 * @brief Clears the TIMx's pending flags. 02464 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 02465 * @param TIM_FLAG: specifies the flag bit to clear. 02466 * This parameter can be any combination of the following values: 02467 * @arg TIM_FLAG_Update_MORT: TIM update Flag 02468 * @arg TIM_FLAG_CC1_MORT: TIM Capture Compare 1 Flag 02469 * @arg TIM_FLAG_CC2_MORT: TIM Capture Compare 2 Flag 02470 * @arg TIM_FLAG_CC3_MORT: TIM Capture Compare 3 Flag 02471 * @arg TIM_FLAG_CC4_MORT: TIM Capture Compare 4 Flag 02472 * @arg TIM_FLAG_COM_MORT: TIM Commutation Flag 02473 * @arg TIM_FLAG_Trigger_MORT: TIM Trigger Flag 02474 * @arg TIM_FLAG_Break_MORT: TIM Break Flag 02475 * @arg TIM_FLAG_CC1OF_MORT: TIM Capture Compare 1 over capture Flag 02476 * @arg TIM_FLAG_CC2OF_MORT: TIM Capture Compare 2 over capture Flag 02477 * @arg TIM_FLAG_CC3OF_MORT: TIM Capture Compare 3 over capture Flag 02478 * @arg TIM_FLAG_CC4OF_MORT: TIM Capture Compare 4 over capture Flag 02479 * 02480 * @note TIM6_MORT and TIM7_MORT can have only one update flag. 02481 * @note TIM_FLAG_COM_MORT and TIM_FLAG_Break_MORT are used only with TIM1_MORT and TIM8_MORT. 02482 * 02483 * @retval None 02484 */ 02485 void TIM_ClearFlag_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_FLAG) 02486 { 02487 /* Check the parameters */ 02488 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 02489 02490 /* Clear the flags */ 02491 TIMx->SR = (uint16_t)~TIM_FLAG; 02492 } 02493 02494 /** 02495 * @brief Checks whether the TIM interrupt has occurred or not. 02496 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 02497 * @param TIM_IT: specifies the TIM interrupt source to check. 02498 * This parameter can be one of the following values: 02499 * @arg TIM_IT_Update_MORT: TIM update Interrupt source 02500 * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source 02501 * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source 02502 * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source 02503 * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source 02504 * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source 02505 * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source 02506 * @arg TIM_IT_Break_MORT: TIM Break Interrupt source 02507 * 02508 * @note TIM6_MORT and TIM7_MORT can generate only an update interrupt. 02509 * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT are used only with TIM1_MORT and TIM8_MORT. 02510 * 02511 * @retval The new state of the TIM_IT(SET or RESET). 02512 */ 02513 ITStatus TIM_GetITStatus_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT) 02514 { 02515 ITStatus bitstatus = RESET; 02516 uint16_t itstatus = 0x0, itenable = 0x0; 02517 /* Check the parameters */ 02518 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 02519 assert_param(IS_TIM_GET_IT_MORT(TIM_IT)); 02520 02521 itstatus = TIMx->SR & TIM_IT; 02522 02523 itenable = TIMx->DIER & TIM_IT; 02524 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 02525 { 02526 bitstatus = SET; 02527 } 02528 else 02529 { 02530 bitstatus = RESET; 02531 } 02532 return bitstatus; 02533 } 02534 02535 /** 02536 * @brief Clears the TIMx's interrupt pending bits. 02537 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. 02538 * @param TIM_IT: specifies the pending bit to clear. 02539 * This parameter can be any combination of the following values: 02540 * @arg TIM_IT_Update_MORT: TIM1_MORT update Interrupt source 02541 * @arg TIM_IT_CC1_MORT: TIM Capture Compare 1 Interrupt source 02542 * @arg TIM_IT_CC2_MORT: TIM Capture Compare 2 Interrupt source 02543 * @arg TIM_IT_CC3_MORT: TIM Capture Compare 3 Interrupt source 02544 * @arg TIM_IT_CC4_MORT: TIM Capture Compare 4 Interrupt source 02545 * @arg TIM_IT_COM_MORT: TIM Commutation Interrupt source 02546 * @arg TIM_IT_Trigger_MORT: TIM Trigger Interrupt source 02547 * @arg TIM_IT_Break_MORT: TIM Break Interrupt source 02548 * 02549 * @note TIM6_MORT and TIM7_MORT can generate only an update interrupt. 02550 * @note TIM_IT_COM_MORT and TIM_IT_Break_MORT are used only with TIM1_MORT and TIM8_MORT. 02551 * 02552 * @retval None 02553 */ 02554 void TIM_ClearITPendingBit_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_IT) 02555 { 02556 /* Check the parameters */ 02557 assert_param(IS_TIM_ALL_PERIPH_MORT(TIMx)); 02558 02559 /* Clear the IT pending Bit */ 02560 TIMx->SR = (uint16_t)~TIM_IT; 02561 } 02562 02563 /** 02564 * @brief Configures the TIMx's DMA interface. 02565 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02566 * @param TIM_DMABase: DMA Base address. 02567 * This parameter can be one of the following values: 02568 * @arg TIM_DMABase_CR1_MORT 02569 * @arg TIM_DMABase_CR2_MORT 02570 * @arg TIM_DMABase_SMCR_MORT 02571 * @arg TIM_DMABase_DIER_MORT 02572 * @arg TIM1_DMABase_SR 02573 * @arg TIM_DMABase_EGR_MORT 02574 * @arg TIM_DMABase_CCMR1_MORT 02575 * @arg TIM_DMABase_CCMR2_MORT 02576 * @arg TIM_DMABase_CCER_MORT 02577 * @arg TIM_DMABase_CNT_MORT 02578 * @arg TIM_DMABase_PSC_MORT 02579 * @arg TIM_DMABase_ARR 02580 * @arg TIM_DMABase_RCR_MORT 02581 * @arg TIM_DMABase_CCR1_MORT 02582 * @arg TIM_DMABase_CCR2_MORT 02583 * @arg TIM_DMABase_CCR3_MORT 02584 * @arg TIM_DMABase_CCR4_MORT 02585 * @arg TIM_DMABase_BDTR_MORT 02586 * @arg TIM_DMABase_DCR_MORT 02587 * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value 02588 * between: TIM_DMABurstLength_1Transfer_MORT and TIM_DMABurstLength_18Transfers_MORT. 02589 * @retval None 02590 */ 02591 void TIM_DMAConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) 02592 { 02593 /* Check the parameters */ 02594 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02595 assert_param(IS_TIM_DMA_BASE_MORT(TIM_DMABase)); 02596 assert_param(IS_TIM_DMA_LENGTH_MORT(TIM_DMABurstLength)); 02597 02598 /* Set the DMA Base and the DMA Burst Length */ 02599 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; 02600 } 02601 02602 /** 02603 * @brief Enables or disables the TIMx's DMA Requests. 02604 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. 02605 * @param TIM_DMASource: specifies the DMA Request sources. 02606 * This parameter can be any combination of the following values: 02607 * @arg TIM_DMA_Update_MORT: TIM update Interrupt source 02608 * @arg TIM_DMA_CC1_MORT: TIM Capture Compare 1 DMA source 02609 * @arg TIM_DMA_CC2_MORT: TIM Capture Compare 2 DMA source 02610 * @arg TIM_DMA_CC3_MORT: TIM Capture Compare 3 DMA source 02611 * @arg TIM_DMA_CC4_MORT: TIM Capture Compare 4 DMA source 02612 * @arg TIM_DMA_COM_MORT: TIM Commutation DMA source 02613 * @arg TIM_DMA_Trigger_MORT: TIM Trigger DMA source 02614 * @param NewState: new state of the DMA Request sources. 02615 * This parameter can be: ENABLE or DISABLE. 02616 * @retval None 02617 */ 02618 void TIM_DMACmd_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) 02619 { 02620 /* Check the parameters */ 02621 assert_param(IS_TIM_LIST5_PERIPH_MORT(TIMx)); 02622 assert_param(IS_TIM_DMA_SOURCE_MORT(TIM_DMASource)); 02623 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02624 02625 if (NewState != DISABLE) 02626 { 02627 /* Enable the DMA sources */ 02628 TIMx->DIER |= TIM_DMASource; 02629 } 02630 else 02631 { 02632 /* Disable the DMA sources */ 02633 TIMx->DIER &= (uint16_t)~TIM_DMASource; 02634 } 02635 } 02636 02637 /** 02638 * @brief Selects the TIMx peripheral Capture Compare DMA source. 02639 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02640 * @param NewState: new state of the Capture Compare DMA source 02641 * This parameter can be: ENABLE or DISABLE. 02642 * @retval None 02643 */ 02644 void TIM_SelectCCDMA_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 02645 { 02646 /* Check the parameters */ 02647 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02648 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02649 02650 if (NewState != DISABLE) 02651 { 02652 /* Set the CCDS Bit */ 02653 TIMx->CR2 |= TIM_CR2_CCDS_MORT; 02654 } 02655 else 02656 { 02657 /* Reset the CCDS Bit */ 02658 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS_MORT; 02659 } 02660 } 02661 /** 02662 * @} 02663 */ 02664 02665 /** @defgroup TIM_Group6 Clocks management functions 02666 * @brief Clocks management functions 02667 * 02668 @verbatim 02669 =============================================================================== 02670 ##### Clocks management functions ##### 02671 =============================================================================== 02672 02673 @endverbatim 02674 * @{ 02675 */ 02676 02677 /** 02678 * @brief Configures the TIMx internal Clock 02679 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 02680 * peripheral. 02681 * @retval None 02682 */ 02683 void TIM_InternalClockConfig_mort(TIM_TypeDef_mort* TIMx) 02684 { 02685 /* Check the parameters */ 02686 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 02687 02688 /* Disable slave mode to clock the prescaler directly with the internal clock */ 02689 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS_MORT; 02690 } 02691 02692 /** 02693 * @brief Configures the TIMx Internal Trigger as External Clock 02694 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 02695 * peripheral. 02696 * @param TIM_InputTriggerSource: Trigger source. 02697 * This parameter can be one of the following values: 02698 * @arg TIM_TS_ITR0_MORT: Internal Trigger 0 02699 * @arg TIM_TS_ITR1_MORT: Internal Trigger 1 02700 * @arg TIM_TS_ITR2_MORT: Internal Trigger 2 02701 * @arg TIM_TS_ITR3_MORT: Internal Trigger 3 02702 * @retval None 02703 */ 02704 void TIM_ITRxExternalClockConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource) 02705 { 02706 /* Check the parameters */ 02707 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 02708 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION_MORT(TIM_InputTriggerSource)); 02709 02710 /* Select the Internal Trigger */ 02711 TIM_SelectInputTrigger_mort(TIMx, TIM_InputTriggerSource); 02712 02713 /* Select the External clock mode1 */ 02714 TIMx->SMCR |= TIM_SlaveMode_External1_MORT; 02715 } 02716 02717 /** 02718 * @brief Configures the TIMx Trigger as External Clock 02719 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 02720 * to select the TIM peripheral. 02721 * @param TIM_TIxExternalCLKSource: Trigger source. 02722 * This parameter can be one of the following values: 02723 * @arg TIM_TIxExternalCLK1Source_TI1ED_MORT: TI1 Edge Detector 02724 * @arg TIM_TIxExternalCLK1Source_TI1_MORT: Filtered Timer Input 1 02725 * @arg TIM_TIxExternalCLK1Source_TI2_MORT: Filtered Timer Input 2 02726 * @param TIM_ICPolarity: specifies the TIx Polarity. 02727 * This parameter can be one of the following values: 02728 * @arg TIM_ICPolarity_Rising_MORT 02729 * @arg TIM_ICPolarity_Falling_MORT 02730 * @param ICFilter: specifies the filter value. 02731 * This parameter must be a value between 0x0 and 0xF. 02732 * @retval None 02733 */ 02734 void TIM_TIxExternalClockConfig(TIM_TypeDef_mort* TIMx, uint16_t TIM_TIxExternalCLKSource, 02735 uint16_t TIM_ICPolarity, uint16_t ICFilter) 02736 { 02737 /* Check the parameters */ 02738 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 02739 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); 02740 assert_param(IS_TIM_IC_FILTER_MORT(ICFilter)); 02741 02742 /* Configure the Timer Input Clock Source */ 02743 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2_MORT) 02744 { 02745 TI2_Config_mort(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI_MORT, ICFilter); 02746 } 02747 else 02748 { 02749 TI1_Config_mort(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI_MORT, ICFilter); 02750 } 02751 /* Select the Trigger source */ 02752 TIM_SelectInputTrigger_mort(TIMx, TIM_TIxExternalCLKSource); 02753 /* Select the External clock mode1 */ 02754 TIMx->SMCR |= TIM_SlaveMode_External1_MORT; 02755 } 02756 02757 /** 02758 * @brief Configures the External clock Mode1 02759 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02760 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 02761 * This parameter can be one of the following values: 02762 * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF. 02763 * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2. 02764 * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4. 02765 * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8. 02766 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 02767 * This parameter can be one of the following values: 02768 * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active. 02769 * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active. 02770 * @param ExtTRGFilter: External Trigger Filter. 02771 * This parameter must be a value between 0x00 and 0x0F 02772 * @retval None 02773 */ 02774 void TIM_ETRClockMode1Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, 02775 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 02776 { 02777 uint16_t tmpsmcr = 0; 02778 02779 /* Check the parameters */ 02780 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02781 assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler)); 02782 assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity)); 02783 assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter)); 02784 /* Configure the ETR Clock source */ 02785 TIM_ETRConfig_mort(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 02786 02787 /* Get the TIMx SMCR register value */ 02788 tmpsmcr = TIMx->SMCR; 02789 02790 /* Reset the SMS Bits */ 02791 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS_MORT; 02792 02793 /* Select the External clock mode1 */ 02794 tmpsmcr |= TIM_SlaveMode_External1_MORT; 02795 02796 /* Select the Trigger selection : ETRF */ 02797 tmpsmcr &= (uint16_t)~TIM_SMCR_TS_MORT; 02798 tmpsmcr |= TIM_TS_ETRF_MORT; 02799 02800 /* Write to TIMx SMCR */ 02801 TIMx->SMCR = tmpsmcr; 02802 } 02803 02804 /** 02805 * @brief Configures the External clock Mode2 02806 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02807 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 02808 * This parameter can be one of the following values: 02809 * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF. 02810 * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2. 02811 * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4. 02812 * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8. 02813 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 02814 * This parameter can be one of the following values: 02815 * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active. 02816 * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active. 02817 * @param ExtTRGFilter: External Trigger Filter. 02818 * This parameter must be a value between 0x00 and 0x0F 02819 * @retval None 02820 */ 02821 void TIM_ETRClockMode2Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, 02822 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 02823 { 02824 /* Check the parameters */ 02825 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 02826 assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler)); 02827 assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity)); 02828 assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter)); 02829 02830 /* Configure the ETR Clock source */ 02831 TIM_ETRConfig_mort(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 02832 02833 /* Enable the External clock mode2 */ 02834 TIMx->SMCR |= TIM_SMCR_ECE_MORT; 02835 } 02836 /** 02837 * @} 02838 */ 02839 02840 /** @defgroup TIM_Group7 Synchronization management functions 02841 * @brief Synchronization management functions 02842 * 02843 @verbatim 02844 =============================================================================== 02845 ##### Synchronization management functions ##### 02846 =============================================================================== 02847 02848 ##### TIM Driver: how to use it in synchronization Mode ##### 02849 =============================================================================== 02850 [..] 02851 02852 *** Case of two/several Timers *** 02853 ================================== 02854 [..] 02855 (#) Configure the Master Timers using the following functions: 02856 (++) void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource); 02857 (++) void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode); 02858 (#) Configure the Slave Timers using the following functions: 02859 (++) void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource); 02860 (++) void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode); 02861 02862 *** Case of Timers and external trigger(ETR pin) *** 02863 ==================================================== 02864 [..] 02865 (#) Configure the External trigger using this function: 02866 (++) void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 02867 uint16_t ExtTRGFilter); 02868 (#) Configure the Slave Timers using the following functions: 02869 (++) void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource); 02870 (++) void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode); 02871 02872 @endverbatim 02873 * @{ 02874 */ 02875 02876 /** 02877 * @brief Selects the Input Trigger source 02878 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 02879 * to select the TIM peripheral. 02880 * @param TIM_InputTriggerSource: The Input Trigger source. 02881 * This parameter can be one of the following values: 02882 * @arg TIM_TS_ITR0_MORT: Internal Trigger 0 02883 * @arg TIM_TS_ITR1_MORT: Internal Trigger 1 02884 * @arg TIM_TS_ITR2_MORT: Internal Trigger 2 02885 * @arg TIM_TS_ITR3_MORT: Internal Trigger 3 02886 * @arg TIM_TS_TI1F_ED_MORT: TI1 Edge Detector 02887 * @arg TIM_TS_TI1FP1_MORT: Filtered Timer Input 1 02888 * @arg TIM_TS_TI2FP2_MORT: Filtered Timer Input 2 02889 * @arg TIM_TS_ETRF_MORT: External Trigger input 02890 * @retval None 02891 */ 02892 void TIM_SelectInputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_InputTriggerSource) 02893 { 02894 uint16_t tmpsmcr = 0; 02895 02896 /* Check the parameters */ 02897 assert_param(IS_TIM_LIST1_PERIPH_MORT(TIMx)); 02898 assert_param(IS_TIM_TRIGGER_SELECTION_MORT(TIM_InputTriggerSource)); 02899 02900 /* Get the TIMx SMCR register value */ 02901 tmpsmcr = TIMx->SMCR; 02902 02903 /* Reset the TS Bits */ 02904 tmpsmcr &= (uint16_t)~TIM_SMCR_TS_MORT; 02905 02906 /* Set the Input Trigger source */ 02907 tmpsmcr |= TIM_InputTriggerSource; 02908 02909 /* Write to TIMx SMCR */ 02910 TIMx->SMCR = tmpsmcr; 02911 } 02912 02913 /** 02914 * @brief Selects the TIMx Trigger Output Mode. 02915 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. 02916 * 02917 * @param TIM_TRGOSource: specifies the Trigger Output source. 02918 * This parameter can be one of the following values: 02919 * 02920 * - For all TIMx 02921 * @arg TIM_TRGOSource_Reset_MORT: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) 02922 * @arg TIM_TRGOSource_Enable_MORT: The Counter Enable CEN is used as the trigger output(TRGO) 02923 * @arg TIM_TRGOSource_Update_MORT: The update event is selected as the trigger output(TRGO) 02924 * 02925 * - For all TIMx except TIM6_MORT and TIM7_MORT 02926 * @arg TIM_TRGOSource_OC1_MORT: The trigger output sends a positive pulse when the CC1IF flag 02927 * is to be set, as soon as a capture or compare match occurs(TRGO) 02928 * @arg TIM_TRGOSource_OC1Ref_MORT: OC1REF signal is used as the trigger output(TRGO) 02929 * @arg TIM_TRGOSource_OC2Ref_MORT: OC2REF signal is used as the trigger output(TRGO) 02930 * @arg TIM_TRGOSource_OC3Ref_MORT: OC3REF signal is used as the trigger output(TRGO) 02931 * @arg TIM_TRGOSource_OC4Ref_MORT: OC4REF signal is used as the trigger output(TRGO) 02932 * 02933 * @retval None 02934 */ 02935 void TIM_SelectOutputTrigger_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_TRGOSource) 02936 { 02937 /* Check the parameters */ 02938 assert_param(IS_TIM_LIST5_PERIPH_MORT(TIMx)); 02939 assert_param(IS_TIM_TRGO_SOURCE_MORT(TIM_TRGOSource)); 02940 02941 /* Reset the MMS Bits */ 02942 TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS_MORT; 02943 /* Select the TRGO source */ 02944 TIMx->CR2 |= TIM_TRGOSource; 02945 } 02946 02947 /** 02948 * @brief Selects the TIMx Slave Mode. 02949 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. 02950 * @param TIM_SlaveMode: specifies the Timer Slave Mode. 02951 * This parameter can be one of the following values: 02952 * @arg TIM_SlaveMode_Reset_MORT: Rising edge of the selected trigger signal(TRGI) reinitialize 02953 * the counter and triggers an update of the registers 02954 * @arg TIM_SlaveMode_Gated_MORT: The counter clock is enabled when the trigger signal (TRGI) is high 02955 * @arg TIM_SlaveMode_Trigger_MORT: The counter starts at a rising edge of the trigger TRGI 02956 * @arg TIM_SlaveMode_External1_MORT: Rising edges of the selected trigger (TRGI) clock the counter 02957 * @retval None 02958 */ 02959 void TIM_SelectSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_SlaveMode) 02960 { 02961 /* Check the parameters */ 02962 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 02963 assert_param(IS_TIM_SLAVE_MODE_MORT(TIM_SlaveMode)); 02964 02965 /* Reset the SMS Bits */ 02966 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS_MORT; 02967 02968 /* Select the Slave Mode */ 02969 TIMx->SMCR |= TIM_SlaveMode; 02970 } 02971 02972 /** 02973 * @brief Sets or Resets the TIMx Master/Slave Mode. 02974 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. 02975 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. 02976 * This parameter can be one of the following values: 02977 * @arg TIM_MasterSlaveMode_Enable_MORT: synchronization between the current timer 02978 * and its slaves (through TRGO) 02979 * @arg TIM_MasterSlaveMode_Disable_MORT: No action 02980 * @retval None 02981 */ 02982 void TIM_SelectMasterSlaveMode_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_MasterSlaveMode) 02983 { 02984 /* Check the parameters */ 02985 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 02986 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); 02987 02988 /* Reset the MSM Bit */ 02989 TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM_MORT; 02990 02991 /* Set or Reset the MSM Bit */ 02992 TIMx->SMCR |= TIM_MasterSlaveMode; 02993 } 02994 02995 /** 02996 * @brief Configures the TIMx External Trigger (ETR). 02997 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02998 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 02999 * This parameter can be one of the following values: 03000 * @arg TIM_ExtTRGPSC_OFF_MORT: ETRP Prescaler OFF. 03001 * @arg TIM_ExtTRGPSC_DIV2_MORT: ETRP frequency divided by 2. 03002 * @arg TIM_ExtTRGPSC_DIV4_MORT: ETRP frequency divided by 4. 03003 * @arg TIM_ExtTRGPSC_DIV8_MORT: ETRP frequency divided by 8. 03004 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 03005 * This parameter can be one of the following values: 03006 * @arg TIM_ExtTRGPolarity_Inverted_MORT: active low or falling edge active. 03007 * @arg TIM_ExtTRGPolarity_NonInverted_MORT: active high or rising edge active. 03008 * @param ExtTRGFilter: External Trigger Filter. 03009 * This parameter must be a value between 0x00 and 0x0F 03010 * @retval None 03011 */ 03012 void TIM_ETRConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ExtTRGPrescaler, 03013 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 03014 { 03015 uint16_t tmpsmcr = 0; 03016 03017 /* Check the parameters */ 03018 assert_param(IS_TIM_LIST3_PERIPH_MORT(TIMx)); 03019 assert_param(IS_TIM_EXT_PRESCALER_MORT(TIM_ExtTRGPrescaler)); 03020 assert_param(IS_TIM_EXT_POLARITY_MORT(TIM_ExtTRGPolarity)); 03021 assert_param(IS_TIM_EXT_FILTER_MORT(ExtTRGFilter)); 03022 03023 tmpsmcr = TIMx->SMCR; 03024 03025 /* Reset the ETR Bits */ 03026 tmpsmcr &= SMCR_ETR_MASK_MORT; 03027 03028 /* Set the Prescaler, the Filter value and the Polarity */ 03029 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); 03030 03031 /* Write to TIMx SMCR */ 03032 TIMx->SMCR = tmpsmcr; 03033 } 03034 /** 03035 * @} 03036 */ 03037 03038 /** @defgroup TIM_Group8 Specific interface management functions 03039 * @brief Specific interface management functions 03040 * 03041 @verbatim 03042 =============================================================================== 03043 ##### Specific interface management functions ##### 03044 =============================================================================== 03045 03046 @endverbatim 03047 * @{ 03048 */ 03049 03050 /** 03051 * @brief Configures the TIMx Encoder Interface. 03052 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 03053 * peripheral. 03054 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. 03055 * This parameter can be one of the following values: 03056 * @arg TIM_EncoderMode_TI1_MORT: Counter counts on TI1FP1 edge depending on TI2FP2 level. 03057 * @arg TIM_EncoderMode_TI2_MORT: Counter counts on TI2FP2 edge depending on TI1FP1 level. 03058 * @arg TIM_EncoderMode_TI12_MORT: Counter counts on both TI1FP1 and TI2FP2 edges depending 03059 * on the level of the other input. 03060 * @param TIM_IC1Polarity: specifies the IC1 Polarity 03061 * This parameter can be one of the following values: 03062 * @arg TIM_ICPolarity_Falling_MORT: IC Falling edge. 03063 * @arg TIM_ICPolarity_Rising_MORT: IC Rising edge. 03064 * @param TIM_IC2Polarity: specifies the IC2 Polarity 03065 * This parameter can be one of the following values: 03066 * @arg TIM_ICPolarity_Falling_MORT: IC Falling edge. 03067 * @arg TIM_ICPolarity_Rising_MORT: IC Rising edge. 03068 * @retval None 03069 */ 03070 void TIM_EncoderInterfaceConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_EncoderMode, 03071 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) 03072 { 03073 uint16_t tmpsmcr = 0; 03074 uint16_t tmpccmr1 = 0; 03075 uint16_t tmpccer = 0; 03076 03077 /* Check the parameters */ 03078 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 03079 assert_param(IS_TIM_ENCODER_MODE_MORT(TIM_EncoderMode)); 03080 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); 03081 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); 03082 03083 /* Get the TIMx SMCR register value */ 03084 tmpsmcr = TIMx->SMCR; 03085 03086 /* Get the TIMx CCMR1 register value */ 03087 tmpccmr1 = TIMx->CCMR1; 03088 03089 /* Get the TIMx CCER register value */ 03090 tmpccer = TIMx->CCER; 03091 03092 /* Set the encoder Mode */ 03093 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS_MORT; 03094 tmpsmcr |= TIM_EncoderMode; 03095 03096 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 03097 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR1_CC2S_MORT); 03098 tmpccmr1 |= TIM_CCMR1_CC1S_0_MORT | TIM_CCMR1_CC2S_0_MORT; 03099 03100 /* Set the TI1 and the TI2 Polarities */ 03101 tmpccer &= ((uint16_t)~TIM_CCER_CC1P_MORT) & ((uint16_t)~TIM_CCER_CC2P_MORT); 03102 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); 03103 03104 /* Write to TIMx SMCR */ 03105 TIMx->SMCR = tmpsmcr; 03106 03107 /* Write to TIMx CCMR1 */ 03108 TIMx->CCMR1 = tmpccmr1; 03109 03110 /* Write to TIMx CCER */ 03111 TIMx->CCER = tmpccer; 03112 } 03113 03114 /** 03115 * @brief Enables or disables the TIMx's Hall sensor interface. 03116 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 03117 * peripheral. 03118 * @param NewState: new state of the TIMx Hall sensor interface. 03119 * This parameter can be: ENABLE or DISABLE. 03120 * @retval None 03121 */ 03122 void TIM_SelectHallSensor_mort(TIM_TypeDef_mort* TIMx, FunctionalState NewState) 03123 { 03124 /* Check the parameters */ 03125 assert_param(IS_TIM_LIST2_PERIPH_MORT(TIMx)); 03126 assert_param(IS_FUNCTIONAL_STATE(NewState)); 03127 03128 if (NewState != DISABLE) 03129 { 03130 /* Set the TI1S Bit */ 03131 TIMx->CR2 |= TIM_CR2_TI1S_MORT; 03132 } 03133 else 03134 { 03135 /* Reset the TI1S Bit */ 03136 TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S_MORT; 03137 } 03138 } 03139 /** 03140 * @} 03141 */ 03142 03143 /** @defgroup TIM_Group9 Specific remapping management function 03144 * @brief Specific remapping management function 03145 * 03146 @verbatim 03147 =============================================================================== 03148 ##### Specific remapping management function ##### 03149 =============================================================================== 03150 03151 @endverbatim 03152 * @{ 03153 */ 03154 03155 /** 03156 * @brief Configures the TIM2_MORT, TIM5_MORT and TIM11_MORT Remapping input capabilities. 03157 * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. 03158 * @param TIM_Remap: specifies the TIM input remapping source. 03159 * This parameter can be one of the following values: 03160 * @arg TIM2_TIM8_TRGO: TIM2_MORT ITR1 input is connected to TIM8_MORT Trigger output(default) 03161 * @arg TIM2_ETH_PTP_MORT: TIM2_MORT ITR1 input is connected to ETH PTP trigger output. 03162 * @arg TIM2_USBFS_SOF_MORT: TIM2_MORT ITR1 input is connected to USB FS SOF. 03163 * @arg TIM2_USBHS_SOF_MORT: TIM2_MORT ITR1 input is connected to USB HS SOF. 03164 * @arg TIM5_GPIO: TIM5_MORT CH4 input is connected to dedicated Timer pin(default) 03165 * @arg TIM5_LSI_MORT: TIM5_MORT CH4 input is connected to LSI clock. 03166 * @arg TIM5_LSE_MORT: TIM5_MORT CH4 input is connected to LSE clock. 03167 * @arg TIM5_RTC_MORT: TIM5_MORT CH4 input is connected to RTC Output event. 03168 * @arg TIM11_GPIO_MORT: TIM11_MORT CH4 input is connected to dedicated Timer pin(default) 03169 * @arg TIM11_HSE_MORT: TIM11_MORT CH4 input is connected to HSE_RTC clock 03170 * (HSE divided by a programmable prescaler) 03171 * @retval None 03172 */ 03173 void TIM_RemapConfig_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_Remap) 03174 { 03175 /* Check the parameters */ 03176 assert_param(IS_TIM_LIST6_PERIPH_MORT(TIMx)); 03177 assert_param(IS_TIM_REMAP(TIM_Remap)); 03178 03179 /* Set the Timer remapping configuration */ 03180 TIMx->OR = TIM_Remap; 03181 } 03182 /** 03183 * @} 03184 */ 03185 03186 /** 03187 * @brief Configure the TI1 as Input. 03188 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 03189 * to select the TIM peripheral. 03190 * @param TIM_ICPolarity : The Input Polarity. 03191 * This parameter can be one of the following values: 03192 * @arg TIM_ICPolarity_Rising_MORT 03193 * @arg TIM_ICPolarity_Falling_MORT 03194 * @arg TIM_ICPolarity_BothEdge_MORT 03195 * @param TIM_ICSelection: specifies the input to be used. 03196 * This parameter can be one of the following values: 03197 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 1 is selected to be connected to IC1. 03198 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 1 is selected to be connected to IC2. 03199 * @arg TIM_ICSelection_TRC_MORT: TIM Input 1 is selected to be connected to TRC. 03200 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03201 * This parameter must be a value between 0x00 and 0x0F. 03202 * @retval None 03203 */ 03204 static void TI1_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03205 uint16_t TIM_ICFilter) 03206 { 03207 uint16_t tmpccmr1 = 0, tmpccer = 0; 03208 03209 /* Disable the Channel 1: Reset the CC1E Bit */ 03210 TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E_MORT; 03211 tmpccmr1 = TIMx->CCMR1; 03212 tmpccer = TIMx->CCER; 03213 03214 /* Select the Input and set the filter */ 03215 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR1_IC1F_MORT); 03216 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 03217 03218 /* Select the Polarity and set the CC1E Bit */ 03219 tmpccer &= (uint16_t)~(TIM_CCER_CC1P_MORT | TIM_CCER_CC1NP_MORT); 03220 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E_MORT); 03221 03222 /* Write to TIMx CCMR1 and CCER registers */ 03223 TIMx->CCMR1 = tmpccmr1; 03224 TIMx->CCER = tmpccer; 03225 } 03226 03227 /** 03228 * @brief Configure the TI2 as Input. 03229 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 03230 * peripheral. 03231 * @param TIM_ICPolarity : The Input Polarity. 03232 * This parameter can be one of the following values: 03233 * @arg TIM_ICPolarity_Rising_MORT 03234 * @arg TIM_ICPolarity_Falling_MORT 03235 * @arg TIM_ICPolarity_BothEdge_MORT 03236 * @param TIM_ICSelection: specifies the input to be used. 03237 * This parameter can be one of the following values: 03238 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 2 is selected to be connected to IC2. 03239 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 2 is selected to be connected to IC1. 03240 * @arg TIM_ICSelection_TRC_MORT: TIM Input 2 is selected to be connected to TRC. 03241 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03242 * This parameter must be a value between 0x00 and 0x0F. 03243 * @retval None 03244 */ 03245 static void TI2_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03246 uint16_t TIM_ICFilter) 03247 { 03248 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; 03249 03250 /* Disable the Channel 2: Reset the CC2E Bit */ 03251 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E_MORT; 03252 tmpccmr1 = TIMx->CCMR1; 03253 tmpccer = TIMx->CCER; 03254 tmp = (uint16_t)(TIM_ICPolarity << 4); 03255 03256 /* Select the Input and set the filter */ 03257 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S_MORT) & ((uint16_t)~TIM_CCMR1_IC2F_MORT); 03258 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); 03259 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 03260 03261 /* Select the Polarity and set the CC2E Bit */ 03262 tmpccer &= (uint16_t)~(TIM_CCER_CC2P_MORT | TIM_CCER_CC2NP_MORT); 03263 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E_MORT); 03264 03265 /* Write to TIMx CCMR1 and CCER registers */ 03266 TIMx->CCMR1 = tmpccmr1 ; 03267 TIMx->CCER = tmpccer; 03268 } 03269 03270 /** 03271 * @brief Configure the TI3 as Input. 03272 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 03273 * @param TIM_ICPolarity : The Input Polarity. 03274 * This parameter can be one of the following values: 03275 * @arg TIM_ICPolarity_Rising_MORT 03276 * @arg TIM_ICPolarity_Falling_MORT 03277 * @arg TIM_ICPolarity_BothEdge_MORT 03278 * @param TIM_ICSelection: specifies the input to be used. 03279 * This parameter can be one of the following values: 03280 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 3 is selected to be connected to IC3. 03281 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 3 is selected to be connected to IC4. 03282 * @arg TIM_ICSelection_TRC_MORT: TIM Input 3 is selected to be connected to TRC. 03283 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03284 * This parameter must be a value between 0x00 and 0x0F. 03285 * @retval None 03286 */ 03287 static void TI3_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03288 uint16_t TIM_ICFilter) 03289 { 03290 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 03291 03292 /* Disable the Channel 3: Reset the CC3E Bit */ 03293 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E_MORT; 03294 tmpccmr2 = TIMx->CCMR2; 03295 tmpccer = TIMx->CCER; 03296 tmp = (uint16_t)(TIM_ICPolarity << 8); 03297 03298 /* Select the Input and set the filter */ 03299 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S_MORT) & ((uint16_t)~TIM_CCMR2_IC3F_MORT); 03300 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 03301 03302 /* Select the Polarity and set the CC3E Bit */ 03303 tmpccer &= (uint16_t)~(TIM_CCER_CC3P_MORT | TIM_CCER_CC3NP_MORT); 03304 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E_MORT); 03305 03306 /* Write to TIMx CCMR2 and CCER registers */ 03307 TIMx->CCMR2 = tmpccmr2; 03308 TIMx->CCER = tmpccer; 03309 } 03310 03311 /** 03312 * @brief Configure the TI4 as Input. 03313 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 03314 * @param TIM_ICPolarity : The Input Polarity. 03315 * This parameter can be one of the following values: 03316 * @arg TIM_ICPolarity_Rising_MORT 03317 * @arg TIM_ICPolarity_Falling_MORT 03318 * @arg TIM_ICPolarity_BothEdge_MORT 03319 * @param TIM_ICSelection: specifies the input to be used. 03320 * This parameter can be one of the following values: 03321 * @arg TIM_ICSelection_DirectTI_MORT: TIM Input 4 is selected to be connected to IC4. 03322 * @arg TIM_ICSelection_IndirectTI_MORT: TIM Input 4 is selected to be connected to IC3. 03323 * @arg TIM_ICSelection_TRC_MORT: TIM Input 4 is selected to be connected to TRC. 03324 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03325 * This parameter must be a value between 0x00 and 0x0F. 03326 * @retval None 03327 */ 03328 static void TI4_Config_mort(TIM_TypeDef_mort* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03329 uint16_t TIM_ICFilter) 03330 { 03331 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 03332 03333 /* Disable the Channel 4: Reset the CC4E Bit */ 03334 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E_MORT; 03335 tmpccmr2 = TIMx->CCMR2; 03336 tmpccer = TIMx->CCER; 03337 tmp = (uint16_t)(TIM_ICPolarity << 12); 03338 03339 /* Select the Input and set the filter */ 03340 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S_MORT) & ((uint16_t)~TIM_CCMR1_IC2F_MORT); 03341 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); 03342 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); 03343 03344 /* Select the Polarity and set the CC4E Bit */ 03345 tmpccer &= (uint16_t)~(TIM_CCER_CC4P_MORT | TIM_CCER_CC4NP_MORT); 03346 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E_MORT); 03347 03348 /* Write to TIMx CCMR2 and CCER registers */ 03349 TIMx->CCMR2 = tmpccmr2; 03350 TIMx->CCER = tmpccer ; 03351 } 03352 03353 /** 03354 * @} 03355 */ 03356 03357 /** 03358 * @} 03359 */ 03360 03361 /** 03362 * @} 03363 */ 03364 03365 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 03366 03367 03368 03369 03370
Generated on Sat Oct 21 2023 04:38:55 by
1.7.2