Rajath Ravi
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ravi_blinkycode
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stm32f4xx_rcc_mort.h
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_rcc.h 00004 * @author MCD Application Team 00005 * @version V1.8.0 00006 * @date 04-November-2016 00007 * @brief This file contains all the functions prototypes for the RCC firmware library. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 00028 /* Define to prevent recursive inclusion -------------------------------------*/ 00029 #ifndef __STM32F4xx_RCC_H_MORT 00030 #define __STM32F4xx_RCC_H_MORT 00031 00032 #ifdef __cplusplus 00033 extern "C" { 00034 #endif 00035 00036 /* Includes ------------------------------------------------------------------*/ 00037 #include "stm32f4xx_mort2.h" 00038 00039 /** @addtogroup STM32F4xx_StdPeriph_Driver 00040 * @{ 00041 */ 00042 00043 /** @addtogroup RCC 00044 * @{ 00045 */ 00046 00047 /* Exported types ------------------------------------------------------------*/ 00048 typedef struct 00049 { 00050 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ 00051 uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ 00052 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ 00053 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ 00054 }RCC_ClocksTypeDef; 00055 00056 /* Exported constants --------------------------------------------------------*/ 00057 00058 /** @defgroup RCC_Exported_Constants 00059 * @{ 00060 */ 00061 00062 /** @defgroup RCC_HSE_configuration 00063 * @{ 00064 */ 00065 #define RCC_HSE_OFF_MORT ((uint8_t)0x00) 00066 #define RCC_HSE_ON_MORT ((uint8_t)0x01) 00067 #define RCC_HSE_Bypass ((uint8_t)0x05) 00068 #define IS_RCC_HSE_MORT(HSE) (((HSE) == RCC_HSE_OFF_MORT) || ((HSE) == RCC_HSE_ON_MORT) || \ 00069 ((HSE) == RCC_HSE_Bypass)) 00070 /** 00071 * @} 00072 */ 00073 00074 /** @defgroup RCC_LSE_Dual_Mode_Selection 00075 * @{ 00076 */ 00077 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 00078 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 00079 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ 00080 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 00081 /** 00082 * @} 00083 */ 00084 00085 /** @defgroup RCC_PLLSAIDivR_Factor 00086 * @{ 00087 */ 00088 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) 00089 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) 00090 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) 00091 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) 00092 #define IS_RCC_PLLSAI_DIVR_VALUE_MORT(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ 00093 ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ 00094 ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ 00095 ((VALUE) == RCC_PLLSAIDivR_Div16)) 00096 /** 00097 * @} 00098 */ 00099 00100 /** @defgroup RCC_PLL_Clock_Source 00101 * @{ 00102 */ 00103 #define RCC_PLLSource_HSI ((uint32_t)0x00000000) 00104 #define RCC_PLLSource_HSE ((uint32_t)0x00400000) 00105 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ 00106 ((SOURCE) == RCC_PLLSource_HSE)) 00107 #define IS_RCC_PLLM_VALUE_MORT(VALUE) ((VALUE) <= 63) 00108 #define IS_RCC_PLLN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 00109 #define IS_RCC_PLLP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 00110 #define IS_RCC_PLLQ_VALUE_MORT(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) 00111 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 00112 #define IS_RCC_PLLR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 00113 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 00114 00115 #define IS_RCC_PLLI2SN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 00116 #define IS_RCC_PLLI2SR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 00117 #define IS_RCC_PLLI2SM_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) 00118 #define IS_RCC_PLLI2SQ_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 00119 #if defined(STM32F446xx) 00120 #define IS_RCC_PLLI2SP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 00121 #define IS_RCC_PLLSAIM_VALUE_MORT(VALUE) ((VALUE) <= 63) 00122 #elif defined(STM32F412xG) || defined(STM32F413_423xx) 00123 #define IS_RCC_PLLI2SP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 00124 #else 00125 #endif /* STM32F446xx */ 00126 #define IS_RCC_PLLSAIN_VALUE_MORT(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 00127 #if defined(STM32F446xx) || defined(STM32F469_479xx) 00128 #define IS_RCC_PLLSAIP_VALUE_MORT(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 00129 #endif /* STM32F446xx || STM32F469_479xx */ 00130 #define IS_RCC_PLLSAIQ_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 00131 #define IS_RCC_PLLSAIR_VALUE_MORT(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 00132 00133 #define IS_RCC_PLLSAI_DIVQ_VALUE_MORT(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 00134 #define IS_RCC_PLLI2S_DIVQ_VALUE_MORT(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 00135 00136 #if defined(STM32F413_423xx) 00137 #define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 00138 #define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 00139 #endif /* STM32F413_423xx */ 00140 /** 00141 * @} 00142 */ 00143 00144 /** @defgroup RCC_System_Clock_Source 00145 * @{ 00146 */ 00147 00148 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 00149 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 00150 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 00151 #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) 00152 #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) 00153 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 00154 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 00155 ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ 00156 ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) 00157 /* Add legacy definition */ 00158 #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK 00159 #endif /* STM32F446xx */ 00160 00161 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 00162 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 00163 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 00164 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 00165 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 00166 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 00167 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 00168 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ 00169 /** 00170 * @} 00171 */ 00172 00173 /** @defgroup RCC_AHB_Clock_Source 00174 * @{ 00175 */ 00176 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 00177 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 00178 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 00179 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 00180 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 00181 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 00182 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 00183 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 00184 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 00185 #define IS_RCC_HCLK_MORT(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 00186 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 00187 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 00188 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 00189 ((HCLK) == RCC_SYSCLK_Div512)) 00190 /** 00191 * @} 00192 */ 00193 00194 /** @defgroup RCC_APB1_APB2_Clock_Source 00195 * @{ 00196 */ 00197 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 00198 #define RCC_HCLK_Div2 ((uint32_t)0x00001000) 00199 #define RCC_HCLK_Div4 ((uint32_t)0x00001400) 00200 #define RCC_HCLK_Div8 ((uint32_t)0x00001800) 00201 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) 00202 #define IS_RCC_PCLK_MORT(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 00203 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 00204 ((PCLK) == RCC_HCLK_Div16)) 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup RCC_Interrupt_Source 00210 * @{ 00211 */ 00212 #define RCC_IT_LSIRDY ((uint8_t)0x01) 00213 #define RCC_IT_LSERDY ((uint8_t)0x02) 00214 #define RCC_IT_HSIRDY ((uint8_t)0x04) 00215 #define RCC_IT_HSERDY ((uint8_t)0x08) 00216 #define RCC_IT_PLLRDY ((uint8_t)0x10) 00217 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 00218 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) 00219 #define RCC_IT_CSS ((uint8_t)0x80) 00220 00221 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 00222 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 00223 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 00224 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 00225 ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) 00226 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) 00227 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup RCC_LSE_Configuration 00233 * @{ 00234 */ 00235 #define RCC_LSE_OFF_MORT ((uint8_t)0x00) 00236 #define RCC_LSE_ON_MORT ((uint8_t)0x01) 00237 #define RCC_LSE_Bypass ((uint8_t)0x04) 00238 #define IS_RCC_LSE_MORT(LSE) (((LSE) == RCC_LSE_OFF_MORT) || ((LSE) == RCC_LSE_ON_MORT) || \ 00239 ((LSE) == RCC_LSE_Bypass)) 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup RCC_RTC_Clock_Source 00245 * @{ 00246 */ 00247 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 00248 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 00249 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) 00250 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) 00251 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 00252 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) 00253 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) 00254 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) 00255 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) 00256 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) 00257 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) 00258 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) 00259 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) 00260 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) 00261 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) 00262 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) 00263 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) 00264 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) 00265 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) 00266 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) 00267 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) 00268 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) 00269 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) 00270 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) 00271 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) 00272 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) 00273 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 00274 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) 00275 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) 00276 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) 00277 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) 00278 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) 00279 #define IS_RCC_RTCCLK_SOURCE_MORT(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 00280 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 00281 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ 00282 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ 00283 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ 00284 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ 00285 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 00286 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ 00287 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ 00288 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ 00289 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ 00290 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ 00291 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ 00292 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ 00293 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ 00294 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ 00295 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ 00296 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ 00297 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ 00298 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ 00299 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ 00300 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ 00301 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ 00302 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ 00303 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ 00304 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ 00305 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ 00306 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ 00307 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ 00308 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ 00309 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ 00310 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) 00311 /** 00312 * @} 00313 */ 00314 00315 #if defined(STM32F410xx) || defined(STM32F413_423xx) 00316 /** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source 00317 * @{ 00318 */ 00319 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) 00320 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 00321 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 00322 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 00323 00324 #define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ 00325 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 00326 /* Legacy Defines */ 00327 #define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE 00328 00329 #if defined(STM32F410xx) 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source 00335 * @{ 00336 */ 00337 #define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000) 00338 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 00339 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 00340 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \ 00341 ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) 00342 /** 00343 * @} 00344 */ 00345 #endif /* STM32F413_423xx */ 00346 #endif /* STM32F410xx || STM32F413_423xx */ 00347 00348 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 00349 /** @defgroup RCC_I2S_Clock_Source 00350 * @{ 00351 */ 00352 #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00) 00353 #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0_MORT) 00354 #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1_MORT) 00355 #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0_MORT | RCC_DCKCFGR_I2S1SRC_1_MORT) 00356 00357 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ 00358 ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) 00359 /** 00360 * @} 00361 */ 00362 00363 /** @defgroup RCC_I2S_APBBus 00364 * @{ 00365 */ 00366 #define RCC_I2SBus_APB1 ((uint8_t)0x00) 00367 #define RCC_I2SBus_APB2 ((uint8_t)0x01) 00368 #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) 00369 /** 00370 * @} 00371 */ 00372 #if defined(STM32F446xx) 00373 /** @defgroup RCC_SAI_Clock_Source 00374 * @{ 00375 */ 00376 #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00) 00377 #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0_MORT) 00378 #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1_MORT) 00379 #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0_MORT | RCC_DCKCFGR_SAI1SRC_1_MORT) 00380 00381 #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ 00382 ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) 00383 /** 00384 * @} 00385 */ 00386 00387 /** @defgroup RCC_SAI_Instance 00388 * @{ 00389 */ 00390 #define RCC_SAIInstance_SAI1 ((uint8_t)0x00) 00391 #define RCC_SAIInstance_SAI2 ((uint8_t)0x01) 00392 #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) 00393 /** 00394 * @} 00395 */ 00396 #endif /* STM32F446xx */ 00397 #if defined(STM32F413_423xx) 00398 00399 /** @defgroup RCC_SAI_BlockA_Clock_Source 00400 * @{ 00401 */ 00402 #define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000) 00403 #define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0_MORT) 00404 #define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1_MORT) 00405 #define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0_MORT | RCC_DCKCFGR_SAI1ASRC_1_MORT) 00406 00407 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \ 00408 ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE)) 00409 /** 00410 * @} 00411 */ 00412 00413 /** @defgroup RCC_SAI_BlockB_Clock_Source 00414 * @{ 00415 */ 00416 #define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000) 00417 #define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0_MORT) 00418 #define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1_MORT) 00419 #define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0_MORT | RCC_DCKCFGR_SAI1BSRC_1_MORT) 00420 00421 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \ 00422 ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE)) 00423 /** 00424 * @} 00425 */ 00426 #endif /* STM32F413_423xx */ 00427 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ 00428 00429 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 00430 /** @defgroup RCC_I2S_Clock_Source 00431 * @{ 00432 */ 00433 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) 00434 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) 00435 00436 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 00437 /** 00438 * @} 00439 */ 00440 00441 /** @defgroup RCC_SAI_BlockA_Clock_Source 00442 * @{ 00443 */ 00444 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) 00445 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) 00446 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) 00447 00448 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ 00449 ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ 00450 ((SOURCE) == RCC_SAIACLKSource_Ext)) 00451 /** 00452 * @} 00453 */ 00454 00455 /** @defgroup RCC_SAI_BlockB_Clock_Source 00456 * @{ 00457 */ 00458 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) 00459 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) 00460 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) 00461 00462 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ 00463 ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ 00464 ((SOURCE) == RCC_SAIBCLKSource_Ext)) 00465 /** 00466 * @} 00467 */ 00468 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ 00469 00470 /** @defgroup RCC_TIM_PRescaler_Selection 00471 * @{ 00472 */ 00473 #define RCC_TIMPrescDesactivated ((uint8_t)0x00) 00474 #define RCC_TIMPrescActivated ((uint8_t)0x01) 00475 00476 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) 00477 /** 00478 * @} 00479 */ 00480 00481 #if defined(STM32F469_479xx) 00482 /** @defgroup RCC_DSI_Clock_Source_Selection 00483 * @{ 00484 */ 00485 #define RCC_DSICLKSource_PHY ((uint8_t)0x00) 00486 #define RCC_DSICLKSource_PLLR ((uint8_t)0x01) 00487 #define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \ 00488 ((CLKSOURCE) == RCC_DSICLKSource_PLLR)) 00489 /** 00490 * @} 00491 */ 00492 #endif /* STM32F469_479xx */ 00493 00494 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 00495 /** @defgroup RCC_SDIO_Clock_Source_Selection 00496 * @{ 00497 */ 00498 #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00) 00499 #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01) 00500 #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \ 00501 ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK)) 00502 /** 00503 * @} 00504 */ 00505 00506 00507 /** @defgroup RCC_48MHZ_Clock_Source_Selection 00508 * @{ 00509 */ 00510 #if defined(STM32F446xx) || defined(STM32F469_479xx) 00511 #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00) 00512 #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01) 00513 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \ 00514 ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI)) 00515 #endif /* STM32F446xx || STM32F469_479xx */ 00516 #if defined(STM32F412xG) || defined(STM32F413_423xx) 00517 #define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00) 00518 #define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */ 00519 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \ 00520 ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ)) 00521 #endif /* STM32F412xG || STM32F413_423xx */ 00522 /** 00523 * @} 00524 */ 00525 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 00526 00527 #if defined(STM32F446xx) 00528 /** @defgroup RCC_SPDIFRX_Clock_Source_Selection 00529 * @{ 00530 */ 00531 #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00) 00532 #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01) 00533 #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \ 00534 ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP)) 00535 /** 00536 * @} 00537 */ 00538 00539 /** @defgroup RCC_CEC_Clock_Source_Selection 00540 * @{ 00541 */ 00542 #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00) 00543 #define RCC_CECCLKSource_LSE ((uint8_t)0x01) 00544 #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \ 00545 ((CLKSOURCE) == RCC_CECCLKSource_LSE)) 00546 /** 00547 * @} 00548 */ 00549 00550 /** @defgroup RCC_AHB1_ClockGating 00551 * @{ 00552 */ 00553 #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) 00554 #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) 00555 #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) 00556 #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008) 00557 #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010) 00558 #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020) 00559 #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040) 00560 00561 #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00)) 00562 00563 /** 00564 * @} 00565 */ 00566 #endif /* STM32F446xx */ 00567 00568 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 00569 /** @defgroup RCC_FMPI2C1_Clock_Source 00570 * @{ 00571 */ 00572 #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) 00573 #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0_MORT) 00574 #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1_MORT) 00575 00576 #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ 00577 ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) 00578 /** 00579 * @} 00580 */ 00581 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ 00582 00583 #if defined(STM32F412xG) || defined(STM32F413_423xx) 00584 /** @defgroup RCC_DFSDM_Clock_Source 00585 * @{ 00586 */ 00587 #define RCC_DFSDMCLKSource_APB ((uint8_t)0x00) 00588 #define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01) 00589 #define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS)) 00590 00591 /* Legacy Defines */ 00592 #define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB 00593 #define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS 00594 #define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE 00595 /** 00596 * @} 00597 */ 00598 00599 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source 00600 * @{ 00601 */ 00602 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) 00603 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) 00604 #define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2)) 00605 00606 /* Legacy Defines */ 00607 #define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE 00608 /** 00609 * @} 00610 */ 00611 00612 #if defined(STM32F413_423xx) 00613 /** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source 00614 * @{ 00615 */ 00616 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) 00617 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) 00618 #define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2)) 00619 /** 00620 * @} 00621 */ 00622 #endif /* STM32F413_423xx */ 00623 #endif /* STM32F412xG || STM32F413_423xx */ 00624 00625 /** @defgroup RCC_AHB1_Peripherals 00626 * @{ 00627 */ 00628 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) 00629 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) 00630 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) 00631 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) 00632 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) 00633 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) 00634 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) 00635 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) 00636 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) 00637 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) 00638 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) 00639 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) 00640 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) 00641 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) 00642 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) 00643 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) 00644 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) 00645 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) 00646 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) 00647 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) 00648 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) 00649 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) 00650 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) 00651 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) 00652 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) 00653 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) 00654 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) 00655 #if defined(STM32F410xx) 00656 #define RCC_AHB1Periph_RNG ((uint32_t)0x80000000) 00657 #endif /* STM32F410xx */ 00658 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00)) 00659 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00)) 00660 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) 00661 00662 /** 00663 * @} 00664 */ 00665 00666 /** @defgroup RCC_AHB2_Peripherals 00667 * @{ 00668 */ 00669 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) 00670 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) 00671 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) 00672 #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 00673 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) 00674 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 00675 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) 00676 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) 00677 /** 00678 * @} 00679 */ 00680 00681 /** @defgroup RCC_AHB3_Peripherals 00682 * @{ 00683 */ 00684 #if defined(STM32F40_41xxx) 00685 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 00686 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 00687 #endif /* STM32F40_41xxx */ 00688 00689 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) 00690 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 00691 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 00692 #endif /* STM32F427_437xx || STM32F429_439xx */ 00693 00694 #if defined(STM32F446xx) || defined(STM32F469_479xx) 00695 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 00696 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) 00697 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) 00698 #endif /* STM32F446xx || STM32F469_479xx */ 00699 00700 #if defined(STM32F412xG) || defined(STM32F413_423xx) 00701 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 00702 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) 00703 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) 00704 #endif /* STM32F412xG || STM32F413_423xx */ 00705 00706 /** 00707 * @} 00708 */ 00709 00710 /** @defgroup RCC_APB1_Peripherals 00711 * @{ 00712 */ 00713 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 00714 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 00715 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 00716 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 00717 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 00718 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 00719 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 00720 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 00721 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 00722 #if defined(STM32F410xx) || defined(STM32F413_423xx) 00723 #define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200) 00724 #endif /* STM32F410xx || STM32F413_423xx */ 00725 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 00726 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 00727 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 00728 #if defined(STM32F446xx) 00729 #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) 00730 #endif /* STM32F446xx */ 00731 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 00732 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 00733 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 00734 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 00735 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 00736 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 00737 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) 00738 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 00739 #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) 00740 #endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ 00741 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 00742 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 00743 #if defined(STM32F413_423xx) 00744 #define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000) 00745 #endif /* STM32F413_423xx */ 00746 #if defined(STM32F446xx) 00747 #define RCC_APB1Periph_CEC ((uint32_t)0x08000000) 00748 #endif /* STM32F446xx */ 00749 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 00750 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 00751 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) 00752 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) 00753 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) 00754 /** 00755 * @} 00756 */ 00757 00758 /** @defgroup RCC_APB2_Peripherals 00759 * @{ 00760 */ 00761 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 00762 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) 00763 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) 00764 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) 00765 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 00766 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) 00767 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) 00768 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) 00769 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) 00770 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 00771 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) 00772 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 00773 #define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000) 00774 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) 00775 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) 00776 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) 00777 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) 00778 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) 00779 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) 00780 #if defined(STM32F446xx) || defined(STM32F469_479xx) 00781 #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000) 00782 #endif /* STM32F446xx || STM32F469_479xx */ 00783 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) 00784 #if defined(STM32F469_479xx) 00785 #define RCC_APB2Periph_DSI ((uint32_t)0x08000000) 00786 #endif /* STM32F469_479xx */ 00787 #if defined(STM32F412xG) || defined(STM32F413_423xx) 00788 #define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000) 00789 #endif /* STM32F412xG || STM32F413_423xx */ 00790 #if defined(STM32F413_423xx) 00791 #define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000) 00792 #define RCC_APB2Periph_UART9 ((uint32_t)0x02000040) 00793 #define RCC_APB2Periph_UART10 ((uint32_t)0x00000080) 00794 #endif /* STM32F413_423xx */ 00795 00796 /* Legacy Defines */ 00797 #define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1 00798 00799 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00)) 00800 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00)) 00801 00802 /** 00803 * @} 00804 */ 00805 00806 /** @defgroup RCC_MCO1_Clock_Source_Prescaler 00807 * @{ 00808 */ 00809 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) 00810 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) 00811 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 00812 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) 00813 #define RCC_MCO1Div_1 ((uint32_t)0x00000000) 00814 #define RCC_MCO1Div_2 ((uint32_t)0x04000000) 00815 #define RCC_MCO1Div_3 ((uint32_t)0x05000000) 00816 #define RCC_MCO1Div_4 ((uint32_t)0x06000000) 00817 #define RCC_MCO1Div_5 ((uint32_t)0x07000000) 00818 #define IS_RCC_MCO1SOURCE_MORT(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ 00819 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) 00820 00821 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ 00822 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ 00823 ((DIV) == RCC_MCO1Div_5)) 00824 /** 00825 * @} 00826 */ 00827 00828 /** @defgroup RCC_MCO2_Clock_Source_Prescaler 00829 * @{ 00830 */ 00831 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) 00832 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) 00833 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) 00834 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) 00835 #define RCC_MCO2Div_1 ((uint32_t)0x00000000) 00836 #define RCC_MCO2Div_2 ((uint32_t)0x20000000) 00837 #define RCC_MCO2Div_3 ((uint32_t)0x28000000) 00838 #define RCC_MCO2Div_4 ((uint32_t)0x30000000) 00839 #define RCC_MCO2Div_5 ((uint32_t)0x38000000) 00840 #define IS_RCC_MCO2SOURCE_MORT(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ 00841 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) 00842 00843 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ 00844 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ 00845 ((DIV) == RCC_MCO2Div_5)) 00846 /** 00847 * @} 00848 */ 00849 00850 /** @defgroup RCC_Flag 00851 * @{ 00852 */ 00853 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 00854 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 00855 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 00856 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 00857 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) 00858 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 00859 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 00860 #define RCC_FLAG_BORRST ((uint8_t)0x79) 00861 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 00862 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 00863 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 00864 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 00865 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 00866 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 00867 00868 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 00869 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 00870 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ 00871 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 00872 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 00873 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ 00874 ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) 00875 00876 #define IS_RCC_CALIBRATION_VALUE_MORT(VALUE) ((VALUE) <= 0x1F) 00877 /** 00878 * @} 00879 */ 00880 00881 /** 00882 * @} 00883 */ 00884 00885 /* Exported macro ------------------------------------------------------------*/ 00886 /* Exported functions --------------------------------------------------------*/ 00887 00888 /* Function used to set the RCC clock configuration to the default reset state */ 00889 void RCC_DeInit(void); 00890 00891 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 00892 void RCC_HSEConfig(uint8_t RCC_HSE); 00893 ErrorStatus RCC_WaitForHSEStartUp(void); 00894 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 00895 void RCC_HSICmd(FunctionalState NewState); 00896 void RCC_LSEConfig(uint8_t RCC_LSE); 00897 void RCC_LSICmd(FunctionalState NewState); 00898 00899 void RCC_PLLCmd(FunctionalState NewState); 00900 00901 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 00902 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR); 00903 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 00904 00905 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 00906 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); 00907 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 00908 00909 void RCC_PLLI2SCmd(FunctionalState NewState); 00910 00911 #if defined(STM32F40_41xxx) || defined(STM32F401xx) 00912 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); 00913 #endif /* STM32F40_41xxx || STM32F401xx */ 00914 #if defined(STM32F411xE) 00915 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); 00916 #endif /* STM32F411xE */ 00917 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 00918 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); 00919 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 00920 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 00921 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR); 00922 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ 00923 00924 void RCC_PLLSAICmd(FunctionalState NewState); 00925 #if defined(STM32F469_479xx) 00926 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR); 00927 #endif /* STM32F469_479xx */ 00928 #if defined(STM32F446xx) 00929 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ); 00930 #endif /* STM32F446xx */ 00931 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 00932 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); 00933 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 00934 00935 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 00936 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); 00937 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); 00938 00939 /* System, AHB and APB busses clocks configuration functions ******************/ 00940 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 00941 uint8_t RCC_GetSYSCLKSource(void); 00942 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 00943 void RCC_PCLK1Config(uint32_t RCC_HCLK); 00944 void RCC_PCLK2Config(uint32_t RCC_HCLK); 00945 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 00946 00947 /* Peripheral clocks configuration functions **********************************/ 00948 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 00949 void RCC_RTCCLKCmd(FunctionalState NewState); 00950 void RCC_BackupResetCmd(FunctionalState NewState); 00951 00952 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 00953 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource); 00954 #if defined(STM32F446xx) 00955 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource); 00956 #endif /* STM32F446xx */ 00957 #if defined(STM32F413_423xx) 00958 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); 00959 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); 00960 #endif /* STM32F413_423xx */ 00961 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ 00962 00963 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 00964 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 00965 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ 00966 00967 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 00968 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); 00969 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); 00970 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 00971 00972 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); 00973 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); 00974 00975 #if defined(STM32F413_423xx) 00976 void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR); 00977 void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR); 00978 #endif /* STM32F413_423xx */ 00979 00980 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); 00981 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); 00982 00983 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 00984 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 00985 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 00986 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00987 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00988 00989 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 00990 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 00991 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 00992 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00993 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00994 00995 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 00996 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 00997 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 00998 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00999 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 01000 01001 /* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */ 01002 void RCC_LSEModeConfig(uint8_t RCC_Mode); 01003 01004 /* Features available only for STM32F469_479xx devices */ 01005 #if defined(STM32F469_479xx) 01006 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource); 01007 #endif /* STM32F469_479xx */ 01008 01009 /* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */ 01010 #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 01011 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource); 01012 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource); 01013 #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ 01014 01015 /* Features available only for STM32F446xx devices */ 01016 #if defined(STM32F446xx) 01017 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState); 01018 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource); 01019 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource); 01020 #endif /* STM32F446xx */ 01021 01022 /* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */ 01023 #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) 01024 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource); 01025 #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ 01026 01027 /* Features available only for STM32F410xx devices */ 01028 #if defined(STM32F410xx) || defined(STM32F413_423xx) 01029 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource); 01030 #if defined(STM32F410xx) 01031 void RCC_MCO1Cmd(FunctionalState NewState); 01032 void RCC_MCO2Cmd(FunctionalState NewState); 01033 #endif /* STM32F410xx */ 01034 #endif /* STM32F410xx || STM32F413_423xx */ 01035 01036 #if defined(STM32F412xG) || defined(STM32F413_423xx) 01037 void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource); 01038 void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource); 01039 #if defined(STM32F413_423xx) 01040 void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource); 01041 #endif /* STM32F413_423xx */ 01042 /* Legacy Defines */ 01043 #define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig 01044 #endif /* STM32F412xG || STM32F413_423xx */ 01045 /* Interrupts and flags management functions **********************************/ 01046 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 01047 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 01048 void RCC_ClearFlag(void); 01049 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 01050 void RCC_ClearITPendingBit(uint8_t RCC_IT); 01051 01052 #ifdef __cplusplus 01053 } 01054 #endif 01055 01056 #endif /* __STM32F4xx_RCC_H */ 01057 01058 /** 01059 * @} 01060 */ 01061 01062 /** 01063 * @} 01064 */ 01065 01066 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01067 01068 01069 01070 01071
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