Rajath Ravi
/
ravi_blinkycode
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stm32f4xx_mort2.h@0:34ee385f4d2d, 2021-10-23 (annotated)
- Committer:
- rajathr
- Date:
- Sat Oct 23 05:49:09 2021 +0000
- Revision:
- 0:34ee385f4d2d
At 23rd Oct 21 - All Code
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| rajathr | 0:34ee385f4d2d | 1 | /** |
| rajathr | 0:34ee385f4d2d | 2 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 3 | * @file stm32f4xx.h |
| rajathr | 0:34ee385f4d2d | 4 | * @author MCD Application Team |
| rajathr | 0:34ee385f4d2d | 5 | * @version V1.8.0 |
| rajathr | 0:34ee385f4d2d | 6 | * @date 09-November-2016 |
| rajathr | 0:34ee385f4d2d | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. |
| rajathr | 0:34ee385f4d2d | 8 | * This file contains all the peripheral register's definitions, bits |
| rajathr | 0:34ee385f4d2d | 9 | * definitions and memory mapping for STM32F4xx devices. |
| rajathr | 0:34ee385f4d2d | 10 | * |
| rajathr | 0:34ee385f4d2d | 11 | * The file is the unique include file that the application programmer |
| rajathr | 0:34ee385f4d2d | 12 | * is using in the C source code, usually in main.c. This file contains: |
| rajathr | 0:34ee385f4d2d | 13 | * - Configuration section that allows to select: |
| rajathr | 0:34ee385f4d2d | 14 | * - The device used in the target application |
| rajathr | 0:34ee385f4d2d | 15 | * - To use or not the peripherals drivers in application code(i.e. |
| rajathr | 0:34ee385f4d2d | 16 | * code will be based on direct access to peripherals registers |
| rajathr | 0:34ee385f4d2d | 17 | * rather than drivers API), this option is controlled by |
| rajathr | 0:34ee385f4d2d | 18 | * "#define USE_STDPERIPH_DRIVER" |
| rajathr | 0:34ee385f4d2d | 19 | * - To change few application-specific parameters such as the HSE |
| rajathr | 0:34ee385f4d2d | 20 | * crystal frequency |
| rajathr | 0:34ee385f4d2d | 21 | * - Data structures and the address mapping for all peripherals |
| rajathr | 0:34ee385f4d2d | 22 | * - Peripherals registers declarations and bits definition |
| rajathr | 0:34ee385f4d2d | 23 | * - Macros to access peripherals registers hardware |
| rajathr | 0:34ee385f4d2d | 24 | * |
| rajathr | 0:34ee385f4d2d | 25 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 26 | * @attention |
| rajathr | 0:34ee385f4d2d | 27 | * |
| rajathr | 0:34ee385f4d2d | 28 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| rajathr | 0:34ee385f4d2d | 29 | * |
| rajathr | 0:34ee385f4d2d | 30 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| rajathr | 0:34ee385f4d2d | 31 | * You may not use this file except in compliance with the License. |
| rajathr | 0:34ee385f4d2d | 32 | * You may obtain a copy of the License at: |
| rajathr | 0:34ee385f4d2d | 33 | * |
| rajathr | 0:34ee385f4d2d | 34 | * http://www.st.com/software_license_agreement_liberty_v2 |
| rajathr | 0:34ee385f4d2d | 35 | * |
| rajathr | 0:34ee385f4d2d | 36 | * Unless required by applicable law or agreed to in writing, software |
| rajathr | 0:34ee385f4d2d | 37 | * distributed under the License is distributed on an "AS IS" BASIS, |
| rajathr | 0:34ee385f4d2d | 38 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| rajathr | 0:34ee385f4d2d | 39 | * See the License for the specific language governing permissions and |
| rajathr | 0:34ee385f4d2d | 40 | * limitations under the License. |
| rajathr | 0:34ee385f4d2d | 41 | * |
| rajathr | 0:34ee385f4d2d | 42 | ****************************************************************************** |
| rajathr | 0:34ee385f4d2d | 43 | */ |
| rajathr | 0:34ee385f4d2d | 44 | |
| rajathr | 0:34ee385f4d2d | 45 | /** @addtogroup CMSIS |
| rajathr | 0:34ee385f4d2d | 46 | * @{ |
| rajathr | 0:34ee385f4d2d | 47 | */ |
| rajathr | 0:34ee385f4d2d | 48 | |
| rajathr | 0:34ee385f4d2d | 49 | /** @addtogroup stm32f4xx |
| rajathr | 0:34ee385f4d2d | 50 | * @{ |
| rajathr | 0:34ee385f4d2d | 51 | */ |
| rajathr | 0:34ee385f4d2d | 52 | |
| rajathr | 0:34ee385f4d2d | 53 | #ifndef __STM32F4xx_H_MORT2_ |
| rajathr | 0:34ee385f4d2d | 54 | #define __STM32F4xx_H_MORT2_ |
| rajathr | 0:34ee385f4d2d | 55 | |
| rajathr | 0:34ee385f4d2d | 56 | #ifdef __cplusplus |
| rajathr | 0:34ee385f4d2d | 57 | extern "C" { |
| rajathr | 0:34ee385f4d2d | 58 | #endif /* __cplusplus */ |
| rajathr | 0:34ee385f4d2d | 59 | |
| rajathr | 0:34ee385f4d2d | 60 | /** @addtogroup Library_configuration_section |
| rajathr | 0:34ee385f4d2d | 61 | * @{ |
| rajathr | 0:34ee385f4d2d | 62 | */ |
| rajathr | 0:34ee385f4d2d | 63 | |
| rajathr | 0:34ee385f4d2d | 64 | /* Uncomment the line below according to the target STM32 device used in your |
| rajathr | 0:34ee385f4d2d | 65 | application |
| rajathr | 0:34ee385f4d2d | 66 | */ |
| rajathr | 0:34ee385f4d2d | 67 | |
| rajathr | 0:34ee385f4d2d | 68 | #if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ |
| rajathr | 0:34ee385f4d2d | 69 | !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx_MORT) && !defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 70 | /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, |
| rajathr | 0:34ee385f4d2d | 71 | STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, |
| rajathr | 0:34ee385f4d2d | 72 | STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ |
| rajathr | 0:34ee385f4d2d | 73 | |
| rajathr | 0:34ee385f4d2d | 74 | /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, |
| rajathr | 0:34ee385f4d2d | 75 | STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ |
| rajathr | 0:34ee385f4d2d | 76 | |
| rajathr | 0:34ee385f4d2d | 77 | /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, |
| rajathr | 0:34ee385f4d2d | 78 | STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, |
| rajathr | 0:34ee385f4d2d | 79 | STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, |
| rajathr | 0:34ee385f4d2d | 80 | STM32F439IG and STM32F439II Devices */ |
| rajathr | 0:34ee385f4d2d | 81 | |
| rajathr | 0:34ee385f4d2d | 82 | /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC, |
| rajathr | 0:34ee385f4d2d | 83 | STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */ |
| rajathr | 0:34ee385f4d2d | 84 | |
| rajathr | 0:34ee385f4d2d | 85 | /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */ |
| rajathr | 0:34ee385f4d2d | 86 | |
| rajathr | 0:34ee385f4d2d | 87 | /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ |
| rajathr | 0:34ee385f4d2d | 88 | |
| rajathr | 0:34ee385f4d2d | 89 | /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ, |
| rajathr | 0:34ee385f4d2d | 90 | STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT, |
| rajathr | 0:34ee385f4d2d | 91 | STM32F412REY and STM32F412RGY Devices */ |
| rajathr | 0:34ee385f4d2d | 92 | |
| rajathr | 0:34ee385f4d2d | 93 | /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT, |
| rajathr | 0:34ee385f4d2d | 94 | STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ, |
| rajathr | 0:34ee385f4d2d | 95 | STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT, |
| rajathr | 0:34ee385f4d2d | 96 | STM32F423VHH and STM32F423ZHJ devices */ |
| rajathr | 0:34ee385f4d2d | 97 | |
| rajathr | 0:34ee385f4d2d | 98 | #define STM32F446xx_MORT /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC |
| rajathr | 0:34ee385f4d2d | 99 | and STM32F446ZE Devices */ |
| rajathr | 0:34ee385f4d2d | 100 | |
| rajathr | 0:34ee385f4d2d | 101 | /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG, |
| rajathr | 0:34ee385f4d2d | 102 | STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */ |
| rajathr | 0:34ee385f4d2d | 103 | |
| rajathr | 0:34ee385f4d2d | 104 | #endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx_MORT && STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 105 | |
| rajathr | 0:34ee385f4d2d | 106 | /* Old STM32F40XX definition, maintained for legacy purpose */ |
| rajathr | 0:34ee385f4d2d | 107 | #ifdef STM32F40XX |
| rajathr | 0:34ee385f4d2d | 108 | #define STM32F40_41xxx |
| rajathr | 0:34ee385f4d2d | 109 | #endif /* STM32F40XX */ |
| rajathr | 0:34ee385f4d2d | 110 | |
| rajathr | 0:34ee385f4d2d | 111 | /* Old STM32F427X definition, maintained for legacy purpose */ |
| rajathr | 0:34ee385f4d2d | 112 | #ifdef STM32F427X |
| rajathr | 0:34ee385f4d2d | 113 | #define STM32F427_437xx |
| rajathr | 0:34ee385f4d2d | 114 | #endif /* STM32F427X */ |
| rajathr | 0:34ee385f4d2d | 115 | |
| rajathr | 0:34ee385f4d2d | 116 | /* Tip: To avoid modifying this file each time you need to switch between these |
| rajathr | 0:34ee385f4d2d | 117 | devices, you can define the device in your toolchain compiler preprocessor. |
| rajathr | 0:34ee385f4d2d | 118 | */ |
| rajathr | 0:34ee385f4d2d | 119 | |
| rajathr | 0:34ee385f4d2d | 120 | #if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ |
| rajathr | 0:34ee385f4d2d | 121 | !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx_MORT) && !defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 122 | #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" |
| rajathr | 0:34ee385f4d2d | 123 | #endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx_MORT && STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 124 | |
| rajathr | 0:34ee385f4d2d | 125 | #if !defined (USE_STDPERIPH_DRIVER) |
| rajathr | 0:34ee385f4d2d | 126 | /** |
| rajathr | 0:34ee385f4d2d | 127 | * @brief Comment the line below if you will not use the peripherals drivers. |
| rajathr | 0:34ee385f4d2d | 128 | In this case, these drivers will not be included and the application code will |
| rajathr | 0:34ee385f4d2d | 129 | be based on direct access to peripherals registers |
| rajathr | 0:34ee385f4d2d | 130 | */ |
| rajathr | 0:34ee385f4d2d | 131 | /*#define USE_STDPERIPH_DRIVER */ |
| rajathr | 0:34ee385f4d2d | 132 | #endif /* USE_STDPERIPH_DRIVER */ |
| rajathr | 0:34ee385f4d2d | 133 | |
| rajathr | 0:34ee385f4d2d | 134 | /** |
| rajathr | 0:34ee385f4d2d | 135 | * @brief In the following line adjust the value of External High Speed oscillator (HSE) |
| rajathr | 0:34ee385f4d2d | 136 | used in your application |
| rajathr | 0:34ee385f4d2d | 137 | |
| rajathr | 0:34ee385f4d2d | 138 | Tip: To avoid modifying this file each time you need to use different HSE, you |
| rajathr | 0:34ee385f4d2d | 139 | can define the HSE value in your toolchain compiler preprocessor. |
| rajathr | 0:34ee385f4d2d | 140 | */ |
| rajathr | 0:34ee385f4d2d | 141 | #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \ |
| rajathr | 0:34ee385f4d2d | 142 | defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 143 | #if !defined (HSE_VALUE) |
| rajathr | 0:34ee385f4d2d | 144 | #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ |
| rajathr | 0:34ee385f4d2d | 145 | #endif /* HSE_VALUE */ |
| rajathr | 0:34ee385f4d2d | 146 | #elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 147 | #if !defined (HSE_VALUE) |
| rajathr | 0:34ee385f4d2d | 148 | #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
| rajathr | 0:34ee385f4d2d | 149 | #endif /* HSE_VALUE */ |
| rajathr | 0:34ee385f4d2d | 150 | #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 151 | /** |
| rajathr | 0:34ee385f4d2d | 152 | * @brief In the following line adjust the External High Speed oscillator (HSE) Startup |
| rajathr | 0:34ee385f4d2d | 153 | Timeout value |
| rajathr | 0:34ee385f4d2d | 154 | */ |
| rajathr | 0:34ee385f4d2d | 155 | #if !defined (HSE_STARTUP_TIMEOUT) |
| rajathr | 0:34ee385f4d2d | 156 | #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ |
| rajathr | 0:34ee385f4d2d | 157 | #endif /* HSE_STARTUP_TIMEOUT */ |
| rajathr | 0:34ee385f4d2d | 158 | |
| rajathr | 0:34ee385f4d2d | 159 | #if !defined (HSI_VALUE) |
| rajathr | 0:34ee385f4d2d | 160 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| rajathr | 0:34ee385f4d2d | 161 | #endif /* HSI_VALUE */ |
| rajathr | 0:34ee385f4d2d | 162 | |
| rajathr | 0:34ee385f4d2d | 163 | /** |
| rajathr | 0:34ee385f4d2d | 164 | * @brief STM32F4XX Standard Peripherals Library version number V1.8.0 |
| rajathr | 0:34ee385f4d2d | 165 | */ |
| rajathr | 0:34ee385f4d2d | 166 | #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ |
| rajathr | 0:34ee385f4d2d | 167 | #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ |
| rajathr | 0:34ee385f4d2d | 168 | #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ |
| rajathr | 0:34ee385f4d2d | 169 | #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ |
| rajathr | 0:34ee385f4d2d | 170 | #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ |
| rajathr | 0:34ee385f4d2d | 171 | |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ |
| rajathr | 0:34ee385f4d2d | 172 | |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ |
| rajathr | 0:34ee385f4d2d | 173 | |(__STM32F4XX_STDPERIPH_VERSION_RC)) |
| rajathr | 0:34ee385f4d2d | 174 | |
| rajathr | 0:34ee385f4d2d | 175 | /** |
| rajathr | 0:34ee385f4d2d | 176 | * @} |
| rajathr | 0:34ee385f4d2d | 177 | */ |
| rajathr | 0:34ee385f4d2d | 178 | |
| rajathr | 0:34ee385f4d2d | 179 | /** @addtogroup Configuration_section_for_CMSIS |
| rajathr | 0:34ee385f4d2d | 180 | * @{ |
| rajathr | 0:34ee385f4d2d | 181 | */ |
| rajathr | 0:34ee385f4d2d | 182 | |
| rajathr | 0:34ee385f4d2d | 183 | /** |
| rajathr | 0:34ee385f4d2d | 184 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| rajathr | 0:34ee385f4d2d | 185 | */ |
| rajathr | 0:34ee385f4d2d | 186 | #define __CM4_REV_MORT 0x0001 /*!< Core revision r0p1 */ |
| rajathr | 0:34ee385f4d2d | 187 | #define __MPU_PRESENT_MORT 1 /*!< STM32F4XX provides an MPU */ |
| rajathr | 0:34ee385f4d2d | 188 | #define __NVIC_PRIO_BITS_MORT 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ |
| rajathr | 0:34ee385f4d2d | 189 | #define __Vendor_SysTickConfig_MORT 0 /*!< Set to 1 if different SysTick Config is used */ |
| rajathr | 0:34ee385f4d2d | 190 | #define __FPU_PRESENT_MORT 1 /*!< FPU present */ |
| rajathr | 0:34ee385f4d2d | 191 | |
| rajathr | 0:34ee385f4d2d | 192 | /** |
| rajathr | 0:34ee385f4d2d | 193 | * @brief STM32F4XX Interrupt Number Definition, according to the selected device |
| rajathr | 0:34ee385f4d2d | 194 | * in @ref Library_configuration_section |
| rajathr | 0:34ee385f4d2d | 195 | */ |
| rajathr | 0:34ee385f4d2d | 196 | typedef enum IRQn_MORT |
| rajathr | 0:34ee385f4d2d | 197 | { |
| rajathr | 0:34ee385f4d2d | 198 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| rajathr | 0:34ee385f4d2d | 199 | NonMaskableInt_IRQn_MORT = -14, /*!< 2 Non Maskable Interrupt */ |
| rajathr | 0:34ee385f4d2d | 200 | MemoryManagement_IRQn_MORT = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| rajathr | 0:34ee385f4d2d | 201 | BusFault_IRQn_MORT = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| rajathr | 0:34ee385f4d2d | 202 | UsageFault_IRQn_MORT = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| rajathr | 0:34ee385f4d2d | 203 | SVCall_IRQn_MORT = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| rajathr | 0:34ee385f4d2d | 204 | DebugMonitor_IRQn_MORT = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| rajathr | 0:34ee385f4d2d | 205 | PendSV_IRQn_MORT = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| rajathr | 0:34ee385f4d2d | 206 | SysTick_IRQn_MORT = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| rajathr | 0:34ee385f4d2d | 207 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| rajathr | 0:34ee385f4d2d | 208 | WWDG_IRQn_MORT = 0, /*!< Window WatchDog Interrupt */ |
| rajathr | 0:34ee385f4d2d | 209 | PVD_IRQn_MORT = 1, /*!< PVD through EXTI_MORT Line detection Interrupt */ |
| rajathr | 0:34ee385f4d2d | 210 | TAMP_STAMP_IRQn_MORT = 2, /*!< Tamper and TimeStamp interrupts through the EXTI_MORT line */ |
| rajathr | 0:34ee385f4d2d | 211 | RTC_WKUP_IRQn_MORT = 3, /*!< RTC_MORT Wakeup interrupt through the EXTI_MORT line */ |
| rajathr | 0:34ee385f4d2d | 212 | FLASH_IRQn_MORT = 4, /*!< FLASH_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 213 | RCC_IRQn_MORT = 5, /*!< RCC_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 214 | EXTI0_IRQn_MORT = 6, /*!< EXTI_MORT Line0 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 215 | EXTI1_IRQn_MORT = 7, /*!< EXTI_MORT Line1 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 216 | EXTI2_IRQn_MORT = 8, /*!< EXTI_MORT Line2 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 217 | EXTI3_IRQn_MORT = 9, /*!< EXTI_MORT Line3 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 218 | EXTI4_IRQn_MORT = 10, /*!< EXTI_MORT Line4 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 219 | DMA1_Stream0_IRQn_MORT = 11, /*!< DMA1_MORT Stream 0 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 220 | DMA1_Stream1_IRQn_MORT = 12, /*!< DMA1_MORT Stream 1 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 221 | DMA1_Stream2_IRQn_MORT = 13, /*!< DMA1_MORT Stream 2 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 222 | DMA1_Stream3_IRQn_MORT = 14, /*!< DMA1_MORT Stream 3 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 223 | DMA1_Stream4_IRQn_MORT = 15, /*!< DMA1_MORT Stream 4 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 224 | DMA1_Stream5_IRQn_MORT = 16, /*!< DMA1_MORT Stream 5 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 225 | DMA1_Stream6_IRQn_MORT = 17, /*!< DMA1_MORT Stream 6 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 226 | ADC_IRQn_MORT = 18, /*!< ADC1_MORT, ADC2_MORT and ADC3_MORT global Interrupts */ |
| rajathr | 0:34ee385f4d2d | 227 | |
| rajathr | 0:34ee385f4d2d | 228 | #if defined(STM32F40_41xxx) |
| rajathr | 0:34ee385f4d2d | 229 | */ |
| rajathr | 0:34ee385f4d2d | 230 | #endif /* STM32F40_41xxx */ |
| rajathr | 0:34ee385f4d2d | 231 | |
| rajathr | 0:34ee385f4d2d | 232 | #if defined(STM32F427_437xx) |
| rajathr | 0:34ee385f4d2d | 233 | */ |
| rajathr | 0:34ee385f4d2d | 234 | #endif /* STM32F427_437xx */ |
| rajathr | 0:34ee385f4d2d | 235 | |
| rajathr | 0:34ee385f4d2d | 236 | #if defined(STM32F429_439xx) |
| rajathr | 0:34ee385f4d2d | 237 | */ |
| rajathr | 0:34ee385f4d2d | 238 | #endif /* STM32F429_439xx */ |
| rajathr | 0:34ee385f4d2d | 239 | |
| rajathr | 0:34ee385f4d2d | 240 | #if defined(STM32F410xx) |
| rajathr | 0:34ee385f4d2d | 241 | */ |
| rajathr | 0:34ee385f4d2d | 242 | #endif /* STM32F410xx */ |
| rajathr | 0:34ee385f4d2d | 243 | |
| rajathr | 0:34ee385f4d2d | 244 | #if defined(STM32F401xx) || defined(STM32F411xE) |
| rajathr | 0:34ee385f4d2d | 245 | */ |
| rajathr | 0:34ee385f4d2d | 246 | #if defined(STM32F401xx) |
| rajathr | 0:34ee385f4d2d | 247 | */ |
| rajathr | 0:34ee385f4d2d | 248 | #endif /* STM32F411xE */ |
| rajathr | 0:34ee385f4d2d | 249 | #if defined(STM32F411xE) |
| rajathr | 0:34ee385f4d2d | 250 | */ |
| rajathr | 0:34ee385f4d2d | 251 | #endif /* STM32F411xE */ |
| rajathr | 0:34ee385f4d2d | 252 | #endif /* STM32F401xx || STM32F411xE */ |
| rajathr | 0:34ee385f4d2d | 253 | |
| rajathr | 0:34ee385f4d2d | 254 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 255 | */ |
| rajathr | 0:34ee385f4d2d | 256 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 257 | |
| rajathr | 0:34ee385f4d2d | 258 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 259 | CAN1_TX_IRQn_MORT = 19, /*!< CAN1_MORT TX Interrupt */ |
| rajathr | 0:34ee385f4d2d | 260 | CAN1_RX0_IRQn_MORT = 20, /*!< CAN1_MORT RX0 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 261 | CAN1_RX1_IRQn_MORT = 21, /*!< CAN1_MORT RX1 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 262 | CAN1_SCE_IRQn_MORT = 22, /*!< CAN1_MORT SCE Interrupt */ |
| rajathr | 0:34ee385f4d2d | 263 | EXTI9_5_IRQn_MORT = 23, /*!< External Line[9:5] Interrupts */ |
| rajathr | 0:34ee385f4d2d | 264 | TIM1_BRK_TIM9_IRQn_MORT = 24, /*!< TIM1_MORT Break interrupt and TIM9_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 265 | TIM1_UP_TIM10_IRQn_MORT = 25, /*!< TIM1_MORT Update Interrupt and TIM10_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 266 | TIM1_TRG_COM_TIM11_IRQn_MORT = 26, /*!< TIM1_MORT Trigger and Commutation Interrupt and TIM11_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 267 | TIM1_CC_IRQn_MORT = 27, /*!< TIM1_MORT Capture Compare Interrupt */ |
| rajathr | 0:34ee385f4d2d | 268 | TIM2_IRQn_MORT = 28, /*!< TIM2_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 269 | TIM3_IRQn_MORT = 29, /*!< TIM3_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 270 | TIM4_IRQn_MORT = 30, /*!< TIM4_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 271 | I2C1_EV_IRQn_MORT = 31, /*!< I2C1_MORT Event Interrupt */ |
| rajathr | 0:34ee385f4d2d | 272 | I2C1_ER_IRQn_MORT = 32, /*!< I2C1_MORT Error Interrupt */ |
| rajathr | 0:34ee385f4d2d | 273 | I2C2_EV_IRQn_MORT = 33, /*!< I2C2_MORT Event Interrupt */ |
| rajathr | 0:34ee385f4d2d | 274 | I2C2_ER_IRQn_MORT = 34, /*!< I2C2_MORT Error Interrupt */ |
| rajathr | 0:34ee385f4d2d | 275 | SPI1_IRQn_MORT = 35, /*!< SPI1_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 276 | SPI2_IRQn_MORT = 36, /*!< SPI2_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 277 | USART1_IRQn_MORT = 37, /*!< USART1_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 278 | USART2_IRQn_MORT = 38, /*!< USART2_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 279 | USART3_IRQn_MORT = 39, /*!< USART3_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 280 | EXTI15_10_IRQn_MORT = 40, /*!< External Line[15:10] Interrupts */ |
| rajathr | 0:34ee385f4d2d | 281 | RTC_Alarm_IRQn_MORT = 41, /*!< RTC_MORT Alarm (A and B) through EXTI_MORT Line Interrupt */ |
| rajathr | 0:34ee385f4d2d | 282 | OTG_FS_WKUP_IRQn_MORT = 42, /*!< USB OTG FS Wakeup through EXTI_MORT line interrupt */ |
| rajathr | 0:34ee385f4d2d | 283 | TIM8_BRK_IRQn_MORT = 43, /*!< TIM8_MORT Break Interrupt */ |
| rajathr | 0:34ee385f4d2d | 284 | TIM8_BRK_TIM12_IRQn_MORT = 43, /*!< TIM8_MORT Break Interrupt and TIM12_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 285 | TIM8_UP_TIM13_IRQn_MORT = 44, /*!< TIM8_MORT Update Interrupt and TIM13_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 286 | TIM8_TRG_COM_TIM14_IRQn_MORT = 45, /*!< TIM8_MORT Trigger and Commutation Interrupt and TIM14_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 287 | DMA1_Stream7_IRQn_MORT = 47, /*!< DMA1_MORT Stream7 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 288 | FMC_IRQn_MORT = 48, /*!< FMC global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 289 | SDIO_IRQn_MORT = 49, /*!< SDIO_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 290 | TIM5_IRQn_MORT = 50, /*!< TIM5_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 291 | SPI3_IRQn_MORT = 51, /*!< SPI3_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 292 | UART4_IRQn_MORT = 52, /*!< UART4_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 293 | UART5_IRQn_MORT = 53, /*!< UART5_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 294 | TIM6_DAC_IRQn_MORT = 54, /*!< TIM6_MORT global and DAC1&2 underrun error interrupts */ |
| rajathr | 0:34ee385f4d2d | 295 | TIM7_IRQn_MORT = 55, /*!< TIM7_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 296 | DMA2_Stream0_IRQn_MORT = 56, /*!< DMA2_MORT Stream 0 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 297 | DMA2_Stream1_IRQn_MORT = 57, /*!< DMA2_MORT Stream 1 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 298 | DMA2_Stream2_IRQn_MORT = 58, /*!< DMA2_MORT Stream 2 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 299 | DMA2_Stream3_IRQn_MORT = 59, /*!< DMA2_MORT Stream 3 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 300 | DMA2_Stream4_IRQn_MORT = 60, /*!< DMA2_MORT Stream 4 global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 301 | CAN2_TX_IRQn_MORT = 63, /*!< CAN2_MORT TX Interrupt */ |
| rajathr | 0:34ee385f4d2d | 302 | CAN2_RX0_IRQn_MORT = 64, /*!< CAN2_MORT RX0 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 303 | CAN2_RX1_IRQn_MORT = 65, /*!< CAN2_MORT RX1 Interrupt */ |
| rajathr | 0:34ee385f4d2d | 304 | CAN2_SCE_IRQn_MORT = 66, /*!< CAN2_MORT SCE Interrupt */ |
| rajathr | 0:34ee385f4d2d | 305 | OTG_FS_IRQn_MORT = 67, /*!< USB OTG FS global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 306 | DMA2_Stream5_IRQn_MORT = 68, /*!< DMA2_MORT Stream 5 global interrupt */ |
| rajathr | 0:34ee385f4d2d | 307 | DMA2_Stream6_IRQn_MORT = 69, /*!< DMA2_MORT Stream 6 global interrupt */ |
| rajathr | 0:34ee385f4d2d | 308 | DMA2_Stream7_IRQn_MORT = 70, /*!< DMA2_MORT Stream 7 global interrupt */ |
| rajathr | 0:34ee385f4d2d | 309 | USART6_IRQn_MORT = 71, /*!< USART6_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 310 | I2C3_EV_IRQn_MORT = 72, /*!< I2C3_MORT event interrupt */ |
| rajathr | 0:34ee385f4d2d | 311 | I2C3_ER_IRQn_MORT = 73, /*!< I2C3_MORT error interrupt */ |
| rajathr | 0:34ee385f4d2d | 312 | OTG_HS_EP1_OUT_IRQn_MORT = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ |
| rajathr | 0:34ee385f4d2d | 313 | OTG_HS_EP1_IN_IRQn_MORT = 75, /*!< USB OTG HS End Point 1 In global interrupt */ |
| rajathr | 0:34ee385f4d2d | 314 | OTG_HS_WKUP_IRQn_MORT = 76, /*!< USB OTG HS Wakeup through EXTI_MORT interrupt */ |
| rajathr | 0:34ee385f4d2d | 315 | OTG_HS_IRQn_MORT = 77, /*!< USB OTG HS global interrupt */ |
| rajathr | 0:34ee385f4d2d | 316 | DCMI_IRQn_MORT = 78, /*!< DCMI_MORT global interrupt */ |
| rajathr | 0:34ee385f4d2d | 317 | FPU_IRQn_MORT = 81, /*!< FPU global interrupt */ |
| rajathr | 0:34ee385f4d2d | 318 | SPI4_IRQn_MORT = 84, /*!< SPI4_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 319 | SAI1_IRQn_MORT = 87, /*!< SAI1_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 320 | SAI2_IRQn_MORT = 91, /*!< SAI2_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 321 | QUADSPI_IRQn_MORT = 92, /*!< QUADSPI_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 322 | CEC_IRQn_MORT = 93, /*!< QUADSPI_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 323 | SPDIF_RX_IRQn_MORT = 94, /*!< QUADSPI_MORT global Interrupt */ |
| rajathr | 0:34ee385f4d2d | 324 | FMPI2C1_EV_IRQn_MORT = 95, /*!< FMPI2C Event Interrupt */ |
| rajathr | 0:34ee385f4d2d | 325 | FMPI2C1_ER_IRQn_MORT = 96 /*!< FMPCI2C Error Interrupt */ |
| rajathr | 0:34ee385f4d2d | 326 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 327 | |
| rajathr | 0:34ee385f4d2d | 328 | #if defined(STM32F412xG) |
| rajathr | 0:34ee385f4d2d | 329 | */ |
| rajathr | 0:34ee385f4d2d | 330 | #endif /* STM32F412xG */ |
| rajathr | 0:34ee385f4d2d | 331 | |
| rajathr | 0:34ee385f4d2d | 332 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 333 | */ |
| rajathr | 0:34ee385f4d2d | 334 | */ |
| rajathr | 0:34ee385f4d2d | 335 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 336 | } IRQn_Type_MORT; |
| rajathr | 0:34ee385f4d2d | 337 | |
| rajathr | 0:34ee385f4d2d | 338 | /** |
| rajathr | 0:34ee385f4d2d | 339 | * @} |
| rajathr | 0:34ee385f4d2d | 340 | */ |
| rajathr | 0:34ee385f4d2d | 341 | #include "stm32f4xx.h" |
| rajathr | 0:34ee385f4d2d | 342 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| rajathr | 0:34ee385f4d2d | 343 | #include "system_stm32f4xx.h" |
| rajathr | 0:34ee385f4d2d | 344 | #include <stdint.h> |
| rajathr | 0:34ee385f4d2d | 345 | |
| rajathr | 0:34ee385f4d2d | 346 | /** @addtogroup Exported_types |
| rajathr | 0:34ee385f4d2d | 347 | * @{ |
| rajathr | 0:34ee385f4d2d | 348 | */ |
| rajathr | 0:34ee385f4d2d | 349 | /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ |
| rajathr | 0:34ee385f4d2d | 350 | //typedef int32_t_mort s32; |
| rajathr | 0:34ee385f4d2d | 351 | //typedef int16_t_mort s16; |
| rajathr | 0:34ee385f4d2d | 352 | //typedef int8_t_mort s8; |
| rajathr | 0:34ee385f4d2d | 353 | |
| rajathr | 0:34ee385f4d2d | 354 | //typedef const int32_t_mort sc32; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 355 | //typedef const int16_t_mort sc16; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 356 | //typedef const int8_t_mort sc8; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 357 | |
| rajathr | 0:34ee385f4d2d | 358 | //typedef __IO int32_t_mort vs32; |
| rajathr | 0:34ee385f4d2d | 359 | //typedef __IO int16_t_mort vs16; |
| rajathr | 0:34ee385f4d2d | 360 | //typedef __IO int8_t_mort vs8; |
| rajathr | 0:34ee385f4d2d | 361 | |
| rajathr | 0:34ee385f4d2d | 362 | //typedef __I int32_t_mort vsc32; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 363 | //typedef __I int16_t_mort vsc16; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 364 | //typedef __I int8_t_mort vsc8; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 365 | |
| rajathr | 0:34ee385f4d2d | 366 | //typedef uint32_t_mort u32; |
| rajathr | 0:34ee385f4d2d | 367 | //typedef uint16_t_mort u16; |
| rajathr | 0:34ee385f4d2d | 368 | //typedef uint8_t_mort u8; |
| rajathr | 0:34ee385f4d2d | 369 | |
| rajathr | 0:34ee385f4d2d | 370 | //typedef const uint32_t_mort uc32; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 371 | //typedef const uint16_t_mort uc16; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 372 | //typedef const uint8_t_mort uc8; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 373 | |
| rajathr | 0:34ee385f4d2d | 374 | //typedef __IO uint32_t_mort vu32; |
| rajathr | 0:34ee385f4d2d | 375 | //typedef __IO uint16_t_mort vu16; |
| rajathr | 0:34ee385f4d2d | 376 | //typedef __IO uint8_t_mort vu8; |
| rajathr | 0:34ee385f4d2d | 377 | |
| rajathr | 0:34ee385f4d2d | 378 | //typedef __I uint32_t_mort vuc32; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 379 | //typedef __I uint16_t_mort vuc16; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 380 | //typedef __I uint8_t_mort vuc8; /*!< Read Only */ |
| rajathr | 0:34ee385f4d2d | 381 | |
| rajathr | 0:34ee385f4d2d | 382 | typedef enum {RESET_MORT = 0, SET_MORT = !RESET_MORT} FlagStatus_MORT, ITStatus_MORT; |
| rajathr | 0:34ee385f4d2d | 383 | |
| rajathr | 0:34ee385f4d2d | 384 | typedef enum {DISABLE_MORT = 0, ENABLE_MORT = !DISABLE_MORT} FunctionalState_MORT; |
| rajathr | 0:34ee385f4d2d | 385 | #define IS_FUNCTIONAL_STATE_MORT(STATE) (((STATE) == DISABLE_MORT) || ((STATE) == ENABLE_MORT)) |
| rajathr | 0:34ee385f4d2d | 386 | |
| rajathr | 0:34ee385f4d2d | 387 | typedef enum {ERROR_MORT = 0, SUCCESS_MORT = !ERROR} ErrorStatus_MORT; |
| rajathr | 0:34ee385f4d2d | 388 | |
| rajathr | 0:34ee385f4d2d | 389 | /** |
| rajathr | 0:34ee385f4d2d | 390 | * @} |
| rajathr | 0:34ee385f4d2d | 391 | */ |
| rajathr | 0:34ee385f4d2d | 392 | |
| rajathr | 0:34ee385f4d2d | 393 | /** @addtogroup Peripheral_registers_structures |
| rajathr | 0:34ee385f4d2d | 394 | * @{ |
| rajathr | 0:34ee385f4d2d | 395 | */ |
| rajathr | 0:34ee385f4d2d | 396 | |
| rajathr | 0:34ee385f4d2d | 397 | /** |
| rajathr | 0:34ee385f4d2d | 398 | * @brief Analog to Digital Converter |
| rajathr | 0:34ee385f4d2d | 399 | */ |
| rajathr | 0:34ee385f4d2d | 400 | |
| rajathr | 0:34ee385f4d2d | 401 | typedef struct |
| rajathr | 0:34ee385f4d2d | 402 | { |
| rajathr | 0:34ee385f4d2d | 403 | __IO uint32_t SR; /*!< ADC_MORT status register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 404 | __IO uint32_t CR1; /*!< ADC_MORT control register 1, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 405 | __IO uint32_t CR2; /*!< ADC_MORT control register 2, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 406 | __IO uint32_t SMPR1; /*!< ADC_MORT sample time register 1, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 407 | __IO uint32_t SMPR2; /*!< ADC_MORT sample time register 2, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 408 | __IO uint32_t JOFR1; /*!< ADC_MORT injected channel data offset register 1, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 409 | __IO uint32_t JOFR2; /*!< ADC_MORT injected channel data offset register 2, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 410 | __IO uint32_t JOFR3; /*!< ADC_MORT injected channel data offset register 3, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 411 | __IO uint32_t JOFR4; /*!< ADC_MORT injected channel data offset register 4, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 412 | __IO uint32_t HTR; /*!< ADC_MORT watchdog higher threshold register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 413 | __IO uint32_t LTR; /*!< ADC_MORT watchdog lower threshold register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 414 | __IO uint32_t SQR1; /*!< ADC_MORT regular sequence register 1, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 415 | __IO uint32_t SQR2; /*!< ADC_MORT regular sequence register 2, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 416 | __IO uint32_t SQR3; /*!< ADC_MORT regular sequence register 3, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 417 | __IO uint32_t JSQR; /*!< ADC_MORT injected sequence register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 418 | __IO uint32_t JDR1; /*!< ADC_MORT injected data register 1, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 419 | __IO uint32_t JDR2; /*!< ADC_MORT injected data register 2, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 420 | __IO uint32_t JDR3; /*!< ADC_MORT injected data register 3, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 421 | __IO uint32_t JDR4; /*!< ADC_MORT injected data register 4, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 422 | __IO uint32_t DR; /*!< ADC_MORT regular data register, Address offset: 0x4C */ |
| rajathr | 0:34ee385f4d2d | 423 | } ADC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 424 | |
| rajathr | 0:34ee385f4d2d | 425 | typedef struct |
| rajathr | 0:34ee385f4d2d | 426 | { |
| rajathr | 0:34ee385f4d2d | 427 | __IO uint32_t CSR; /*!< ADC_MORT Common status register, Address offset: ADC1_MORT base address + 0x300 */ |
| rajathr | 0:34ee385f4d2d | 428 | __IO uint32_t CCR; /*!< ADC_MORT common control register, Address offset: ADC1_MORT base address + 0x304 */ |
| rajathr | 0:34ee385f4d2d | 429 | __IO uint32_t CDR; /*!< ADC_MORT common regular data register for dual |
| rajathr | 0:34ee385f4d2d | 430 | AND triple modes, Address offset: ADC1_MORT base address + 0x308 */ |
| rajathr | 0:34ee385f4d2d | 431 | } ADC_Common_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 432 | |
| rajathr | 0:34ee385f4d2d | 433 | |
| rajathr | 0:34ee385f4d2d | 434 | /** |
| rajathr | 0:34ee385f4d2d | 435 | * @brief Controller Area Network TxMailBox |
| rajathr | 0:34ee385f4d2d | 436 | */ |
| rajathr | 0:34ee385f4d2d | 437 | |
| rajathr | 0:34ee385f4d2d | 438 | typedef struct |
| rajathr | 0:34ee385f4d2d | 439 | { |
| rajathr | 0:34ee385f4d2d | 440 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| rajathr | 0:34ee385f4d2d | 441 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| rajathr | 0:34ee385f4d2d | 442 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| rajathr | 0:34ee385f4d2d | 443 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| rajathr | 0:34ee385f4d2d | 444 | } CAN_TxMailBox_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 445 | |
| rajathr | 0:34ee385f4d2d | 446 | /** |
| rajathr | 0:34ee385f4d2d | 447 | * @brief Controller Area Network FIFOMailBox |
| rajathr | 0:34ee385f4d2d | 448 | */ |
| rajathr | 0:34ee385f4d2d | 449 | |
| rajathr | 0:34ee385f4d2d | 450 | typedef struct |
| rajathr | 0:34ee385f4d2d | 451 | { |
| rajathr | 0:34ee385f4d2d | 452 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| rajathr | 0:34ee385f4d2d | 453 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| rajathr | 0:34ee385f4d2d | 454 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| rajathr | 0:34ee385f4d2d | 455 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| rajathr | 0:34ee385f4d2d | 456 | } CAN_FIFOMailBox_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 457 | |
| rajathr | 0:34ee385f4d2d | 458 | /** |
| rajathr | 0:34ee385f4d2d | 459 | * @brief Controller Area Network FilterRegister |
| rajathr | 0:34ee385f4d2d | 460 | */ |
| rajathr | 0:34ee385f4d2d | 461 | |
| rajathr | 0:34ee385f4d2d | 462 | typedef struct |
| rajathr | 0:34ee385f4d2d | 463 | { |
| rajathr | 0:34ee385f4d2d | 464 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| rajathr | 0:34ee385f4d2d | 465 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| rajathr | 0:34ee385f4d2d | 466 | } CAN_FilterRegister_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 467 | |
| rajathr | 0:34ee385f4d2d | 468 | /** |
| rajathr | 0:34ee385f4d2d | 469 | * @brief Controller Area Network |
| rajathr | 0:34ee385f4d2d | 470 | */ |
| rajathr | 0:34ee385f4d2d | 471 | |
| rajathr | 0:34ee385f4d2d | 472 | typedef struct |
| rajathr | 0:34ee385f4d2d | 473 | { |
| rajathr | 0:34ee385f4d2d | 474 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 475 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 476 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 477 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 478 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 479 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 480 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 481 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 482 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| rajathr | 0:34ee385f4d2d | 483 | CAN_TxMailBox_TypeDef_mort sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| rajathr | 0:34ee385f4d2d | 484 | CAN_FIFOMailBox_TypeDef_mort sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| rajathr | 0:34ee385f4d2d | 485 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| rajathr | 0:34ee385f4d2d | 486 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| rajathr | 0:34ee385f4d2d | 487 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| rajathr | 0:34ee385f4d2d | 488 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| rajathr | 0:34ee385f4d2d | 489 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| rajathr | 0:34ee385f4d2d | 490 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| rajathr | 0:34ee385f4d2d | 491 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| rajathr | 0:34ee385f4d2d | 492 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| rajathr | 0:34ee385f4d2d | 493 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| rajathr | 0:34ee385f4d2d | 494 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| rajathr | 0:34ee385f4d2d | 495 | CAN_FilterRegister_TypeDef_mort sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| rajathr | 0:34ee385f4d2d | 496 | } CAN_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 497 | |
| rajathr | 0:34ee385f4d2d | 498 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 499 | /** |
| rajathr | 0:34ee385f4d2d | 500 | * @brief Consumer Electronics Control |
| rajathr | 0:34ee385f4d2d | 501 | */ |
| rajathr | 0:34ee385f4d2d | 502 | typedef struct |
| rajathr | 0:34ee385f4d2d | 503 | { |
| rajathr | 0:34ee385f4d2d | 504 | __IO uint32_t CR; /*!< CEC_MORT control register, Address offset:0x00 */ |
| rajathr | 0:34ee385f4d2d | 505 | __IO uint32_t CFGR; /*!< CEC_MORT configuration register, Address offset:0x04 */ |
| rajathr | 0:34ee385f4d2d | 506 | __IO uint32_t TXDR; /*!< CEC_MORT Tx data register , Address offset:0x08 */ |
| rajathr | 0:34ee385f4d2d | 507 | __IO uint32_t RXDR; /*!< CEC_MORT Rx Data Register, Address offset:0x0C */ |
| rajathr | 0:34ee385f4d2d | 508 | __IO uint32_t ISR; /*!< CEC_MORT Interrupt and Status Register, Address offset:0x10 */ |
| rajathr | 0:34ee385f4d2d | 509 | __IO uint32_t IER; /*!< CEC_MORT interrupt enable register, Address offset:0x14 */ |
| rajathr | 0:34ee385f4d2d | 510 | }CEC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 511 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 512 | |
| rajathr | 0:34ee385f4d2d | 513 | /** |
| rajathr | 0:34ee385f4d2d | 514 | * @brief CRC_MORT calculation unit |
| rajathr | 0:34ee385f4d2d | 515 | */ |
| rajathr | 0:34ee385f4d2d | 516 | |
| rajathr | 0:34ee385f4d2d | 517 | typedef struct |
| rajathr | 0:34ee385f4d2d | 518 | { |
| rajathr | 0:34ee385f4d2d | 519 | __IO uint32_t DR; /*!< CRC_MORT Data register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 520 | __IO uint8_t IDR; /*!< CRC_MORT Independent data register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 521 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| rajathr | 0:34ee385f4d2d | 522 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 523 | __IO uint32_t CR; /*!< CRC_MORT Control register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 524 | } CRC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 525 | |
| rajathr | 0:34ee385f4d2d | 526 | /** |
| rajathr | 0:34ee385f4d2d | 527 | * @brief Digital to Analog Converter |
| rajathr | 0:34ee385f4d2d | 528 | */ |
| rajathr | 0:34ee385f4d2d | 529 | |
| rajathr | 0:34ee385f4d2d | 530 | typedef struct |
| rajathr | 0:34ee385f4d2d | 531 | { |
| rajathr | 0:34ee385f4d2d | 532 | __IO uint32_t CR; /*!< DAC_MORT control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 533 | __IO uint32_t SWTRIGR; /*!< DAC_MORT software trigger register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 534 | __IO uint32_t DHR12R1; /*!< DAC_MORT channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 535 | __IO uint32_t DHR12L1; /*!< DAC_MORT channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 536 | __IO uint32_t DHR8R1; /*!< DAC_MORT channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 537 | __IO uint32_t DHR12R2; /*!< DAC_MORT channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 538 | __IO uint32_t DHR12L2; /*!< DAC_MORT channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 539 | __IO uint32_t DHR8R2; /*!< DAC_MORT channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 540 | __IO uint32_t DHR12RD; /*!< Dual DAC_MORT 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 541 | __IO uint32_t DHR12LD; /*!< DUAL DAC_MORT 12-bit left aligned data holding register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 542 | __IO uint32_t DHR8RD; /*!< DUAL DAC_MORT 8-bit right aligned data holding register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 543 | __IO uint32_t DOR1; /*!< DAC_MORT channel1 data output register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 544 | __IO uint32_t DOR2; /*!< DAC_MORT channel2 data output register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 545 | __IO uint32_t SR; /*!< DAC_MORT status register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 546 | } DAC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 547 | |
| rajathr | 0:34ee385f4d2d | 548 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 549 | /** |
| rajathr | 0:34ee385f4d2d | 550 | * @brief DFSDM module registers |
| rajathr | 0:34ee385f4d2d | 551 | */ |
| rajathr | 0:34ee385f4d2d | 552 | typedef struct |
| rajathr | 0:34ee385f4d2d | 553 | { |
| rajathr | 0:34ee385f4d2d | 554 | __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ |
| rajathr | 0:34ee385f4d2d | 555 | __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ |
| rajathr | 0:34ee385f4d2d | 556 | __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ |
| rajathr | 0:34ee385f4d2d | 557 | __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ |
| rajathr | 0:34ee385f4d2d | 558 | __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ |
| rajathr | 0:34ee385f4d2d | 559 | __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ |
| rajathr | 0:34ee385f4d2d | 560 | __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ |
| rajathr | 0:34ee385f4d2d | 561 | __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ |
| rajathr | 0:34ee385f4d2d | 562 | __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ |
| rajathr | 0:34ee385f4d2d | 563 | __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ |
| rajathr | 0:34ee385f4d2d | 564 | __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ |
| rajathr | 0:34ee385f4d2d | 565 | __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ |
| rajathr | 0:34ee385f4d2d | 566 | __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ |
| rajathr | 0:34ee385f4d2d | 567 | __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ |
| rajathr | 0:34ee385f4d2d | 568 | __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ |
| rajathr | 0:34ee385f4d2d | 569 | } DFSDM_Filter_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 570 | |
| rajathr | 0:34ee385f4d2d | 571 | /** |
| rajathr | 0:34ee385f4d2d | 572 | * @brief DFSDM channel configuration registers |
| rajathr | 0:34ee385f4d2d | 573 | */ |
| rajathr | 0:34ee385f4d2d | 574 | typedef struct |
| rajathr | 0:34ee385f4d2d | 575 | { |
| rajathr | 0:34ee385f4d2d | 576 | __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 577 | __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 578 | __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and |
| rajathr | 0:34ee385f4d2d | 579 | short circuit detector register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 580 | __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 581 | __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 582 | } DFSDM_Channel_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 583 | |
| rajathr | 0:34ee385f4d2d | 584 | /* Legacy Defines */ |
| rajathr | 0:34ee385f4d2d | 585 | #define DFSDM_TypeDef DFSDM_Filter_TypeDef_mort |
| rajathr | 0:34ee385f4d2d | 586 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 587 | /** |
| rajathr | 0:34ee385f4d2d | 588 | * @brief Debug MCU |
| rajathr | 0:34ee385f4d2d | 589 | */ |
| rajathr | 0:34ee385f4d2d | 590 | |
| rajathr | 0:34ee385f4d2d | 591 | typedef struct |
| rajathr | 0:34ee385f4d2d | 592 | { |
| rajathr | 0:34ee385f4d2d | 593 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 594 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 595 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 596 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 597 | }DBGMCU_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 598 | |
| rajathr | 0:34ee385f4d2d | 599 | /** |
| rajathr | 0:34ee385f4d2d | 600 | * @brief DCMI_MORT |
| rajathr | 0:34ee385f4d2d | 601 | */ |
| rajathr | 0:34ee385f4d2d | 602 | |
| rajathr | 0:34ee385f4d2d | 603 | typedef struct |
| rajathr | 0:34ee385f4d2d | 604 | { |
| rajathr | 0:34ee385f4d2d | 605 | __IO uint32_t CR; /*!< DCMI_MORT control register 1, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 606 | __IO uint32_t SR; /*!< DCMI_MORT status register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 607 | __IO uint32_t RISR; /*!< DCMI_MORT raw interrupt status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 608 | __IO uint32_t IER; /*!< DCMI_MORT interrupt enable register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 609 | __IO uint32_t MISR; /*!< DCMI_MORT masked interrupt status register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 610 | __IO uint32_t ICR; /*!< DCMI_MORT interrupt clear register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 611 | __IO uint32_t ESCR; /*!< DCMI_MORT embedded synchronization code register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 612 | __IO uint32_t ESUR; /*!< DCMI_MORT embedded synchronization unmask register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 613 | __IO uint32_t CWSTRTR; /*!< DCMI_MORT crop window start, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 614 | __IO uint32_t CWSIZER; /*!< DCMI_MORT crop window size, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 615 | __IO uint32_t DR; /*!< DCMI_MORT data register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 616 | } DCMI_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 617 | |
| rajathr | 0:34ee385f4d2d | 618 | /** |
| rajathr | 0:34ee385f4d2d | 619 | * @brief DMA Controller |
| rajathr | 0:34ee385f4d2d | 620 | */ |
| rajathr | 0:34ee385f4d2d | 621 | |
| rajathr | 0:34ee385f4d2d | 622 | typedef struct |
| rajathr | 0:34ee385f4d2d | 623 | { |
| rajathr | 0:34ee385f4d2d | 624 | __IO uint32_t CR; /*!< DMA stream x configuration register */ |
| rajathr | 0:34ee385f4d2d | 625 | __IO uint32_t NDTR; /*!< DMA stream x number of data register */ |
| rajathr | 0:34ee385f4d2d | 626 | __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ |
| rajathr | 0:34ee385f4d2d | 627 | __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ |
| rajathr | 0:34ee385f4d2d | 628 | __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ |
| rajathr | 0:34ee385f4d2d | 629 | __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ |
| rajathr | 0:34ee385f4d2d | 630 | } DMA_Stream_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 631 | |
| rajathr | 0:34ee385f4d2d | 632 | typedef struct |
| rajathr | 0:34ee385f4d2d | 633 | { |
| rajathr | 0:34ee385f4d2d | 634 | __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 635 | __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 636 | __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 637 | __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 638 | } DMA_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 639 | |
| rajathr | 0:34ee385f4d2d | 640 | /** |
| rajathr | 0:34ee385f4d2d | 641 | * @brief DMA2D_MORT Controller |
| rajathr | 0:34ee385f4d2d | 642 | */ |
| rajathr | 0:34ee385f4d2d | 643 | |
| rajathr | 0:34ee385f4d2d | 644 | typedef struct |
| rajathr | 0:34ee385f4d2d | 645 | { |
| rajathr | 0:34ee385f4d2d | 646 | __IO uint32_t CR; /*!< DMA2D_MORT Control Register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 647 | __IO uint32_t ISR; /*!< DMA2D_MORT Interrupt Status Register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 648 | __IO uint32_t IFCR; /*!< DMA2D_MORT Interrupt Flag Clear Register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 649 | __IO uint32_t FGMAR; /*!< DMA2D_MORT Foreground Memory Address Register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 650 | __IO uint32_t FGOR; /*!< DMA2D_MORT Foreground Offset Register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 651 | __IO uint32_t BGMAR; /*!< DMA2D_MORT Background Memory Address Register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 652 | __IO uint32_t BGOR; /*!< DMA2D_MORT Background Offset Register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 653 | __IO uint32_t FGPFCCR; /*!< DMA2D_MORT Foreground PFC Control Register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 654 | __IO uint32_t FGCOLR; /*!< DMA2D_MORT Foreground Color Register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 655 | __IO uint32_t BGPFCCR; /*!< DMA2D_MORT Background PFC Control Register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 656 | __IO uint32_t BGCOLR; /*!< DMA2D_MORT Background Color Register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 657 | __IO uint32_t FGCMAR; /*!< DMA2D_MORT Foreground CLUT Memory Address Register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 658 | __IO uint32_t BGCMAR; /*!< DMA2D_MORT Background CLUT Memory Address Register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 659 | __IO uint32_t OPFCCR; /*!< DMA2D_MORT Output PFC Control Register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 660 | __IO uint32_t OCOLR; /*!< DMA2D_MORT Output Color Register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 661 | __IO uint32_t OMAR; /*!< DMA2D_MORT Output Memory Address Register, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 662 | __IO uint32_t OOR; /*!< DMA2D_MORT Output Offset Register, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 663 | __IO uint32_t NLR; /*!< DMA2D_MORT Number of Line Register, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 664 | __IO uint32_t LWR; /*!< DMA2D_MORT Line Watermark Register, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 665 | __IO uint32_t AMTCR; /*!< DMA2D_MORT AHB Master Timer Configuration Register, Address offset: 0x4C */ |
| rajathr | 0:34ee385f4d2d | 666 | uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ |
| rajathr | 0:34ee385f4d2d | 667 | __IO uint32_t FGCLUT[256]; /*!< DMA2D_MORT Foreground CLUT, Address offset:400-7FF */ |
| rajathr | 0:34ee385f4d2d | 668 | __IO uint32_t BGCLUT[256]; /*!< DMA2D_MORT Background CLUT, Address offset:800-BFF */ |
| rajathr | 0:34ee385f4d2d | 669 | } DMA2D_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 670 | |
| rajathr | 0:34ee385f4d2d | 671 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 672 | /** |
| rajathr | 0:34ee385f4d2d | 673 | * @brief DSI_MORT Controller |
| rajathr | 0:34ee385f4d2d | 674 | */ |
| rajathr | 0:34ee385f4d2d | 675 | |
| rajathr | 0:34ee385f4d2d | 676 | typedef struct |
| rajathr | 0:34ee385f4d2d | 677 | { |
| rajathr | 0:34ee385f4d2d | 678 | __IO uint32_t VR; /*!< DSI_MORT Host Version Register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 679 | __IO uint32_t CR; /*!< DSI_MORT Host Control Register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 680 | __IO uint32_t CCR; /*!< DSI_MORT HOST Clock Control Register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 681 | __IO uint32_t LVCIDR; /*!< DSI_MORT Host LTDC_MORT VCID Register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 682 | __IO uint32_t LCOLCR; /*!< DSI_MORT Host LTDC_MORT Color Coding Register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 683 | __IO uint32_t LPCR; /*!< DSI_MORT Host LTDC_MORT Polarity Configuration Register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 684 | __IO uint32_t LPMCR; /*!< DSI_MORT Host Low-Power Mode Configuration Register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 685 | uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ |
| rajathr | 0:34ee385f4d2d | 686 | __IO uint32_t PCR; /*!< DSI_MORT Host Protocol Configuration Register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 687 | __IO uint32_t GVCIDR; /*!< DSI_MORT Host Generic VCID Register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 688 | __IO uint32_t MCR; /*!< DSI_MORT Host Mode Configuration Register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 689 | __IO uint32_t VMCR; /*!< DSI_MORT Host Video Mode Configuration Register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 690 | __IO uint32_t VPCR; /*!< DSI_MORT Host Video Packet Configuration Register, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 691 | __IO uint32_t VCCR; /*!< DSI_MORT Host Video Chunks Configuration Register, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 692 | __IO uint32_t VNPCR; /*!< DSI_MORT Host Video Null Packet Configuration Register, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 693 | __IO uint32_t VHSACR; /*!< DSI_MORT Host Video HSA Configuration Register, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 694 | __IO uint32_t VHBPCR; /*!< DSI_MORT Host Video HBP Configuration Register, Address offset: 0x4C */ |
| rajathr | 0:34ee385f4d2d | 695 | __IO uint32_t VLCR; /*!< DSI_MORT Host Video Line Configuration Register, Address offset: 0x50 */ |
| rajathr | 0:34ee385f4d2d | 696 | __IO uint32_t VVSACR; /*!< DSI_MORT Host Video VSA Configuration Register, Address offset: 0x54 */ |
| rajathr | 0:34ee385f4d2d | 697 | __IO uint32_t VVBPCR; /*!< DSI_MORT Host Video VBP Configuration Register, Address offset: 0x58 */ |
| rajathr | 0:34ee385f4d2d | 698 | __IO uint32_t VVFPCR; /*!< DSI_MORT Host Video VFP Configuration Register, Address offset: 0x5C */ |
| rajathr | 0:34ee385f4d2d | 699 | __IO uint32_t VVACR; /*!< DSI_MORT Host Video VA Configuration Register, Address offset: 0x60 */ |
| rajathr | 0:34ee385f4d2d | 700 | __IO uint32_t LCCR; /*!< DSI_MORT Host LTDC_MORT Command Configuration Register, Address offset: 0x64 */ |
| rajathr | 0:34ee385f4d2d | 701 | __IO uint32_t CMCR; /*!< DSI_MORT Host Command Mode Configuration Register, Address offset: 0x68 */ |
| rajathr | 0:34ee385f4d2d | 702 | __IO uint32_t GHCR; /*!< DSI_MORT Host Generic Header Configuration Register, Address offset: 0x6C */ |
| rajathr | 0:34ee385f4d2d | 703 | __IO uint32_t GPDR; /*!< DSI_MORT Host Generic Payload Data Register, Address offset: 0x70 */ |
| rajathr | 0:34ee385f4d2d | 704 | __IO uint32_t GPSR; /*!< DSI_MORT Host Generic Packet Status Register, Address offset: 0x74 */ |
| rajathr | 0:34ee385f4d2d | 705 | __IO uint32_t TCCR[6]; /*!< DSI_MORT Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ |
| rajathr | 0:34ee385f4d2d | 706 | __IO uint32_t TDCR; /*!< DSI_MORT Host 3D Configuration Register, Address offset: 0x90 */ |
| rajathr | 0:34ee385f4d2d | 707 | __IO uint32_t CLCR; /*!< DSI_MORT Host Clock Lane Configuration Register, Address offset: 0x94 */ |
| rajathr | 0:34ee385f4d2d | 708 | __IO uint32_t CLTCR; /*!< DSI_MORT Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ |
| rajathr | 0:34ee385f4d2d | 709 | __IO uint32_t DLTCR; /*!< DSI_MORT Host Data Lane Timer Configuration Register, Address offset: 0x9C */ |
| rajathr | 0:34ee385f4d2d | 710 | __IO uint32_t PCTLR; /*!< DSI_MORT Host PHY Control Register, Address offset: 0xA0 */ |
| rajathr | 0:34ee385f4d2d | 711 | __IO uint32_t PCONFR; /*!< DSI_MORT Host PHY Configuration Register, Address offset: 0xA4 */ |
| rajathr | 0:34ee385f4d2d | 712 | __IO uint32_t PUCR; /*!< DSI_MORT Host PHY ULPS Control Register, Address offset: 0xA8 */ |
| rajathr | 0:34ee385f4d2d | 713 | __IO uint32_t PTTCR; /*!< DSI_MORT Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ |
| rajathr | 0:34ee385f4d2d | 714 | __IO uint32_t PSR; /*!< DSI_MORT Host PHY Status Register, Address offset: 0xB0 */ |
| rajathr | 0:34ee385f4d2d | 715 | uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ |
| rajathr | 0:34ee385f4d2d | 716 | __IO uint32_t ISR[2]; /*!< DSI_MORT Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ |
| rajathr | 0:34ee385f4d2d | 717 | __IO uint32_t IER[2]; /*!< DSI_MORT Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ |
| rajathr | 0:34ee385f4d2d | 718 | uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ |
| rajathr | 0:34ee385f4d2d | 719 | __IO uint32_t FIR[2]; /*!< DSI_MORT Host Force Interrupt Register, Address offset: 0xD8-0xDF */ |
| rajathr | 0:34ee385f4d2d | 720 | uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ |
| rajathr | 0:34ee385f4d2d | 721 | __IO uint32_t VSCR; /*!< DSI_MORT Host Video Shadow Control Register, Address offset: 0x100 */ |
| rajathr | 0:34ee385f4d2d | 722 | uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ |
| rajathr | 0:34ee385f4d2d | 723 | __IO uint32_t LCVCIDR; /*!< DSI_MORT Host LTDC_MORT Current VCID Register, Address offset: 0x10C */ |
| rajathr | 0:34ee385f4d2d | 724 | __IO uint32_t LCCCR; /*!< DSI_MORT Host LTDC_MORT Current Color Coding Register, Address offset: 0x110 */ |
| rajathr | 0:34ee385f4d2d | 725 | uint32_t RESERVED5; /*!< Reserved, 0x114 */ |
| rajathr | 0:34ee385f4d2d | 726 | __IO uint32_t LPMCCR; /*!< DSI_MORT Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ |
| rajathr | 0:34ee385f4d2d | 727 | uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ |
| rajathr | 0:34ee385f4d2d | 728 | __IO uint32_t VMCCR; /*!< DSI_MORT Host Video Mode Current Configuration Register, Address offset: 0x138 */ |
| rajathr | 0:34ee385f4d2d | 729 | __IO uint32_t VPCCR; /*!< DSI_MORT Host Video Packet Current Configuration Register, Address offset: 0x13C */ |
| rajathr | 0:34ee385f4d2d | 730 | __IO uint32_t VCCCR; /*!< DSI_MORT Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ |
| rajathr | 0:34ee385f4d2d | 731 | __IO uint32_t VNPCCR; /*!< DSI_MORT Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ |
| rajathr | 0:34ee385f4d2d | 732 | __IO uint32_t VHSACCR; /*!< DSI_MORT Host Video HSA Current Configuration Register, Address offset: 0x148 */ |
| rajathr | 0:34ee385f4d2d | 733 | __IO uint32_t VHBPCCR; /*!< DSI_MORT Host Video HBP Current Configuration Register, Address offset: 0x14C */ |
| rajathr | 0:34ee385f4d2d | 734 | __IO uint32_t VLCCR; /*!< DSI_MORT Host Video Line Current Configuration Register, Address offset: 0x150 */ |
| rajathr | 0:34ee385f4d2d | 735 | __IO uint32_t VVSACCR; /*!< DSI_MORT Host Video VSA Current Configuration Register, Address offset: 0x154 */ |
| rajathr | 0:34ee385f4d2d | 736 | __IO uint32_t VVBPCCR; /*!< DSI_MORT Host Video VBP Current Configuration Register, Address offset: 0x158 */ |
| rajathr | 0:34ee385f4d2d | 737 | __IO uint32_t VVFPCCR; /*!< DSI_MORT Host Video VFP Current Configuration Register, Address offset: 0x15C */ |
| rajathr | 0:34ee385f4d2d | 738 | __IO uint32_t VVACCR; /*!< DSI_MORT Host Video VA Current Configuration Register, Address offset: 0x160 */ |
| rajathr | 0:34ee385f4d2d | 739 | uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ |
| rajathr | 0:34ee385f4d2d | 740 | __IO uint32_t TDCCR; /*!< DSI_MORT Host 3D Current Configuration Register, Address offset: 0x190 */ |
| rajathr | 0:34ee385f4d2d | 741 | uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ |
| rajathr | 0:34ee385f4d2d | 742 | __IO uint32_t WCFGR; /*!< DSI_MORT Wrapper Configuration Register, Address offset: 0x400 */ |
| rajathr | 0:34ee385f4d2d | 743 | __IO uint32_t WCR; /*!< DSI_MORT Wrapper Control Register, Address offset: 0x404 */ |
| rajathr | 0:34ee385f4d2d | 744 | __IO uint32_t WIER; /*!< DSI_MORT Wrapper Interrupt Enable Register, Address offset: 0x408 */ |
| rajathr | 0:34ee385f4d2d | 745 | __IO uint32_t WISR; /*!< DSI_MORT Wrapper Interrupt and Status Register, Address offset: 0x40C */ |
| rajathr | 0:34ee385f4d2d | 746 | __IO uint32_t WIFCR; /*!< DSI_MORT Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ |
| rajathr | 0:34ee385f4d2d | 747 | uint32_t RESERVED9; /*!< Reserved, 0x414 */ |
| rajathr | 0:34ee385f4d2d | 748 | __IO uint32_t WPCR[5]; /*!< DSI_MORT Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ |
| rajathr | 0:34ee385f4d2d | 749 | uint32_t RESERVED10; /*!< Reserved, 0x42C */ |
| rajathr | 0:34ee385f4d2d | 750 | __IO uint32_t WRPCR; /*!< DSI_MORT Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ |
| rajathr | 0:34ee385f4d2d | 751 | } DSI_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 752 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 753 | |
| rajathr | 0:34ee385f4d2d | 754 | /** |
| rajathr | 0:34ee385f4d2d | 755 | * @brief Ethernet MAC |
| rajathr | 0:34ee385f4d2d | 756 | */ |
| rajathr | 0:34ee385f4d2d | 757 | |
| rajathr | 0:34ee385f4d2d | 758 | typedef struct |
| rajathr | 0:34ee385f4d2d | 759 | { |
| rajathr | 0:34ee385f4d2d | 760 | __IO uint32_t MACCR; |
| rajathr | 0:34ee385f4d2d | 761 | __IO uint32_t MACFFR; |
| rajathr | 0:34ee385f4d2d | 762 | __IO uint32_t MACHTHR; |
| rajathr | 0:34ee385f4d2d | 763 | __IO uint32_t MACHTLR; |
| rajathr | 0:34ee385f4d2d | 764 | __IO uint32_t MACMIIAR; |
| rajathr | 0:34ee385f4d2d | 765 | __IO uint32_t MACMIIDR; |
| rajathr | 0:34ee385f4d2d | 766 | __IO uint32_t MACFCR; |
| rajathr | 0:34ee385f4d2d | 767 | __IO uint32_t MACVLANTR; /* 8 */ |
| rajathr | 0:34ee385f4d2d | 768 | uint32_t RESERVED0[2]; |
| rajathr | 0:34ee385f4d2d | 769 | __IO uint32_t MACRWUFFR; /* 11 */ |
| rajathr | 0:34ee385f4d2d | 770 | __IO uint32_t MACPMTCSR; |
| rajathr | 0:34ee385f4d2d | 771 | uint32_t RESERVED1[2]; |
| rajathr | 0:34ee385f4d2d | 772 | __IO uint32_t MACSR; /* 15 */ |
| rajathr | 0:34ee385f4d2d | 773 | __IO uint32_t MACIMR; |
| rajathr | 0:34ee385f4d2d | 774 | __IO uint32_t MACA0HR; |
| rajathr | 0:34ee385f4d2d | 775 | __IO uint32_t MACA0LR; |
| rajathr | 0:34ee385f4d2d | 776 | __IO uint32_t MACA1HR; |
| rajathr | 0:34ee385f4d2d | 777 | __IO uint32_t MACA1LR; |
| rajathr | 0:34ee385f4d2d | 778 | __IO uint32_t MACA2HR; |
| rajathr | 0:34ee385f4d2d | 779 | __IO uint32_t MACA2LR; |
| rajathr | 0:34ee385f4d2d | 780 | __IO uint32_t MACA3HR; |
| rajathr | 0:34ee385f4d2d | 781 | __IO uint32_t MACA3LR; /* 24 */ |
| rajathr | 0:34ee385f4d2d | 782 | uint32_t RESERVED2[40]; |
| rajathr | 0:34ee385f4d2d | 783 | __IO uint32_t MMCCR; /* 65 */ |
| rajathr | 0:34ee385f4d2d | 784 | __IO uint32_t MMCRIR; |
| rajathr | 0:34ee385f4d2d | 785 | __IO uint32_t MMCTIR; |
| rajathr | 0:34ee385f4d2d | 786 | __IO uint32_t MMCRIMR; |
| rajathr | 0:34ee385f4d2d | 787 | __IO uint32_t MMCTIMR; /* 69 */ |
| rajathr | 0:34ee385f4d2d | 788 | uint32_t RESERVED3[14]; |
| rajathr | 0:34ee385f4d2d | 789 | __IO uint32_t MMCTGFSCCR; /* 84 */ |
| rajathr | 0:34ee385f4d2d | 790 | __IO uint32_t MMCTGFMSCCR; |
| rajathr | 0:34ee385f4d2d | 791 | uint32_t RESERVED4[5]; |
| rajathr | 0:34ee385f4d2d | 792 | __IO uint32_t MMCTGFCR; |
| rajathr | 0:34ee385f4d2d | 793 | uint32_t RESERVED5[10]; |
| rajathr | 0:34ee385f4d2d | 794 | __IO uint32_t MMCRFCECR; |
| rajathr | 0:34ee385f4d2d | 795 | __IO uint32_t MMCRFAECR; |
| rajathr | 0:34ee385f4d2d | 796 | uint32_t RESERVED6[10]; |
| rajathr | 0:34ee385f4d2d | 797 | __IO uint32_t MMCRGUFCR; |
| rajathr | 0:34ee385f4d2d | 798 | uint32_t RESERVED7[334]; |
| rajathr | 0:34ee385f4d2d | 799 | __IO uint32_t PTPTSCR; |
| rajathr | 0:34ee385f4d2d | 800 | __IO uint32_t PTPSSIR; |
| rajathr | 0:34ee385f4d2d | 801 | __IO uint32_t PTPTSHR; |
| rajathr | 0:34ee385f4d2d | 802 | __IO uint32_t PTPTSLR; |
| rajathr | 0:34ee385f4d2d | 803 | __IO uint32_t PTPTSHUR; |
| rajathr | 0:34ee385f4d2d | 804 | __IO uint32_t PTPTSLUR; |
| rajathr | 0:34ee385f4d2d | 805 | __IO uint32_t PTPTSAR; |
| rajathr | 0:34ee385f4d2d | 806 | __IO uint32_t PTPTTHR; |
| rajathr | 0:34ee385f4d2d | 807 | __IO uint32_t PTPTTLR; |
| rajathr | 0:34ee385f4d2d | 808 | __IO uint32_t RESERVED8; |
| rajathr | 0:34ee385f4d2d | 809 | __IO uint32_t PTPTSSR; |
| rajathr | 0:34ee385f4d2d | 810 | uint32_t RESERVED9[565]; |
| rajathr | 0:34ee385f4d2d | 811 | __IO uint32_t DMABMR; |
| rajathr | 0:34ee385f4d2d | 812 | __IO uint32_t DMATPDR; |
| rajathr | 0:34ee385f4d2d | 813 | __IO uint32_t DMARPDR; |
| rajathr | 0:34ee385f4d2d | 814 | __IO uint32_t DMARDLAR; |
| rajathr | 0:34ee385f4d2d | 815 | __IO uint32_t DMATDLAR; |
| rajathr | 0:34ee385f4d2d | 816 | __IO uint32_t DMASR; |
| rajathr | 0:34ee385f4d2d | 817 | __IO uint32_t DMAOMR; |
| rajathr | 0:34ee385f4d2d | 818 | __IO uint32_t DMAIER; |
| rajathr | 0:34ee385f4d2d | 819 | __IO uint32_t DMAMFBOCR; |
| rajathr | 0:34ee385f4d2d | 820 | __IO uint32_t DMARSWTR; |
| rajathr | 0:34ee385f4d2d | 821 | uint32_t RESERVED10[8]; |
| rajathr | 0:34ee385f4d2d | 822 | __IO uint32_t DMACHTDR; |
| rajathr | 0:34ee385f4d2d | 823 | __IO uint32_t DMACHRDR; |
| rajathr | 0:34ee385f4d2d | 824 | __IO uint32_t DMACHTBAR; |
| rajathr | 0:34ee385f4d2d | 825 | __IO uint32_t DMACHRBAR; |
| rajathr | 0:34ee385f4d2d | 826 | } ETH_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 827 | |
| rajathr | 0:34ee385f4d2d | 828 | /** |
| rajathr | 0:34ee385f4d2d | 829 | * @brief External Interrupt/Event Controller |
| rajathr | 0:34ee385f4d2d | 830 | */ |
| rajathr | 0:34ee385f4d2d | 831 | |
| rajathr | 0:34ee385f4d2d | 832 | typedef struct |
| rajathr | 0:34ee385f4d2d | 833 | { |
| rajathr | 0:34ee385f4d2d | 834 | __IO uint32_t IMR; /*!< EXTI_MORT Interrupt mask register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 835 | __IO uint32_t EMR; /*!< EXTI_MORT Event mask register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 836 | __IO uint32_t RTSR; /*!< EXTI_MORT Rising trigger selection register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 837 | __IO uint32_t FTSR; /*!< EXTI_MORT Falling trigger selection register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 838 | __IO uint32_t SWIER; /*!< EXTI_MORT Software interrupt event register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 839 | __IO uint32_t PR; /*!< EXTI_MORT Pending register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 840 | } EXTI_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 841 | |
| rajathr | 0:34ee385f4d2d | 842 | /** |
| rajathr | 0:34ee385f4d2d | 843 | * @brief FLASH_MORT Registers |
| rajathr | 0:34ee385f4d2d | 844 | */ |
| rajathr | 0:34ee385f4d2d | 845 | |
| rajathr | 0:34ee385f4d2d | 846 | typedef struct |
| rajathr | 0:34ee385f4d2d | 847 | { |
| rajathr | 0:34ee385f4d2d | 848 | __IO uint32_t ACR; /*!< FLASH_MORT access control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 849 | __IO uint32_t KEYR; /*!< FLASH_MORT key register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 850 | __IO uint32_t OPTKEYR; /*!< FLASH_MORT option key register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 851 | __IO uint32_t SR; /*!< FLASH_MORT status register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 852 | __IO uint32_t CR; /*!< FLASH_MORT control register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 853 | __IO uint32_t OPTCR; /*!< FLASH_MORT option control register , Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 854 | __IO uint32_t OPTCR1; /*!< FLASH_MORT option control register 1, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 855 | } FLASH_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 856 | |
| rajathr | 0:34ee385f4d2d | 857 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 858 | /** |
| rajathr | 0:34ee385f4d2d | 859 | * @brief Flexible Static Memory Controller |
| rajathr | 0:34ee385f4d2d | 860 | */ |
| rajathr | 0:34ee385f4d2d | 861 | |
| rajathr | 0:34ee385f4d2d | 862 | typedef struct |
| rajathr | 0:34ee385f4d2d | 863 | { |
| rajathr | 0:34ee385f4d2d | 864 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| rajathr | 0:34ee385f4d2d | 865 | } FSMC_Bank1_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 866 | |
| rajathr | 0:34ee385f4d2d | 867 | /** |
| rajathr | 0:34ee385f4d2d | 868 | * @brief Flexible Static Memory Controller Bank1E |
| rajathr | 0:34ee385f4d2d | 869 | */ |
| rajathr | 0:34ee385f4d2d | 870 | |
| rajathr | 0:34ee385f4d2d | 871 | typedef struct |
| rajathr | 0:34ee385f4d2d | 872 | { |
| rajathr | 0:34ee385f4d2d | 873 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| rajathr | 0:34ee385f4d2d | 874 | } FSMC_Bank1E_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 875 | |
| rajathr | 0:34ee385f4d2d | 876 | /** |
| rajathr | 0:34ee385f4d2d | 877 | * @brief Flexible Static Memory Controller Bank2 |
| rajathr | 0:34ee385f4d2d | 878 | */ |
| rajathr | 0:34ee385f4d2d | 879 | |
| rajathr | 0:34ee385f4d2d | 880 | typedef struct |
| rajathr | 0:34ee385f4d2d | 881 | { |
| rajathr | 0:34ee385f4d2d | 882 | __IO uint32_t PCR2; /*!< NAND FLASH_MORT control register 2, Address offset: 0x60 */ |
| rajathr | 0:34ee385f4d2d | 883 | __IO uint32_t SR2; /*!< NAND FLASH_MORT FIFO status and interrupt register 2, Address offset: 0x64 */ |
| rajathr | 0:34ee385f4d2d | 884 | __IO uint32_t PMEM2; /*!< NAND FLASH_MORT Common memory space timing register 2, Address offset: 0x68 */ |
| rajathr | 0:34ee385f4d2d | 885 | __IO uint32_t PATT2; /*!< NAND FLASH_MORT Attribute memory space timing register 2, Address offset: 0x6C */ |
| rajathr | 0:34ee385f4d2d | 886 | uint32_t RESERVED0; /*!< Reserved, 0x70 */ |
| rajathr | 0:34ee385f4d2d | 887 | __IO uint32_t ECCR2; /*!< NAND FLASH_MORT ECC result registers 2, Address offset: 0x74 */ |
| rajathr | 0:34ee385f4d2d | 888 | } FSMC_Bank2_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 889 | |
| rajathr | 0:34ee385f4d2d | 890 | /** |
| rajathr | 0:34ee385f4d2d | 891 | * @brief Flexible Static Memory Controller Bank3 |
| rajathr | 0:34ee385f4d2d | 892 | */ |
| rajathr | 0:34ee385f4d2d | 893 | |
| rajathr | 0:34ee385f4d2d | 894 | typedef struct |
| rajathr | 0:34ee385f4d2d | 895 | { |
| rajathr | 0:34ee385f4d2d | 896 | __IO uint32_t PCR3; /*!< NAND FLASH_MORT control register 3, Address offset: 0x80 */ |
| rajathr | 0:34ee385f4d2d | 897 | __IO uint32_t SR3; /*!< NAND FLASH_MORT FIFO status and interrupt register 3, Address offset: 0x84 */ |
| rajathr | 0:34ee385f4d2d | 898 | __IO uint32_t PMEM3; /*!< NAND FLASH_MORT Common memory space timing register 3, Address offset: 0x88 */ |
| rajathr | 0:34ee385f4d2d | 899 | __IO uint32_t PATT3; /*!< NAND FLASH_MORT Attribute memory space timing register 3, Address offset: 0x8C */ |
| rajathr | 0:34ee385f4d2d | 900 | uint32_t RESERVED0; /*!< Reserved, 0x90 */ |
| rajathr | 0:34ee385f4d2d | 901 | __IO uint32_t ECCR3; /*!< NAND FLASH_MORT ECC result registers 3, Address offset: 0x94 */ |
| rajathr | 0:34ee385f4d2d | 902 | } FSMC_Bank3_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 903 | |
| rajathr | 0:34ee385f4d2d | 904 | /** |
| rajathr | 0:34ee385f4d2d | 905 | * @brief Flexible Static Memory Controller Bank4 |
| rajathr | 0:34ee385f4d2d | 906 | */ |
| rajathr | 0:34ee385f4d2d | 907 | |
| rajathr | 0:34ee385f4d2d | 908 | typedef struct |
| rajathr | 0:34ee385f4d2d | 909 | { |
| rajathr | 0:34ee385f4d2d | 910 | __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ |
| rajathr | 0:34ee385f4d2d | 911 | __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ |
| rajathr | 0:34ee385f4d2d | 912 | __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ |
| rajathr | 0:34ee385f4d2d | 913 | __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ |
| rajathr | 0:34ee385f4d2d | 914 | __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ |
| rajathr | 0:34ee385f4d2d | 915 | } FSMC_Bank4_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 916 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 917 | |
| rajathr | 0:34ee385f4d2d | 918 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 919 | /** |
| rajathr | 0:34ee385f4d2d | 920 | * @brief Flexible Memory Controller |
| rajathr | 0:34ee385f4d2d | 921 | */ |
| rajathr | 0:34ee385f4d2d | 922 | |
| rajathr | 0:34ee385f4d2d | 923 | typedef struct |
| rajathr | 0:34ee385f4d2d | 924 | { |
| rajathr | 0:34ee385f4d2d | 925 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| rajathr | 0:34ee385f4d2d | 926 | } FMC_Bank1_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 927 | |
| rajathr | 0:34ee385f4d2d | 928 | /** |
| rajathr | 0:34ee385f4d2d | 929 | * @brief Flexible Memory Controller Bank1E |
| rajathr | 0:34ee385f4d2d | 930 | */ |
| rajathr | 0:34ee385f4d2d | 931 | |
| rajathr | 0:34ee385f4d2d | 932 | typedef struct |
| rajathr | 0:34ee385f4d2d | 933 | { |
| rajathr | 0:34ee385f4d2d | 934 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| rajathr | 0:34ee385f4d2d | 935 | } FMC_Bank1E_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 936 | |
| rajathr | 0:34ee385f4d2d | 937 | /** |
| rajathr | 0:34ee385f4d2d | 938 | * @brief Flexible Memory Controller Bank2 |
| rajathr | 0:34ee385f4d2d | 939 | */ |
| rajathr | 0:34ee385f4d2d | 940 | |
| rajathr | 0:34ee385f4d2d | 941 | typedef struct |
| rajathr | 0:34ee385f4d2d | 942 | { |
| rajathr | 0:34ee385f4d2d | 943 | __IO uint32_t PCR2; /*!< NAND FLASH_MORT control register 2, Address offset: 0x60 */ |
| rajathr | 0:34ee385f4d2d | 944 | __IO uint32_t SR2; /*!< NAND FLASH_MORT FIFO status and interrupt register 2, Address offset: 0x64 */ |
| rajathr | 0:34ee385f4d2d | 945 | __IO uint32_t PMEM2; /*!< NAND FLASH_MORT Common memory space timing register 2, Address offset: 0x68 */ |
| rajathr | 0:34ee385f4d2d | 946 | __IO uint32_t PATT2; /*!< NAND FLASH_MORT Attribute memory space timing register 2, Address offset: 0x6C */ |
| rajathr | 0:34ee385f4d2d | 947 | uint32_t RESERVED0; /*!< Reserved, 0x70 */ |
| rajathr | 0:34ee385f4d2d | 948 | __IO uint32_t ECCR2; /*!< NAND FLASH_MORT ECC result registers 2, Address offset: 0x74 */ |
| rajathr | 0:34ee385f4d2d | 949 | } FMC_Bank2_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 950 | |
| rajathr | 0:34ee385f4d2d | 951 | /** |
| rajathr | 0:34ee385f4d2d | 952 | * @brief Flexible Memory Controller Bank3 |
| rajathr | 0:34ee385f4d2d | 953 | */ |
| rajathr | 0:34ee385f4d2d | 954 | |
| rajathr | 0:34ee385f4d2d | 955 | typedef struct |
| rajathr | 0:34ee385f4d2d | 956 | { |
| rajathr | 0:34ee385f4d2d | 957 | __IO uint32_t PCR3; /*!< NAND FLASH_MORT control register 3, Address offset: 0x80 */ |
| rajathr | 0:34ee385f4d2d | 958 | __IO uint32_t SR3; /*!< NAND FLASH_MORT FIFO status and interrupt register 3, Address offset: 0x84 */ |
| rajathr | 0:34ee385f4d2d | 959 | __IO uint32_t PMEM3; /*!< NAND FLASH_MORT Common memory space timing register 3, Address offset: 0x88 */ |
| rajathr | 0:34ee385f4d2d | 960 | __IO uint32_t PATT3; /*!< NAND FLASH_MORT Attribute memory space timing register 3, Address offset: 0x8C */ |
| rajathr | 0:34ee385f4d2d | 961 | uint32_t RESERVED0; /*!< Reserved, 0x90 */ |
| rajathr | 0:34ee385f4d2d | 962 | __IO uint32_t ECCR3; /*!< NAND FLASH_MORT ECC result registers 3, Address offset: 0x94 */ |
| rajathr | 0:34ee385f4d2d | 963 | } FMC_Bank3_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 964 | |
| rajathr | 0:34ee385f4d2d | 965 | /** |
| rajathr | 0:34ee385f4d2d | 966 | * @brief Flexible Memory Controller Bank4 |
| rajathr | 0:34ee385f4d2d | 967 | */ |
| rajathr | 0:34ee385f4d2d | 968 | |
| rajathr | 0:34ee385f4d2d | 969 | typedef struct |
| rajathr | 0:34ee385f4d2d | 970 | { |
| rajathr | 0:34ee385f4d2d | 971 | __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ |
| rajathr | 0:34ee385f4d2d | 972 | __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ |
| rajathr | 0:34ee385f4d2d | 973 | __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ |
| rajathr | 0:34ee385f4d2d | 974 | __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ |
| rajathr | 0:34ee385f4d2d | 975 | __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ |
| rajathr | 0:34ee385f4d2d | 976 | } FMC_Bank4_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 977 | |
| rajathr | 0:34ee385f4d2d | 978 | /** |
| rajathr | 0:34ee385f4d2d | 979 | * @brief Flexible Memory Controller Bank5_6 |
| rajathr | 0:34ee385f4d2d | 980 | */ |
| rajathr | 0:34ee385f4d2d | 981 | |
| rajathr | 0:34ee385f4d2d | 982 | typedef struct |
| rajathr | 0:34ee385f4d2d | 983 | { |
| rajathr | 0:34ee385f4d2d | 984 | __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ |
| rajathr | 0:34ee385f4d2d | 985 | __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ |
| rajathr | 0:34ee385f4d2d | 986 | __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ |
| rajathr | 0:34ee385f4d2d | 987 | __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ |
| rajathr | 0:34ee385f4d2d | 988 | __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ |
| rajathr | 0:34ee385f4d2d | 989 | } FMC_Bank5_6_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 990 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 991 | |
| rajathr | 0:34ee385f4d2d | 992 | /** |
| rajathr | 0:34ee385f4d2d | 993 | * @brief General Purpose I/O |
| rajathr | 0:34ee385f4d2d | 994 | */ |
| rajathr | 0:34ee385f4d2d | 995 | |
| rajathr | 0:34ee385f4d2d | 996 | typedef struct |
| rajathr | 0:34ee385f4d2d | 997 | { |
| rajathr | 0:34ee385f4d2d | 998 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 999 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1000 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1001 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1002 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1003 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1004 | __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1005 | __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1006 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1007 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| rajathr | 0:34ee385f4d2d | 1008 | } GPIO_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1009 | |
| rajathr | 0:34ee385f4d2d | 1010 | /** |
| rajathr | 0:34ee385f4d2d | 1011 | * @brief System configuration controller |
| rajathr | 0:34ee385f4d2d | 1012 | */ |
| rajathr | 0:34ee385f4d2d | 1013 | |
| rajathr | 0:34ee385f4d2d | 1014 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1015 | { |
| rajathr | 0:34ee385f4d2d | 1016 | __IO uint32_t MEMRMP; /*!< SYSCFG_MORT memory remap register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1017 | __IO uint32_t PMC; /*!< SYSCFG_MORT peripheral mode configuration register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1018 | __IO uint32_t EXTICR[4]; /*!< SYSCFG_MORT external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| rajathr | 0:34ee385f4d2d | 1019 | #if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1020 | uint32_t RESERVED; /*!< Reserved, 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1021 | __IO uint32_t CFGR2; /*!< Reserved, 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1022 | __IO uint32_t CMPCR; /*!< SYSCFG_MORT Compensation cell control register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1023 | uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */ |
| rajathr | 0:34ee385f4d2d | 1024 | __IO uint32_t CFGR; /*!< SYSCFG_MORT Configuration register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1025 | #else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1026 | uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ |
| rajathr | 0:34ee385f4d2d | 1027 | __IO uint32_t CMPCR; /*!< SYSCFG_MORT Compensation cell control register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1028 | #endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */ |
| rajathr | 0:34ee385f4d2d | 1029 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1030 | __IO uint32_t MCHDLYCR; /*!< SYSCFG_MORT multi-channel delay register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1031 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1032 | } SYSCFG_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1033 | |
| rajathr | 0:34ee385f4d2d | 1034 | /** |
| rajathr | 0:34ee385f4d2d | 1035 | * @brief Inter-integrated Circuit Interface |
| rajathr | 0:34ee385f4d2d | 1036 | */ |
| rajathr | 0:34ee385f4d2d | 1037 | |
| rajathr | 0:34ee385f4d2d | 1038 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1039 | { |
| rajathr | 0:34ee385f4d2d | 1040 | __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1041 | uint16_t RESERVED0; /*!< Reserved, 0x02 */ |
| rajathr | 0:34ee385f4d2d | 1042 | __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1043 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 1044 | __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1045 | uint16_t RESERVED2; /*!< Reserved, 0x0A */ |
| rajathr | 0:34ee385f4d2d | 1046 | __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1047 | uint16_t RESERVED3; /*!< Reserved, 0x0E */ |
| rajathr | 0:34ee385f4d2d | 1048 | __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1049 | uint16_t RESERVED4; /*!< Reserved, 0x12 */ |
| rajathr | 0:34ee385f4d2d | 1050 | __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1051 | uint16_t RESERVED5; /*!< Reserved, 0x16 */ |
| rajathr | 0:34ee385f4d2d | 1052 | __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1053 | uint16_t RESERVED6; /*!< Reserved, 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1054 | __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1055 | uint16_t RESERVED7; /*!< Reserved, 0x1E */ |
| rajathr | 0:34ee385f4d2d | 1056 | __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1057 | uint16_t RESERVED8; /*!< Reserved, 0x22 */ |
| rajathr | 0:34ee385f4d2d | 1058 | __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1059 | uint16_t RESERVED9; /*!< Reserved, 0x26 */ |
| rajathr | 0:34ee385f4d2d | 1060 | } I2C_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1061 | |
| rajathr | 0:34ee385f4d2d | 1062 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1063 | /** |
| rajathr | 0:34ee385f4d2d | 1064 | * @brief Inter-integrated Circuit Interface |
| rajathr | 0:34ee385f4d2d | 1065 | */ |
| rajathr | 0:34ee385f4d2d | 1066 | |
| rajathr | 0:34ee385f4d2d | 1067 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1068 | { |
| rajathr | 0:34ee385f4d2d | 1069 | __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1070 | __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1071 | __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1072 | __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1073 | __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1074 | __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1075 | __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1076 | __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1077 | __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1078 | __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1079 | __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1080 | }FMPI2C_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1081 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1082 | |
| rajathr | 0:34ee385f4d2d | 1083 | /** |
| rajathr | 0:34ee385f4d2d | 1084 | * @brief Independent WATCHDOG |
| rajathr | 0:34ee385f4d2d | 1085 | */ |
| rajathr | 0:34ee385f4d2d | 1086 | |
| rajathr | 0:34ee385f4d2d | 1087 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1088 | { |
| rajathr | 0:34ee385f4d2d | 1089 | __IO uint32_t KR; /*!< IWDG_MORT Key register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1090 | __IO uint32_t PR; /*!< IWDG_MORT Prescaler register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1091 | __IO uint32_t RLR; /*!< IWDG_MORT Reload register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1092 | __IO uint32_t SR; /*!< IWDG_MORT Status register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1093 | } IWDG_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1094 | |
| rajathr | 0:34ee385f4d2d | 1095 | /** |
| rajathr | 0:34ee385f4d2d | 1096 | * @brief LCD-TFT Display Controller |
| rajathr | 0:34ee385f4d2d | 1097 | */ |
| rajathr | 0:34ee385f4d2d | 1098 | |
| rajathr | 0:34ee385f4d2d | 1099 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1100 | { |
| rajathr | 0:34ee385f4d2d | 1101 | uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ |
| rajathr | 0:34ee385f4d2d | 1102 | __IO uint32_t SSCR; /*!< LTDC_MORT Synchronization Size Configuration Register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1103 | __IO uint32_t BPCR; /*!< LTDC_MORT Back Porch Configuration Register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1104 | __IO uint32_t AWCR; /*!< LTDC_MORT Active Width Configuration Register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1105 | __IO uint32_t TWCR; /*!< LTDC_MORT Total Width Configuration Register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1106 | __IO uint32_t GCR; /*!< LTDC_MORT Global Control Register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1107 | uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ |
| rajathr | 0:34ee385f4d2d | 1108 | __IO uint32_t SRCR; /*!< LTDC_MORT Shadow Reload Configuration Register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1109 | uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1110 | __IO uint32_t BCCR; /*!< LTDC_MORT Background Color Configuration Register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1111 | uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1112 | __IO uint32_t IER; /*!< LTDC_MORT Interrupt Enable Register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 1113 | __IO uint32_t ISR; /*!< LTDC_MORT Interrupt Status Register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 1114 | __IO uint32_t ICR; /*!< LTDC_MORT Interrupt Clear Register, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 1115 | __IO uint32_t LIPCR; /*!< LTDC_MORT Line Interrupt Position Configuration Register, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 1116 | __IO uint32_t CPSR; /*!< LTDC_MORT Current Position Status Register, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 1117 | __IO uint32_t CDSR; /*!< LTDC_MORT Current Display Status Register, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 1118 | } LTDC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1119 | |
| rajathr | 0:34ee385f4d2d | 1120 | /** |
| rajathr | 0:34ee385f4d2d | 1121 | * @brief LCD-TFT Display layer x Controller |
| rajathr | 0:34ee385f4d2d | 1122 | */ |
| rajathr | 0:34ee385f4d2d | 1123 | |
| rajathr | 0:34ee385f4d2d | 1124 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1125 | { |
| rajathr | 0:34ee385f4d2d | 1126 | __IO uint32_t CR; /*!< LTDC_MORT Layerx Control Register Address offset: 0x84 */ |
| rajathr | 0:34ee385f4d2d | 1127 | __IO uint32_t WHPCR; /*!< LTDC_MORT Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ |
| rajathr | 0:34ee385f4d2d | 1128 | __IO uint32_t WVPCR; /*!< LTDC_MORT Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ |
| rajathr | 0:34ee385f4d2d | 1129 | __IO uint32_t CKCR; /*!< LTDC_MORT Layerx Color Keying Configuration Register Address offset: 0x90 */ |
| rajathr | 0:34ee385f4d2d | 1130 | __IO uint32_t PFCR; /*!< LTDC_MORT Layerx Pixel Format Configuration Register Address offset: 0x94 */ |
| rajathr | 0:34ee385f4d2d | 1131 | __IO uint32_t CACR; /*!< LTDC_MORT Layerx Constant Alpha Configuration Register Address offset: 0x98 */ |
| rajathr | 0:34ee385f4d2d | 1132 | __IO uint32_t DCCR; /*!< LTDC_MORT Layerx Default Color Configuration Register Address offset: 0x9C */ |
| rajathr | 0:34ee385f4d2d | 1133 | __IO uint32_t BFCR; /*!< LTDC_MORT Layerx Blending Factors Configuration Register Address offset: 0xA0 */ |
| rajathr | 0:34ee385f4d2d | 1134 | uint32_t RESERVED0[2]; /*!< Reserved */ |
| rajathr | 0:34ee385f4d2d | 1135 | __IO uint32_t CFBAR; /*!< LTDC_MORT Layerx Color Frame Buffer Address Register Address offset: 0xAC */ |
| rajathr | 0:34ee385f4d2d | 1136 | __IO uint32_t CFBLR; /*!< LTDC_MORT Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ |
| rajathr | 0:34ee385f4d2d | 1137 | __IO uint32_t CFBLNR; /*!< LTDC_MORT Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ |
| rajathr | 0:34ee385f4d2d | 1138 | uint32_t RESERVED1[3]; /*!< Reserved */ |
| rajathr | 0:34ee385f4d2d | 1139 | __IO uint32_t CLUTWR; /*!< LTDC_MORT Layerx CLUT Write Register Address offset: 0x144 */ |
| rajathr | 0:34ee385f4d2d | 1140 | |
| rajathr | 0:34ee385f4d2d | 1141 | } LTDC_Layer_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1142 | |
| rajathr | 0:34ee385f4d2d | 1143 | /** |
| rajathr | 0:34ee385f4d2d | 1144 | * @brief Power Control |
| rajathr | 0:34ee385f4d2d | 1145 | */ |
| rajathr | 0:34ee385f4d2d | 1146 | |
| rajathr | 0:34ee385f4d2d | 1147 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1148 | { |
| rajathr | 0:34ee385f4d2d | 1149 | __IO uint32_t CR; /*!< PWR_MORT power control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1150 | __IO uint32_t CSR; /*!< PWR_MORT power control/status register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1151 | } PWR_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1152 | |
| rajathr | 0:34ee385f4d2d | 1153 | /** |
| rajathr | 0:34ee385f4d2d | 1154 | * @brief Reset and Clock Control |
| rajathr | 0:34ee385f4d2d | 1155 | */ |
| rajathr | 0:34ee385f4d2d | 1156 | |
| rajathr | 0:34ee385f4d2d | 1157 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1158 | { |
| rajathr | 0:34ee385f4d2d | 1159 | __IO uint32_t CR; /*!< RCC_MORT clock control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1160 | __IO uint32_t PLLCFGR; /*!< RCC_MORT PLL configuration register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1161 | __IO uint32_t CFGR; /*!< RCC_MORT clock configuration register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1162 | __IO uint32_t CIR; /*!< RCC_MORT clock interrupt register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1163 | __IO uint32_t AHB1RSTR; /*!< RCC_MORT AHB1 peripheral reset register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1164 | __IO uint32_t AHB2RSTR; /*!< RCC_MORT AHB2 peripheral reset register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1165 | __IO uint32_t AHB3RSTR; /*!< RCC_MORT AHB3 peripheral reset register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1166 | uint32_t RESERVED0; /*!< Reserved, 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1167 | __IO uint32_t APB1RSTR; /*!< RCC_MORT APB1 peripheral reset register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1168 | __IO uint32_t APB2RSTR; /*!< RCC_MORT APB2 peripheral reset register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1169 | uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ |
| rajathr | 0:34ee385f4d2d | 1170 | __IO uint32_t AHB1ENR; /*!< RCC_MORT AHB1 peripheral clock register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1171 | __IO uint32_t AHB2ENR; /*!< RCC_MORT AHB2 peripheral clock register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 1172 | __IO uint32_t AHB3ENR; /*!< RCC_MORT AHB3 peripheral clock register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 1173 | uint32_t RESERVED2; /*!< Reserved, 0x3C */ |
| rajathr | 0:34ee385f4d2d | 1174 | __IO uint32_t APB1ENR; /*!< RCC_MORT APB1 peripheral clock enable register, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 1175 | __IO uint32_t APB2ENR; /*!< RCC_MORT APB2 peripheral clock enable register, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 1176 | uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ |
| rajathr | 0:34ee385f4d2d | 1177 | __IO uint32_t AHB1LPENR; /*!< RCC_MORT AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ |
| rajathr | 0:34ee385f4d2d | 1178 | __IO uint32_t AHB2LPENR; /*!< RCC_MORT AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ |
| rajathr | 0:34ee385f4d2d | 1179 | __IO uint32_t AHB3LPENR; /*!< RCC_MORT AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ |
| rajathr | 0:34ee385f4d2d | 1180 | uint32_t RESERVED4; /*!< Reserved, 0x5C */ |
| rajathr | 0:34ee385f4d2d | 1181 | __IO uint32_t APB1LPENR; /*!< RCC_MORT APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ |
| rajathr | 0:34ee385f4d2d | 1182 | __IO uint32_t APB2LPENR; /*!< RCC_MORT APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ |
| rajathr | 0:34ee385f4d2d | 1183 | uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ |
| rajathr | 0:34ee385f4d2d | 1184 | __IO uint32_t BDCR; /*!< RCC_MORT Backup domain control register, Address offset: 0x70 */ |
| rajathr | 0:34ee385f4d2d | 1185 | __IO uint32_t CSR; /*!< RCC_MORT clock control & status register, Address offset: 0x74 */ |
| rajathr | 0:34ee385f4d2d | 1186 | uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ |
| rajathr | 0:34ee385f4d2d | 1187 | __IO uint32_t SSCGR; /*!< RCC_MORT spread spectrum clock generation register, Address offset: 0x80 */ |
| rajathr | 0:34ee385f4d2d | 1188 | __IO uint32_t PLLI2SCFGR; /*!< RCC_MORT PLLI2S configuration register, Address offset: 0x84 */ |
| rajathr | 0:34ee385f4d2d | 1189 | __IO uint32_t PLLSAICFGR; /*!< RCC_MORT PLLSAI configuration register, Address offset: 0x88 */ |
| rajathr | 0:34ee385f4d2d | 1190 | __IO uint32_t DCKCFGR; /*!< RCC_MORT Dedicated Clocks configuration register, Address offset: 0x8C */ |
| rajathr | 0:34ee385f4d2d | 1191 | __IO uint32_t CKGATENR; /*!< RCC_MORT Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx_MORT devices */ |
| rajathr | 0:34ee385f4d2d | 1192 | __IO uint32_t DCKCFGR2; /*!< RCC_MORT Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx_MORT devices */ |
| rajathr | 0:34ee385f4d2d | 1193 | |
| rajathr | 0:34ee385f4d2d | 1194 | } RCC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1195 | |
| rajathr | 0:34ee385f4d2d | 1196 | /** |
| rajathr | 0:34ee385f4d2d | 1197 | * @brief Real-Time Clock |
| rajathr | 0:34ee385f4d2d | 1198 | */ |
| rajathr | 0:34ee385f4d2d | 1199 | |
| rajathr | 0:34ee385f4d2d | 1200 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1201 | { |
| rajathr | 0:34ee385f4d2d | 1202 | __IO uint32_t TR; /*!< RTC_MORT time register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1203 | __IO uint32_t DR; /*!< RTC_MORT date register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1204 | __IO uint32_t CR; /*!< RTC_MORT control register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1205 | __IO uint32_t ISR; /*!< RTC_MORT initialization and status register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1206 | __IO uint32_t PRER; /*!< RTC_MORT prescaler register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1207 | __IO uint32_t WUTR; /*!< RTC_MORT wakeup timer register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1208 | __IO uint32_t CALIBR; /*!< RTC_MORT calibration register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1209 | __IO uint32_t ALRMAR; /*!< RTC_MORT alarm A register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1210 | __IO uint32_t ALRMBR; /*!< RTC_MORT alarm B register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1211 | __IO uint32_t WPR; /*!< RTC_MORT write protection register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1212 | __IO uint32_t SSR; /*!< RTC_MORT sub second register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1213 | __IO uint32_t SHIFTR; /*!< RTC_MORT shift control register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1214 | __IO uint32_t TSTR; /*!< RTC_MORT time stamp time register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1215 | __IO uint32_t TSDR; /*!< RTC_MORT time stamp date register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 1216 | __IO uint32_t TSSSR; /*!< RTC_MORT time-stamp sub second register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 1217 | __IO uint32_t CALR; /*!< RTC_MORT calibration register, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 1218 | __IO uint32_t TAFCR; /*!< RTC_MORT tamper and alternate function configuration register, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 1219 | __IO uint32_t ALRMASSR;/*!< RTC_MORT alarm A sub second register, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 1220 | __IO uint32_t ALRMBSSR;/*!< RTC_MORT alarm B sub second register, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 1221 | uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
| rajathr | 0:34ee385f4d2d | 1222 | __IO uint32_t BKP0R; /*!< RTC_MORT backup register 1, Address offset: 0x50 */ |
| rajathr | 0:34ee385f4d2d | 1223 | __IO uint32_t BKP1R; /*!< RTC_MORT backup register 1, Address offset: 0x54 */ |
| rajathr | 0:34ee385f4d2d | 1224 | __IO uint32_t BKP2R; /*!< RTC_MORT backup register 2, Address offset: 0x58 */ |
| rajathr | 0:34ee385f4d2d | 1225 | __IO uint32_t BKP3R; /*!< RTC_MORT backup register 3, Address offset: 0x5C */ |
| rajathr | 0:34ee385f4d2d | 1226 | __IO uint32_t BKP4R; /*!< RTC_MORT backup register 4, Address offset: 0x60 */ |
| rajathr | 0:34ee385f4d2d | 1227 | __IO uint32_t BKP5R; /*!< RTC_MORT backup register 5, Address offset: 0x64 */ |
| rajathr | 0:34ee385f4d2d | 1228 | __IO uint32_t BKP6R; /*!< RTC_MORT backup register 6, Address offset: 0x68 */ |
| rajathr | 0:34ee385f4d2d | 1229 | __IO uint32_t BKP7R; /*!< RTC_MORT backup register 7, Address offset: 0x6C */ |
| rajathr | 0:34ee385f4d2d | 1230 | __IO uint32_t BKP8R; /*!< RTC_MORT backup register 8, Address offset: 0x70 */ |
| rajathr | 0:34ee385f4d2d | 1231 | __IO uint32_t BKP9R; /*!< RTC_MORT backup register 9, Address offset: 0x74 */ |
| rajathr | 0:34ee385f4d2d | 1232 | __IO uint32_t BKP10R; /*!< RTC_MORT backup register 10, Address offset: 0x78 */ |
| rajathr | 0:34ee385f4d2d | 1233 | __IO uint32_t BKP11R; /*!< RTC_MORT backup register 11, Address offset: 0x7C */ |
| rajathr | 0:34ee385f4d2d | 1234 | __IO uint32_t BKP12R; /*!< RTC_MORT backup register 12, Address offset: 0x80 */ |
| rajathr | 0:34ee385f4d2d | 1235 | __IO uint32_t BKP13R; /*!< RTC_MORT backup register 13, Address offset: 0x84 */ |
| rajathr | 0:34ee385f4d2d | 1236 | __IO uint32_t BKP14R; /*!< RTC_MORT backup register 14, Address offset: 0x88 */ |
| rajathr | 0:34ee385f4d2d | 1237 | __IO uint32_t BKP15R; /*!< RTC_MORT backup register 15, Address offset: 0x8C */ |
| rajathr | 0:34ee385f4d2d | 1238 | __IO uint32_t BKP16R; /*!< RTC_MORT backup register 16, Address offset: 0x90 */ |
| rajathr | 0:34ee385f4d2d | 1239 | __IO uint32_t BKP17R; /*!< RTC_MORT backup register 17, Address offset: 0x94 */ |
| rajathr | 0:34ee385f4d2d | 1240 | __IO uint32_t BKP18R; /*!< RTC_MORT backup register 18, Address offset: 0x98 */ |
| rajathr | 0:34ee385f4d2d | 1241 | __IO uint32_t BKP19R; /*!< RTC_MORT backup register 19, Address offset: 0x9C */ |
| rajathr | 0:34ee385f4d2d | 1242 | } RTC_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1243 | |
| rajathr | 0:34ee385f4d2d | 1244 | |
| rajathr | 0:34ee385f4d2d | 1245 | /** |
| rajathr | 0:34ee385f4d2d | 1246 | * @brief Serial Audio Interface |
| rajathr | 0:34ee385f4d2d | 1247 | */ |
| rajathr | 0:34ee385f4d2d | 1248 | |
| rajathr | 0:34ee385f4d2d | 1249 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1250 | { |
| rajathr | 0:34ee385f4d2d | 1251 | __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1252 | } SAI_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1253 | |
| rajathr | 0:34ee385f4d2d | 1254 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1255 | { |
| rajathr | 0:34ee385f4d2d | 1256 | __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1257 | __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1258 | __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1259 | __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1260 | __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1261 | __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1262 | __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1263 | __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1264 | } SAI_Block_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1265 | |
| rajathr | 0:34ee385f4d2d | 1266 | /** |
| rajathr | 0:34ee385f4d2d | 1267 | * @brief SD host Interface |
| rajathr | 0:34ee385f4d2d | 1268 | */ |
| rajathr | 0:34ee385f4d2d | 1269 | |
| rajathr | 0:34ee385f4d2d | 1270 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1271 | { |
| rajathr | 0:34ee385f4d2d | 1272 | __IO uint32_t POWER; /*!< SDIO_MORT power control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1273 | __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1274 | __IO uint32_t ARG; /*!< SDIO_MORT argument register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1275 | __IO uint32_t CMD; /*!< SDIO_MORT command register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1276 | __I uint32_t RESPCMD; /*!< SDIO_MORT command response register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1277 | __I uint32_t RESP1; /*!< SDIO_MORT response 1 register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1278 | __I uint32_t RESP2; /*!< SDIO_MORT response 2 register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1279 | __I uint32_t RESP3; /*!< SDIO_MORT response 3 register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1280 | __I uint32_t RESP4; /*!< SDIO_MORT response 4 register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1281 | __IO uint32_t DTIMER; /*!< SDIO_MORT data timer register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1282 | __IO uint32_t DLEN; /*!< SDIO_MORT data length register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1283 | __IO uint32_t DCTRL; /*!< SDIO_MORT data control register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1284 | __I uint32_t DCOUNT; /*!< SDIO_MORT data counter register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1285 | __I uint32_t STA; /*!< SDIO_MORT status register, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 1286 | __IO uint32_t ICR; /*!< SDIO_MORT interrupt clear register, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 1287 | __IO uint32_t MASK; /*!< SDIO_MORT mask register, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 1288 | uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
| rajathr | 0:34ee385f4d2d | 1289 | __I uint32_t FIFOCNT; /*!< SDIO_MORT FIFO counter register, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 1290 | uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
| rajathr | 0:34ee385f4d2d | 1291 | __IO uint32_t FIFO; /*!< SDIO_MORT data FIFO register, Address offset: 0x80 */ |
| rajathr | 0:34ee385f4d2d | 1292 | } SDIO_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1293 | |
| rajathr | 0:34ee385f4d2d | 1294 | /** |
| rajathr | 0:34ee385f4d2d | 1295 | * @brief Serial Peripheral Interface |
| rajathr | 0:34ee385f4d2d | 1296 | */ |
| rajathr | 0:34ee385f4d2d | 1297 | |
| rajathr | 0:34ee385f4d2d | 1298 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1299 | { |
| rajathr | 0:34ee385f4d2d | 1300 | __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1301 | uint16_t RESERVED0; /*!< Reserved, 0x02 */ |
| rajathr | 0:34ee385f4d2d | 1302 | __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1303 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 1304 | __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1305 | uint16_t RESERVED2; /*!< Reserved, 0x0A */ |
| rajathr | 0:34ee385f4d2d | 1306 | __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1307 | uint16_t RESERVED3; /*!< Reserved, 0x0E */ |
| rajathr | 0:34ee385f4d2d | 1308 | __IO uint16_t CRCPR; /*!< SPI CRC_MORT polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1309 | uint16_t RESERVED4; /*!< Reserved, 0x12 */ |
| rajathr | 0:34ee385f4d2d | 1310 | __IO uint16_t RXCRCR; /*!< SPI RX CRC_MORT register (not used in I2S mode), Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1311 | uint16_t RESERVED5; /*!< Reserved, 0x16 */ |
| rajathr | 0:34ee385f4d2d | 1312 | __IO uint16_t TXCRCR; /*!< SPI TX CRC_MORT register (not used in I2S mode), Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1313 | uint16_t RESERVED6; /*!< Reserved, 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1314 | __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1315 | uint16_t RESERVED7; /*!< Reserved, 0x1E */ |
| rajathr | 0:34ee385f4d2d | 1316 | __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1317 | uint16_t RESERVED8; /*!< Reserved, 0x22 */ |
| rajathr | 0:34ee385f4d2d | 1318 | } SPI_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1319 | |
| rajathr | 0:34ee385f4d2d | 1320 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1321 | /** |
| rajathr | 0:34ee385f4d2d | 1322 | * @brief SPDIFRX_MORT Interface |
| rajathr | 0:34ee385f4d2d | 1323 | */ |
| rajathr | 0:34ee385f4d2d | 1324 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1325 | { |
| rajathr | 0:34ee385f4d2d | 1326 | __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1327 | __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1328 | uint16_t RESERVED0; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 1329 | __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1330 | __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1331 | uint16_t RESERVED1; /*!< Reserved, 0x0E */ |
| rajathr | 0:34ee385f4d2d | 1332 | __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1333 | __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1334 | __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1335 | uint16_t RESERVED2; /*!< Reserved, 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1336 | } SPDIFRX_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1337 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1338 | |
| rajathr | 0:34ee385f4d2d | 1339 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1340 | /** |
| rajathr | 0:34ee385f4d2d | 1341 | * @brief QUAD Serial Peripheral Interface |
| rajathr | 0:34ee385f4d2d | 1342 | */ |
| rajathr | 0:34ee385f4d2d | 1343 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1344 | { |
| rajathr | 0:34ee385f4d2d | 1345 | __IO uint32_t CR; /*!< QUADSPI_MORT Control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1346 | __IO uint32_t DCR; /*!< QUADSPI_MORT Device Configuration register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1347 | __IO uint32_t SR; /*!< QUADSPI_MORT Status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1348 | __IO uint32_t FCR; /*!< QUADSPI_MORT Flag Clear register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1349 | __IO uint32_t DLR; /*!< QUADSPI_MORT Data Length register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1350 | __IO uint32_t CCR; /*!< QUADSPI_MORT Communication Configuration register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1351 | __IO uint32_t AR; /*!< QUADSPI_MORT Address register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1352 | __IO uint32_t ABR; /*!< QUADSPI_MORT Alternate Bytes register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1353 | __IO uint32_t DR; /*!< QUADSPI_MORT Data register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1354 | __IO uint32_t PSMKR; /*!< QUADSPI_MORT Polling Status Mask register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1355 | __IO uint32_t PSMAR; /*!< QUADSPI_MORT Polling Status Match register, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1356 | __IO uint32_t PIR; /*!< QUADSPI_MORT Polling Interval register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1357 | __IO uint32_t LPTR; /*!< QUADSPI_MORT Low Power Timeout register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1358 | } QUADSPI_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1359 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1360 | |
| rajathr | 0:34ee385f4d2d | 1361 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1362 | /** |
| rajathr | 0:34ee385f4d2d | 1363 | * @brief SPDIF-RX Interface |
| rajathr | 0:34ee385f4d2d | 1364 | */ |
| rajathr | 0:34ee385f4d2d | 1365 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1366 | { |
| rajathr | 0:34ee385f4d2d | 1367 | __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1368 | __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1369 | uint16_t RESERVED0; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 1370 | __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1371 | __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1372 | uint16_t RESERVED1; /*!< Reserved, 0x0E */ |
| rajathr | 0:34ee385f4d2d | 1373 | __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1374 | __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1375 | __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1376 | uint16_t RESERVED2; /*!< Reserved, 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1377 | } SPDIF_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1378 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1379 | |
| rajathr | 0:34ee385f4d2d | 1380 | /** |
| rajathr | 0:34ee385f4d2d | 1381 | * @brief TIM |
| rajathr | 0:34ee385f4d2d | 1382 | */ |
| rajathr | 0:34ee385f4d2d | 1383 | |
| rajathr | 0:34ee385f4d2d | 1384 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1385 | { |
| rajathr | 0:34ee385f4d2d | 1386 | __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1387 | uint16_t RESERVED0; /*!< Reserved, 0x02 */ |
| rajathr | 0:34ee385f4d2d | 1388 | __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1389 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 1390 | __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1391 | uint16_t RESERVED2; /*!< Reserved, 0x0A */ |
| rajathr | 0:34ee385f4d2d | 1392 | __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1393 | uint16_t RESERVED3; /*!< Reserved, 0x0E */ |
| rajathr | 0:34ee385f4d2d | 1394 | __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1395 | uint16_t RESERVED4; /*!< Reserved, 0x12 */ |
| rajathr | 0:34ee385f4d2d | 1396 | __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1397 | uint16_t RESERVED5; /*!< Reserved, 0x16 */ |
| rajathr | 0:34ee385f4d2d | 1398 | __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1399 | uint16_t RESERVED6; /*!< Reserved, 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1400 | __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1401 | uint16_t RESERVED7; /*!< Reserved, 0x1E */ |
| rajathr | 0:34ee385f4d2d | 1402 | __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1403 | uint16_t RESERVED8; /*!< Reserved, 0x22 */ |
| rajathr | 0:34ee385f4d2d | 1404 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1405 | __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1406 | uint16_t RESERVED9; /*!< Reserved, 0x2A */ |
| rajathr | 0:34ee385f4d2d | 1407 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1408 | __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1409 | uint16_t RESERVED10; /*!< Reserved, 0x32 */ |
| rajathr | 0:34ee385f4d2d | 1410 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 1411 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 1412 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 1413 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 1414 | __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 1415 | uint16_t RESERVED11; /*!< Reserved, 0x46 */ |
| rajathr | 0:34ee385f4d2d | 1416 | __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 1417 | uint16_t RESERVED12; /*!< Reserved, 0x4A */ |
| rajathr | 0:34ee385f4d2d | 1418 | __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| rajathr | 0:34ee385f4d2d | 1419 | uint16_t RESERVED13; /*!< Reserved, 0x4E */ |
| rajathr | 0:34ee385f4d2d | 1420 | __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| rajathr | 0:34ee385f4d2d | 1421 | uint16_t RESERVED14; /*!< Reserved, 0x52 */ |
| rajathr | 0:34ee385f4d2d | 1422 | } TIM_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1423 | |
| rajathr | 0:34ee385f4d2d | 1424 | /** |
| rajathr | 0:34ee385f4d2d | 1425 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| rajathr | 0:34ee385f4d2d | 1426 | */ |
| rajathr | 0:34ee385f4d2d | 1427 | |
| rajathr | 0:34ee385f4d2d | 1428 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1429 | { |
| rajathr | 0:34ee385f4d2d | 1430 | __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1431 | uint16_t RESERVED0; /*!< Reserved, 0x02 */ |
| rajathr | 0:34ee385f4d2d | 1432 | __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1433 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| rajathr | 0:34ee385f4d2d | 1434 | __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1435 | uint16_t RESERVED2; /*!< Reserved, 0x0A */ |
| rajathr | 0:34ee385f4d2d | 1436 | __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1437 | uint16_t RESERVED3; /*!< Reserved, 0x0E */ |
| rajathr | 0:34ee385f4d2d | 1438 | __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1439 | uint16_t RESERVED4; /*!< Reserved, 0x12 */ |
| rajathr | 0:34ee385f4d2d | 1440 | __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1441 | uint16_t RESERVED5; /*!< Reserved, 0x16 */ |
| rajathr | 0:34ee385f4d2d | 1442 | __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1443 | uint16_t RESERVED6; /*!< Reserved, 0x1A */ |
| rajathr | 0:34ee385f4d2d | 1444 | } USART_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1445 | |
| rajathr | 0:34ee385f4d2d | 1446 | /** |
| rajathr | 0:34ee385f4d2d | 1447 | * @brief Window WATCHDOG |
| rajathr | 0:34ee385f4d2d | 1448 | */ |
| rajathr | 0:34ee385f4d2d | 1449 | |
| rajathr | 0:34ee385f4d2d | 1450 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1451 | { |
| rajathr | 0:34ee385f4d2d | 1452 | __IO uint32_t CR; /*!< WWDG_MORT Control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1453 | __IO uint32_t CFR; /*!< WWDG_MORT Configuration register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1454 | __IO uint32_t SR; /*!< WWDG_MORT Status register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1455 | } WWDG_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1456 | |
| rajathr | 0:34ee385f4d2d | 1457 | /** |
| rajathr | 0:34ee385f4d2d | 1458 | * @brief Crypto Processor |
| rajathr | 0:34ee385f4d2d | 1459 | */ |
| rajathr | 0:34ee385f4d2d | 1460 | |
| rajathr | 0:34ee385f4d2d | 1461 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1462 | { |
| rajathr | 0:34ee385f4d2d | 1463 | __IO uint32_t CR; /*!< CRYP_MORT control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1464 | __IO uint32_t SR; /*!< CRYP_MORT status register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1465 | __IO uint32_t DR; /*!< CRYP_MORT data input register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1466 | __IO uint32_t DOUT; /*!< CRYP_MORT data output register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1467 | __IO uint32_t DMACR; /*!< CRYP_MORT DMA control register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1468 | __IO uint32_t IMSCR; /*!< CRYP_MORT interrupt mask set/clear register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1469 | __IO uint32_t RISR; /*!< CRYP_MORT raw interrupt status register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1470 | __IO uint32_t MISR; /*!< CRYP_MORT masked interrupt status register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1471 | __IO uint32_t K0LR; /*!< CRYP_MORT key left register 0, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1472 | __IO uint32_t K0RR; /*!< CRYP_MORT key right register 0, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1473 | __IO uint32_t K1LR; /*!< CRYP_MORT key left register 1, Address offset: 0x28 */ |
| rajathr | 0:34ee385f4d2d | 1474 | __IO uint32_t K1RR; /*!< CRYP_MORT key right register 1, Address offset: 0x2C */ |
| rajathr | 0:34ee385f4d2d | 1475 | __IO uint32_t K2LR; /*!< CRYP_MORT key left register 2, Address offset: 0x30 */ |
| rajathr | 0:34ee385f4d2d | 1476 | __IO uint32_t K2RR; /*!< CRYP_MORT key right register 2, Address offset: 0x34 */ |
| rajathr | 0:34ee385f4d2d | 1477 | __IO uint32_t K3LR; /*!< CRYP_MORT key left register 3, Address offset: 0x38 */ |
| rajathr | 0:34ee385f4d2d | 1478 | __IO uint32_t K3RR; /*!< CRYP_MORT key right register 3, Address offset: 0x3C */ |
| rajathr | 0:34ee385f4d2d | 1479 | __IO uint32_t IV0LR; /*!< CRYP_MORT initialization vector left-word register 0, Address offset: 0x40 */ |
| rajathr | 0:34ee385f4d2d | 1480 | __IO uint32_t IV0RR; /*!< CRYP_MORT initialization vector right-word register 0, Address offset: 0x44 */ |
| rajathr | 0:34ee385f4d2d | 1481 | __IO uint32_t IV1LR; /*!< CRYP_MORT initialization vector left-word register 1, Address offset: 0x48 */ |
| rajathr | 0:34ee385f4d2d | 1482 | __IO uint32_t IV1RR; /*!< CRYP_MORT initialization vector right-word register 1, Address offset: 0x4C */ |
| rajathr | 0:34ee385f4d2d | 1483 | __IO uint32_t CSGCMCCM0R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ |
| rajathr | 0:34ee385f4d2d | 1484 | __IO uint32_t CSGCMCCM1R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ |
| rajathr | 0:34ee385f4d2d | 1485 | __IO uint32_t CSGCMCCM2R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ |
| rajathr | 0:34ee385f4d2d | 1486 | __IO uint32_t CSGCMCCM3R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ |
| rajathr | 0:34ee385f4d2d | 1487 | __IO uint32_t CSGCMCCM4R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ |
| rajathr | 0:34ee385f4d2d | 1488 | __IO uint32_t CSGCMCCM5R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ |
| rajathr | 0:34ee385f4d2d | 1489 | __IO uint32_t CSGCMCCM6R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ |
| rajathr | 0:34ee385f4d2d | 1490 | __IO uint32_t CSGCMCCM7R; /*!< CRYP_MORT GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ |
| rajathr | 0:34ee385f4d2d | 1491 | __IO uint32_t CSGCM0R; /*!< CRYP_MORT GCM/GMAC context swap register 0, Address offset: 0x70 */ |
| rajathr | 0:34ee385f4d2d | 1492 | __IO uint32_t CSGCM1R; /*!< CRYP_MORT GCM/GMAC context swap register 1, Address offset: 0x74 */ |
| rajathr | 0:34ee385f4d2d | 1493 | __IO uint32_t CSGCM2R; /*!< CRYP_MORT GCM/GMAC context swap register 2, Address offset: 0x78 */ |
| rajathr | 0:34ee385f4d2d | 1494 | __IO uint32_t CSGCM3R; /*!< CRYP_MORT GCM/GMAC context swap register 3, Address offset: 0x7C */ |
| rajathr | 0:34ee385f4d2d | 1495 | __IO uint32_t CSGCM4R; /*!< CRYP_MORT GCM/GMAC context swap register 4, Address offset: 0x80 */ |
| rajathr | 0:34ee385f4d2d | 1496 | __IO uint32_t CSGCM5R; /*!< CRYP_MORT GCM/GMAC context swap register 5, Address offset: 0x84 */ |
| rajathr | 0:34ee385f4d2d | 1497 | __IO uint32_t CSGCM6R; /*!< CRYP_MORT GCM/GMAC context swap register 6, Address offset: 0x88 */ |
| rajathr | 0:34ee385f4d2d | 1498 | __IO uint32_t CSGCM7R; /*!< CRYP_MORT GCM/GMAC context swap register 7, Address offset: 0x8C */ |
| rajathr | 0:34ee385f4d2d | 1499 | } CRYP_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1500 | |
| rajathr | 0:34ee385f4d2d | 1501 | /** |
| rajathr | 0:34ee385f4d2d | 1502 | * @brief HASH_MORT |
| rajathr | 0:34ee385f4d2d | 1503 | */ |
| rajathr | 0:34ee385f4d2d | 1504 | |
| rajathr | 0:34ee385f4d2d | 1505 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1506 | { |
| rajathr | 0:34ee385f4d2d | 1507 | __IO uint32_t CR; /*!< HASH_MORT control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1508 | __IO uint32_t DIN; /*!< HASH_MORT data input register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1509 | __IO uint32_t STR; /*!< HASH_MORT start register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1510 | __IO uint32_t HR[5]; /*!< HASH_MORT digest registers, Address offset: 0x0C-0x1C */ |
| rajathr | 0:34ee385f4d2d | 1511 | __IO uint32_t IMR; /*!< HASH_MORT interrupt enable register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1512 | __IO uint32_t SR; /*!< HASH_MORT status register, Address offset: 0x24 */ |
| rajathr | 0:34ee385f4d2d | 1513 | uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ |
| rajathr | 0:34ee385f4d2d | 1514 | __IO uint32_t CSR[54]; /*!< HASH_MORT context swap registers, Address offset: 0x0F8-0x1CC */ |
| rajathr | 0:34ee385f4d2d | 1515 | } HASH_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1516 | |
| rajathr | 0:34ee385f4d2d | 1517 | /** |
| rajathr | 0:34ee385f4d2d | 1518 | * @brief HASH_DIGEST_MORT |
| rajathr | 0:34ee385f4d2d | 1519 | */ |
| rajathr | 0:34ee385f4d2d | 1520 | |
| rajathr | 0:34ee385f4d2d | 1521 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1522 | { |
| rajathr | 0:34ee385f4d2d | 1523 | __IO uint32_t HR[8]; /*!< HASH_MORT digest registers, Address offset: 0x310-0x32C */ |
| rajathr | 0:34ee385f4d2d | 1524 | } HASH_DIGEST_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1525 | |
| rajathr | 0:34ee385f4d2d | 1526 | /** |
| rajathr | 0:34ee385f4d2d | 1527 | * @brief RNG_MORT |
| rajathr | 0:34ee385f4d2d | 1528 | */ |
| rajathr | 0:34ee385f4d2d | 1529 | |
| rajathr | 0:34ee385f4d2d | 1530 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1531 | { |
| rajathr | 0:34ee385f4d2d | 1532 | __IO uint32_t CR; /*!< RNG_MORT control register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1533 | __IO uint32_t SR; /*!< RNG_MORT status register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1534 | __IO uint32_t DR; /*!< RNG_MORT data register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1535 | } RNG_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1536 | |
| rajathr | 0:34ee385f4d2d | 1537 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1538 | /** |
| rajathr | 0:34ee385f4d2d | 1539 | * @brief LPTIMER |
| rajathr | 0:34ee385f4d2d | 1540 | */ |
| rajathr | 0:34ee385f4d2d | 1541 | typedef struct |
| rajathr | 0:34ee385f4d2d | 1542 | { |
| rajathr | 0:34ee385f4d2d | 1543 | __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ |
| rajathr | 0:34ee385f4d2d | 1544 | __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ |
| rajathr | 0:34ee385f4d2d | 1545 | __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ |
| rajathr | 0:34ee385f4d2d | 1546 | __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ |
| rajathr | 0:34ee385f4d2d | 1547 | __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ |
| rajathr | 0:34ee385f4d2d | 1548 | __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ |
| rajathr | 0:34ee385f4d2d | 1549 | __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ |
| rajathr | 0:34ee385f4d2d | 1550 | __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ |
| rajathr | 0:34ee385f4d2d | 1551 | __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ |
| rajathr | 0:34ee385f4d2d | 1552 | } LPTIM_TypeDef_mort; |
| rajathr | 0:34ee385f4d2d | 1553 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1554 | /** |
| rajathr | 0:34ee385f4d2d | 1555 | * @} |
| rajathr | 0:34ee385f4d2d | 1556 | */ |
| rajathr | 0:34ee385f4d2d | 1557 | |
| rajathr | 0:34ee385f4d2d | 1558 | /** @addtogroup Peripheral_memory_map |
| rajathr | 0:34ee385f4d2d | 1559 | * @{ |
| rajathr | 0:34ee385f4d2d | 1560 | */ |
| rajathr | 0:34ee385f4d2d | 1561 | |
| rajathr | 0:34ee385f4d2d | 1562 | #define FLASH_BASE_MORT ((uint32_t)0x08000000) /*!< FLASH_MORT(up to 1 MB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1563 | #define CCMDATARAM_BASE_MORT ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1564 | #define SRAM1_BASE_MORT ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1565 | #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1566 | #define SRAM2_BASE_MORT ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1567 | #define SRAM3_BASE_MORT ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1568 | #elif defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1569 | #define SRAM2_BASE_MORT ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1570 | #define SRAM3_BASE_MORT ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1571 | #elif defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1572 | #define SRAM2_BASE_MORT ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1573 | #else /* STM32F411xE || STM32F410xx || STM32F412xG */ |
| rajathr | 0:34ee385f4d2d | 1574 | #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1575 | #define PERIPH_BASE_MORT ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1576 | #define BKPSRAM_BASE_MORT ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ |
| rajathr | 0:34ee385f4d2d | 1577 | |
| rajathr | 0:34ee385f4d2d | 1578 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1579 | #define FSMC_R_BASE_MORT ((uint32_t)0xA0000000) /*!< FSMC registers base address */ |
| rajathr | 0:34ee385f4d2d | 1580 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1581 | |
| rajathr | 0:34ee385f4d2d | 1582 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1583 | #define FMC_R_BASE_MORT ((uint32_t)0xA0000000) /*!< FMC registers base address */ |
| rajathr | 0:34ee385f4d2d | 1584 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1585 | |
| rajathr | 0:34ee385f4d2d | 1586 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1587 | #define QSPI_R_BASE_MORT ((uint32_t)0xA0001000) /*!< QUADSPI_MORT registers base address */ |
| rajathr | 0:34ee385f4d2d | 1588 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1589 | |
| rajathr | 0:34ee385f4d2d | 1590 | #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1591 | #define SRAM1_BB_BASE_MORT ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1592 | #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1593 | #define SRAM2_BB_BASE_MORT ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1594 | #define SRAM3_BB_BASE_MORT ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1595 | #elif defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1596 | #define SRAM2_BB_BASE_MORT ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1597 | #define SRAM3_BB_BASE_MORT ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1598 | #elif defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1599 | #define SRAM2_BB_BASE_MORT ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1600 | #else /* STM32F411xE || STM32F410xx || STM32F412xG */ |
| rajathr | 0:34ee385f4d2d | 1601 | #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1602 | #define PERIPH_BB_BASE_MORT ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1603 | #define BKPSRAM_BB_BASE_MORT ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ |
| rajathr | 0:34ee385f4d2d | 1604 | |
| rajathr | 0:34ee385f4d2d | 1605 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 1606 | #define SRAM_BASE_MORT SRAM1_BASE_MORT |
| rajathr | 0:34ee385f4d2d | 1607 | #define SRAM_BB_BASE_MORT SRAM1_BB_BASE_MORT |
| rajathr | 0:34ee385f4d2d | 1608 | |
| rajathr | 0:34ee385f4d2d | 1609 | |
| rajathr | 0:34ee385f4d2d | 1610 | /*!< Peripheral memory map */ |
| rajathr | 0:34ee385f4d2d | 1611 | #define APB1PERIPH_BASE_MORT PERIPH_BASE_MORT |
| rajathr | 0:34ee385f4d2d | 1612 | #define APB2PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x00010000) |
| rajathr | 0:34ee385f4d2d | 1613 | #define AHB1PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x00020000) |
| rajathr | 0:34ee385f4d2d | 1614 | #define AHB2PERIPH_BASE_MORT (PERIPH_BASE_MORT + 0x10000000) |
| rajathr | 0:34ee385f4d2d | 1615 | |
| rajathr | 0:34ee385f4d2d | 1616 | /*!< APB1 peripherals */ |
| rajathr | 0:34ee385f4d2d | 1617 | #define TIM2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0000) |
| rajathr | 0:34ee385f4d2d | 1618 | #define TIM3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0400) |
| rajathr | 0:34ee385f4d2d | 1619 | #define TIM4_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0800) |
| rajathr | 0:34ee385f4d2d | 1620 | #define TIM5_BASE_MORT (APB1PERIPH_BASE_MORT + 0x0C00) |
| rajathr | 0:34ee385f4d2d | 1621 | #define TIM6_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1000) |
| rajathr | 0:34ee385f4d2d | 1622 | #define TIM7_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1400) |
| rajathr | 0:34ee385f4d2d | 1623 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1624 | #define LPTIM1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2400) |
| rajathr | 0:34ee385f4d2d | 1625 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1626 | #define TIM12_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1800) |
| rajathr | 0:34ee385f4d2d | 1627 | #define TIM13_BASE_MORT (APB1PERIPH_BASE_MORT + 0x1C00) |
| rajathr | 0:34ee385f4d2d | 1628 | #define TIM14_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2000) |
| rajathr | 0:34ee385f4d2d | 1629 | #define RTC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2800) |
| rajathr | 0:34ee385f4d2d | 1630 | #define WWDG_BASE_MORT (APB1PERIPH_BASE_MORT + 0x2C00) |
| rajathr | 0:34ee385f4d2d | 1631 | #define IWDG_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3000) |
| rajathr | 0:34ee385f4d2d | 1632 | #define I2S2ext_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3400) |
| rajathr | 0:34ee385f4d2d | 1633 | #define SPI2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3800) |
| rajathr | 0:34ee385f4d2d | 1634 | #define SPI3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x3C00) |
| rajathr | 0:34ee385f4d2d | 1635 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1636 | #define SPDIFRX_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4000) |
| rajathr | 0:34ee385f4d2d | 1637 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1638 | #define I2S3ext_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4000) |
| rajathr | 0:34ee385f4d2d | 1639 | #define USART2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4400) |
| rajathr | 0:34ee385f4d2d | 1640 | #define USART3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4800) |
| rajathr | 0:34ee385f4d2d | 1641 | #define UART4_BASE_MORT (APB1PERIPH_BASE_MORT + 0x4C00) |
| rajathr | 0:34ee385f4d2d | 1642 | #define UART5_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5000) |
| rajathr | 0:34ee385f4d2d | 1643 | #define I2C1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5400) |
| rajathr | 0:34ee385f4d2d | 1644 | #define I2C2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5800) |
| rajathr | 0:34ee385f4d2d | 1645 | #define I2C3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x5C00) |
| rajathr | 0:34ee385f4d2d | 1646 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1647 | #define FMPI2C1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6000) |
| rajathr | 0:34ee385f4d2d | 1648 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1649 | #define CAN1_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6400) |
| rajathr | 0:34ee385f4d2d | 1650 | #define CAN2_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6800) |
| rajathr | 0:34ee385f4d2d | 1651 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1652 | #define CAN3_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6C00) |
| rajathr | 0:34ee385f4d2d | 1653 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1654 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1655 | #define CEC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x6C00) |
| rajathr | 0:34ee385f4d2d | 1656 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1657 | #define PWR_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7000) |
| rajathr | 0:34ee385f4d2d | 1658 | #define DAC_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7400) |
| rajathr | 0:34ee385f4d2d | 1659 | #define UART7_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7800) |
| rajathr | 0:34ee385f4d2d | 1660 | #define UART8_BASE_MORT (APB1PERIPH_BASE_MORT + 0x7C00) |
| rajathr | 0:34ee385f4d2d | 1661 | |
| rajathr | 0:34ee385f4d2d | 1662 | /*!< APB2 peripherals */ |
| rajathr | 0:34ee385f4d2d | 1663 | #define TIM1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x0000) |
| rajathr | 0:34ee385f4d2d | 1664 | #define TIM8_BASE_MORT (APB2PERIPH_BASE_MORT + 0x0400) |
| rajathr | 0:34ee385f4d2d | 1665 | #define USART1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1000) |
| rajathr | 0:34ee385f4d2d | 1666 | #define USART6_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1400) |
| rajathr | 0:34ee385f4d2d | 1667 | #define UART9_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1800U) |
| rajathr | 0:34ee385f4d2d | 1668 | #define UART10_BASE_MORT (APB2PERIPH_BASE_MORT + 0x1C00U) |
| rajathr | 0:34ee385f4d2d | 1669 | #define ADC1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2000) |
| rajathr | 0:34ee385f4d2d | 1670 | #define ADC2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2100) |
| rajathr | 0:34ee385f4d2d | 1671 | #define ADC3_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2200) |
| rajathr | 0:34ee385f4d2d | 1672 | #define ADC_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2300) |
| rajathr | 0:34ee385f4d2d | 1673 | #define SDIO_BASE_MORT (APB2PERIPH_BASE_MORT + 0x2C00) |
| rajathr | 0:34ee385f4d2d | 1674 | #define SPI1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3000) |
| rajathr | 0:34ee385f4d2d | 1675 | #define SPI4_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3400) |
| rajathr | 0:34ee385f4d2d | 1676 | #define SYSCFG_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3800) |
| rajathr | 0:34ee385f4d2d | 1677 | #define EXTI_BASE_MORT (APB2PERIPH_BASE_MORT + 0x3C00) |
| rajathr | 0:34ee385f4d2d | 1678 | #define TIM9_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4000) |
| rajathr | 0:34ee385f4d2d | 1679 | #define TIM10_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4400) |
| rajathr | 0:34ee385f4d2d | 1680 | #define TIM11_BASE_MORT (APB2PERIPH_BASE_MORT + 0x4800) |
| rajathr | 0:34ee385f4d2d | 1681 | #define SPI5_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5000) |
| rajathr | 0:34ee385f4d2d | 1682 | #define SPI6_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5400) |
| rajathr | 0:34ee385f4d2d | 1683 | #define SAI1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5800) |
| rajathr | 0:34ee385f4d2d | 1684 | #define SAI1_Block_A_BASE_MORT (SAI1_BASE_MORT + 0x004) |
| rajathr | 0:34ee385f4d2d | 1685 | #define SAI1_Block_B_BASE_MORT (SAI1_BASE_MORT + 0x024) |
| rajathr | 0:34ee385f4d2d | 1686 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1687 | #define SAI2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x5C00) |
| rajathr | 0:34ee385f4d2d | 1688 | #define SAI2_Block_A_BASE_MORT (SAI2_BASE_MORT + 0x004) |
| rajathr | 0:34ee385f4d2d | 1689 | #define SAI2_Block_B_BASE_MORT (SAI2_BASE_MORT + 0x024) |
| rajathr | 0:34ee385f4d2d | 1690 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1691 | #define LTDC_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6800) |
| rajathr | 0:34ee385f4d2d | 1692 | #define LTDC_Layer1_BASE_MORT (LTDC_BASE_MORT + 0x84) |
| rajathr | 0:34ee385f4d2d | 1693 | #define LTDC_Layer2_BASE_MORT (LTDC_BASE_MORT + 0x104) |
| rajathr | 0:34ee385f4d2d | 1694 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1695 | #define DSI_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6C00) |
| rajathr | 0:34ee385f4d2d | 1696 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1697 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1698 | #define DFSDM1_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6000) |
| rajathr | 0:34ee385f4d2d | 1699 | #define DFSDM1_Channel0_BASE_MORT (DFSDM1_BASE_MORT + 0x00) |
| rajathr | 0:34ee385f4d2d | 1700 | #define DFSDM1_Channel1_BASE_MORT (DFSDM1_BASE_MORT + 0x20) |
| rajathr | 0:34ee385f4d2d | 1701 | #define DFSDM1_Channel2_BASE_MORT (DFSDM1_BASE_MORT + 0x40) |
| rajathr | 0:34ee385f4d2d | 1702 | #define DFSDM1_Channel3_BASE_MORT (DFSDM1_BASE_MORT + 0x60) |
| rajathr | 0:34ee385f4d2d | 1703 | #define DFSDM1_Filter0_BASE_MORT (DFSDM1_BASE_MORT + 0x100) |
| rajathr | 0:34ee385f4d2d | 1704 | #define DFSDM1_Filter1_BASE_MORT (DFSDM1_BASE_MORT + 0x180) |
| rajathr | 0:34ee385f4d2d | 1705 | #define DFSDM1_0_MORT ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1706 | #define DFSDM1_1_MORT ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1707 | /* Legacy Defines */ |
| rajathr | 0:34ee385f4d2d | 1708 | #define DFSDM0 DFSDM1_0_MORT |
| rajathr | 0:34ee385f4d2d | 1709 | #define DFSDM1 DFSDM1_1_MORT |
| rajathr | 0:34ee385f4d2d | 1710 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1711 | #define DFSDM2_BASE_MORT (APB2PERIPH_BASE_MORT + 0x6400U) |
| rajathr | 0:34ee385f4d2d | 1712 | #define DFSDM2_Channel0_BASE_MORT (DFSDM2_BASE_MORT + 0x00U) |
| rajathr | 0:34ee385f4d2d | 1713 | #define DFSDM2_Channel1_BASE_MORT (DFSDM2_BASE_MORT + 0x20U) |
| rajathr | 0:34ee385f4d2d | 1714 | #define DFSDM2_Channel2_BASE_MORT (DFSDM2_BASE_MORT + 0x40U) |
| rajathr | 0:34ee385f4d2d | 1715 | #define DFSDM2_Channel3_BASE_MORT (DFSDM2_BASE_MORT + 0x60U) |
| rajathr | 0:34ee385f4d2d | 1716 | #define DFSDM2_Channel4_BASE_MORT (DFSDM2_BASE_MORT + 0x80U) |
| rajathr | 0:34ee385f4d2d | 1717 | #define DFSDM2_Channel5_BASE_MORT (DFSDM2_BASE_MORT + 0xA0U) |
| rajathr | 0:34ee385f4d2d | 1718 | #define DFSDM2_Channel6_BASE_MORT (DFSDM2_BASE_MORT + 0xC0U) |
| rajathr | 0:34ee385f4d2d | 1719 | #define DFSDM2_Channel7_BASE_MORT (DFSDM2_BASE_MORT + 0xE0U) |
| rajathr | 0:34ee385f4d2d | 1720 | #define DFSDM2_Filter0_BASE_MORT (DFSDM2_BASE_MORT + 0x100U) |
| rajathr | 0:34ee385f4d2d | 1721 | #define DFSDM2_Filter1_BASE_MORT (DFSDM2_BASE_MORT + 0x180U) |
| rajathr | 0:34ee385f4d2d | 1722 | #define DFSDM2_Filter2_BASE_MORT (DFSDM2_BASE_MORT + 0x200U) |
| rajathr | 0:34ee385f4d2d | 1723 | #define DFSDM2_Filter3_BASE_MORT (DFSDM2_BASE_MORT + 0x280U) |
| rajathr | 0:34ee385f4d2d | 1724 | #define DFSDM2_0_MORT ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1725 | #define DFSDM2_1_MORT ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1726 | #define DFSDM2_2_MORT ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1727 | #define DFSDM2_3_MORT ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1728 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1729 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1730 | |
| rajathr | 0:34ee385f4d2d | 1731 | /*!< AHB1 peripherals */ |
| rajathr | 0:34ee385f4d2d | 1732 | #define GPIOA_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0000) |
| rajathr | 0:34ee385f4d2d | 1733 | #define GPIOB_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0400) |
| rajathr | 0:34ee385f4d2d | 1734 | #define GPIOC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0800) |
| rajathr | 0:34ee385f4d2d | 1735 | #define GPIOD_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x0C00) |
| rajathr | 0:34ee385f4d2d | 1736 | #define GPIOE_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1000) |
| rajathr | 0:34ee385f4d2d | 1737 | #define GPIOF_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1400) |
| rajathr | 0:34ee385f4d2d | 1738 | #define GPIOG_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1800) |
| rajathr | 0:34ee385f4d2d | 1739 | #define GPIOH_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x1C00) |
| rajathr | 0:34ee385f4d2d | 1740 | #define GPIOI_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2000) |
| rajathr | 0:34ee385f4d2d | 1741 | #define GPIOJ_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2400) |
| rajathr | 0:34ee385f4d2d | 1742 | #define GPIOK_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x2800) |
| rajathr | 0:34ee385f4d2d | 1743 | #define CRC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3000) |
| rajathr | 0:34ee385f4d2d | 1744 | #define RCC_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3800) |
| rajathr | 0:34ee385f4d2d | 1745 | #define FLASH_R_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x3C00) |
| rajathr | 0:34ee385f4d2d | 1746 | #define DMA1_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x6000) |
| rajathr | 0:34ee385f4d2d | 1747 | #define DMA1_Stream0_BASE_MORT (DMA1_BASE_MORT + 0x010) |
| rajathr | 0:34ee385f4d2d | 1748 | #define DMA1_Stream1_BASE_MORT (DMA1_BASE_MORT + 0x028) |
| rajathr | 0:34ee385f4d2d | 1749 | #define DMA1_Stream2_BASE_MORT (DMA1_BASE_MORT + 0x040) |
| rajathr | 0:34ee385f4d2d | 1750 | #define DMA1_Stream3_BASE_MORT (DMA1_BASE_MORT + 0x058) |
| rajathr | 0:34ee385f4d2d | 1751 | #define DMA1_Stream4_BASE_MORT (DMA1_BASE_MORT + 0x070) |
| rajathr | 0:34ee385f4d2d | 1752 | #define DMA1_Stream5_BASE_MORT (DMA1_BASE_MORT + 0x088) |
| rajathr | 0:34ee385f4d2d | 1753 | #define DMA1_Stream6_BASE_MORT (DMA1_BASE_MORT + 0x0A0) |
| rajathr | 0:34ee385f4d2d | 1754 | #define DMA1_Stream7_BASE_MORT (DMA1_BASE_MORT + 0x0B8) |
| rajathr | 0:34ee385f4d2d | 1755 | #define DMA2_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x6400) |
| rajathr | 0:34ee385f4d2d | 1756 | #define DMA2_Stream0_BASE_MORT (DMA2_BASE_MORT + 0x010) |
| rajathr | 0:34ee385f4d2d | 1757 | #define DMA2_Stream1_BASE_MORT (DMA2_BASE_MORT + 0x028) |
| rajathr | 0:34ee385f4d2d | 1758 | #define DMA2_Stream2_BASE_MORT (DMA2_BASE_MORT + 0x040) |
| rajathr | 0:34ee385f4d2d | 1759 | #define DMA2_Stream3_BASE_MORT (DMA2_BASE_MORT + 0x058) |
| rajathr | 0:34ee385f4d2d | 1760 | #define DMA2_Stream4_BASE_MORT (DMA2_BASE_MORT + 0x070) |
| rajathr | 0:34ee385f4d2d | 1761 | #define DMA2_Stream5_BASE_MORT (DMA2_BASE_MORT + 0x088) |
| rajathr | 0:34ee385f4d2d | 1762 | #define DMA2_Stream6_BASE_MORT (DMA2_BASE_MORT + 0x0A0) |
| rajathr | 0:34ee385f4d2d | 1763 | #define DMA2_Stream7_BASE_MORT (DMA2_BASE_MORT + 0x0B8) |
| rajathr | 0:34ee385f4d2d | 1764 | #define ETH_BASE_MORT (AHB1PERIPH_BASE_MORT + 0x8000) |
| rajathr | 0:34ee385f4d2d | 1765 | #define ETH_MAC_BASE_MORT (ETH_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1766 | #define ETH_MMC_BASE_MORT (ETH_BASE_MORT + 0x0100) |
| rajathr | 0:34ee385f4d2d | 1767 | #define ETH_PTP_BASE_MORT (ETH_BASE_MORT + 0x0700) |
| rajathr | 0:34ee385f4d2d | 1768 | #define ETH_DMA_BASE_MORT (ETH_BASE_MORT + 0x1000) |
| rajathr | 0:34ee385f4d2d | 1769 | #define DMA2D_BASE_MORT (AHB1PERIPH_BASE_MORT + 0xB000) |
| rajathr | 0:34ee385f4d2d | 1770 | |
| rajathr | 0:34ee385f4d2d | 1771 | /*!< AHB2 peripherals */ |
| rajathr | 0:34ee385f4d2d | 1772 | #define DCMI_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x50000) |
| rajathr | 0:34ee385f4d2d | 1773 | #define CRYP_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60000) |
| rajathr | 0:34ee385f4d2d | 1774 | #define HASH_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60400) |
| rajathr | 0:34ee385f4d2d | 1775 | #define HASH_DIGEST_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60710) |
| rajathr | 0:34ee385f4d2d | 1776 | #define RNG_BASE_MORT (AHB2PERIPH_BASE_MORT + 0x60800) |
| rajathr | 0:34ee385f4d2d | 1777 | |
| rajathr | 0:34ee385f4d2d | 1778 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1779 | /*!< FSMC Bankx registers base address */ |
| rajathr | 0:34ee385f4d2d | 1780 | #define FSMC_Bank1_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0000) |
| rajathr | 0:34ee385f4d2d | 1781 | #define FSMC_Bank1E_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0104) |
| rajathr | 0:34ee385f4d2d | 1782 | #define FSMC_Bank2_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0060) |
| rajathr | 0:34ee385f4d2d | 1783 | #define FSMC_Bank3_R_BASE_MORT (FSMC_R_BASE_MORT + 0x0080) |
| rajathr | 0:34ee385f4d2d | 1784 | #define FSMC_Bank4_R_BASE_MORT (FSMC_R_BASE_MORT + 0x00A0) |
| rajathr | 0:34ee385f4d2d | 1785 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1786 | |
| rajathr | 0:34ee385f4d2d | 1787 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1788 | /*!< FMC Bankx registers base address */ |
| rajathr | 0:34ee385f4d2d | 1789 | #define FMC_Bank1_R_BASE_MORT (FMC_R_BASE_MORT + 0x0000) |
| rajathr | 0:34ee385f4d2d | 1790 | #define FMC_Bank1E_R_BASE_MORT (FMC_R_BASE_MORT + 0x0104) |
| rajathr | 0:34ee385f4d2d | 1791 | #define FMC_Bank2_R_BASE_MORT (FMC_R_BASE_MORT + 0x0060) |
| rajathr | 0:34ee385f4d2d | 1792 | #define FMC_Bank3_R_BASE_MORT (FMC_R_BASE_MORT + 0x0080) |
| rajathr | 0:34ee385f4d2d | 1793 | #define FMC_Bank4_R_BASE_MORT (FMC_R_BASE_MORT + 0x00A0) |
| rajathr | 0:34ee385f4d2d | 1794 | #define FMC_Bank5_6_R_BASE_MORT (FMC_R_BASE_MORT + 0x0140) |
| rajathr | 0:34ee385f4d2d | 1795 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1796 | |
| rajathr | 0:34ee385f4d2d | 1797 | /* Debug MCU registers base address */ |
| rajathr | 0:34ee385f4d2d | 1798 | #define DBGMCU_BASE_MORT ((uint32_t )0xE0042000) |
| rajathr | 0:34ee385f4d2d | 1799 | |
| rajathr | 0:34ee385f4d2d | 1800 | /** |
| rajathr | 0:34ee385f4d2d | 1801 | * @} |
| rajathr | 0:34ee385f4d2d | 1802 | */ |
| rajathr | 0:34ee385f4d2d | 1803 | |
| rajathr | 0:34ee385f4d2d | 1804 | /** @addtogroup Peripheral_declaration |
| rajathr | 0:34ee385f4d2d | 1805 | * @{ |
| rajathr | 0:34ee385f4d2d | 1806 | */ |
| rajathr | 0:34ee385f4d2d | 1807 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1808 | #define QUADSPI_MORT ((QUADSPI_TypeDef_mort *) QSPI_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1809 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1810 | #define TIM2_MORT ((TIM_TypeDef_mort *) TIM2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1811 | #define TIM3_MORT ((TIM_TypeDef_mort *) TIM3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1812 | #define TIM4_MORT ((TIM_TypeDef_mort *) TIM4_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1813 | #define TIM5_MORT ((TIM_TypeDef_mort *) TIM5_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1814 | #define TIM6_MORT ((TIM_TypeDef_mort *) TIM6_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1815 | #define TIM7_MORT ((TIM_TypeDef_mort *) TIM7_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1816 | #define TIM12_MORT ((TIM_TypeDef_mort *) TIM12_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1817 | #define TIM13_MORT ((TIM_TypeDef_mort *) TIM13_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1818 | #define TIM14_MORT ((TIM_TypeDef_mort *) TIM14_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1819 | #define RTC_MORT ((RTC_TypeDef_mort *) RTC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1820 | #define WWDG_MORT ((WWDG_TypeDef_mort *) WWDG_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1821 | #define IWDG_MORT ((IWDG_TypeDef_mort *) IWDG_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1822 | #define I2S2ext_MORT ((SPI_TypeDef_mort *) I2S2ext_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1823 | #define SPI2_MORT ((SPI_TypeDef_mort *) SPI2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1824 | #define SPI3_MORT ((SPI_TypeDef_mort *) SPI3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1825 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1826 | #define SPDIFRX_MORT ((SPDIFRX_TypeDef_mort *) SPDIFRX_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1827 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1828 | #define I2S3ext_MORT ((SPI_TypeDef_mort *) I2S3ext_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1829 | #define USART2_MORT ((USART_TypeDef_mort *) USART2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1830 | #define USART3_MORT ((USART_TypeDef_mort *) USART3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1831 | #define UART4_MORT ((USART_TypeDef_mort *) UART4_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1832 | #define UART5_MORT ((USART_TypeDef_mort *) UART5_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1833 | #define I2C1_MORT ((I2C_TypeDef_mort *) I2C1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1834 | #define I2C2_MORT ((I2C_TypeDef_mort *) I2C2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1835 | #define I2C3_MORT ((I2C_TypeDef_mort *) I2C3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1836 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1837 | #define FMPI2C1_MORT ((FMPI2C_TypeDef_mort *) FMPI2C1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1838 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1839 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1840 | #define LPTIM1_MORT ((LPTIM_TypeDef_mort *) LPTIM1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1841 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1842 | #define CAN1_MORT ((CAN_TypeDef_mort *) CAN1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1843 | #define CAN2_MORT ((CAN_TypeDef_mort *) CAN2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1844 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1845 | #define CAN3_MORT ((CAN_TypeDef_mort *) CAN3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1846 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1847 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1848 | #define CEC_MORT ((CEC_TypeDef_mort *) CEC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1849 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1850 | #define PWR_MORT ((PWR_TypeDef_mort *) PWR_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1851 | #define DAC_MORT ((DAC_TypeDef_mort *) DAC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1852 | #define UART7_MORT ((USART_TypeDef_mort *) UART7_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1853 | #define UART8_MORT ((USART_TypeDef_mort *) UART8_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1854 | #define UART9_MORT ((USART_TypeDef_mort *) UART9_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1855 | #define UART10_MORT ((USART_TypeDef_mort *) UART10_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1856 | #define TIM1_MORT ((TIM_TypeDef_mort *) TIM1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1857 | #define TIM8_MORT ((TIM_TypeDef_mort *) TIM8_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1858 | #define USART1_MORT ((USART_TypeDef_mort *) USART1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1859 | #define USART6_MORT ((USART_TypeDef_mort *) USART6_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1860 | #define ADC_MORT ((ADC_Common_TypeDef_mort *) ADC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1861 | #define ADC1_MORT ((ADC_TypeDef_mort *) ADC1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1862 | #define ADC2_MORT ((ADC_TypeDef_mort *) ADC2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1863 | #define ADC3_MORT ((ADC_TypeDef_mort *) ADC3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1864 | #define SDIO_MORT ((SDIO_TypeDef_mort *) SDIO_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1865 | #define SPI1_MORT ((SPI_TypeDef_mort *) SPI1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1866 | #define SPI4_MORT ((SPI_TypeDef_mort *) SPI4_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1867 | #define SYSCFG_MORT ((SYSCFG_TypeDef_mort *) SYSCFG_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1868 | #define EXTI_MORT ((EXTI_TypeDef_mort *) EXTI_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1869 | #define TIM9_MORT ((TIM_TypeDef_mort *) TIM9_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1870 | #define TIM10_MORT ((TIM_TypeDef_mort *) TIM10_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1871 | #define TIM11_MORT ((TIM_TypeDef_mort *) TIM11_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1872 | #define SPI5_MORT ((SPI_TypeDef_mort *) SPI5_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1873 | #define SPI6_MORT ((SPI_TypeDef_mort *) SPI6_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1874 | #define SAI1_MORT ((SAI_TypeDef_mort *) SAI1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1875 | #define SAI1_Block_A_MORT ((SAI_Block_TypeDef_mort *)SAI1_Block_A_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1876 | #define SAI1_Block_B_MORT ((SAI_Block_TypeDef_mort *)SAI1_Block_B_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1877 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 1878 | #define SAI2_MORT ((SAI_TypeDef_mort *) SAI2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1879 | #define SAI2_Block_A_MORT ((SAI_Block_TypeDef_mort *)SAI2_Block_A_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1880 | #define SAI2_Block_B_MORT ((SAI_Block_TypeDef_mort *)SAI2_Block_B_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1881 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 1882 | #define LTDC_MORT ((LTDC_TypeDef_mort *)LTDC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1883 | #define LTDC_Layer1_MORT ((LTDC_Layer_TypeDef_mort *)LTDC_Layer1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1884 | #define LTDC_Layer2_MORT ((LTDC_Layer_TypeDef_mort *)LTDC_Layer2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1885 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1886 | #define DSI_MORT ((DSI_TypeDef_mort *)DSI_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1887 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1888 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1889 | #define DFSDM1_Channel0_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1890 | #define DFSDM1_Channel1_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1891 | #define DFSDM1_Channel2_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1892 | #define DFSDM1_Channel3_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM1_Channel3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1893 | #define DFSDM1_Filter0_MORT ((DFSDM_TypeDef *) DFSDM_Filter0_BASE) |
| rajathr | 0:34ee385f4d2d | 1894 | #define DFSDM1_Filter1_MORT ((DFSDM_TypeDef *) DFSDM_Filter1_BASE) |
| rajathr | 0:34ee385f4d2d | 1895 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1896 | #define DFSDM2_Channel0_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1897 | #define DFSDM2_Channel1_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1898 | #define DFSDM2_Channel2_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1899 | #define DFSDM2_Channel3_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1900 | #define DFSDM2_Channel4_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel4_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1901 | #define DFSDM2_Channel5_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel5_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1902 | #define DFSDM2_Channel6_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel6_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1903 | #define DFSDM2_Channel7_MORT ((DFSDM_Channel_TypeDef_mort *) DFSDM2_Channel7_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1904 | #define DFSDM2_Filter0_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1905 | #define DFSDM2_Filter1_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1906 | #define DFSDM2_Filter2_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1907 | #define DFSDM2_Filter3_MORT ((DFSDM_Filter_TypeDef_mort *) DFSDM2_Filter3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1908 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1909 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1910 | #define GPIOA_MORT ((GPIO_TypeDef_mort *) GPIOA_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1911 | #define GPIOB_MORT ((GPIO_TypeDef_mort *) GPIOB_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1912 | #define GPIOC_MORT ((GPIO_TypeDef_mort *) GPIOC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1913 | #define GPIOD_MORT ((GPIO_TypeDef_mort *) GPIOD_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1914 | #define GPIOE_MORT ((GPIO_TypeDef_mort *) GPIOE_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1915 | #define GPIOF_MORT ((GPIO_TypeDef_mort *) GPIOF_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1916 | #define GPIOG_MORT ((GPIO_TypeDef_mort *) GPIOG_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1917 | #define GPIOH_MORT ((GPIO_TypeDef_mort *) GPIOH_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1918 | #define GPIOI_MORT ((GPIO_TypeDef_mort *) GPIOI_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1919 | #define GPIOJ_MORT ((GPIO_TypeDef_mort *) GPIOJ_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1920 | #define GPIOK_MORT ((GPIO_TypeDef_mort *) GPIOK_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1921 | #define CRC_MORT ((CRC_TypeDef_mort *) CRC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1922 | #define RCC_MORT ((RCC_TypeDef_mort *) RCC_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1923 | #define FLASH_MORT ((FLASH_TypeDef_mort *) FLASH_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1924 | #define DMA1_MORT ((DMA_TypeDef_mort *) DMA1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1925 | #define DMA1_Stream0_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1926 | #define DMA1_Stream1_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1927 | #define DMA1_Stream2_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1928 | #define DMA1_Stream3_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1929 | #define DMA1_Stream4_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream4_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1930 | #define DMA1_Stream5_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream5_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1931 | #define DMA1_Stream6_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream6_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1932 | #define DMA1_Stream7_MORT ((DMA_Stream_TypeDef_mort *) DMA1_Stream7_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1933 | #define DMA2_MORT ((DMA_TypeDef_mort *) DMA2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1934 | #define DMA2_Stream0_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream0_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1935 | #define DMA2_Stream1_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream1_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1936 | #define DMA2_Stream2_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream2_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1937 | #define DMA2_Stream3_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream3_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1938 | #define DMA2_Stream4_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream4_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1939 | #define DMA2_Stream5_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream5_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1940 | #define DMA2_Stream6_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream6_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1941 | #define DMA2_Stream7_MORT ((DMA_Stream_TypeDef_mort *) DMA2_Stream7_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1942 | #define ETH_MORT ((ETH_TypeDef_mort *) ETH_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1943 | #define DMA2D_MORT ((DMA2D_TypeDef_mort *)DMA2D_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1944 | #define DCMI_MORT ((DCMI_TypeDef_mort *) DCMI_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1945 | #define CRYP_MORT ((CRYP_TypeDef_mort *) CRYP_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1946 | #define HASH_MORT ((HASH_TypeDef_mort *) HASH_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1947 | #define HASH_DIGEST_MORT ((HASH_DIGEST_TypeDef_mort *) HASH_DIGEST_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1948 | #define RNG_MORT ((RNG_TypeDef_mort *) RNG_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1949 | |
| rajathr | 0:34ee385f4d2d | 1950 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 1951 | #define FSMC_Bank1_MORT ((FSMC_Bank1_TypeDef_mort *) FSMC_Bank1_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1952 | #define FSMC_Bank1E_MORT ((FSMC_Bank1E_TypeDef_mort *) FSMC_Bank1E_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1953 | #define FSMC_Bank2_MORT ((FSMC_Bank2_TypeDef_mort *) FSMC_Bank2_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1954 | #define FSMC_Bank3_MORT ((FSMC_Bank3_TypeDef_mort *) FSMC_Bank3_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1955 | #define FSMC_Bank4_MORT ((FSMC_Bank4_TypeDef_mort *) FSMC_Bank4_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1956 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 1957 | |
| rajathr | 0:34ee385f4d2d | 1958 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 1959 | #define FMC_Bank1_MORT ((FMC_Bank1_TypeDef_mort *) FMC_Bank1_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1960 | #define FMC_Bank1E_MORT ((FMC_Bank1E_TypeDef_mort *) FMC_Bank1E_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1961 | #define FMC_Bank2_MORT ((FMC_Bank2_TypeDef_mort *) FMC_Bank2_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1962 | #define FMC_Bank3_MORT ((FMC_Bank3_TypeDef_mort *) FMC_Bank3_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1963 | #define FMC_Bank4_MORT ((FMC_Bank4_TypeDef_mort *) FMC_Bank4_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1964 | #define FMC_Bank5_6_MORT ((FMC_Bank5_6_TypeDef_mort *) FMC_Bank5_6_R_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1965 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 1966 | |
| rajathr | 0:34ee385f4d2d | 1967 | #define DBGMCU_MORT ((DBGMCU_TypeDef_mort *) DBGMCU_BASE_MORT) |
| rajathr | 0:34ee385f4d2d | 1968 | |
| rajathr | 0:34ee385f4d2d | 1969 | /** |
| rajathr | 0:34ee385f4d2d | 1970 | * @} |
| rajathr | 0:34ee385f4d2d | 1971 | */ |
| rajathr | 0:34ee385f4d2d | 1972 | |
| rajathr | 0:34ee385f4d2d | 1973 | /** @addtogroup Exported_constants |
| rajathr | 0:34ee385f4d2d | 1974 | * @{ |
| rajathr | 0:34ee385f4d2d | 1975 | */ |
| rajathr | 0:34ee385f4d2d | 1976 | |
| rajathr | 0:34ee385f4d2d | 1977 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| rajathr | 0:34ee385f4d2d | 1978 | * @{ |
| rajathr | 0:34ee385f4d2d | 1979 | */ |
| rajathr | 0:34ee385f4d2d | 1980 | |
| rajathr | 0:34ee385f4d2d | 1981 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 1982 | /* Peripheral Registers_Bits_Definition */ |
| rajathr | 0:34ee385f4d2d | 1983 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 1984 | |
| rajathr | 0:34ee385f4d2d | 1985 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 1986 | /* */ |
| rajathr | 0:34ee385f4d2d | 1987 | /* Analog to Digital Converter */ |
| rajathr | 0:34ee385f4d2d | 1988 | /* */ |
| rajathr | 0:34ee385f4d2d | 1989 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 1990 | /******************** Bit definition for ADC_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 1991 | #define ADC_SR_AWD_MORT ((uint8_t)0x01) /*!<Analog watchdog flag */ |
| rajathr | 0:34ee385f4d2d | 1992 | #define ADC_SR_EOC_MORT ((uint8_t)0x02) /*!<End of conversion */ |
| rajathr | 0:34ee385f4d2d | 1993 | #define ADC_SR_JEOC_MORT ((uint8_t)0x04) /*!<Injected channel end of conversion */ |
| rajathr | 0:34ee385f4d2d | 1994 | #define ADC_SR_JSTRT_MORT ((uint8_t)0x08) /*!<Injected channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 1995 | #define ADC_SR_STRT_MORT ((uint8_t)0x10) /*!<Regular channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 1996 | #define ADC_SR_OVR_MORT ((uint8_t)0x20) /*!<Overrun flag */ |
| rajathr | 0:34ee385f4d2d | 1997 | |
| rajathr | 0:34ee385f4d2d | 1998 | /******************* Bit definition for ADC_CR1 register ********************/ |
| rajathr | 0:34ee385f4d2d | 1999 | #define ADC_CR1_AWDCH_MORT ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| rajathr | 0:34ee385f4d2d | 2000 | #define ADC_CR1_AWDCH_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2001 | #define ADC_CR1_AWDCH_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2002 | #define ADC_CR1_AWDCH_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2003 | #define ADC_CR1_AWDCH_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2004 | #define ADC_CR1_AWDCH_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2005 | #define ADC_CR1_EOCIE_MORT ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */ |
| rajathr | 0:34ee385f4d2d | 2006 | #define ADC_CR1_AWDIE_MORT ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 2007 | #define ADC_CR1_JEOCIE_MORT ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */ |
| rajathr | 0:34ee385f4d2d | 2008 | #define ADC_CR1_SCAN_MORT ((uint32_t)0x00000100) /*!<Scan mode */ |
| rajathr | 0:34ee385f4d2d | 2009 | #define ADC_CR1_AWDSGL_MORT ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */ |
| rajathr | 0:34ee385f4d2d | 2010 | #define ADC_CR1_JAUTO_MORT ((uint32_t)0x00000400) /*!<Automatic injected group conversion */ |
| rajathr | 0:34ee385f4d2d | 2011 | #define ADC_CR1_DISCEN_MORT ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */ |
| rajathr | 0:34ee385f4d2d | 2012 | #define ADC_CR1_JDISCEN_MORT ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */ |
| rajathr | 0:34ee385f4d2d | 2013 | #define ADC_CR1_DISCNUM_MORT ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
| rajathr | 0:34ee385f4d2d | 2014 | #define ADC_CR1_DISCNUM_0_MORT ((uint32_t)0x00002000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2015 | #define ADC_CR1_DISCNUM_1_MORT ((uint32_t)0x00004000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2016 | #define ADC_CR1_DISCNUM_2_MORT ((uint32_t)0x00008000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2017 | #define ADC_CR1_JAWDEN_MORT ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */ |
| rajathr | 0:34ee385f4d2d | 2018 | #define ADC_CR1_AWDEN_MORT ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */ |
| rajathr | 0:34ee385f4d2d | 2019 | #define ADC_CR1_RES_MORT ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */ |
| rajathr | 0:34ee385f4d2d | 2020 | #define ADC_CR1_RES_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2021 | #define ADC_CR1_RES_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2022 | #define ADC_CR1_OVRIE_MORT ((uint32_t)0x04000000) /*!<overrun interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 2023 | |
| rajathr | 0:34ee385f4d2d | 2024 | /******************* Bit definition for ADC_CR2 register ********************/ |
| rajathr | 0:34ee385f4d2d | 2025 | #define ADC_CR2_ADON_MORT ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */ |
| rajathr | 0:34ee385f4d2d | 2026 | #define ADC_CR2_CONT_MORT ((uint32_t)0x00000002) /*!<Continuous Conversion */ |
| rajathr | 0:34ee385f4d2d | 2027 | #define ADC_CR2_DMA_MORT ((uint32_t)0x00000100) /*!<Direct Memory access mode */ |
| rajathr | 0:34ee385f4d2d | 2028 | #define ADC_CR2_DDS_MORT ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC_MORT) */ |
| rajathr | 0:34ee385f4d2d | 2029 | #define ADC_CR2_EOCS_MORT ((uint32_t)0x00000400) /*!<End of conversion selection */ |
| rajathr | 0:34ee385f4d2d | 2030 | #define ADC_CR2_ALIGN_MORT ((uint32_t)0x00000800) /*!<Data Alignment */ |
| rajathr | 0:34ee385f4d2d | 2031 | #define ADC_CR2_JEXTSEL_MORT ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */ |
| rajathr | 0:34ee385f4d2d | 2032 | #define ADC_CR2_JEXTSEL_0_MORT ((uint32_t)0x00010000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2033 | #define ADC_CR2_JEXTSEL_1_MORT ((uint32_t)0x00020000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2034 | #define ADC_CR2_JEXTSEL_2_MORT ((uint32_t)0x00040000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2035 | #define ADC_CR2_JEXTSEL_3_MORT ((uint32_t)0x00080000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2036 | #define ADC_CR2_JEXTEN_MORT ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ |
| rajathr | 0:34ee385f4d2d | 2037 | #define ADC_CR2_JEXTEN_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2038 | #define ADC_CR2_JEXTEN_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2039 | #define ADC_CR2_JSWSTART_MORT ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */ |
| rajathr | 0:34ee385f4d2d | 2040 | #define ADC_CR2_EXTSEL_MORT ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ |
| rajathr | 0:34ee385f4d2d | 2041 | #define ADC_CR2_EXTSEL_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2042 | #define ADC_CR2_EXTSEL_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2043 | #define ADC_CR2_EXTSEL_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2044 | #define ADC_CR2_EXTSEL_3_MORT ((uint32_t)0x08000000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2045 | #define ADC_CR2_EXTEN_MORT ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ |
| rajathr | 0:34ee385f4d2d | 2046 | #define ADC_CR2_EXTEN_0_MORT ((uint32_t)0x10000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2047 | #define ADC_CR2_EXTEN_1_MORT ((uint32_t)0x20000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2048 | #define ADC_CR2_SWSTART_MORT ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */ |
| rajathr | 0:34ee385f4d2d | 2049 | |
| rajathr | 0:34ee385f4d2d | 2050 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2051 | #define ADC_SMPR1_SMP10_MORT ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2052 | #define ADC_SMPR1_SMP10_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2053 | #define ADC_SMPR1_SMP10_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2054 | #define ADC_SMPR1_SMP10_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2055 | #define ADC_SMPR1_SMP11_MORT ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2056 | #define ADC_SMPR1_SMP11_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2057 | #define ADC_SMPR1_SMP11_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2058 | #define ADC_SMPR1_SMP11_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2059 | #define ADC_SMPR1_SMP12_MORT ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2060 | #define ADC_SMPR1_SMP12_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2061 | #define ADC_SMPR1_SMP12_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2062 | #define ADC_SMPR1_SMP12_2_MORT ((uint32_t)0x00000100) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2063 | #define ADC_SMPR1_SMP13_MORT ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2064 | #define ADC_SMPR1_SMP13_0_MORT ((uint32_t)0x00000200) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2065 | #define ADC_SMPR1_SMP13_1_MORT ((uint32_t)0x00000400) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2066 | #define ADC_SMPR1_SMP13_2_MORT ((uint32_t)0x00000800) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2067 | #define ADC_SMPR1_SMP14_MORT ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2068 | #define ADC_SMPR1_SMP14_0_MORT ((uint32_t)0x00001000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2069 | #define ADC_SMPR1_SMP14_1_MORT ((uint32_t)0x00002000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2070 | #define ADC_SMPR1_SMP14_2_MORT ((uint32_t)0x00004000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2071 | #define ADC_SMPR1_SMP15_MORT ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2072 | #define ADC_SMPR1_SMP15_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2073 | #define ADC_SMPR1_SMP15_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2074 | #define ADC_SMPR1_SMP15_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2075 | #define ADC_SMPR1_SMP16_MORT ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2076 | #define ADC_SMPR1_SMP16_0_MORT ((uint32_t)0x00040000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2077 | #define ADC_SMPR1_SMP16_1_MORT ((uint32_t)0x00080000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2078 | #define ADC_SMPR1_SMP16_2_MORT ((uint32_t)0x00100000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2079 | #define ADC_SMPR1_SMP17_MORT ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2080 | #define ADC_SMPR1_SMP17_0_MORT ((uint32_t)0x00200000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2081 | #define ADC_SMPR1_SMP17_1_MORT ((uint32_t)0x00400000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2082 | #define ADC_SMPR1_SMP17_2_MORT ((uint32_t)0x00800000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2083 | #define ADC_SMPR1_SMP18_MORT ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2084 | #define ADC_SMPR1_SMP18_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2085 | #define ADC_SMPR1_SMP18_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2086 | #define ADC_SMPR1_SMP18_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2087 | |
| rajathr | 0:34ee385f4d2d | 2088 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2089 | #define ADC_SMPR2_SMP0_MORT ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2090 | #define ADC_SMPR2_SMP0_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2091 | #define ADC_SMPR2_SMP0_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2092 | #define ADC_SMPR2_SMP0_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2093 | #define ADC_SMPR2_SMP1_MORT ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2094 | #define ADC_SMPR2_SMP1_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2095 | #define ADC_SMPR2_SMP1_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2096 | #define ADC_SMPR2_SMP1_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2097 | #define ADC_SMPR2_SMP2_MORT ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2098 | #define ADC_SMPR2_SMP2_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2099 | #define ADC_SMPR2_SMP2_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2100 | #define ADC_SMPR2_SMP2_2_MORT ((uint32_t)0x00000100) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2101 | #define ADC_SMPR2_SMP3_MORT ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2102 | #define ADC_SMPR2_SMP3_0_MORT ((uint32_t)0x00000200) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2103 | #define ADC_SMPR2_SMP3_1_MORT ((uint32_t)0x00000400) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2104 | #define ADC_SMPR2_SMP3_2_MORT ((uint32_t)0x00000800) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2105 | #define ADC_SMPR2_SMP4_MORT ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2106 | #define ADC_SMPR2_SMP4_0_MORT ((uint32_t)0x00001000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2107 | #define ADC_SMPR2_SMP4_1_MORT ((uint32_t)0x00002000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2108 | #define ADC_SMPR2_SMP4_2_MORT ((uint32_t)0x00004000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2109 | #define ADC_SMPR2_SMP5_MORT ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2110 | #define ADC_SMPR2_SMP5_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2111 | #define ADC_SMPR2_SMP5_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2112 | #define ADC_SMPR2_SMP5_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2113 | #define ADC_SMPR2_SMP6_MORT ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2114 | #define ADC_SMPR2_SMP6_0_MORT ((uint32_t)0x00040000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2115 | #define ADC_SMPR2_SMP6_1_MORT ((uint32_t)0x00080000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2116 | #define ADC_SMPR2_SMP6_2_MORT ((uint32_t)0x00100000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2117 | #define ADC_SMPR2_SMP7_MORT ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2118 | #define ADC_SMPR2_SMP7_0_MORT ((uint32_t)0x00200000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2119 | #define ADC_SMPR2_SMP7_1_MORT ((uint32_t)0x00400000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2120 | #define ADC_SMPR2_SMP7_2_MORT ((uint32_t)0x00800000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2121 | #define ADC_SMPR2_SMP8_MORT ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2122 | #define ADC_SMPR2_SMP8_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2123 | #define ADC_SMPR2_SMP8_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2124 | #define ADC_SMPR2_SMP8_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2125 | #define ADC_SMPR2_SMP9_MORT ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
| rajathr | 0:34ee385f4d2d | 2126 | #define ADC_SMPR2_SMP9_0_MORT ((uint32_t)0x08000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2127 | #define ADC_SMPR2_SMP9_1_MORT ((uint32_t)0x10000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2128 | #define ADC_SMPR2_SMP9_2_MORT ((uint32_t)0x20000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2129 | |
| rajathr | 0:34ee385f4d2d | 2130 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2131 | #define ADC_JOFR1_JOFFSET1_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */ |
| rajathr | 0:34ee385f4d2d | 2132 | |
| rajathr | 0:34ee385f4d2d | 2133 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2134 | #define ADC_JOFR2_JOFFSET2_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */ |
| rajathr | 0:34ee385f4d2d | 2135 | |
| rajathr | 0:34ee385f4d2d | 2136 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2137 | #define ADC_JOFR3_JOFFSET3_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */ |
| rajathr | 0:34ee385f4d2d | 2138 | |
| rajathr | 0:34ee385f4d2d | 2139 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2140 | #define ADC_JOFR4_JOFFSET4_MORT ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */ |
| rajathr | 0:34ee385f4d2d | 2141 | |
| rajathr | 0:34ee385f4d2d | 2142 | /******************* Bit definition for ADC_HTR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2143 | #define ADC_HTR_HT_MORT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */ |
| rajathr | 0:34ee385f4d2d | 2144 | |
| rajathr | 0:34ee385f4d2d | 2145 | /******************* Bit definition for ADC_LTR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2146 | #define ADC_LTR_LT_MORT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */ |
| rajathr | 0:34ee385f4d2d | 2147 | |
| rajathr | 0:34ee385f4d2d | 2148 | /******************* Bit definition for ADC_SQR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2149 | #define ADC_SQR1_SQ13_MORT ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2150 | #define ADC_SQR1_SQ13_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2151 | #define ADC_SQR1_SQ13_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2152 | #define ADC_SQR1_SQ13_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2153 | #define ADC_SQR1_SQ13_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2154 | #define ADC_SQR1_SQ13_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2155 | #define ADC_SQR1_SQ14_MORT ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2156 | #define ADC_SQR1_SQ14_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2157 | #define ADC_SQR1_SQ14_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2158 | #define ADC_SQR1_SQ14_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2159 | #define ADC_SQR1_SQ14_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2160 | #define ADC_SQR1_SQ14_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2161 | #define ADC_SQR1_SQ15_MORT ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2162 | #define ADC_SQR1_SQ15_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2163 | #define ADC_SQR1_SQ15_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2164 | #define ADC_SQR1_SQ15_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2165 | #define ADC_SQR1_SQ15_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2166 | #define ADC_SQR1_SQ15_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2167 | #define ADC_SQR1_SQ16_MORT ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2168 | #define ADC_SQR1_SQ16_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2169 | #define ADC_SQR1_SQ16_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2170 | #define ADC_SQR1_SQ16_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2171 | #define ADC_SQR1_SQ16_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2172 | #define ADC_SQR1_SQ16_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2173 | #define ADC_SQR1_L_MORT ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */ |
| rajathr | 0:34ee385f4d2d | 2174 | #define ADC_SQR1_L__0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2175 | #define ADC_SQR1_L__1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2176 | #define ADC_SQR1_L__2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2177 | #define ADC_SQR1_L__3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2178 | |
| rajathr | 0:34ee385f4d2d | 2179 | /******************* Bit definition for ADC_SQR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2180 | #define ADC_SQR2_SQ7_MORT ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2181 | #define ADC_SQR2_SQ7_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2182 | #define ADC_SQR2_SQ7_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2183 | #define ADC_SQR2_SQ7_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2184 | #define ADC_SQR2_SQ7_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2185 | #define ADC_SQR2_SQ7_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2186 | #define ADC_SQR2_SQ8_MORT ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2187 | #define ADC_SQR2_SQ8_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2188 | #define ADC_SQR2_SQ8_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2189 | #define ADC_SQR2_SQ8_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2190 | #define ADC_SQR2_SQ8_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2191 | #define ADC_SQR2_SQ8_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2192 | #define ADC_SQR2_SQ9_MORT ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2193 | #define ADC_SQR2_SQ9_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2194 | #define ADC_SQR2_SQ9_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2195 | #define ADC_SQR2_SQ9_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2196 | #define ADC_SQR2_SQ9_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2197 | #define ADC_SQR2_SQ9_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2198 | #define ADC_SQR2_SQ10_MORT ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2199 | #define ADC_SQR2_SQ10_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2200 | #define ADC_SQR2_SQ10_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2201 | #define ADC_SQR2_SQ10_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2202 | #define ADC_SQR2_SQ10_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2203 | #define ADC_SQR2_SQ10_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2204 | #define ADC_SQR2_SQ11_MORT ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2205 | #define ADC_SQR2_SQ11_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2206 | #define ADC_SQR2_SQ11_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2207 | #define ADC_SQR2_SQ11_2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2208 | #define ADC_SQR2_SQ11_3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2209 | #define ADC_SQR2_SQ11_4_MORT ((uint32_t)0x01000000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2210 | #define ADC_SQR2_SQ12_MORT ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2211 | #define ADC_SQR2_SQ12_0_MORT ((uint32_t)0x02000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2212 | #define ADC_SQR2_SQ12_1_MORT ((uint32_t)0x04000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2213 | #define ADC_SQR2_SQ12_2_MORT ((uint32_t)0x08000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2214 | #define ADC_SQR2_SQ12_3_MORT ((uint32_t)0x10000000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2215 | #define ADC_SQR2_SQ12_4_MORT ((uint32_t)0x20000000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2216 | |
| rajathr | 0:34ee385f4d2d | 2217 | /******************* Bit definition for ADC_SQR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2218 | #define ADC_SQR3_SQ1_MORT ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2219 | #define ADC_SQR3_SQ1_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2220 | #define ADC_SQR3_SQ1_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2221 | #define ADC_SQR3_SQ1_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2222 | #define ADC_SQR3_SQ1_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2223 | #define ADC_SQR3_SQ1_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2224 | #define ADC_SQR3_SQ2_MORT ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2225 | #define ADC_SQR3_SQ2_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2226 | #define ADC_SQR3_SQ2_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2227 | #define ADC_SQR3_SQ2_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2228 | #define ADC_SQR3_SQ2_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2229 | #define ADC_SQR3_SQ2_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2230 | #define ADC_SQR3_SQ3_MORT ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2231 | #define ADC_SQR3_SQ3_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2232 | #define ADC_SQR3_SQ3_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2233 | #define ADC_SQR3_SQ3_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2234 | #define ADC_SQR3_SQ3_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2235 | #define ADC_SQR3_SQ3_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2236 | #define ADC_SQR3_SQ4_MORT ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2237 | #define ADC_SQR3_SQ4_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2238 | #define ADC_SQR3_SQ4_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2239 | #define ADC_SQR3_SQ4_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2240 | #define ADC_SQR3_SQ4_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2241 | #define ADC_SQR3_SQ4_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2242 | #define ADC_SQR3_SQ5_MORT ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2243 | #define ADC_SQR3_SQ5_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2244 | #define ADC_SQR3_SQ5_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2245 | #define ADC_SQR3_SQ5_2_MORT ((uint32_t)0x00400000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2246 | #define ADC_SQR3_SQ5_3_MORT ((uint32_t)0x00800000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2247 | #define ADC_SQR3_SQ5_4_MORT ((uint32_t)0x01000000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2248 | #define ADC_SQR3_SQ6_MORT ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
| rajathr | 0:34ee385f4d2d | 2249 | #define ADC_SQR3_SQ6_0_MORT ((uint32_t)0x02000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2250 | #define ADC_SQR3_SQ6_1_MORT ((uint32_t)0x04000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2251 | #define ADC_SQR3_SQ6_2_MORT ((uint32_t)0x08000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2252 | #define ADC_SQR3_SQ6_3_MORT ((uint32_t)0x10000000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2253 | #define ADC_SQR3_SQ6_4_MORT ((uint32_t)0x20000000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2254 | |
| rajathr | 0:34ee385f4d2d | 2255 | /******************* Bit definition for ADC_JSQR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2256 | #define ADC_JSQR_JSQ1_MORT ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
| rajathr | 0:34ee385f4d2d | 2257 | #define ADC_JSQR_JSQ1_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2258 | #define ADC_JSQR_JSQ1_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2259 | #define ADC_JSQR_JSQ1_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2260 | #define ADC_JSQR_JSQ1_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2261 | #define ADC_JSQR_JSQ1_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2262 | #define ADC_JSQR_JSQ2_MORT ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
| rajathr | 0:34ee385f4d2d | 2263 | #define ADC_JSQR_JSQ2_0_MORT ((uint32_t)0x00000020) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2264 | #define ADC_JSQR_JSQ2_1_MORT ((uint32_t)0x00000040) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2265 | #define ADC_JSQR_JSQ2_2_MORT ((uint32_t)0x00000080) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2266 | #define ADC_JSQR_JSQ2_3_MORT ((uint32_t)0x00000100) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2267 | #define ADC_JSQR_JSQ2_4_MORT ((uint32_t)0x00000200) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2268 | #define ADC_JSQR_JSQ3_MORT ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
| rajathr | 0:34ee385f4d2d | 2269 | #define ADC_JSQR_JSQ3_0_MORT ((uint32_t)0x00000400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2270 | #define ADC_JSQR_JSQ3_1_MORT ((uint32_t)0x00000800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2271 | #define ADC_JSQR_JSQ3_2_MORT ((uint32_t)0x00001000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2272 | #define ADC_JSQR_JSQ3_3_MORT ((uint32_t)0x00002000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2273 | #define ADC_JSQR_JSQ3_4_MORT ((uint32_t)0x00004000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2274 | #define ADC_JSQR_JSQ4_MORT ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
| rajathr | 0:34ee385f4d2d | 2275 | #define ADC_JSQR_JSQ4_0_MORT ((uint32_t)0x00008000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2276 | #define ADC_JSQR_JSQ4_1_MORT ((uint32_t)0x00010000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2277 | #define ADC_JSQR_JSQ4_2_MORT ((uint32_t)0x00020000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2278 | #define ADC_JSQR_JSQ4_3_MORT ((uint32_t)0x00040000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2279 | #define ADC_JSQR_JSQ4_4_MORT ((uint32_t)0x00080000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2280 | #define ADC_JSQR_JL_MORT ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */ |
| rajathr | 0:34ee385f4d2d | 2281 | #define ADC_JSQR_JL_0_MORT ((uint32_t)0x00100000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2282 | #define ADC_JSQR_JL_1_MORT ((uint32_t)0x00200000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2283 | |
| rajathr | 0:34ee385f4d2d | 2284 | /******************* Bit definition for ADC_JDR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2285 | #define ADC_JDR1_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ |
| rajathr | 0:34ee385f4d2d | 2286 | |
| rajathr | 0:34ee385f4d2d | 2287 | /******************* Bit definition for ADC_JDR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2288 | #define ADC_JDR2_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ |
| rajathr | 0:34ee385f4d2d | 2289 | |
| rajathr | 0:34ee385f4d2d | 2290 | /******************* Bit definition for ADC_JDR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2291 | #define ADC_JDR3_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ |
| rajathr | 0:34ee385f4d2d | 2292 | |
| rajathr | 0:34ee385f4d2d | 2293 | /******************* Bit definition for ADC_JDR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2294 | #define ADC_JDR4_JDATA_MORT ((uint16_t)0xFFFF) /*!<Injected data */ |
| rajathr | 0:34ee385f4d2d | 2295 | |
| rajathr | 0:34ee385f4d2d | 2296 | /******************** Bit definition for ADC_DR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2297 | #define ADC_DR_DATA_MORT ((uint32_t)0x0000FFFF) /*!<Regular data */ |
| rajathr | 0:34ee385f4d2d | 2298 | #define ADC_DR_ADC2DATA_MORT ((uint32_t)0xFFFF0000) /*!<ADC2_MORT data */ |
| rajathr | 0:34ee385f4d2d | 2299 | |
| rajathr | 0:34ee385f4d2d | 2300 | /******************* Bit definition for ADC_CSR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2301 | #define ADC_CSR_AWD1_MORT ((uint32_t)0x00000001) /*!<ADC1_MORT Analog watchdog flag */ |
| rajathr | 0:34ee385f4d2d | 2302 | #define ADC_CSR_EOC1_MORT ((uint32_t)0x00000002) /*!<ADC1_MORT End of conversion */ |
| rajathr | 0:34ee385f4d2d | 2303 | #define ADC_CSR_JEOC1_MORT ((uint32_t)0x00000004) /*!<ADC1_MORT Injected channel end of conversion */ |
| rajathr | 0:34ee385f4d2d | 2304 | #define ADC_CSR_JSTRT1_MORT ((uint32_t)0x00000008) /*!<ADC1_MORT Injected channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 2305 | #define ADC_CSR_STRT1_MORT ((uint32_t)0x00000010) /*!<ADC1_MORT Regular channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 2306 | #define ADC_CSR_OVR1_MORT ((uint32_t)0x00000020) /*!<ADC1_MORT DMA overrun flag */ |
| rajathr | 0:34ee385f4d2d | 2307 | #define ADC_CSR_AWD2_MORT ((uint32_t)0x00000100) /*!<ADC2_MORT Analog watchdog flag */ |
| rajathr | 0:34ee385f4d2d | 2308 | #define ADC_CSR_EOC2_MORT ((uint32_t)0x00000200) /*!<ADC2_MORT End of conversion */ |
| rajathr | 0:34ee385f4d2d | 2309 | #define ADC_CSR_JEOC2_MORT ((uint32_t)0x00000400) /*!<ADC2_MORT Injected channel end of conversion */ |
| rajathr | 0:34ee385f4d2d | 2310 | #define ADC_CSR_JSTRT2_MORT ((uint32_t)0x00000800) /*!<ADC2_MORT Injected channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 2311 | #define ADC_CSR_STRT2_MORT ((uint32_t)0x00001000) /*!<ADC2_MORT Regular channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 2312 | #define ADC_CSR_OVR2_MORT ((uint32_t)0x00002000) /*!<ADC2_MORT DMA overrun flag */ |
| rajathr | 0:34ee385f4d2d | 2313 | #define ADC_CSR_AWD3_MORT ((uint32_t)0x00010000) /*!<ADC3_MORT Analog watchdog flag */ |
| rajathr | 0:34ee385f4d2d | 2314 | #define ADC_CSR_EOC3_MORT ((uint32_t)0x00020000) /*!<ADC3_MORT End of conversion */ |
| rajathr | 0:34ee385f4d2d | 2315 | #define ADC_CSR_JEOC3_MORT ((uint32_t)0x00040000) /*!<ADC3_MORT Injected channel end of conversion */ |
| rajathr | 0:34ee385f4d2d | 2316 | #define ADC_CSR_JSTRT3_MORT ((uint32_t)0x00080000) /*!<ADC3_MORT Injected channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 2317 | #define ADC_CSR_STRT3_MORT ((uint32_t)0x00100000) /*!<ADC3_MORT Regular channel Start flag */ |
| rajathr | 0:34ee385f4d2d | 2318 | #define ADC_CSR_OVR3_MORT ((uint32_t)0x00200000) /*!<ADC3_MORT DMA overrun flag */ |
| rajathr | 0:34ee385f4d2d | 2319 | |
| rajathr | 0:34ee385f4d2d | 2320 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 2321 | #define ADC_CSR_DOVR1_MORT ADC_CSR_OVR1_MORT |
| rajathr | 0:34ee385f4d2d | 2322 | #define ADC_CSR_DOVR2_MORT ADC_CSR_OVR2_MORT |
| rajathr | 0:34ee385f4d2d | 2323 | #define ADC_CSR_DOVR3_MORT ADC_CSR_OVR3_MORT |
| rajathr | 0:34ee385f4d2d | 2324 | |
| rajathr | 0:34ee385f4d2d | 2325 | /******************* Bit definition for ADC_CCR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2326 | #define ADC_CCR_MULTI_MORT ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC_MORT mode selection) */ |
| rajathr | 0:34ee385f4d2d | 2327 | #define ADC_CCR_MULTI_0_MORT ((uint32_t)0x00000001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2328 | #define ADC_CCR_MULTI_1_MORT ((uint32_t)0x00000002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2329 | #define ADC_CCR_MULTI_2_MORT ((uint32_t)0x00000004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2330 | #define ADC_CCR_MULTI_3_MORT ((uint32_t)0x00000008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2331 | #define ADC_CCR_MULTI_4_MORT ((uint32_t)0x00000010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 2332 | #define ADC_CCR_DELAY_MORT ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ |
| rajathr | 0:34ee385f4d2d | 2333 | #define ADC_CCR_DELAY_0_MORT ((uint32_t)0x00000100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2334 | #define ADC_CCR_DELAY_1_MORT ((uint32_t)0x00000200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2335 | #define ADC_CCR_DELAY_2_MORT ((uint32_t)0x00000400) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2336 | #define ADC_CCR_DELAY_3_MORT ((uint32_t)0x00000800) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2337 | #define ADC_CCR_DDS_MORT ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC_MORT mode) */ |
| rajathr | 0:34ee385f4d2d | 2338 | #define ADC_CCR_DMA_MORT ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ |
| rajathr | 0:34ee385f4d2d | 2339 | #define ADC_CCR_DMA_0_MORT ((uint32_t)0x00004000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2340 | #define ADC_CCR_DMA_1_MORT ((uint32_t)0x00008000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2341 | #define ADC_CCR_ADCPRE_MORT ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC_MORT prescaler) */ |
| rajathr | 0:34ee385f4d2d | 2342 | #define ADC_CCR_ADCPRE_0_MORT ((uint32_t)0x00010000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2343 | #define ADC_CCR_ADCPRE_1_MORT ((uint32_t)0x00020000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2344 | #define ADC_CCR_VBATE_MORT ((uint32_t)0x00400000) /*!<VBAT Enable */ |
| rajathr | 0:34ee385f4d2d | 2345 | #define ADC_CCR_TSVREFE_MORT ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */ |
| rajathr | 0:34ee385f4d2d | 2346 | |
| rajathr | 0:34ee385f4d2d | 2347 | /******************* Bit definition for ADC_CDR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2348 | #define ADC_CDR_DATA1_MORT ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */ |
| rajathr | 0:34ee385f4d2d | 2349 | #define ADC_CDR_DATA2_MORT ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */ |
| rajathr | 0:34ee385f4d2d | 2350 | |
| rajathr | 0:34ee385f4d2d | 2351 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2352 | /* */ |
| rajathr | 0:34ee385f4d2d | 2353 | /* Controller Area Network */ |
| rajathr | 0:34ee385f4d2d | 2354 | /* */ |
| rajathr | 0:34ee385f4d2d | 2355 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2356 | /*!<CAN control and status registers */ |
| rajathr | 0:34ee385f4d2d | 2357 | /******************* Bit definition for CAN_MCR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2358 | |
| rajathr | 0:34ee385f4d2d | 2359 | |
| rajathr | 0:34ee385f4d2d | 2360 | /******************* Bit definition for CAN_MSR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2361 | |
| rajathr | 0:34ee385f4d2d | 2362 | |
| rajathr | 0:34ee385f4d2d | 2363 | /******************* Bit definition for CAN_TSR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2364 | |
| rajathr | 0:34ee385f4d2d | 2365 | |
| rajathr | 0:34ee385f4d2d | 2366 | /******************* Bit definition for CAN_RF0R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2367 | |
| rajathr | 0:34ee385f4d2d | 2368 | |
| rajathr | 0:34ee385f4d2d | 2369 | /******************* Bit definition for CAN_RF1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2370 | |
| rajathr | 0:34ee385f4d2d | 2371 | |
| rajathr | 0:34ee385f4d2d | 2372 | /******************** Bit definition for CAN_IER register *******************/ |
| rajathr | 0:34ee385f4d2d | 2373 | |
| rajathr | 0:34ee385f4d2d | 2374 | |
| rajathr | 0:34ee385f4d2d | 2375 | /******************** Bit definition for CAN_ESR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2376 | |
| rajathr | 0:34ee385f4d2d | 2377 | /******************* Bit definition for CAN_BTR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2378 | |
| rajathr | 0:34ee385f4d2d | 2379 | |
| rajathr | 0:34ee385f4d2d | 2380 | /*!<Mailbox registers */ |
| rajathr | 0:34ee385f4d2d | 2381 | /****************** Bit definition for CAN_TI0R register ********************/ |
| rajathr | 0:34ee385f4d2d | 2382 | |
| rajathr | 0:34ee385f4d2d | 2383 | |
| rajathr | 0:34ee385f4d2d | 2384 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2385 | |
| rajathr | 0:34ee385f4d2d | 2386 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2387 | |
| rajathr | 0:34ee385f4d2d | 2388 | |
| rajathr | 0:34ee385f4d2d | 2389 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2390 | |
| rajathr | 0:34ee385f4d2d | 2391 | /******************* Bit definition for CAN_TI1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2392 | |
| rajathr | 0:34ee385f4d2d | 2393 | |
| rajathr | 0:34ee385f4d2d | 2394 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2395 | |
| rajathr | 0:34ee385f4d2d | 2396 | |
| rajathr | 0:34ee385f4d2d | 2397 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2398 | |
| rajathr | 0:34ee385f4d2d | 2399 | |
| rajathr | 0:34ee385f4d2d | 2400 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2401 | |
| rajathr | 0:34ee385f4d2d | 2402 | |
| rajathr | 0:34ee385f4d2d | 2403 | /******************* Bit definition for CAN_TI2R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2404 | |
| rajathr | 0:34ee385f4d2d | 2405 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2406 | |
| rajathr | 0:34ee385f4d2d | 2407 | |
| rajathr | 0:34ee385f4d2d | 2408 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2409 | |
| rajathr | 0:34ee385f4d2d | 2410 | |
| rajathr | 0:34ee385f4d2d | 2411 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2412 | |
| rajathr | 0:34ee385f4d2d | 2413 | |
| rajathr | 0:34ee385f4d2d | 2414 | /******************* Bit definition for CAN_RI0R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2415 | |
| rajathr | 0:34ee385f4d2d | 2416 | |
| rajathr | 0:34ee385f4d2d | 2417 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2418 | |
| rajathr | 0:34ee385f4d2d | 2419 | |
| rajathr | 0:34ee385f4d2d | 2420 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2421 | |
| rajathr | 0:34ee385f4d2d | 2422 | |
| rajathr | 0:34ee385f4d2d | 2423 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2424 | |
| rajathr | 0:34ee385f4d2d | 2425 | |
| rajathr | 0:34ee385f4d2d | 2426 | /******************* Bit definition for CAN_RI1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2427 | |
| rajathr | 0:34ee385f4d2d | 2428 | |
| rajathr | 0:34ee385f4d2d | 2429 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2430 | |
| rajathr | 0:34ee385f4d2d | 2431 | |
| rajathr | 0:34ee385f4d2d | 2432 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2433 | |
| rajathr | 0:34ee385f4d2d | 2434 | |
| rajathr | 0:34ee385f4d2d | 2435 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| rajathr | 0:34ee385f4d2d | 2436 | |
| rajathr | 0:34ee385f4d2d | 2437 | |
| rajathr | 0:34ee385f4d2d | 2438 | /*!<CAN filter registers */ |
| rajathr | 0:34ee385f4d2d | 2439 | /******************* Bit definition for CAN_FMR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2440 | |
| rajathr | 0:34ee385f4d2d | 2441 | |
| rajathr | 0:34ee385f4d2d | 2442 | /******************* Bit definition for CAN_FM1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2443 | |
| rajathr | 0:34ee385f4d2d | 2444 | |
| rajathr | 0:34ee385f4d2d | 2445 | /******************* Bit definition for CAN_FS1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2446 | |
| rajathr | 0:34ee385f4d2d | 2447 | |
| rajathr | 0:34ee385f4d2d | 2448 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2449 | |
| rajathr | 0:34ee385f4d2d | 2450 | |
| rajathr | 0:34ee385f4d2d | 2451 | /******************* Bit definition for CAN_FA1R register *******************/ |
| rajathr | 0:34ee385f4d2d | 2452 | |
| rajathr | 0:34ee385f4d2d | 2453 | |
| rajathr | 0:34ee385f4d2d | 2454 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2455 | |
| rajathr | 0:34ee385f4d2d | 2456 | |
| rajathr | 0:34ee385f4d2d | 2457 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2458 | |
| rajathr | 0:34ee385f4d2d | 2459 | |
| rajathr | 0:34ee385f4d2d | 2460 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2461 | |
| rajathr | 0:34ee385f4d2d | 2462 | |
| rajathr | 0:34ee385f4d2d | 2463 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2464 | |
| rajathr | 0:34ee385f4d2d | 2465 | |
| rajathr | 0:34ee385f4d2d | 2466 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2467 | |
| rajathr | 0:34ee385f4d2d | 2468 | |
| rajathr | 0:34ee385f4d2d | 2469 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2470 | |
| rajathr | 0:34ee385f4d2d | 2471 | |
| rajathr | 0:34ee385f4d2d | 2472 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2473 | |
| rajathr | 0:34ee385f4d2d | 2474 | |
| rajathr | 0:34ee385f4d2d | 2475 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2476 | |
| rajathr | 0:34ee385f4d2d | 2477 | |
| rajathr | 0:34ee385f4d2d | 2478 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2479 | |
| rajathr | 0:34ee385f4d2d | 2480 | |
| rajathr | 0:34ee385f4d2d | 2481 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2482 | |
| rajathr | 0:34ee385f4d2d | 2483 | |
| rajathr | 0:34ee385f4d2d | 2484 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2485 | |
| rajathr | 0:34ee385f4d2d | 2486 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2487 | |
| rajathr | 0:34ee385f4d2d | 2488 | |
| rajathr | 0:34ee385f4d2d | 2489 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2490 | |
| rajathr | 0:34ee385f4d2d | 2491 | |
| rajathr | 0:34ee385f4d2d | 2492 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2493 | |
| rajathr | 0:34ee385f4d2d | 2494 | |
| rajathr | 0:34ee385f4d2d | 2495 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2496 | |
| rajathr | 0:34ee385f4d2d | 2497 | |
| rajathr | 0:34ee385f4d2d | 2498 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2499 | |
| rajathr | 0:34ee385f4d2d | 2500 | |
| rajathr | 0:34ee385f4d2d | 2501 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2502 | |
| rajathr | 0:34ee385f4d2d | 2503 | |
| rajathr | 0:34ee385f4d2d | 2504 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2505 | |
| rajathr | 0:34ee385f4d2d | 2506 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2507 | |
| rajathr | 0:34ee385f4d2d | 2508 | |
| rajathr | 0:34ee385f4d2d | 2509 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2510 | |
| rajathr | 0:34ee385f4d2d | 2511 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2512 | |
| rajathr | 0:34ee385f4d2d | 2513 | |
| rajathr | 0:34ee385f4d2d | 2514 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2515 | |
| rajathr | 0:34ee385f4d2d | 2516 | |
| rajathr | 0:34ee385f4d2d | 2517 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2518 | |
| rajathr | 0:34ee385f4d2d | 2519 | |
| rajathr | 0:34ee385f4d2d | 2520 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2521 | |
| rajathr | 0:34ee385f4d2d | 2522 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2523 | |
| rajathr | 0:34ee385f4d2d | 2524 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2525 | |
| rajathr | 0:34ee385f4d2d | 2526 | |
| rajathr | 0:34ee385f4d2d | 2527 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2528 | |
| rajathr | 0:34ee385f4d2d | 2529 | |
| rajathr | 0:34ee385f4d2d | 2530 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2531 | |
| rajathr | 0:34ee385f4d2d | 2532 | |
| rajathr | 0:34ee385f4d2d | 2533 | |
| rajathr | 0:34ee385f4d2d | 2534 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 2535 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2536 | /* */ |
| rajathr | 0:34ee385f4d2d | 2537 | /* HDMI-CEC_MORT (CEC_MORT) */ |
| rajathr | 0:34ee385f4d2d | 2538 | /* */ |
| rajathr | 0:34ee385f4d2d | 2539 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2540 | |
| rajathr | 0:34ee385f4d2d | 2541 | /******************* Bit definition for CEC_CR register *********************/ |
| rajathr | 0:34ee385f4d2d | 2542 | #define CEC_CR_CECEN_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Enable */ |
| rajathr | 0:34ee385f4d2d | 2543 | #define CEC_CR_TXSOM_MORT ((uint32_t)0x00000002) /*!< CEC_MORT Tx Start Of Message */ |
| rajathr | 0:34ee385f4d2d | 2544 | #define CEC_CR_TXEOM_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Tx End Of Message */ |
| rajathr | 0:34ee385f4d2d | 2545 | |
| rajathr | 0:34ee385f4d2d | 2546 | /******************* Bit definition for CEC_CFGR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2547 | #define CEC_CFGR_SFT_MORT ((uint32_t)0x00000007) /*!< CEC_MORT Signal Free Time */ |
| rajathr | 0:34ee385f4d2d | 2548 | #define CEC_CFGR_RXTOL_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Tolerance */ |
| rajathr | 0:34ee385f4d2d | 2549 | #define CEC_CFGR_BRESTP_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Stop */ |
| rajathr | 0:34ee385f4d2d | 2550 | #define CEC_CFGR_BREGEN_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Bit Rising Error generation */ |
| rajathr | 0:34ee385f4d2d | 2551 | #define CEC_CFGR_LREGEN_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Long Period Error generation */ |
| rajathr | 0:34ee385f4d2d | 2552 | #define CEC_CFGR_SFTOPT_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Signal Free Time optional */ |
| rajathr | 0:34ee385f4d2d | 2553 | #define CEC_CFGR_BRDNOGEN_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Broadcast No error generation */ |
| rajathr | 0:34ee385f4d2d | 2554 | #define CEC_CFGR_OAR_MORT ((uint32_t)0x7FFF0000) /*!< CEC_MORT Own Address */ |
| rajathr | 0:34ee385f4d2d | 2555 | #define CEC_CFGR_LSTN_MORT ((uint32_t)0x80000000) /*!< CEC_MORT Listen mode */ |
| rajathr | 0:34ee385f4d2d | 2556 | |
| rajathr | 0:34ee385f4d2d | 2557 | /******************* Bit definition for CEC_TXDR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2558 | #define CEC_TXDR_TXD_MORT ((uint32_t)0x000000FF) /*!< CEC_MORT Tx Data */ |
| rajathr | 0:34ee385f4d2d | 2559 | |
| rajathr | 0:34ee385f4d2d | 2560 | /******************* Bit definition for CEC_RXDR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2561 | #define CEC_TXDR_RXD_MORT ((uint32_t)0x000000FF) /*!< CEC_MORT Rx Data */ |
| rajathr | 0:34ee385f4d2d | 2562 | |
| rajathr | 0:34ee385f4d2d | 2563 | /******************* Bit definition for CEC_ISR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2564 | #define CEC_ISR_RXBR_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Rx-Byte Received */ |
| rajathr | 0:34ee385f4d2d | 2565 | #define CEC_ISR_RXEND_MORT ((uint32_t)0x00000002) /*!< CEC_MORT End Of Reception */ |
| rajathr | 0:34ee385f4d2d | 2566 | #define CEC_ISR_RXOVR_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Rx-Overrun */ |
| rajathr | 0:34ee385f4d2d | 2567 | #define CEC_ISR_BRE_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Rx Bit Rising Error */ |
| rajathr | 0:34ee385f4d2d | 2568 | #define CEC_ISR_SBPE_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Short Bit period Error */ |
| rajathr | 0:34ee385f4d2d | 2569 | #define CEC_ISR_LBPE_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Rx Long Bit period Error */ |
| rajathr | 0:34ee385f4d2d | 2570 | #define CEC_ISR_RXACKE_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Rx Missing Acknowledge */ |
| rajathr | 0:34ee385f4d2d | 2571 | #define CEC_ISR_ARBLST_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Arbitration Lost */ |
| rajathr | 0:34ee385f4d2d | 2572 | #define CEC_ISR_TXBR_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Tx Byte Request */ |
| rajathr | 0:34ee385f4d2d | 2573 | #define CEC_ISR_TXEND_MORT ((uint32_t)0x00000200) /*!< CEC_MORT End of Transmission */ |
| rajathr | 0:34ee385f4d2d | 2574 | #define CEC_ISR_TXUDR_MORT ((uint32_t)0x00000400) /*!< CEC_MORT Tx-Buffer Underrun */ |
| rajathr | 0:34ee385f4d2d | 2575 | #define CEC_ISR_TXERR_MORT ((uint32_t)0x00000800) /*!< CEC_MORT Tx-Error */ |
| rajathr | 0:34ee385f4d2d | 2576 | #define CEC_ISR_TXACKE_MORT ((uint32_t)0x00001000) /*!< CEC_MORT Tx Missing Acknowledge */ |
| rajathr | 0:34ee385f4d2d | 2577 | |
| rajathr | 0:34ee385f4d2d | 2578 | /******************* Bit definition for CEC_IER register ********************/ |
| rajathr | 0:34ee385f4d2d | 2579 | #define CEC_IER_RXBRIE_MORT ((uint32_t)0x00000001) /*!< CEC_MORT Rx-Byte Received IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2580 | #define CEC_IER_RXENDIE_MORT ((uint32_t)0x00000002) /*!< CEC_MORT End Of Reception IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2581 | #define CEC_IER_RXOVRIE_MORT ((uint32_t)0x00000004) /*!< CEC_MORT Rx-Overrun IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2582 | #define CEC_IER_BREIEIE_MORT ((uint32_t)0x00000008) /*!< CEC_MORT Rx Bit Rising Error IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2583 | #define CEC_IER_SBPEIE_MORT ((uint32_t)0x00000010) /*!< CEC_MORT Rx Short Bit period Error IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2584 | #define CEC_IER_LBPEIE_MORT ((uint32_t)0x00000020) /*!< CEC_MORT Rx Long Bit period Error IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2585 | #define CEC_IER_RXACKEIE_MORT ((uint32_t)0x00000040) /*!< CEC_MORT Rx Missing Acknowledge IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2586 | #define CEC_IER_ARBLSTIE_MORT ((uint32_t)0x00000080) /*!< CEC_MORT Arbitration Lost IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2587 | #define CEC_IER_TXBRIE_MORT ((uint32_t)0x00000100) /*!< CEC_MORT Tx Byte Request IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2588 | #define CEC_IER_TXENDIE_MORT ((uint32_t)0x00000200) /*!< CEC_MORT End of Transmission IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2589 | #define CEC_IER_TXUDRIE_MORT ((uint32_t)0x00000400) /*!< CEC_MORT Tx-Buffer Underrun IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2590 | #define CEC_IER_TXERRIE_MORT ((uint32_t)0x00000800) /*!< CEC_MORT Tx-Error IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2591 | #define CEC_IER_TXACKEIE_MORT ((uint32_t)0x00001000) /*!< CEC_MORT Tx Missing Acknowledge IT Enable */ |
| rajathr | 0:34ee385f4d2d | 2592 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 2593 | |
| rajathr | 0:34ee385f4d2d | 2594 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2595 | /* */ |
| rajathr | 0:34ee385f4d2d | 2596 | /* CRC_MORT calculation unit */ |
| rajathr | 0:34ee385f4d2d | 2597 | /* */ |
| rajathr | 0:34ee385f4d2d | 2598 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2599 | /******************* Bit definition for CRC_DR register *********************/ |
| rajathr | 0:34ee385f4d2d | 2600 | #define CRC_DR_DR_MORT ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
| rajathr | 0:34ee385f4d2d | 2601 | |
| rajathr | 0:34ee385f4d2d | 2602 | |
| rajathr | 0:34ee385f4d2d | 2603 | /******************* Bit definition for CRC_IDR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2604 | #define CRC_IDR_IDR_MORT ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
| rajathr | 0:34ee385f4d2d | 2605 | |
| rajathr | 0:34ee385f4d2d | 2606 | |
| rajathr | 0:34ee385f4d2d | 2607 | /******************** Bit definition for CRC_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2608 | #define CRC_CR_RESET_MORT ((uint8_t)0x01) /*!< RESET bit */ |
| rajathr | 0:34ee385f4d2d | 2609 | |
| rajathr | 0:34ee385f4d2d | 2610 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2611 | /* */ |
| rajathr | 0:34ee385f4d2d | 2612 | /* Crypto Processor */ |
| rajathr | 0:34ee385f4d2d | 2613 | /* */ |
| rajathr | 0:34ee385f4d2d | 2614 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2615 | /******************* Bits definition for CRYP_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2616 | |
| rajathr | 0:34ee385f4d2d | 2617 | |
| rajathr | 0:34ee385f4d2d | 2618 | /****************** Bits definition for CRYP_SR register *********************/ |
| rajathr | 0:34ee385f4d2d | 2619 | |
| rajathr | 0:34ee385f4d2d | 2620 | /****************** Bits definition for CRYP_DMACR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2621 | |
| rajathr | 0:34ee385f4d2d | 2622 | /***************** Bits definition for CRYP_IMSCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2623 | |
| rajathr | 0:34ee385f4d2d | 2624 | /****************** Bits definition for CRYP_RISR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2625 | |
| rajathr | 0:34ee385f4d2d | 2626 | /****************** Bits definition for CRYP_MISR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2627 | |
| rajathr | 0:34ee385f4d2d | 2628 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2629 | /* */ |
| rajathr | 0:34ee385f4d2d | 2630 | /* Digital to Analog Converter */ |
| rajathr | 0:34ee385f4d2d | 2631 | /* */ |
| rajathr | 0:34ee385f4d2d | 2632 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2633 | /******************** Bit definition for DAC_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2634 | #define DAC_CR_EN1_MORT ((uint32_t)0x00000001) /*!<DAC_MORT channel1 enable */ |
| rajathr | 0:34ee385f4d2d | 2635 | #define DAC_CR_BOFF1_MORT ((uint32_t)0x00000002) /*!<DAC_MORT channel1 output buffer disable */ |
| rajathr | 0:34ee385f4d2d | 2636 | #define DAC_CR_TEN1_MORT ((uint32_t)0x00000004) /*!<DAC_MORT channel1 Trigger enable */ |
| rajathr | 0:34ee385f4d2d | 2637 | |
| rajathr | 0:34ee385f4d2d | 2638 | #define DAC_CR_TSEL1_MORT ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC_MORT channel1 Trigger selection) */ |
| rajathr | 0:34ee385f4d2d | 2639 | #define DAC_CR_TSEL1_0_MORT ((uint32_t)0x00000008) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2640 | #define DAC_CR_TSEL1_1_MORT ((uint32_t)0x00000010) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2641 | #define DAC_CR_TSEL1_2_MORT ((uint32_t)0x00000020) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2642 | |
| rajathr | 0:34ee385f4d2d | 2643 | #define DAC_CR_WAVE1_MORT ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC_MORT channel1 noise/triangle wave generation enable) */ |
| rajathr | 0:34ee385f4d2d | 2644 | #define DAC_CR_WAVE1_0_MORT ((uint32_t)0x00000040) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2645 | #define DAC_CR_WAVE1_1_MORT ((uint32_t)0x00000080) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2646 | |
| rajathr | 0:34ee385f4d2d | 2647 | #define DAC_CR_MAMP1_MORT ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC_MORT channel1 Mask/Amplitude selector) */ |
| rajathr | 0:34ee385f4d2d | 2648 | #define DAC_CR_MAMP1_0_MORT ((uint32_t)0x00000100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2649 | #define DAC_CR_MAMP1_1_MORT ((uint32_t)0x00000200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2650 | #define DAC_CR_MAMP1_2_MORT ((uint32_t)0x00000400) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2651 | #define DAC_CR_MAMP1_3_MORT ((uint32_t)0x00000800) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2652 | |
| rajathr | 0:34ee385f4d2d | 2653 | #define DAC_CR_DMAEN1_MORT ((uint32_t)0x00001000) /*!<DAC_MORT channel1 DMA enable */ |
| rajathr | 0:34ee385f4d2d | 2654 | #define DAC_CR_DMAUDRIE1_MORT ((uint32_t)0x00002000) /*!<DAC_MORT channel1 DMA underrun interrupt enable*/ |
| rajathr | 0:34ee385f4d2d | 2655 | #define DAC_CR_EN2_MORT ((uint32_t)0x00010000) /*!<DAC_MORT channel2 enable */ |
| rajathr | 0:34ee385f4d2d | 2656 | #define DAC_CR_BOFF2_MORT ((uint32_t)0x00020000) /*!<DAC_MORT channel2 output buffer disable */ |
| rajathr | 0:34ee385f4d2d | 2657 | #define DAC_CR_TEN2_MORT ((uint32_t)0x00040000) /*!<DAC_MORT channel2 Trigger enable */ |
| rajathr | 0:34ee385f4d2d | 2658 | |
| rajathr | 0:34ee385f4d2d | 2659 | #define DAC_CR_TSEL2_MORT ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC_MORT channel2 Trigger selection) */ |
| rajathr | 0:34ee385f4d2d | 2660 | #define DAC_CR_TSEL2_0_MORT ((uint32_t)0x00080000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2661 | #define DAC_CR_TSEL2_1_MORT ((uint32_t)0x00100000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2662 | #define DAC_CR_TSEL2_2_MORT ((uint32_t)0x00200000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2663 | |
| rajathr | 0:34ee385f4d2d | 2664 | #define DAC_CR_WAVE2_MORT ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC_MORT channel2 noise/triangle wave generation enable) */ |
| rajathr | 0:34ee385f4d2d | 2665 | #define DAC_CR_WAVE2_0_MORT ((uint32_t)0x00400000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2666 | #define DAC_CR_WAVE2_1_MORT ((uint32_t)0x00800000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2667 | |
| rajathr | 0:34ee385f4d2d | 2668 | #define DAC_CR_MAMP2_MORT ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC_MORT channel2 Mask/Amplitude selector) */ |
| rajathr | 0:34ee385f4d2d | 2669 | #define DAC_CR_MAMP2_0_MORT ((uint32_t)0x01000000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 2670 | #define DAC_CR_MAMP2_1_MORT ((uint32_t)0x02000000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 2671 | #define DAC_CR_MAMP2_2_MORT ((uint32_t)0x04000000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 2672 | #define DAC_CR_MAMP2_3_MORT ((uint32_t)0x08000000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 2673 | |
| rajathr | 0:34ee385f4d2d | 2674 | #define DAC_CR_DMAEN2_MORT ((uint32_t)0x10000000) /*!<DAC_MORT channel2 DMA enabled */ |
| rajathr | 0:34ee385f4d2d | 2675 | #define DAC_CR_DMAUDRIE2_MORT ((uint32_t)0x20000000U) /*!<DAC_MORT channel2 DMA underrun interrupt enable*/ |
| rajathr | 0:34ee385f4d2d | 2676 | |
| rajathr | 0:34ee385f4d2d | 2677 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2678 | #define DAC_SWTRIGR_SWTRIG1_MORT ((uint8_t)0x01) /*!<DAC_MORT channel1 software trigger */ |
| rajathr | 0:34ee385f4d2d | 2679 | #define DAC_SWTRIGR_SWTRIG2_MORT ((uint8_t)0x02) /*!<DAC_MORT channel2 software trigger */ |
| rajathr | 0:34ee385f4d2d | 2680 | |
| rajathr | 0:34ee385f4d2d | 2681 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2682 | #define DAC_DHR12R1_DACC1DHR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel1 12-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2683 | |
| rajathr | 0:34ee385f4d2d | 2684 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2685 | #define DAC_DHR12L1_DACC1DHR_MORT ((uint16_t)0xFFF0) /*!<DAC_MORT channel1 12-bit Left aligned data */ |
| rajathr | 0:34ee385f4d2d | 2686 | |
| rajathr | 0:34ee385f4d2d | 2687 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2688 | #define DAC_DHR8R1_DACC1DHR_MORT ((uint8_t)0xFF) /*!<DAC_MORT channel1 8-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2689 | |
| rajathr | 0:34ee385f4d2d | 2690 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2691 | #define DAC_DHR12R2_DACC2DHR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel2 12-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2692 | |
| rajathr | 0:34ee385f4d2d | 2693 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2694 | #define DAC_DHR12L2_DACC2DHR_MORT ((uint16_t)0xFFF0) /*!<DAC_MORT channel2 12-bit Left aligned data */ |
| rajathr | 0:34ee385f4d2d | 2695 | |
| rajathr | 0:34ee385f4d2d | 2696 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2697 | #define DAC_DHR8R2_DACC2DHR_MORT ((uint8_t)0xFF) /*!<DAC_MORT channel2 8-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2698 | |
| rajathr | 0:34ee385f4d2d | 2699 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| rajathr | 0:34ee385f4d2d | 2700 | #define DAC_DHR12RD_DACC1DHR_MORT ((uint32_t)0x00000FFF) /*!<DAC_MORT channel1 12-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2701 | #define DAC_DHR12RD_DACC2DHR_MORT ((uint32_t)0x0FFF0000) /*!<DAC_MORT channel2 12-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2702 | |
| rajathr | 0:34ee385f4d2d | 2703 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| rajathr | 0:34ee385f4d2d | 2704 | #define DAC_DHR12LD_DACC1DHR_MORT ((uint32_t)0x0000FFF0) /*!<DAC_MORT channel1 12-bit Left aligned data */ |
| rajathr | 0:34ee385f4d2d | 2705 | #define DAC_DHR12LD_DACC2DHR_MORT ((uint32_t)0xFFF00000) /*!<DAC_MORT channel2 12-bit Left aligned data */ |
| rajathr | 0:34ee385f4d2d | 2706 | |
| rajathr | 0:34ee385f4d2d | 2707 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| rajathr | 0:34ee385f4d2d | 2708 | #define DAC_DHR8RD_DACC1DHR_MORT ((uint16_t)0x00FF) /*!<DAC_MORT channel1 8-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2709 | #define DAC_DHR8RD_DACC2DHR_MORT ((uint16_t)0xFF00) /*!<DAC_MORT channel2 8-bit Right aligned data */ |
| rajathr | 0:34ee385f4d2d | 2710 | |
| rajathr | 0:34ee385f4d2d | 2711 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2712 | #define DAC_DOR1_DACC1DOR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel1 data output */ |
| rajathr | 0:34ee385f4d2d | 2713 | |
| rajathr | 0:34ee385f4d2d | 2714 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2715 | #define DAC_DOR2_DACC2DOR_MORT ((uint16_t)0x0FFF) /*!<DAC_MORT channel2 data output */ |
| rajathr | 0:34ee385f4d2d | 2716 | |
| rajathr | 0:34ee385f4d2d | 2717 | /******************** Bit definition for DAC_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 2718 | #define DAC_SR_DMAUDR1_MORT ((uint32_t)0x00002000) /*!<DAC_MORT channel1 DMA underrun flag */ |
| rajathr | 0:34ee385f4d2d | 2719 | #define DAC_SR_DMAUDR2_MORT ((uint32_t)0x20000000) /*!<DAC_MORT channel2 DMA underrun flag */ |
| rajathr | 0:34ee385f4d2d | 2720 | |
| rajathr | 0:34ee385f4d2d | 2721 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2722 | /* */ |
| rajathr | 0:34ee385f4d2d | 2723 | /* Debug MCU */ |
| rajathr | 0:34ee385f4d2d | 2724 | /* */ |
| rajathr | 0:34ee385f4d2d | 2725 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2726 | |
| rajathr | 0:34ee385f4d2d | 2727 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2728 | /* */ |
| rajathr | 0:34ee385f4d2d | 2729 | /* DCMI_MORT */ |
| rajathr | 0:34ee385f4d2d | 2730 | /* */ |
| rajathr | 0:34ee385f4d2d | 2731 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2732 | /******************** Bits definition for DCMI_CR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2733 | |
| rajathr | 0:34ee385f4d2d | 2734 | |
| rajathr | 0:34ee385f4d2d | 2735 | /******************** Bits definition for DCMI_SR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2736 | |
| rajathr | 0:34ee385f4d2d | 2737 | |
| rajathr | 0:34ee385f4d2d | 2738 | /******************** Bits definition for DCMI_RIS register *****************/ |
| rajathr | 0:34ee385f4d2d | 2739 | |
| rajathr | 0:34ee385f4d2d | 2740 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 2741 | |
| rajathr | 0:34ee385f4d2d | 2742 | |
| rajathr | 0:34ee385f4d2d | 2743 | /******************** Bits definition for DCMI_IER register *****************/ |
| rajathr | 0:34ee385f4d2d | 2744 | |
| rajathr | 0:34ee385f4d2d | 2745 | |
| rajathr | 0:34ee385f4d2d | 2746 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 2747 | |
| rajathr | 0:34ee385f4d2d | 2748 | |
| rajathr | 0:34ee385f4d2d | 2749 | /******************** Bits definition for DCMI_MIS register ****************/ |
| rajathr | 0:34ee385f4d2d | 2750 | |
| rajathr | 0:34ee385f4d2d | 2751 | |
| rajathr | 0:34ee385f4d2d | 2752 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 2753 | |
| rajathr | 0:34ee385f4d2d | 2754 | |
| rajathr | 0:34ee385f4d2d | 2755 | /******************** Bits definition for DCMI_ICR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2756 | |
| rajathr | 0:34ee385f4d2d | 2757 | |
| rajathr | 0:34ee385f4d2d | 2758 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 2759 | |
| rajathr | 0:34ee385f4d2d | 2760 | /******************** Bits definition for DCMI_ESCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2761 | |
| rajathr | 0:34ee385f4d2d | 2762 | |
| rajathr | 0:34ee385f4d2d | 2763 | /******************** Bits definition for DCMI_ESUR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2764 | |
| rajathr | 0:34ee385f4d2d | 2765 | |
| rajathr | 0:34ee385f4d2d | 2766 | /******************** Bits definition for DCMI_CWSTRT register ******************/ |
| rajathr | 0:34ee385f4d2d | 2767 | |
| rajathr | 0:34ee385f4d2d | 2768 | |
| rajathr | 0:34ee385f4d2d | 2769 | /******************** Bits definition for DCMI_CWSIZE register ******************/ |
| rajathr | 0:34ee385f4d2d | 2770 | |
| rajathr | 0:34ee385f4d2d | 2771 | |
| rajathr | 0:34ee385f4d2d | 2772 | /******************** Bits definition for DCMI_DR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2773 | |
| rajathr | 0:34ee385f4d2d | 2774 | |
| rajathr | 0:34ee385f4d2d | 2775 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2776 | /* */ |
| rajathr | 0:34ee385f4d2d | 2777 | /* Digital Filter for Sigma Delta Modulators */ |
| rajathr | 0:34ee385f4d2d | 2778 | /* */ |
| rajathr | 0:34ee385f4d2d | 2779 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2780 | |
| rajathr | 0:34ee385f4d2d | 2781 | /**************** DFSDM channel configuration registers ********************/ |
| rajathr | 0:34ee385f4d2d | 2782 | |
| rajathr | 0:34ee385f4d2d | 2783 | /*************** Bit definition for DFSDM_CHCFGR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2784 | |
| rajathr | 0:34ee385f4d2d | 2785 | /*************** Bit definition for DFSDM_CHCFGR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 2786 | |
| rajathr | 0:34ee385f4d2d | 2787 | /****************** Bit definition for DFSDM_CHAWSCDR register ***************/ |
| rajathr | 0:34ee385f4d2d | 2788 | |
| rajathr | 0:34ee385f4d2d | 2789 | /**************** Bit definition for DFSDM_CHWDATR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2790 | |
| rajathr | 0:34ee385f4d2d | 2791 | /**************** Bit definition for DFSDM_CHDATINR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2792 | |
| rajathr | 0:34ee385f4d2d | 2793 | /************************ DFSDM module registers ****************************/ |
| rajathr | 0:34ee385f4d2d | 2794 | |
| rajathr | 0:34ee385f4d2d | 2795 | /***************** Bit definition for DFSDM_FLTCR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 2796 | |
| rajathr | 0:34ee385f4d2d | 2797 | /******************** Bit definition for DFSDM_FLTCR2 register ***************/ |
| rajathr | 0:34ee385f4d2d | 2798 | |
| rajathr | 0:34ee385f4d2d | 2799 | /***************** Bit definition for DFSDM_FLTISR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2800 | |
| rajathr | 0:34ee385f4d2d | 2801 | /***************** Bit definition for DFSDM_FLTICR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2802 | |
| rajathr | 0:34ee385f4d2d | 2803 | /**************** Bit definition for DFSDM_FLTJCHGR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2804 | |
| rajathr | 0:34ee385f4d2d | 2805 | /***************** Bit definition for DFSDM_FLTFCR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2806 | |
| rajathr | 0:34ee385f4d2d | 2807 | /*************** Bit definition for DFSDM_FLTJDATAR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2808 | |
| rajathr | 0:34ee385f4d2d | 2809 | /*************** Bit definition for DFSDM_FLTRDATAR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2810 | |
| rajathr | 0:34ee385f4d2d | 2811 | /*************** Bit definition for DFSDM_FLTAWHTR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2812 | |
| rajathr | 0:34ee385f4d2d | 2813 | /*************** Bit definition for DFSDM_FLTAWLTR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2814 | |
| rajathr | 0:34ee385f4d2d | 2815 | /*************** Bit definition for DFSDM_FLTAWSR register *******************/ |
| rajathr | 0:34ee385f4d2d | 2816 | |
| rajathr | 0:34ee385f4d2d | 2817 | /*************** Bit definition for DFSDM_FLTAWCFR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2818 | |
| rajathr | 0:34ee385f4d2d | 2819 | /*************** Bit definition for DFSDM_FLTEXMAX register ******************/ |
| rajathr | 0:34ee385f4d2d | 2820 | |
| rajathr | 0:34ee385f4d2d | 2821 | /*************** Bit definition for DFSDM_FLTEXMIN register ******************/ |
| rajathr | 0:34ee385f4d2d | 2822 | |
| rajathr | 0:34ee385f4d2d | 2823 | /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/ |
| rajathr | 0:34ee385f4d2d | 2824 | |
| rajathr | 0:34ee385f4d2d | 2825 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2826 | /* */ |
| rajathr | 0:34ee385f4d2d | 2827 | /* DMA Controller */ |
| rajathr | 0:34ee385f4d2d | 2828 | /* */ |
| rajathr | 0:34ee385f4d2d | 2829 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2830 | /******************** Bits definition for DMA_SxCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2831 | #define DMA_SxCR_CHSEL_MORT ((uint32_t)0x0E000000) |
| rajathr | 0:34ee385f4d2d | 2832 | #define DMA_SxCR_CHSEL_0_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 2833 | #define DMA_SxCR_CHSEL_1_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 2834 | #define DMA_SxCR_CHSEL_2_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 2835 | #define DMA_SxCR_MBURST_MORT ((uint32_t)0x01800000) |
| rajathr | 0:34ee385f4d2d | 2836 | #define DMA_SxCR_MBURST_0_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 2837 | #define DMA_SxCR_MBURST_1_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 2838 | #define DMA_SxCR_PBURST_MORT ((uint32_t)0x00600000) |
| rajathr | 0:34ee385f4d2d | 2839 | #define DMA_SxCR_PBURST_0_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 2840 | #define DMA_SxCR_PBURST_1_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 2841 | #define DMA_SxCR_ACK_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 2842 | #define DMA_SxCR_CT_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 2843 | #define DMA_SxCR_DBM_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 2844 | #define DMA_SxCR_PL_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 2845 | #define DMA_SxCR_PL_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 2846 | #define DMA_SxCR_PL_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 2847 | #define DMA_SxCR_PINCOS_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 2848 | #define DMA_SxCR_MSIZE_MORT ((uint32_t)0x00006000) |
| rajathr | 0:34ee385f4d2d | 2849 | #define DMA_SxCR_MSIZE_0_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 2850 | #define DMA_SxCR_MSIZE_1_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 2851 | #define DMA_SxCR_PSIZE_MORT ((uint32_t)0x00001800) |
| rajathr | 0:34ee385f4d2d | 2852 | #define DMA_SxCR_PSIZE_0_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 2853 | #define DMA_SxCR_PSIZE_1_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 2854 | #define DMA_SxCR_MINC_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 2855 | #define DMA_SxCR_PINC_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 2856 | #define DMA_SxCR_CIRC_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 2857 | #define DMA_SxCR_DIR_MORT ((uint32_t)0x000000C0) |
| rajathr | 0:34ee385f4d2d | 2858 | #define DMA_SxCR_DIR_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 2859 | #define DMA_SxCR_DIR_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 2860 | #define DMA_SxCR_PFCTRL_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2861 | #define DMA_SxCR_TCIE_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2862 | #define DMA_SxCR_HTIE_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2863 | #define DMA_SxCR_TEIE_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2864 | #define DMA_SxCR_DMEIE_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 2865 | #define DMA_SxCR_EN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2866 | |
| rajathr | 0:34ee385f4d2d | 2867 | /******************** Bits definition for DMA_SxCNDTR register **************/ |
| rajathr | 0:34ee385f4d2d | 2868 | #define DMA_SxNDT_MORT ((uint32_t)0x0000FFFF) |
| rajathr | 0:34ee385f4d2d | 2869 | #define DMA_SxNDT_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2870 | #define DMA_SxNDT_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 2871 | #define DMA_SxNDT_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2872 | #define DMA_SxNDT_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2873 | #define DMA_SxNDT_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2874 | #define DMA_SxNDT_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2875 | #define DMA_SxNDT_6_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 2876 | #define DMA_SxNDT_7_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 2877 | #define DMA_SxNDT_8_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 2878 | #define DMA_SxNDT_9_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 2879 | #define DMA_SxNDT_10_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 2880 | #define DMA_SxNDT_11_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 2881 | #define DMA_SxNDT_12_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 2882 | #define DMA_SxNDT_13_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 2883 | #define DMA_SxNDT_14_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 2884 | #define DMA_SxNDT_15_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 2885 | |
| rajathr | 0:34ee385f4d2d | 2886 | /******************** Bits definition for DMA_SxFCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 2887 | #define DMA_SxFCR_FEIE_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 2888 | #define DMA_SxFCR_FS_MORT ((uint32_t)0x00000038) |
| rajathr | 0:34ee385f4d2d | 2889 | #define DMA_SxFCR_FS_0_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2890 | #define DMA_SxFCR_FS_1_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2891 | #define DMA_SxFCR_FS_2_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2892 | #define DMA_SxFCR_DMDIS_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2893 | #define DMA_SxFCR_FTH_MORT ((uint32_t)0x00000003) |
| rajathr | 0:34ee385f4d2d | 2894 | #define DMA_SxFCR_FTH_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2895 | #define DMA_SxFCR_FTH_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 2896 | |
| rajathr | 0:34ee385f4d2d | 2897 | /******************** Bits definition for DMA_LISR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2898 | #define DMA_LISR_TCIF3_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 2899 | #define DMA_LISR_HTIF3_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 2900 | #define DMA_LISR_TEIF3_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 2901 | #define DMA_LISR_DMEIF3_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 2902 | #define DMA_LISR_FEIF3_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 2903 | #define DMA_LISR_TCIF2_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 2904 | #define DMA_LISR_HTIF2_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 2905 | #define DMA_LISR_TEIF2_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 2906 | #define DMA_LISR_DMEIF2_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 2907 | #define DMA_LISR_FEIF2_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 2908 | #define DMA_LISR_TCIF1_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 2909 | #define DMA_LISR_HTIF1_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 2910 | #define DMA_LISR_TEIF1_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 2911 | #define DMA_LISR_DMEIF1_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 2912 | #define DMA_LISR_FEIF1_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 2913 | #define DMA_LISR_TCIF0_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2914 | #define DMA_LISR_HTIF0_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2915 | #define DMA_LISR_TEIF0_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2916 | #define DMA_LISR_DMEIF0_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2917 | #define DMA_LISR_FEIF0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2918 | |
| rajathr | 0:34ee385f4d2d | 2919 | /******************** Bits definition for DMA_HISR register *****************/ |
| rajathr | 0:34ee385f4d2d | 2920 | #define DMA_HISR_TCIF7_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 2921 | #define DMA_HISR_HTIF7_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 2922 | #define DMA_HISR_TEIF7_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 2923 | #define DMA_HISR_DMEIF7_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 2924 | #define DMA_HISR_FEIF7_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 2925 | #define DMA_HISR_TCIF6_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 2926 | #define DMA_HISR_HTIF6_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 2927 | #define DMA_HISR_TEIF6_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 2928 | #define DMA_HISR_DMEIF6_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 2929 | #define DMA_HISR_FEIF6_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 2930 | #define DMA_HISR_TCIF5_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 2931 | #define DMA_HISR_HTIF5_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 2932 | #define DMA_HISR_TEIF5_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 2933 | #define DMA_HISR_DMEIF5_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 2934 | #define DMA_HISR_FEIF5_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 2935 | #define DMA_HISR_TCIF4_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2936 | #define DMA_HISR_HTIF4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2937 | #define DMA_HISR_TEIF4_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2938 | #define DMA_HISR_DMEIF4_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2939 | #define DMA_HISR_FEIF4_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2940 | |
| rajathr | 0:34ee385f4d2d | 2941 | /******************** Bits definition for DMA_LIFCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 2942 | #define DMA_LIFCR_CTCIF3_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 2943 | #define DMA_LIFCR_CHTIF3_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 2944 | #define DMA_LIFCR_CTEIF3_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 2945 | #define DMA_LIFCR_CDMEIF3_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 2946 | #define DMA_LIFCR_CFEIF3_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 2947 | #define DMA_LIFCR_CTCIF2_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 2948 | #define DMA_LIFCR_CHTIF2_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 2949 | #define DMA_LIFCR_CTEIF2_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 2950 | #define DMA_LIFCR_CDMEIF2_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 2951 | #define DMA_LIFCR_CFEIF2_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 2952 | #define DMA_LIFCR_CTCIF1_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 2953 | #define DMA_LIFCR_CHTIF1_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 2954 | #define DMA_LIFCR_CTEIF1_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 2955 | #define DMA_LIFCR_CDMEIF1_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 2956 | #define DMA_LIFCR_CFEIF1_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 2957 | #define DMA_LIFCR_CTCIF0_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2958 | #define DMA_LIFCR_CHTIF0_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2959 | #define DMA_LIFCR_CTEIF0_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2960 | #define DMA_LIFCR_CDMEIF0_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2961 | #define DMA_LIFCR_CFEIF0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2962 | |
| rajathr | 0:34ee385f4d2d | 2963 | /******************** Bits definition for DMA_HIFCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 2964 | #define DMA_HIFCR_CTCIF7_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 2965 | #define DMA_HIFCR_CHTIF7_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 2966 | #define DMA_HIFCR_CTEIF7_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 2967 | #define DMA_HIFCR_CDMEIF7_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 2968 | #define DMA_HIFCR_CFEIF7_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 2969 | #define DMA_HIFCR_CTCIF6_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 2970 | #define DMA_HIFCR_CHTIF6_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 2971 | #define DMA_HIFCR_CTEIF6_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 2972 | #define DMA_HIFCR_CDMEIF6_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 2973 | #define DMA_HIFCR_CFEIF6_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 2974 | #define DMA_HIFCR_CTCIF5_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 2975 | #define DMA_HIFCR_CHTIF5_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 2976 | #define DMA_HIFCR_CTEIF5_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 2977 | #define DMA_HIFCR_CDMEIF5_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 2978 | #define DMA_HIFCR_CFEIF5_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 2979 | #define DMA_HIFCR_CTCIF4_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 2980 | #define DMA_HIFCR_CHTIF4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 2981 | #define DMA_HIFCR_CTEIF4_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 2982 | #define DMA_HIFCR_CDMEIF4_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 2983 | #define DMA_HIFCR_CFEIF4_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 2984 | |
| rajathr | 0:34ee385f4d2d | 2985 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2986 | /* */ |
| rajathr | 0:34ee385f4d2d | 2987 | /* AHB Master DMA2D_MORT Controller (DMA2D_MORT) */ |
| rajathr | 0:34ee385f4d2d | 2988 | /* */ |
| rajathr | 0:34ee385f4d2d | 2989 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 2990 | |
| rajathr | 0:34ee385f4d2d | 2991 | /******************** Bit definition for DMA2D_CR register ******************/ |
| rajathr | 0:34ee385f4d2d | 2992 | |
| rajathr | 0:34ee385f4d2d | 2993 | #define DMA2D_CR_START_MORT ((uint32_t)0x00000001) /*!< Start transfer */ |
| rajathr | 0:34ee385f4d2d | 2994 | #define DMA2D_CR_SUSP_MORT ((uint32_t)0x00000002) /*!< Suspend transfer */ |
| rajathr | 0:34ee385f4d2d | 2995 | #define DMA2D_CR_ABORT_MORT ((uint32_t)0x00000004) /*!< Abort transfer */ |
| rajathr | 0:34ee385f4d2d | 2996 | #define DMA2D_CR_TEIE_MORT ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 2997 | #define DMA2D_CR_TCIE_MORT ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 2998 | #define DMA2D_CR_TWIE_MORT ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 2999 | #define DMA2D_CR_CAEIE_MORT ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 3000 | #define DMA2D_CR_CTCIE_MORT ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 3001 | #define DMA2D_CR_CEIE_MORT ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 3002 | #define DMA2D_CR_MODE_MORT ((uint32_t)0x00030000) /*!< DMA2D_MORT Mode */ |
| rajathr | 0:34ee385f4d2d | 3003 | |
| rajathr | 0:34ee385f4d2d | 3004 | /******************** Bit definition for DMA2D_ISR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3005 | |
| rajathr | 0:34ee385f4d2d | 3006 | #define DMA2D_ISR_TEIF_MORT ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3007 | #define DMA2D_ISR_TCIF_MORT ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3008 | #define DMA2D_ISR_TWIF_MORT ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3009 | #define DMA2D_ISR_CAEIF_MORT ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3010 | #define DMA2D_ISR_CTCIF_MORT ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3011 | #define DMA2D_ISR_CEIF_MORT ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3012 | |
| rajathr | 0:34ee385f4d2d | 3013 | /******************** Bit definition for DMA2D_IFCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 3014 | |
| rajathr | 0:34ee385f4d2d | 3015 | #define DMA2D_IFCR_CTEIF_MORT ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3016 | #define DMA2D_IFCR_CTCIF_MORT ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3017 | #define DMA2D_IFCR_CTWIF_MORT ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3018 | #define DMA2D_IFCR_CAECIF_MORT ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3019 | #define DMA2D_IFCR_CCTCIF_MORT ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3020 | #define DMA2D_IFCR_CCEIF_MORT ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3021 | |
| rajathr | 0:34ee385f4d2d | 3022 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 3023 | #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF_MORT /*!< Clears Transfer Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3024 | #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF_MORT /*!< Clears Transfer Complete Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3025 | #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF_MORT /*!< Clears Transfer Watermark Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3026 | #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF_MORT /*!< Clears CLUT Access Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3027 | #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF_MORT /*!< Clears CLUT Transfer Complete Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3028 | #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF_MORT /*!< Clears Configuration Error Interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 3029 | |
| rajathr | 0:34ee385f4d2d | 3030 | /******************** Bit definition for DMA2D_FGMAR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3031 | |
| rajathr | 0:34ee385f4d2d | 3032 | #define DMA2D_FGMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| rajathr | 0:34ee385f4d2d | 3033 | |
| rajathr | 0:34ee385f4d2d | 3034 | /******************** Bit definition for DMA2D_FGOR register ****************/ |
| rajathr | 0:34ee385f4d2d | 3035 | |
| rajathr | 0:34ee385f4d2d | 3036 | #define DMA2D_FGOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */ |
| rajathr | 0:34ee385f4d2d | 3037 | |
| rajathr | 0:34ee385f4d2d | 3038 | /******************** Bit definition for DMA2D_BGMAR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3039 | |
| rajathr | 0:34ee385f4d2d | 3040 | #define DMA2D_BGMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| rajathr | 0:34ee385f4d2d | 3041 | |
| rajathr | 0:34ee385f4d2d | 3042 | /******************** Bit definition for DMA2D_BGOR register ****************/ |
| rajathr | 0:34ee385f4d2d | 3043 | |
| rajathr | 0:34ee385f4d2d | 3044 | #define DMA2D_BGOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */ |
| rajathr | 0:34ee385f4d2d | 3045 | |
| rajathr | 0:34ee385f4d2d | 3046 | /******************** Bit definition for DMA2D_FGPFCCR register *************/ |
| rajathr | 0:34ee385f4d2d | 3047 | |
| rajathr | 0:34ee385f4d2d | 3048 | #define DMA2D_FGPFCCR_CM_MORT ((uint32_t)0x0000000F) /*!< Input color mode CM[3:0] */ |
| rajathr | 0:34ee385f4d2d | 3049 | #define DMA2D_FGPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Input color mode CM bit 0 */ |
| rajathr | 0:34ee385f4d2d | 3050 | #define DMA2D_FGPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Input color mode CM bit 1 */ |
| rajathr | 0:34ee385f4d2d | 3051 | #define DMA2D_FGPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Input color mode CM bit 2 */ |
| rajathr | 0:34ee385f4d2d | 3052 | #define DMA2D_FGPFCCR_CM_3_MORT ((uint32_t)0x00000008) /*!< Input color mode CM bit 3 */ |
| rajathr | 0:34ee385f4d2d | 3053 | #define DMA2D_FGPFCCR_CCM_MORT ((uint32_t)0x00000010) /*!< CLUT Color mode */ |
| rajathr | 0:34ee385f4d2d | 3054 | #define DMA2D_FGPFCCR_START_MORT ((uint32_t)0x00000020) /*!< Start */ |
| rajathr | 0:34ee385f4d2d | 3055 | #define DMA2D_FGPFCCR_CS_MORT ((uint32_t)0x0000FF00) /*!< CLUT size */ |
| rajathr | 0:34ee385f4d2d | 3056 | #define DMA2D_FGPFCCR_AM_MORT ((uint32_t)0x00030000) /*!< Alpha mode AM[1:0] */ |
| rajathr | 0:34ee385f4d2d | 3057 | #define DMA2D_FGPFCCR_AM_0_MORT ((uint32_t)0x00010000) /*!< Alpha mode AM bit 0 */ |
| rajathr | 0:34ee385f4d2d | 3058 | #define DMA2D_FGPFCCR_AM_1_MORT ((uint32_t)0x00020000) /*!< Alpha mode AM bit 1 */ |
| rajathr | 0:34ee385f4d2d | 3059 | #define DMA2D_FGPFCCR_ALPHA_MORT ((uint32_t)0xFF000000) /*!< Alpha value */ |
| rajathr | 0:34ee385f4d2d | 3060 | |
| rajathr | 0:34ee385f4d2d | 3061 | /******************** Bit definition for DMA2D_FGCOLR register **************/ |
| rajathr | 0:34ee385f4d2d | 3062 | |
| rajathr | 0:34ee385f4d2d | 3063 | #define DMA2D_FGCOLR_BLUE_MORT ((uint32_t)0x000000FF) /*!< Blue Value */ |
| rajathr | 0:34ee385f4d2d | 3064 | #define DMA2D_FGCOLR_GREEN_MORT ((uint32_t)0x0000FF00) /*!< Green Value */ |
| rajathr | 0:34ee385f4d2d | 3065 | #define DMA2D_FGCOLR_RED_MORT ((uint32_t)0x00FF0000) /*!< Red Value */ |
| rajathr | 0:34ee385f4d2d | 3066 | |
| rajathr | 0:34ee385f4d2d | 3067 | /******************** Bit definition for DMA2D_BGPFCCR register *************/ |
| rajathr | 0:34ee385f4d2d | 3068 | |
| rajathr | 0:34ee385f4d2d | 3069 | #define DMA2D_BGPFCCR_CM_MORT ((uint32_t)0x0000000F) /*!< Input color mode CM[3:0] */ |
| rajathr | 0:34ee385f4d2d | 3070 | #define DMA2D_BGPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Input color mode CM bit 0 */ |
| rajathr | 0:34ee385f4d2d | 3071 | #define DMA2D_BGPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Input color mode CM bit 1 */ |
| rajathr | 0:34ee385f4d2d | 3072 | #define DMA2D_BGPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Input color mode CM bit 2 */ |
| rajathr | 0:34ee385f4d2d | 3073 | #define DMA2D_FGPFCCR_CM_3_MORT ((uint32_t)0x00000008) /*!< Input color mode CM bit 3 */ |
| rajathr | 0:34ee385f4d2d | 3074 | #define DMA2D_BGPFCCR_CCM_MORT ((uint32_t)0x00000010) /*!< CLUT Color mode */ |
| rajathr | 0:34ee385f4d2d | 3075 | #define DMA2D_BGPFCCR_START_MORT ((uint32_t)0x00000020) /*!< Start */ |
| rajathr | 0:34ee385f4d2d | 3076 | #define DMA2D_BGPFCCR_CS_MORT ((uint32_t)0x0000FF00) /*!< CLUT size */ |
| rajathr | 0:34ee385f4d2d | 3077 | #define DMA2D_BGPFCCR_AM_MORT ((uint32_t)0x00030000) /*!< Alpha mode AM[1:0] */ |
| rajathr | 0:34ee385f4d2d | 3078 | #define DMA2D_BGPFCCR_AM_0_MORT ((uint32_t)0x00010000) /*!< Alpha mode AM bit 0 */ |
| rajathr | 0:34ee385f4d2d | 3079 | #define DMA2D_BGPFCCR_AM_1_MORT ((uint32_t)0x00020000) /*!< Alpha mode AM bit 1 */ |
| rajathr | 0:34ee385f4d2d | 3080 | #define DMA2D_BGPFCCR_ALPHA_MORT ((uint32_t)0xFF000000) /*!< Alpha value */ |
| rajathr | 0:34ee385f4d2d | 3081 | |
| rajathr | 0:34ee385f4d2d | 3082 | /******************** Bit definition for DMA2D_BGCOLR register **************/ |
| rajathr | 0:34ee385f4d2d | 3083 | |
| rajathr | 0:34ee385f4d2d | 3084 | #define DMA2D_BGCOLR_BLUE_MORT ((uint32_t)0x000000FF) /*!< Blue Value */ |
| rajathr | 0:34ee385f4d2d | 3085 | #define DMA2D_BGCOLR_GREEN_MORT ((uint32_t)0x0000FF00) /*!< Green Value */ |
| rajathr | 0:34ee385f4d2d | 3086 | #define DMA2D_BGCOLR_RED_MORT ((uint32_t)0x00FF0000) /*!< Red Value */ |
| rajathr | 0:34ee385f4d2d | 3087 | |
| rajathr | 0:34ee385f4d2d | 3088 | /******************** Bit definition for DMA2D_FGCMAR register **************/ |
| rajathr | 0:34ee385f4d2d | 3089 | |
| rajathr | 0:34ee385f4d2d | 3090 | #define DMA2D_FGCMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| rajathr | 0:34ee385f4d2d | 3091 | |
| rajathr | 0:34ee385f4d2d | 3092 | /******************** Bit definition for DMA2D_BGCMAR register **************/ |
| rajathr | 0:34ee385f4d2d | 3093 | |
| rajathr | 0:34ee385f4d2d | 3094 | #define DMA2D_BGCMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| rajathr | 0:34ee385f4d2d | 3095 | |
| rajathr | 0:34ee385f4d2d | 3096 | /******************** Bit definition for DMA2D_OPFCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 3097 | |
| rajathr | 0:34ee385f4d2d | 3098 | #define DMA2D_OPFCCR_CM_MORT ((uint32_t)0x00000007) /*!< Color mode CM[2:0] */ |
| rajathr | 0:34ee385f4d2d | 3099 | #define DMA2D_OPFCCR_CM_0_MORT ((uint32_t)0x00000001) /*!< Color mode CM bit 0 */ |
| rajathr | 0:34ee385f4d2d | 3100 | #define DMA2D_OPFCCR_CM_1_MORT ((uint32_t)0x00000002) /*!< Color mode CM bit 1 */ |
| rajathr | 0:34ee385f4d2d | 3101 | #define DMA2D_OPFCCR_CM_2_MORT ((uint32_t)0x00000004) /*!< Color mode CM bit 2 */ |
| rajathr | 0:34ee385f4d2d | 3102 | |
| rajathr | 0:34ee385f4d2d | 3103 | /******************** Bit definition for DMA2D_OCOLR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3104 | |
| rajathr | 0:34ee385f4d2d | 3105 | /*!<Mode_ARGB8888/RGB888 */ |
| rajathr | 0:34ee385f4d2d | 3106 | |
| rajathr | 0:34ee385f4d2d | 3107 | #define DMA2D_OCOLR_BLUE_1_MORT ((uint32_t)0x000000FF) /*!< BLUE Value */ |
| rajathr | 0:34ee385f4d2d | 3108 | #define DMA2D_OCOLR_GREEN_1_MORT ((uint32_t)0x0000FF00) /*!< GREEN Value */ |
| rajathr | 0:34ee385f4d2d | 3109 | #define DMA2D_OCOLR_RED_1_MORT ((uint32_t)0x00FF0000) /*!< Red Value */ |
| rajathr | 0:34ee385f4d2d | 3110 | #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */ |
| rajathr | 0:34ee385f4d2d | 3111 | |
| rajathr | 0:34ee385f4d2d | 3112 | /*!<Mode_RGB565 */ |
| rajathr | 0:34ee385f4d2d | 3113 | #define DMA2D_OCOLR_BLUE_2_MORT ((uint32_t)0x0000001F) /*!< BLUE Value */ |
| rajathr | 0:34ee385f4d2d | 3114 | #define DMA2D_OCOLR_GREEN_2_MORT ((uint32_t)0x000007E0) /*!< GREEN Value */ |
| rajathr | 0:34ee385f4d2d | 3115 | #define DMA2D_OCOLR_RED_2_MORT ((uint32_t)0x0000F800) /*!< Red Value */ |
| rajathr | 0:34ee385f4d2d | 3116 | |
| rajathr | 0:34ee385f4d2d | 3117 | /*!<Mode_ARGB1555 */ |
| rajathr | 0:34ee385f4d2d | 3118 | #define DMA2D_OCOLR_BLUE_3_MORT ((uint32_t)0x0000001F) /*!< BLUE Value */ |
| rajathr | 0:34ee385f4d2d | 3119 | #define DMA2D_OCOLR_GREEN_3_MORT ((uint32_t)0x000003E0) /*!< GREEN Value */ |
| rajathr | 0:34ee385f4d2d | 3120 | #define DMA2D_OCOLR_RED_3_MORT ((uint32_t)0x00007C00) /*!< Red Value */ |
| rajathr | 0:34ee385f4d2d | 3121 | #define DMA2D_OCOLR_ALPHA_3_MORT ((uint32_t)0x00008000) /*!< Alpha Channel Value */ |
| rajathr | 0:34ee385f4d2d | 3122 | |
| rajathr | 0:34ee385f4d2d | 3123 | /*!<Mode_ARGB4444 */ |
| rajathr | 0:34ee385f4d2d | 3124 | #define DMA2D_OCOLR_BLUE_4_MORT ((uint32_t)0x0000000F) /*!< BLUE Value */ |
| rajathr | 0:34ee385f4d2d | 3125 | #define DMA2D_OCOLR_GREEN_4_MORT ((uint32_t)0x000000F0) /*!< GREEN Value */ |
| rajathr | 0:34ee385f4d2d | 3126 | #define DMA2D_OCOLR_RED_4_MORT ((uint32_t)0x00000F00) /*!< Red Value */ |
| rajathr | 0:34ee385f4d2d | 3127 | #define DMA2D_OCOLR_ALPHA_4_MORT ((uint32_t)0x0000F000) /*!< Alpha Channel Value */ |
| rajathr | 0:34ee385f4d2d | 3128 | |
| rajathr | 0:34ee385f4d2d | 3129 | /******************** Bit definition for DMA2D_OMAR register ****************/ |
| rajathr | 0:34ee385f4d2d | 3130 | |
| rajathr | 0:34ee385f4d2d | 3131 | #define DMA2D_OMAR_MA_MORT ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| rajathr | 0:34ee385f4d2d | 3132 | |
| rajathr | 0:34ee385f4d2d | 3133 | /******************** Bit definition for DMA2D_OOR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3134 | |
| rajathr | 0:34ee385f4d2d | 3135 | #define DMA2D_OOR_LO_MORT ((uint32_t)0x00003FFF) /*!< Line Offset */ |
| rajathr | 0:34ee385f4d2d | 3136 | |
| rajathr | 0:34ee385f4d2d | 3137 | /******************** Bit definition for DMA2D_NLR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3138 | |
| rajathr | 0:34ee385f4d2d | 3139 | #define DMA2D_NLR_NL_MORT ((uint32_t)0x0000FFFF) /*!< Number of Lines */ |
| rajathr | 0:34ee385f4d2d | 3140 | #define DMA2D_NLR_PL_MORT ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */ |
| rajathr | 0:34ee385f4d2d | 3141 | |
| rajathr | 0:34ee385f4d2d | 3142 | /******************** Bit definition for DMA2D_LWR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3143 | |
| rajathr | 0:34ee385f4d2d | 3144 | #define DMA2D_LWR_LW_MORT ((uint32_t)0x0000FFFF) /*!< Line Watermark */ |
| rajathr | 0:34ee385f4d2d | 3145 | |
| rajathr | 0:34ee385f4d2d | 3146 | /******************** Bit definition for DMA2D_AMTCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3147 | |
| rajathr | 0:34ee385f4d2d | 3148 | #define DMA2D_AMTCR_EN_MORT ((uint32_t)0x00000001) /*!< Enable */ |
| rajathr | 0:34ee385f4d2d | 3149 | #define DMA2D_AMTCR_DT_MORT ((uint32_t)0x0000FF00) /*!< Dead Time */ |
| rajathr | 0:34ee385f4d2d | 3150 | |
| rajathr | 0:34ee385f4d2d | 3151 | |
| rajathr | 0:34ee385f4d2d | 3152 | |
| rajathr | 0:34ee385f4d2d | 3153 | /******************** Bit definition for DMA2D_FGCLUT register **************/ |
| rajathr | 0:34ee385f4d2d | 3154 | |
| rajathr | 0:34ee385f4d2d | 3155 | /******************** Bit definition for DMA2D_BGCLUT register **************/ |
| rajathr | 0:34ee385f4d2d | 3156 | |
| rajathr | 0:34ee385f4d2d | 3157 | |
| rajathr | 0:34ee385f4d2d | 3158 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3159 | /* */ |
| rajathr | 0:34ee385f4d2d | 3160 | /* External Interrupt/Event Controller */ |
| rajathr | 0:34ee385f4d2d | 3161 | /* */ |
| rajathr | 0:34ee385f4d2d | 3162 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3163 | /******************* Bit definition for EXTI_IMR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3164 | #define EXTI_IMR_MR0_MORT ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
| rajathr | 0:34ee385f4d2d | 3165 | #define EXTI_IMR_MR1_MORT ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
| rajathr | 0:34ee385f4d2d | 3166 | #define EXTI_IMR_MR2_MORT ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
| rajathr | 0:34ee385f4d2d | 3167 | #define EXTI_IMR_MR3_MORT ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
| rajathr | 0:34ee385f4d2d | 3168 | #define EXTI_IMR_MR4_MORT ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
| rajathr | 0:34ee385f4d2d | 3169 | #define EXTI_IMR_MR5_MORT ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
| rajathr | 0:34ee385f4d2d | 3170 | #define EXTI_IMR_MR6_MORT ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
| rajathr | 0:34ee385f4d2d | 3171 | #define EXTI_IMR_MR7_MORT ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
| rajathr | 0:34ee385f4d2d | 3172 | #define EXTI_IMR_MR8_MORT ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
| rajathr | 0:34ee385f4d2d | 3173 | #define EXTI_IMR_MR9_MORT ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
| rajathr | 0:34ee385f4d2d | 3174 | #define EXTI_IMR_MR10_MORT ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
| rajathr | 0:34ee385f4d2d | 3175 | #define EXTI_IMR_MR11_MORT ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
| rajathr | 0:34ee385f4d2d | 3176 | #define EXTI_IMR_MR12_MORT ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
| rajathr | 0:34ee385f4d2d | 3177 | #define EXTI_IMR_MR13_MORT ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
| rajathr | 0:34ee385f4d2d | 3178 | #define EXTI_IMR_MR14_MORT ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
| rajathr | 0:34ee385f4d2d | 3179 | #define EXTI_IMR_MR15_MORT ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
| rajathr | 0:34ee385f4d2d | 3180 | #define EXTI_IMR_MR16_MORT ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
| rajathr | 0:34ee385f4d2d | 3181 | #define EXTI_IMR_MR17_MORT ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
| rajathr | 0:34ee385f4d2d | 3182 | #define EXTI_IMR_MR18_MORT ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
| rajathr | 0:34ee385f4d2d | 3183 | #define EXTI_IMR_MR19_MORT ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
| rajathr | 0:34ee385f4d2d | 3184 | #define EXTI_IMR_MR23_MORT ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ |
| rajathr | 0:34ee385f4d2d | 3185 | |
| rajathr | 0:34ee385f4d2d | 3186 | /******************* Bit definition for EXTI_EMR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3187 | #define EXTI_EMR_MR0_MORT ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
| rajathr | 0:34ee385f4d2d | 3188 | #define EXTI_EMR_MR1_MORT ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
| rajathr | 0:34ee385f4d2d | 3189 | #define EXTI_EMR_MR2_MORT ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
| rajathr | 0:34ee385f4d2d | 3190 | #define EXTI_EMR_MR3_MORT ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
| rajathr | 0:34ee385f4d2d | 3191 | #define EXTI_EMR_MR4_MORT ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
| rajathr | 0:34ee385f4d2d | 3192 | #define EXTI_EMR_MR5_MORT ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
| rajathr | 0:34ee385f4d2d | 3193 | #define EXTI_EMR_MR6_MORT ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
| rajathr | 0:34ee385f4d2d | 3194 | #define EXTI_EMR_MR7_MORT ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
| rajathr | 0:34ee385f4d2d | 3195 | #define EXTI_EMR_MR8_MORT ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
| rajathr | 0:34ee385f4d2d | 3196 | #define EXTI_EMR_MR9_MORT ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
| rajathr | 0:34ee385f4d2d | 3197 | #define EXTI_EMR_MR10_MORT ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
| rajathr | 0:34ee385f4d2d | 3198 | #define EXTI_EMR_MR11_MORT ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
| rajathr | 0:34ee385f4d2d | 3199 | #define EXTI_EMR_MR12_MORT ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
| rajathr | 0:34ee385f4d2d | 3200 | #define EXTI_EMR_MR13_MORT ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
| rajathr | 0:34ee385f4d2d | 3201 | #define EXTI_EMR_MR14_MORT ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
| rajathr | 0:34ee385f4d2d | 3202 | #define EXTI_EMR_MR15_MORT ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
| rajathr | 0:34ee385f4d2d | 3203 | #define EXTI_EMR_MR16_MORT ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
| rajathr | 0:34ee385f4d2d | 3204 | #define EXTI_EMR_MR17_MORT ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
| rajathr | 0:34ee385f4d2d | 3205 | #define EXTI_EMR_MR18_MORT ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
| rajathr | 0:34ee385f4d2d | 3206 | #define EXTI_EMR_MR19_MORT ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
| rajathr | 0:34ee385f4d2d | 3207 | #define EXTI_EMR_MR23_MORT ((uint32_t)0x00800000) /*!< Event Mask on line 19 */ |
| rajathr | 0:34ee385f4d2d | 3208 | |
| rajathr | 0:34ee385f4d2d | 3209 | /****************** Bit definition for EXTI_RTSR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3210 | #define EXTI_RTSR_TR0_MORT ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
| rajathr | 0:34ee385f4d2d | 3211 | #define EXTI_RTSR_TR1_MORT ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
| rajathr | 0:34ee385f4d2d | 3212 | #define EXTI_RTSR_TR2_MORT ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
| rajathr | 0:34ee385f4d2d | 3213 | #define EXTI_RTSR_TR3_MORT ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
| rajathr | 0:34ee385f4d2d | 3214 | #define EXTI_RTSR_TR4_MORT ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
| rajathr | 0:34ee385f4d2d | 3215 | #define EXTI_RTSR_TR5_MORT ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
| rajathr | 0:34ee385f4d2d | 3216 | #define EXTI_RTSR_TR6_MORT ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
| rajathr | 0:34ee385f4d2d | 3217 | #define EXTI_RTSR_TR7_MORT ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
| rajathr | 0:34ee385f4d2d | 3218 | #define EXTI_RTSR_TR8_MORT ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
| rajathr | 0:34ee385f4d2d | 3219 | #define EXTI_RTSR_TR9_MORT ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
| rajathr | 0:34ee385f4d2d | 3220 | #define EXTI_RTSR_TR10_MORT ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
| rajathr | 0:34ee385f4d2d | 3221 | #define EXTI_RTSR_TR11_MORT ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
| rajathr | 0:34ee385f4d2d | 3222 | #define EXTI_RTSR_TR12_MORT ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
| rajathr | 0:34ee385f4d2d | 3223 | #define EXTI_RTSR_TR13_MORT ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
| rajathr | 0:34ee385f4d2d | 3224 | #define EXTI_RTSR_TR14_MORT ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
| rajathr | 0:34ee385f4d2d | 3225 | #define EXTI_RTSR_TR15_MORT ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
| rajathr | 0:34ee385f4d2d | 3226 | #define EXTI_RTSR_TR16_MORT ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
| rajathr | 0:34ee385f4d2d | 3227 | #define EXTI_RTSR_TR17_MORT ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
| rajathr | 0:34ee385f4d2d | 3228 | #define EXTI_RTSR_TR18_MORT ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
| rajathr | 0:34ee385f4d2d | 3229 | #define EXTI_RTSR_TR19_MORT ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
| rajathr | 0:34ee385f4d2d | 3230 | #define EXTI_RTSR_TR23_MORT ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ |
| rajathr | 0:34ee385f4d2d | 3231 | |
| rajathr | 0:34ee385f4d2d | 3232 | /****************** Bit definition for EXTI_FTSR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3233 | #define EXTI_FTSR_TR0_MORT ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
| rajathr | 0:34ee385f4d2d | 3234 | #define EXTI_FTSR_TR1_MORT ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
| rajathr | 0:34ee385f4d2d | 3235 | #define EXTI_FTSR_TR2_MORT ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
| rajathr | 0:34ee385f4d2d | 3236 | #define EXTI_FTSR_TR3_MORT ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
| rajathr | 0:34ee385f4d2d | 3237 | #define EXTI_FTSR_TR4_MORT ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
| rajathr | 0:34ee385f4d2d | 3238 | #define EXTI_FTSR_TR5_MORT ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
| rajathr | 0:34ee385f4d2d | 3239 | #define EXTI_FTSR_TR6_MORT ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
| rajathr | 0:34ee385f4d2d | 3240 | #define EXTI_FTSR_TR7_MORT ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
| rajathr | 0:34ee385f4d2d | 3241 | #define EXTI_FTSR_TR8_MORT ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
| rajathr | 0:34ee385f4d2d | 3242 | #define EXTI_FTSR_TR9_MORT ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
| rajathr | 0:34ee385f4d2d | 3243 | #define EXTI_FTSR_TR10_MORT ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
| rajathr | 0:34ee385f4d2d | 3244 | #define EXTI_FTSR_TR11_MORT ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
| rajathr | 0:34ee385f4d2d | 3245 | #define EXTI_FTSR_TR12_MORT ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
| rajathr | 0:34ee385f4d2d | 3246 | #define EXTI_FTSR_TR13_MORT ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
| rajathr | 0:34ee385f4d2d | 3247 | #define EXTI_FTSR_TR14_MORT ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
| rajathr | 0:34ee385f4d2d | 3248 | #define EXTI_FTSR_TR15_MORT ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
| rajathr | 0:34ee385f4d2d | 3249 | #define EXTI_FTSR_TR16_MORT ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
| rajathr | 0:34ee385f4d2d | 3250 | #define EXTI_FTSR_TR17_MORT ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
| rajathr | 0:34ee385f4d2d | 3251 | #define EXTI_FTSR_TR18_MORT ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
| rajathr | 0:34ee385f4d2d | 3252 | #define EXTI_FTSR_TR19_MORT ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
| rajathr | 0:34ee385f4d2d | 3253 | #define EXTI_FTSR_TR23_MORT ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ |
| rajathr | 0:34ee385f4d2d | 3254 | |
| rajathr | 0:34ee385f4d2d | 3255 | /****************** Bit definition for EXTI_SWIER register ******************/ |
| rajathr | 0:34ee385f4d2d | 3256 | #define EXTI_SWIER_SWIER0_MORT ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
| rajathr | 0:34ee385f4d2d | 3257 | #define EXTI_SWIER_SWIER1_MORT ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
| rajathr | 0:34ee385f4d2d | 3258 | #define EXTI_SWIER_SWIER2_MORT ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
| rajathr | 0:34ee385f4d2d | 3259 | #define EXTI_SWIER_SWIER3_MORT ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
| rajathr | 0:34ee385f4d2d | 3260 | #define EXTI_SWIER_SWIER4_MORT ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
| rajathr | 0:34ee385f4d2d | 3261 | #define EXTI_SWIER_SWIER5_MORT ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
| rajathr | 0:34ee385f4d2d | 3262 | #define EXTI_SWIER_SWIER6_MORT ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
| rajathr | 0:34ee385f4d2d | 3263 | #define EXTI_SWIER_SWIER7_MORT ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
| rajathr | 0:34ee385f4d2d | 3264 | #define EXTI_SWIER_SWIER8_MORT ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
| rajathr | 0:34ee385f4d2d | 3265 | #define EXTI_SWIER_SWIER9_MORT ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
| rajathr | 0:34ee385f4d2d | 3266 | #define EXTI_SWIER_SWIER10_MORT ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
| rajathr | 0:34ee385f4d2d | 3267 | #define EXTI_SWIER_SWIER11_MORT ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
| rajathr | 0:34ee385f4d2d | 3268 | #define EXTI_SWIER_SWIER12_MORT ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
| rajathr | 0:34ee385f4d2d | 3269 | #define EXTI_SWIER_SWIER13_MORT ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
| rajathr | 0:34ee385f4d2d | 3270 | #define EXTI_SWIER_SWIER14_MORT ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
| rajathr | 0:34ee385f4d2d | 3271 | #define EXTI_SWIER_SWIER15_MORT ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
| rajathr | 0:34ee385f4d2d | 3272 | #define EXTI_SWIER_SWIER16_MORT ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
| rajathr | 0:34ee385f4d2d | 3273 | #define EXTI_SWIER_SWIER17_MORT ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
| rajathr | 0:34ee385f4d2d | 3274 | #define EXTI_SWIER_SWIER18_MORT ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
| rajathr | 0:34ee385f4d2d | 3275 | #define EXTI_SWIER_SWIER19_MORT ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
| rajathr | 0:34ee385f4d2d | 3276 | #define EXTI_SWIER_SWIER23_MORT ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ |
| rajathr | 0:34ee385f4d2d | 3277 | |
| rajathr | 0:34ee385f4d2d | 3278 | /******************* Bit definition for EXTI_PR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3279 | #define EXTI_PR_PR0_MORT ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
| rajathr | 0:34ee385f4d2d | 3280 | #define EXTI_PR_PR1_MORT ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
| rajathr | 0:34ee385f4d2d | 3281 | #define EXTI_PR_PR2_MORT ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
| rajathr | 0:34ee385f4d2d | 3282 | #define EXTI_PR_PR3_MORT ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
| rajathr | 0:34ee385f4d2d | 3283 | #define EXTI_PR_PR4_MORT ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
| rajathr | 0:34ee385f4d2d | 3284 | #define EXTI_PR_PR5_MORT ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
| rajathr | 0:34ee385f4d2d | 3285 | #define EXTI_PR_PR6_MORT ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
| rajathr | 0:34ee385f4d2d | 3286 | #define EXTI_PR_PR7_MORT ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
| rajathr | 0:34ee385f4d2d | 3287 | #define EXTI_PR_PR8_MORT ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
| rajathr | 0:34ee385f4d2d | 3288 | #define EXTI_PR_PR9_MORT ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
| rajathr | 0:34ee385f4d2d | 3289 | #define EXTI_PR_PR10_MORT ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
| rajathr | 0:34ee385f4d2d | 3290 | #define EXTI_PR_PR11_MORT ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
| rajathr | 0:34ee385f4d2d | 3291 | #define EXTI_PR_PR12_MORT ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
| rajathr | 0:34ee385f4d2d | 3292 | #define EXTI_PR_PR13_MORT ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
| rajathr | 0:34ee385f4d2d | 3293 | #define EXTI_PR_PR14_MORT ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
| rajathr | 0:34ee385f4d2d | 3294 | #define EXTI_PR_PR15_MORT ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
| rajathr | 0:34ee385f4d2d | 3295 | #define EXTI_PR_PR16_MORT ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
| rajathr | 0:34ee385f4d2d | 3296 | #define EXTI_PR_PR17_MORT ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
| rajathr | 0:34ee385f4d2d | 3297 | #define EXTI_PR_PR18_MORT ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
| rajathr | 0:34ee385f4d2d | 3298 | #define EXTI_PR_PR19_MORT ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
| rajathr | 0:34ee385f4d2d | 3299 | #define EXTI_PR_PR23_MORT ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ |
| rajathr | 0:34ee385f4d2d | 3300 | |
| rajathr | 0:34ee385f4d2d | 3301 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3302 | /* */ |
| rajathr | 0:34ee385f4d2d | 3303 | /* FLASH_MORT */ |
| rajathr | 0:34ee385f4d2d | 3304 | /* */ |
| rajathr | 0:34ee385f4d2d | 3305 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3306 | /******************* Bits definition for FLASH_ACR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3307 | |
| rajathr | 0:34ee385f4d2d | 3308 | /******************* Bits definition for FLASH_SR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3309 | |
| rajathr | 0:34ee385f4d2d | 3310 | /******************* Bits definition for FLASH_CR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3311 | |
| rajathr | 0:34ee385f4d2d | 3312 | /******************* Bits definition for FLASH_OPTCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3313 | |
| rajathr | 0:34ee385f4d2d | 3314 | /****************** Bits definition for FLASH_OPTCR1 register ***************/ |
| rajathr | 0:34ee385f4d2d | 3315 | |
| rajathr | 0:34ee385f4d2d | 3316 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 3317 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3318 | /* */ |
| rajathr | 0:34ee385f4d2d | 3319 | /* Flexible Static Memory Controller */ |
| rajathr | 0:34ee385f4d2d | 3320 | /* */ |
| rajathr | 0:34ee385f4d2d | 3321 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3322 | /****************** Bit definition for FSMC_BCR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3323 | |
| rajathr | 0:34ee385f4d2d | 3324 | |
| rajathr | 0:34ee385f4d2d | 3325 | /****************** Bit definition for FSMC_BCR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3326 | |
| rajathr | 0:34ee385f4d2d | 3327 | |
| rajathr | 0:34ee385f4d2d | 3328 | /****************** Bit definition for FSMC_BCR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3329 | |
| rajathr | 0:34ee385f4d2d | 3330 | |
| rajathr | 0:34ee385f4d2d | 3331 | /****************** Bit definition for FSMC_BCR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3332 | |
| rajathr | 0:34ee385f4d2d | 3333 | |
| rajathr | 0:34ee385f4d2d | 3334 | /****************** Bit definition for FSMC_BTR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3335 | |
| rajathr | 0:34ee385f4d2d | 3336 | |
| rajathr | 0:34ee385f4d2d | 3337 | /****************** Bit definition for FSMC_BTR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3338 | |
| rajathr | 0:34ee385f4d2d | 3339 | |
| rajathr | 0:34ee385f4d2d | 3340 | /******************* Bit definition for FSMC_BTR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3341 | |
| rajathr | 0:34ee385f4d2d | 3342 | |
| rajathr | 0:34ee385f4d2d | 3343 | |
| rajathr | 0:34ee385f4d2d | 3344 | /****************** Bit definition for FSMC_BTR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3345 | |
| rajathr | 0:34ee385f4d2d | 3346 | |
| rajathr | 0:34ee385f4d2d | 3347 | /****************** Bit definition for FSMC_BWTR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3348 | |
| rajathr | 0:34ee385f4d2d | 3349 | |
| rajathr | 0:34ee385f4d2d | 3350 | /****************** Bit definition for FSMC_BWTR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3351 | |
| rajathr | 0:34ee385f4d2d | 3352 | |
| rajathr | 0:34ee385f4d2d | 3353 | /****************** Bit definition for FSMC_BWTR3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3354 | |
| rajathr | 0:34ee385f4d2d | 3355 | |
| rajathr | 0:34ee385f4d2d | 3356 | /****************** Bit definition for FSMC_BWTR4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3357 | |
| rajathr | 0:34ee385f4d2d | 3358 | |
| rajathr | 0:34ee385f4d2d | 3359 | /****************** Bit definition for FSMC_PCR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3360 | |
| rajathr | 0:34ee385f4d2d | 3361 | |
| rajathr | 0:34ee385f4d2d | 3362 | /****************** Bit definition for FSMC_PCR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3363 | |
| rajathr | 0:34ee385f4d2d | 3364 | |
| rajathr | 0:34ee385f4d2d | 3365 | /****************** Bit definition for FSMC_PCR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3366 | |
| rajathr | 0:34ee385f4d2d | 3367 | |
| rajathr | 0:34ee385f4d2d | 3368 | /******************* Bit definition for FSMC_SR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3369 | |
| rajathr | 0:34ee385f4d2d | 3370 | |
| rajathr | 0:34ee385f4d2d | 3371 | /******************* Bit definition for FSMC_SR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3372 | |
| rajathr | 0:34ee385f4d2d | 3373 | |
| rajathr | 0:34ee385f4d2d | 3374 | /******************* Bit definition for FSMC_SR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3375 | |
| rajathr | 0:34ee385f4d2d | 3376 | /****************** Bit definition for FSMC_PMEM2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3377 | |
| rajathr | 0:34ee385f4d2d | 3378 | |
| rajathr | 0:34ee385f4d2d | 3379 | /****************** Bit definition for FSMC_PMEM3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3380 | |
| rajathr | 0:34ee385f4d2d | 3381 | |
| rajathr | 0:34ee385f4d2d | 3382 | /****************** Bit definition for FSMC_PMEM4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3383 | |
| rajathr | 0:34ee385f4d2d | 3384 | |
| rajathr | 0:34ee385f4d2d | 3385 | /****************** Bit definition for FSMC_PATT2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3386 | |
| rajathr | 0:34ee385f4d2d | 3387 | |
| rajathr | 0:34ee385f4d2d | 3388 | /****************** Bit definition for FSMC_PATT3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3389 | |
| rajathr | 0:34ee385f4d2d | 3390 | |
| rajathr | 0:34ee385f4d2d | 3391 | /****************** Bit definition for FSMC_PATT4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3392 | |
| rajathr | 0:34ee385f4d2d | 3393 | /****************** Bit definition for FSMC_PIO4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3394 | |
| rajathr | 0:34ee385f4d2d | 3395 | |
| rajathr | 0:34ee385f4d2d | 3396 | /****************** Bit definition for FSMC_ECCR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3397 | |
| rajathr | 0:34ee385f4d2d | 3398 | |
| rajathr | 0:34ee385f4d2d | 3399 | /****************** Bit definition for FSMC_ECCR3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3400 | |
| rajathr | 0:34ee385f4d2d | 3401 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 3402 | |
| rajathr | 0:34ee385f4d2d | 3403 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 3404 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3405 | /* */ |
| rajathr | 0:34ee385f4d2d | 3406 | /* Flexible Memory Controller */ |
| rajathr | 0:34ee385f4d2d | 3407 | /* */ |
| rajathr | 0:34ee385f4d2d | 3408 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3409 | /****************** Bit definition for FMC_BCR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3410 | |
| rajathr | 0:34ee385f4d2d | 3411 | /****************** Bit definition for FMC_BCR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3412 | |
| rajathr | 0:34ee385f4d2d | 3413 | /****************** Bit definition for FMC_BCR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3414 | |
| rajathr | 0:34ee385f4d2d | 3415 | /****************** Bit definition for FMC_BCR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3416 | |
| rajathr | 0:34ee385f4d2d | 3417 | /****************** Bit definition for FMC_BTR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3418 | |
| rajathr | 0:34ee385f4d2d | 3419 | |
| rajathr | 0:34ee385f4d2d | 3420 | /****************** Bit definition for FMC_BTR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3421 | |
| rajathr | 0:34ee385f4d2d | 3422 | |
| rajathr | 0:34ee385f4d2d | 3423 | /******************* Bit definition for FMC_BTR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3424 | |
| rajathr | 0:34ee385f4d2d | 3425 | /****************** Bit definition for FMC_BTR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3426 | |
| rajathr | 0:34ee385f4d2d | 3427 | |
| rajathr | 0:34ee385f4d2d | 3428 | /****************** Bit definition for FMC_BWTR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3429 | |
| rajathr | 0:34ee385f4d2d | 3430 | /****************** Bit definition for FMC_BWTR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3431 | |
| rajathr | 0:34ee385f4d2d | 3432 | /****************** Bit definition for FMC_BWTR3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3433 | |
| rajathr | 0:34ee385f4d2d | 3434 | /****************** Bit definition for FMC_BWTR4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3435 | |
| rajathr | 0:34ee385f4d2d | 3436 | /****************** Bit definition for FMC_PCR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3437 | |
| rajathr | 0:34ee385f4d2d | 3438 | /****************** Bit definition for FMC_PCR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3439 | |
| rajathr | 0:34ee385f4d2d | 3440 | /****************** Bit definition for FMC_PCR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3441 | |
| rajathr | 0:34ee385f4d2d | 3442 | /******************* Bit definition for FMC_SR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3443 | |
| rajathr | 0:34ee385f4d2d | 3444 | /******************* Bit definition for FMC_SR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3445 | |
| rajathr | 0:34ee385f4d2d | 3446 | /******************* Bit definition for FMC_SR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3447 | |
| rajathr | 0:34ee385f4d2d | 3448 | /****************** Bit definition for FMC_PMEM2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3449 | |
| rajathr | 0:34ee385f4d2d | 3450 | |
| rajathr | 0:34ee385f4d2d | 3451 | /****************** Bit definition for FMC_PMEM3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3452 | |
| rajathr | 0:34ee385f4d2d | 3453 | /****************** Bit definition for FMC_PMEM4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3454 | |
| rajathr | 0:34ee385f4d2d | 3455 | /****************** Bit definition for FMC_PATT2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3456 | |
| rajathr | 0:34ee385f4d2d | 3457 | /****************** Bit definition for FMC_PATT3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3458 | |
| rajathr | 0:34ee385f4d2d | 3459 | /****************** Bit definition for FMC_PATT4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3460 | |
| rajathr | 0:34ee385f4d2d | 3461 | /****************** Bit definition for FMC_PIO4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3462 | |
| rajathr | 0:34ee385f4d2d | 3463 | /****************** Bit definition for FMC_ECCR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3464 | |
| rajathr | 0:34ee385f4d2d | 3465 | /****************** Bit definition for FMC_ECCR3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3466 | |
| rajathr | 0:34ee385f4d2d | 3467 | /****************** Bit definition for FMC_SDCR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3468 | |
| rajathr | 0:34ee385f4d2d | 3469 | /****************** Bit definition for FMC_SDCR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3470 | |
| rajathr | 0:34ee385f4d2d | 3471 | /****************** Bit definition for FMC_SDTR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3472 | |
| rajathr | 0:34ee385f4d2d | 3473 | /****************** Bit definition for FMC_SDTR2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3474 | |
| rajathr | 0:34ee385f4d2d | 3475 | /****************** Bit definition for FMC_SDCMR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3476 | |
| rajathr | 0:34ee385f4d2d | 3477 | /****************** Bit definition for FMC_SDRTR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3478 | |
| rajathr | 0:34ee385f4d2d | 3479 | /****************** Bit definition for FMC_SDSR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3480 | |
| rajathr | 0:34ee385f4d2d | 3481 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 3482 | |
| rajathr | 0:34ee385f4d2d | 3483 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3484 | /* */ |
| rajathr | 0:34ee385f4d2d | 3485 | /* General Purpose I/O */ |
| rajathr | 0:34ee385f4d2d | 3486 | /* */ |
| rajathr | 0:34ee385f4d2d | 3487 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3488 | /****************** Bits definition for GPIO_MODER register *****************/ |
| rajathr | 0:34ee385f4d2d | 3489 | #define GPIO_MODER_MODER0_MORT ((uint32_t)0x00000003) |
| rajathr | 0:34ee385f4d2d | 3490 | #define GPIO_MODER_MODER0_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3491 | #define GPIO_MODER_MODER0_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3492 | |
| rajathr | 0:34ee385f4d2d | 3493 | #define GPIO_MODER_MODER1_MORT ((uint32_t)0x0000000C) |
| rajathr | 0:34ee385f4d2d | 3494 | #define GPIO_MODER_MODER1_0_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3495 | #define GPIO_MODER_MODER1_1_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3496 | |
| rajathr | 0:34ee385f4d2d | 3497 | #define GPIO_MODER_MODER2_MORT ((uint32_t)0x00000030) |
| rajathr | 0:34ee385f4d2d | 3498 | #define GPIO_MODER_MODER2_0_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3499 | #define GPIO_MODER_MODER2_1_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3500 | |
| rajathr | 0:34ee385f4d2d | 3501 | #define GPIO_MODER_MODER3_MORT ((uint32_t)0x000000C0) |
| rajathr | 0:34ee385f4d2d | 3502 | #define GPIO_MODER_MODER3_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3503 | #define GPIO_MODER_MODER3_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3504 | |
| rajathr | 0:34ee385f4d2d | 3505 | #define GPIO_MODER_MODER4_MORT ((uint32_t)0x00000300) |
| rajathr | 0:34ee385f4d2d | 3506 | #define GPIO_MODER_MODER4_0_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3507 | #define GPIO_MODER_MODER4_1_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3508 | |
| rajathr | 0:34ee385f4d2d | 3509 | #define GPIO_MODER_MODER5_MORT ((uint32_t)0x00000C00) |
| rajathr | 0:34ee385f4d2d | 3510 | #define GPIO_MODER_MODER5_0_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3511 | #define GPIO_MODER_MODER5_1_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3512 | |
| rajathr | 0:34ee385f4d2d | 3513 | #define GPIO_MODER_MODER6_MORT ((uint32_t)0x00003000) |
| rajathr | 0:34ee385f4d2d | 3514 | #define GPIO_MODER_MODER6_0_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3515 | #define GPIO_MODER_MODER6_1_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3516 | |
| rajathr | 0:34ee385f4d2d | 3517 | #define GPIO_MODER_MODER7_MORT ((uint32_t)0x0000C000) |
| rajathr | 0:34ee385f4d2d | 3518 | #define GPIO_MODER_MODER7_0_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3519 | #define GPIO_MODER_MODER7_1_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3520 | |
| rajathr | 0:34ee385f4d2d | 3521 | #define GPIO_MODER_MODER8_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 3522 | #define GPIO_MODER_MODER8_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 3523 | #define GPIO_MODER_MODER8_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 3524 | |
| rajathr | 0:34ee385f4d2d | 3525 | #define GPIO_MODER_MODER9_MORT ((uint32_t)0x000C0000) |
| rajathr | 0:34ee385f4d2d | 3526 | #define GPIO_MODER_MODER9_0_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 3527 | #define GPIO_MODER_MODER9_1_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 3528 | |
| rajathr | 0:34ee385f4d2d | 3529 | #define GPIO_MODER_MODER10_MORT ((uint32_t)0x00300000) |
| rajathr | 0:34ee385f4d2d | 3530 | #define GPIO_MODER_MODER10_0_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 3531 | #define GPIO_MODER_MODER10_1_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 3532 | |
| rajathr | 0:34ee385f4d2d | 3533 | #define GPIO_MODER_MODER11_MORT ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 3534 | #define GPIO_MODER_MODER11_0_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 3535 | #define GPIO_MODER_MODER11_1_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 3536 | |
| rajathr | 0:34ee385f4d2d | 3537 | #define GPIO_MODER_MODER12_MORT ((uint32_t)0x03000000) |
| rajathr | 0:34ee385f4d2d | 3538 | #define GPIO_MODER_MODER12_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 3539 | #define GPIO_MODER_MODER12_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 3540 | |
| rajathr | 0:34ee385f4d2d | 3541 | #define GPIO_MODER_MODER13_MORT ((uint32_t)0x0C000000) |
| rajathr | 0:34ee385f4d2d | 3542 | #define GPIO_MODER_MODER13_0_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 3543 | #define GPIO_MODER_MODER13_1_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 3544 | |
| rajathr | 0:34ee385f4d2d | 3545 | #define GPIO_MODER_MODER14_MORT ((uint32_t)0x30000000) |
| rajathr | 0:34ee385f4d2d | 3546 | #define GPIO_MODER_MODER14_0_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 3547 | #define GPIO_MODER_MODER14_1_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 3548 | |
| rajathr | 0:34ee385f4d2d | 3549 | #define GPIO_MODER_MODER15_MORT ((uint32_t)0xC0000000) |
| rajathr | 0:34ee385f4d2d | 3550 | #define GPIO_MODER_MODER15_0_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 3551 | #define GPIO_MODER_MODER15_1_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 3552 | |
| rajathr | 0:34ee385f4d2d | 3553 | /****************** Bits definition for GPIO_OTYPER register ****************/ |
| rajathr | 0:34ee385f4d2d | 3554 | #define GPIO_OTYPER_OT_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3555 | #define GPIO_OTYPER_OT_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3556 | #define GPIO_OTYPER_OT_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3557 | #define GPIO_OTYPER_OT_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3558 | #define GPIO_OTYPER_OT_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3559 | #define GPIO_OTYPER_OT_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3560 | #define GPIO_OTYPER_OT_6_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3561 | #define GPIO_OTYPER_OT_7_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3562 | #define GPIO_OTYPER_OT_8_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3563 | #define GPIO_OTYPER_OT_9_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3564 | #define GPIO_OTYPER_OT_10_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3565 | #define GPIO_OTYPER_OT_11_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3566 | #define GPIO_OTYPER_OT_12_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3567 | #define GPIO_OTYPER_OT_13_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3568 | #define GPIO_OTYPER_OT_14_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3569 | #define GPIO_OTYPER_OT_15_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3570 | |
| rajathr | 0:34ee385f4d2d | 3571 | /****************** Bits definition for GPIO_OSPEEDR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3572 | #define GPIO_OSPEEDER_OSPEEDR0_MORT ((uint32_t)0x00000003) |
| rajathr | 0:34ee385f4d2d | 3573 | #define GPIO_OSPEEDER_OSPEEDR0_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3574 | #define GPIO_OSPEEDER_OSPEEDR0_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3575 | |
| rajathr | 0:34ee385f4d2d | 3576 | #define GPIO_OSPEEDER_OSPEEDR1_MORT ((uint32_t)0x0000000C) |
| rajathr | 0:34ee385f4d2d | 3577 | #define GPIO_OSPEEDER_OSPEEDR1_0_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3578 | #define GPIO_OSPEEDER_OSPEEDR1_1_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3579 | |
| rajathr | 0:34ee385f4d2d | 3580 | #define GPIO_OSPEEDER_OSPEEDR2_MORT ((uint32_t)0x00000030) |
| rajathr | 0:34ee385f4d2d | 3581 | #define GPIO_OSPEEDER_OSPEEDR2_0_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3582 | #define GPIO_OSPEEDER_OSPEEDR2_1_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3583 | |
| rajathr | 0:34ee385f4d2d | 3584 | #define GPIO_OSPEEDER_OSPEEDR3_MORT ((uint32_t)0x000000C0) |
| rajathr | 0:34ee385f4d2d | 3585 | #define GPIO_OSPEEDER_OSPEEDR3_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3586 | #define GPIO_OSPEEDER_OSPEEDR3_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3587 | |
| rajathr | 0:34ee385f4d2d | 3588 | #define GPIO_OSPEEDER_OSPEEDR4_MORT ((uint32_t)0x00000300) |
| rajathr | 0:34ee385f4d2d | 3589 | #define GPIO_OSPEEDER_OSPEEDR4_0_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3590 | #define GPIO_OSPEEDER_OSPEEDR4_1_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3591 | |
| rajathr | 0:34ee385f4d2d | 3592 | #define GPIO_OSPEEDER_OSPEEDR5_MORT ((uint32_t)0x00000C00) |
| rajathr | 0:34ee385f4d2d | 3593 | #define GPIO_OSPEEDER_OSPEEDR5_0_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3594 | #define GPIO_OSPEEDER_OSPEEDR5_1_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3595 | |
| rajathr | 0:34ee385f4d2d | 3596 | #define GPIO_OSPEEDER_OSPEEDR6_MORT ((uint32_t)0x00003000) |
| rajathr | 0:34ee385f4d2d | 3597 | #define GPIO_OSPEEDER_OSPEEDR6_0_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3598 | #define GPIO_OSPEEDER_OSPEEDR6_1_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3599 | |
| rajathr | 0:34ee385f4d2d | 3600 | #define GPIO_OSPEEDER_OSPEEDR7_MORT ((uint32_t)0x0000C000) |
| rajathr | 0:34ee385f4d2d | 3601 | #define GPIO_OSPEEDER_OSPEEDR7_0_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3602 | #define GPIO_OSPEEDER_OSPEEDR7_1_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3603 | |
| rajathr | 0:34ee385f4d2d | 3604 | #define GPIO_OSPEEDER_OSPEEDR8_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 3605 | #define GPIO_OSPEEDER_OSPEEDR8_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 3606 | #define GPIO_OSPEEDER_OSPEEDR8_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 3607 | |
| rajathr | 0:34ee385f4d2d | 3608 | #define GPIO_OSPEEDER_OSPEEDR9_MORT ((uint32_t)0x000C0000) |
| rajathr | 0:34ee385f4d2d | 3609 | #define GPIO_OSPEEDER_OSPEEDR9_0_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 3610 | #define GPIO_OSPEEDER_OSPEEDR9_1_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 3611 | |
| rajathr | 0:34ee385f4d2d | 3612 | #define GPIO_OSPEEDER_OSPEEDR10_MORT ((uint32_t)0x00300000) |
| rajathr | 0:34ee385f4d2d | 3613 | #define GPIO_OSPEEDER_OSPEEDR10_0_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 3614 | #define GPIO_OSPEEDER_OSPEEDR10_1_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 3615 | |
| rajathr | 0:34ee385f4d2d | 3616 | #define GPIO_OSPEEDER_OSPEEDR11_MORT ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 3617 | #define GPIO_OSPEEDER_OSPEEDR11_0_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 3618 | #define GPIO_OSPEEDER_OSPEEDR11_1_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 3619 | |
| rajathr | 0:34ee385f4d2d | 3620 | #define GPIO_OSPEEDER_OSPEEDR12_MORT ((uint32_t)0x03000000) |
| rajathr | 0:34ee385f4d2d | 3621 | #define GPIO_OSPEEDER_OSPEEDR12_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 3622 | #define GPIO_OSPEEDER_OSPEEDR12_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 3623 | |
| rajathr | 0:34ee385f4d2d | 3624 | #define GPIO_OSPEEDER_OSPEEDR13_MORT ((uint32_t)0x0C000000) |
| rajathr | 0:34ee385f4d2d | 3625 | #define GPIO_OSPEEDER_OSPEEDR13_0_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 3626 | #define GPIO_OSPEEDER_OSPEEDR13_1_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 3627 | |
| rajathr | 0:34ee385f4d2d | 3628 | #define GPIO_OSPEEDER_OSPEEDR14_MORT ((uint32_t)0x30000000) |
| rajathr | 0:34ee385f4d2d | 3629 | #define GPIO_OSPEEDER_OSPEEDR14_0_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 3630 | #define GPIO_OSPEEDER_OSPEEDR14_1_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 3631 | |
| rajathr | 0:34ee385f4d2d | 3632 | #define GPIO_OSPEEDER_OSPEEDR15_MORT ((uint32_t)0xC0000000) |
| rajathr | 0:34ee385f4d2d | 3633 | #define GPIO_OSPEEDER_OSPEEDR15_0_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 3634 | #define GPIO_OSPEEDER_OSPEEDR15_1_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 3635 | |
| rajathr | 0:34ee385f4d2d | 3636 | /****************** Bits definition for GPIO_PUPDR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3637 | #define GPIO_PUPDR_PUPDR0_MORT ((uint32_t)0x00000003) |
| rajathr | 0:34ee385f4d2d | 3638 | #define GPIO_PUPDR_PUPDR0_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3639 | #define GPIO_PUPDR_PUPDR0_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3640 | |
| rajathr | 0:34ee385f4d2d | 3641 | #define GPIO_PUPDR_PUPDR1_MORT ((uint32_t)0x0000000C) |
| rajathr | 0:34ee385f4d2d | 3642 | #define GPIO_PUPDR_PUPDR1_0_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3643 | #define GPIO_PUPDR_PUPDR1_1_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3644 | |
| rajathr | 0:34ee385f4d2d | 3645 | #define GPIO_PUPDR_PUPDR2_MORT ((uint32_t)0x00000030) |
| rajathr | 0:34ee385f4d2d | 3646 | #define GPIO_PUPDR_PUPDR2_0_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3647 | #define GPIO_PUPDR_PUPDR2_1_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3648 | |
| rajathr | 0:34ee385f4d2d | 3649 | #define GPIO_PUPDR_PUPDR3_MORT ((uint32_t)0x000000C0) |
| rajathr | 0:34ee385f4d2d | 3650 | #define GPIO_PUPDR_PUPDR3_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3651 | #define GPIO_PUPDR_PUPDR3_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3652 | |
| rajathr | 0:34ee385f4d2d | 3653 | #define GPIO_PUPDR_PUPDR4_MORT ((uint32_t)0x00000300) |
| rajathr | 0:34ee385f4d2d | 3654 | #define GPIO_PUPDR_PUPDR4_0_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3655 | #define GPIO_PUPDR_PUPDR4_1_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3656 | |
| rajathr | 0:34ee385f4d2d | 3657 | #define GPIO_PUPDR_PUPDR5_MORT ((uint32_t)0x00000C00) |
| rajathr | 0:34ee385f4d2d | 3658 | #define GPIO_PUPDR_PUPDR5_0_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3659 | #define GPIO_PUPDR_PUPDR5_1_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3660 | |
| rajathr | 0:34ee385f4d2d | 3661 | #define GPIO_PUPDR_PUPDR6_MORT ((uint32_t)0x00003000) |
| rajathr | 0:34ee385f4d2d | 3662 | #define GPIO_PUPDR_PUPDR6_0_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3663 | #define GPIO_PUPDR_PUPDR6_1_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3664 | |
| rajathr | 0:34ee385f4d2d | 3665 | #define GPIO_PUPDR_PUPDR7_MORT ((uint32_t)0x0000C000) |
| rajathr | 0:34ee385f4d2d | 3666 | #define GPIO_PUPDR_PUPDR7_0_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3667 | #define GPIO_PUPDR_PUPDR7_1_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3668 | |
| rajathr | 0:34ee385f4d2d | 3669 | #define GPIO_PUPDR_PUPDR8_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 3670 | #define GPIO_PUPDR_PUPDR8_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 3671 | #define GPIO_PUPDR_PUPDR8_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 3672 | |
| rajathr | 0:34ee385f4d2d | 3673 | #define GPIO_PUPDR_PUPDR9_MORT ((uint32_t)0x000C0000) |
| rajathr | 0:34ee385f4d2d | 3674 | #define GPIO_PUPDR_PUPDR9_0_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 3675 | #define GPIO_PUPDR_PUPDR9_1_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 3676 | |
| rajathr | 0:34ee385f4d2d | 3677 | #define GPIO_PUPDR_PUPDR10_MORT ((uint32_t)0x00300000) |
| rajathr | 0:34ee385f4d2d | 3678 | #define GPIO_PUPDR_PUPDR10_0_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 3679 | #define GPIO_PUPDR_PUPDR10_1_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 3680 | |
| rajathr | 0:34ee385f4d2d | 3681 | #define GPIO_PUPDR_PUPDR11_MORT ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 3682 | #define GPIO_PUPDR_PUPDR11_0_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 3683 | #define GPIO_PUPDR_PUPDR11_1_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 3684 | |
| rajathr | 0:34ee385f4d2d | 3685 | #define GPIO_PUPDR_PUPDR12_MORT ((uint32_t)0x03000000) |
| rajathr | 0:34ee385f4d2d | 3686 | #define GPIO_PUPDR_PUPDR12_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 3687 | #define GPIO_PUPDR_PUPDR12_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 3688 | |
| rajathr | 0:34ee385f4d2d | 3689 | #define GPIO_PUPDR_PUPDR13_MORT ((uint32_t)0x0C000000) |
| rajathr | 0:34ee385f4d2d | 3690 | #define GPIO_PUPDR_PUPDR13_0_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 3691 | #define GPIO_PUPDR_PUPDR13_1_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 3692 | |
| rajathr | 0:34ee385f4d2d | 3693 | #define GPIO_PUPDR_PUPDR14_MORT ((uint32_t)0x30000000) |
| rajathr | 0:34ee385f4d2d | 3694 | #define GPIO_PUPDR_PUPDR14_0_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 3695 | #define GPIO_PUPDR_PUPDR14_1_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 3696 | |
| rajathr | 0:34ee385f4d2d | 3697 | #define GPIO_PUPDR_PUPDR15_MORT ((uint32_t)0xC0000000) |
| rajathr | 0:34ee385f4d2d | 3698 | #define GPIO_PUPDR_PUPDR15_0_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 3699 | #define GPIO_PUPDR_PUPDR15_1_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 3700 | |
| rajathr | 0:34ee385f4d2d | 3701 | /****************** Bits definition for GPIO_IDR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3702 | #define GPIO_IDR_IDR_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3703 | #define GPIO_IDR_IDR_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3704 | #define GPIO_IDR_IDR_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3705 | #define GPIO_IDR_IDR_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3706 | #define GPIO_IDR_IDR_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3707 | #define GPIO_IDR_IDR_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3708 | #define GPIO_IDR_IDR_6_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3709 | #define GPIO_IDR_IDR_7_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3710 | #define GPIO_IDR_IDR_8_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3711 | #define GPIO_IDR_IDR_9_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3712 | #define GPIO_IDR_IDR_10_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3713 | #define GPIO_IDR_IDR_11_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3714 | #define GPIO_IDR_IDR_12_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3715 | #define GPIO_IDR_IDR_13_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3716 | #define GPIO_IDR_IDR_14_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3717 | #define GPIO_IDR_IDR_15_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3718 | /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ |
| rajathr | 0:34ee385f4d2d | 3719 | #define GPIO_OTYPER_IDR_0_MORT GPIO_IDR_IDR_0_MORT |
| rajathr | 0:34ee385f4d2d | 3720 | #define GPIO_OTYPER_IDR_1_MORT GPIO_IDR_IDR_1_MORT |
| rajathr | 0:34ee385f4d2d | 3721 | #define GPIO_OTYPER_IDR_2_MORT GPIO_IDR_IDR_2_MORT |
| rajathr | 0:34ee385f4d2d | 3722 | #define GPIO_OTYPER_IDR_3_MORT GPIO_IDR_IDR_3_MORT |
| rajathr | 0:34ee385f4d2d | 3723 | #define GPIO_OTYPER_IDR_4_MORT GPIO_IDR_IDR_4_MORT |
| rajathr | 0:34ee385f4d2d | 3724 | #define GPIO_OTYPER_IDR_5_MORT GPIO_IDR_IDR_5_MORT |
| rajathr | 0:34ee385f4d2d | 3725 | #define GPIO_OTYPER_IDR_6_MORT GPIO_IDR_IDR_6_MORT |
| rajathr | 0:34ee385f4d2d | 3726 | #define GPIO_OTYPER_IDR_7_MORT GPIO_IDR_IDR_7_MORT |
| rajathr | 0:34ee385f4d2d | 3727 | #define GPIO_OTYPER_IDR_8_MORT GPIO_IDR_IDR_8_MORT |
| rajathr | 0:34ee385f4d2d | 3728 | #define GPIO_OTYPER_IDR_9_MORT GPIO_IDR_IDR_9_MORT |
| rajathr | 0:34ee385f4d2d | 3729 | #define GPIO_OTYPER_IDR_10_MORT GPIO_IDR_IDR_10_MORT |
| rajathr | 0:34ee385f4d2d | 3730 | #define GPIO_OTYPER_IDR_11_MORT GPIO_IDR_IDR_11_MORT |
| rajathr | 0:34ee385f4d2d | 3731 | #define GPIO_OTYPER_IDR_12_MORT GPIO_IDR_IDR_12_MORT |
| rajathr | 0:34ee385f4d2d | 3732 | #define GPIO_OTYPER_IDR_13_MORT GPIO_IDR_IDR_13_MORT |
| rajathr | 0:34ee385f4d2d | 3733 | #define GPIO_OTYPER_IDR_14_MORT GPIO_IDR_IDR_14_MORT |
| rajathr | 0:34ee385f4d2d | 3734 | #define GPIO_OTYPER_IDR_15_MORT GPIO_IDR_IDR_15_MORT |
| rajathr | 0:34ee385f4d2d | 3735 | |
| rajathr | 0:34ee385f4d2d | 3736 | /****************** Bits definition for GPIO_ODR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3737 | #define GPIO_ODR_ODR_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3738 | #define GPIO_ODR_ODR_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3739 | #define GPIO_ODR_ODR_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3740 | #define GPIO_ODR_ODR_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3741 | #define GPIO_ODR_ODR_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3742 | #define GPIO_ODR_ODR_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3743 | #define GPIO_ODR_ODR_6_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3744 | #define GPIO_ODR_ODR_7_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3745 | #define GPIO_ODR_ODR_8_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3746 | #define GPIO_ODR_ODR_9_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3747 | #define GPIO_ODR_ODR_10_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3748 | #define GPIO_ODR_ODR_11_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3749 | #define GPIO_ODR_ODR_12_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3750 | #define GPIO_ODR_ODR_13_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3751 | #define GPIO_ODR_ODR_14_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3752 | #define GPIO_ODR_ODR_15_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3753 | /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ |
| rajathr | 0:34ee385f4d2d | 3754 | #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0_MORT |
| rajathr | 0:34ee385f4d2d | 3755 | #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1_MORT |
| rajathr | 0:34ee385f4d2d | 3756 | #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2_MORT |
| rajathr | 0:34ee385f4d2d | 3757 | #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3_MORT |
| rajathr | 0:34ee385f4d2d | 3758 | #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4_MORT |
| rajathr | 0:34ee385f4d2d | 3759 | #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5_MORT |
| rajathr | 0:34ee385f4d2d | 3760 | #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6_MORT |
| rajathr | 0:34ee385f4d2d | 3761 | #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7_MORT |
| rajathr | 0:34ee385f4d2d | 3762 | #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8_MORT |
| rajathr | 0:34ee385f4d2d | 3763 | #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9_MORT |
| rajathr | 0:34ee385f4d2d | 3764 | #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10_MORT |
| rajathr | 0:34ee385f4d2d | 3765 | #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11_MORT |
| rajathr | 0:34ee385f4d2d | 3766 | #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12_MORT |
| rajathr | 0:34ee385f4d2d | 3767 | #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13_MORT |
| rajathr | 0:34ee385f4d2d | 3768 | #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14_MORT |
| rajathr | 0:34ee385f4d2d | 3769 | #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15_MORT |
| rajathr | 0:34ee385f4d2d | 3770 | |
| rajathr | 0:34ee385f4d2d | 3771 | /****************** Bits definition for GPIO_BSRR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3772 | #define GPIO_BSRR_BS_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 3773 | #define GPIO_BSRR_BS_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 3774 | #define GPIO_BSRR_BS_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 3775 | #define GPIO_BSRR_BS_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 3776 | #define GPIO_BSRR_BS_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 3777 | #define GPIO_BSRR_BS_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 3778 | #define GPIO_BSRR_BS_6_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 3779 | #define GPIO_BSRR_BS_7_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 3780 | #define GPIO_BSRR_BS_8_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 3781 | #define GPIO_BSRR_BS_9_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 3782 | #define GPIO_BSRR_BS_10_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 3783 | #define GPIO_BSRR_BS_11_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 3784 | #define GPIO_BSRR_BS_12_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 3785 | #define GPIO_BSRR_BS_13_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 3786 | #define GPIO_BSRR_BS_14_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 3787 | #define GPIO_BSRR_BS_15_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 3788 | #define GPIO_BSRR_BR_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 3789 | #define GPIO_BSRR_BR_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 3790 | #define GPIO_BSRR_BR_2_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 3791 | #define GPIO_BSRR_BR_3_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 3792 | #define GPIO_BSRR_BR_4_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 3793 | #define GPIO_BSRR_BR_5_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 3794 | #define GPIO_BSRR_BR_6_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 3795 | #define GPIO_BSRR_BR_7_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 3796 | #define GPIO_BSRR_BR_8_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 3797 | #define GPIO_BSRR_BR_9_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 3798 | #define GPIO_BSRR_BR_10_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 3799 | #define GPIO_BSRR_BR_11_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 3800 | #define GPIO_BSRR_BR_12_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 3801 | #define GPIO_BSRR_BR_13_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 3802 | #define GPIO_BSRR_BR_14_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 3803 | #define GPIO_BSRR_BR_15_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 3804 | |
| rajathr | 0:34ee385f4d2d | 3805 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3806 | /* */ |
| rajathr | 0:34ee385f4d2d | 3807 | /* HASH_MORT */ |
| rajathr | 0:34ee385f4d2d | 3808 | /* */ |
| rajathr | 0:34ee385f4d2d | 3809 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3810 | /****************** Bits definition for HASH_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3811 | |
| rajathr | 0:34ee385f4d2d | 3812 | |
| rajathr | 0:34ee385f4d2d | 3813 | /****************** Bits definition for HASH_STR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3814 | |
| rajathr | 0:34ee385f4d2d | 3815 | |
| rajathr | 0:34ee385f4d2d | 3816 | /****************** Bits definition for HASH_IMR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3817 | |
| rajathr | 0:34ee385f4d2d | 3818 | |
| rajathr | 0:34ee385f4d2d | 3819 | /****************** Bits definition for HASH_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3820 | |
| rajathr | 0:34ee385f4d2d | 3821 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3822 | /* */ |
| rajathr | 0:34ee385f4d2d | 3823 | /* Inter-integrated Circuit Interface */ |
| rajathr | 0:34ee385f4d2d | 3824 | /* */ |
| rajathr | 0:34ee385f4d2d | 3825 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3826 | /******************* Bit definition for I2C_CR1 register ********************/ |
| rajathr | 0:34ee385f4d2d | 3827 | |
| rajathr | 0:34ee385f4d2d | 3828 | /******************* Bit definition for I2C_CR2 register ********************/ |
| rajathr | 0:34ee385f4d2d | 3829 | |
| rajathr | 0:34ee385f4d2d | 3830 | /******************* Bit definition for I2C_OAR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3831 | |
| rajathr | 0:34ee385f4d2d | 3832 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3833 | |
| rajathr | 0:34ee385f4d2d | 3834 | /******************** Bit definition for I2C_DR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3835 | |
| rajathr | 0:34ee385f4d2d | 3836 | /******************* Bit definition for I2C_SR1 register ********************/ |
| rajathr | 0:34ee385f4d2d | 3837 | |
| rajathr | 0:34ee385f4d2d | 3838 | /******************* Bit definition for I2C_SR2 register ********************/ |
| rajathr | 0:34ee385f4d2d | 3839 | |
| rajathr | 0:34ee385f4d2d | 3840 | /******************* Bit definition for I2C_CCR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3841 | |
| rajathr | 0:34ee385f4d2d | 3842 | /****************** Bit definition for I2C_TRISE register *******************/ |
| rajathr | 0:34ee385f4d2d | 3843 | |
| rajathr | 0:34ee385f4d2d | 3844 | /****************** Bit definition for I2C_FLTR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3845 | |
| rajathr | 0:34ee385f4d2d | 3846 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 3847 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3848 | /* */ |
| rajathr | 0:34ee385f4d2d | 3849 | /* Fast-mode Plus Inter-integrated circuit (FMPI2C) */ |
| rajathr | 0:34ee385f4d2d | 3850 | /* */ |
| rajathr | 0:34ee385f4d2d | 3851 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3852 | /******************* Bit definition for I2C_CR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3853 | |
| rajathr | 0:34ee385f4d2d | 3854 | /****************** Bit definition for I2C_CR2 register ********************/ |
| rajathr | 0:34ee385f4d2d | 3855 | |
| rajathr | 0:34ee385f4d2d | 3856 | /******************* Bit definition for I2C_OAR1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 3857 | |
| rajathr | 0:34ee385f4d2d | 3858 | /******************* Bit definition for I2C_OAR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 3859 | |
| rajathr | 0:34ee385f4d2d | 3860 | /******************* Bit definition for I2C_TIMINGR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3861 | |
| rajathr | 0:34ee385f4d2d | 3862 | /******************* Bit definition for I2C_TIMEOUTR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3863 | |
| rajathr | 0:34ee385f4d2d | 3864 | /****************** Bit definition for I2C_ISR register *********************/ |
| rajathr | 0:34ee385f4d2d | 3865 | |
| rajathr | 0:34ee385f4d2d | 3866 | /****************** Bit definition for I2C_ICR register *********************/ |
| rajathr | 0:34ee385f4d2d | 3867 | |
| rajathr | 0:34ee385f4d2d | 3868 | /****************** Bit definition for I2C_PECR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3869 | |
| rajathr | 0:34ee385f4d2d | 3870 | /****************** Bit definition for I2C_RXDR register *********************/ |
| rajathr | 0:34ee385f4d2d | 3871 | |
| rajathr | 0:34ee385f4d2d | 3872 | /****************** Bit definition for I2C_TXDR register *********************/ |
| rajathr | 0:34ee385f4d2d | 3873 | |
| rajathr | 0:34ee385f4d2d | 3874 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 3875 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3876 | /* */ |
| rajathr | 0:34ee385f4d2d | 3877 | /* Independent WATCHDOG */ |
| rajathr | 0:34ee385f4d2d | 3878 | /* */ |
| rajathr | 0:34ee385f4d2d | 3879 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3880 | /******************* Bit definition for IWDG_KR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3881 | |
| rajathr | 0:34ee385f4d2d | 3882 | /******************* Bit definition for IWDG_PR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3883 | |
| rajathr | 0:34ee385f4d2d | 3884 | /******************* Bit definition for IWDG_RLR register *******************/ |
| rajathr | 0:34ee385f4d2d | 3885 | |
| rajathr | 0:34ee385f4d2d | 3886 | /******************* Bit definition for IWDG_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 3887 | |
| rajathr | 0:34ee385f4d2d | 3888 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3889 | /* */ |
| rajathr | 0:34ee385f4d2d | 3890 | /* LCD-TFT Display Controller (LTDC_MORT) */ |
| rajathr | 0:34ee385f4d2d | 3891 | /* */ |
| rajathr | 0:34ee385f4d2d | 3892 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3893 | |
| rajathr | 0:34ee385f4d2d | 3894 | /******************** Bit definition for LTDC_SSCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3895 | |
| rajathr | 0:34ee385f4d2d | 3896 | |
| rajathr | 0:34ee385f4d2d | 3897 | /******************** Bit definition for LTDC_BPCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3898 | |
| rajathr | 0:34ee385f4d2d | 3899 | |
| rajathr | 0:34ee385f4d2d | 3900 | /******************** Bit definition for LTDC_AWCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3901 | |
| rajathr | 0:34ee385f4d2d | 3902 | |
| rajathr | 0:34ee385f4d2d | 3903 | /******************** Bit definition for LTDC_TWCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3904 | |
| rajathr | 0:34ee385f4d2d | 3905 | |
| rajathr | 0:34ee385f4d2d | 3906 | /******************** Bit definition for LTDC_GCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3907 | |
| rajathr | 0:34ee385f4d2d | 3908 | |
| rajathr | 0:34ee385f4d2d | 3909 | /* Legacy defines */ |
| rajathr | 0:34ee385f4d2d | 3910 | |
| rajathr | 0:34ee385f4d2d | 3911 | /******************** Bit definition for LTDC_SRCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3912 | |
| rajathr | 0:34ee385f4d2d | 3913 | |
| rajathr | 0:34ee385f4d2d | 3914 | /******************** Bit definition for LTDC_BCCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3915 | |
| rajathr | 0:34ee385f4d2d | 3916 | |
| rajathr | 0:34ee385f4d2d | 3917 | /******************** Bit definition for LTDC_IER register ******************/ |
| rajathr | 0:34ee385f4d2d | 3918 | |
| rajathr | 0:34ee385f4d2d | 3919 | |
| rajathr | 0:34ee385f4d2d | 3920 | /******************** Bit definition for LTDC_ISR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3921 | |
| rajathr | 0:34ee385f4d2d | 3922 | |
| rajathr | 0:34ee385f4d2d | 3923 | /******************** Bit definition for LTDC_ICR register ******************/ |
| rajathr | 0:34ee385f4d2d | 3924 | |
| rajathr | 0:34ee385f4d2d | 3925 | |
| rajathr | 0:34ee385f4d2d | 3926 | /******************** Bit definition for LTDC_LIPCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 3927 | |
| rajathr | 0:34ee385f4d2d | 3928 | |
| rajathr | 0:34ee385f4d2d | 3929 | /******************** Bit definition for LTDC_CPSR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3930 | |
| rajathr | 0:34ee385f4d2d | 3931 | |
| rajathr | 0:34ee385f4d2d | 3932 | /******************** Bit definition for LTDC_CDSR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3933 | |
| rajathr | 0:34ee385f4d2d | 3934 | |
| rajathr | 0:34ee385f4d2d | 3935 | /******************** Bit definition for LTDC_LxCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3936 | |
| rajathr | 0:34ee385f4d2d | 3937 | |
| rajathr | 0:34ee385f4d2d | 3938 | /******************** Bit definition for LTDC_LxWHPCR register **************/ |
| rajathr | 0:34ee385f4d2d | 3939 | |
| rajathr | 0:34ee385f4d2d | 3940 | |
| rajathr | 0:34ee385f4d2d | 3941 | /******************** Bit definition for LTDC_LxWVPCR register **************/ |
| rajathr | 0:34ee385f4d2d | 3942 | |
| rajathr | 0:34ee385f4d2d | 3943 | |
| rajathr | 0:34ee385f4d2d | 3944 | /******************** Bit definition for LTDC_LxCKCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3945 | |
| rajathr | 0:34ee385f4d2d | 3946 | |
| rajathr | 0:34ee385f4d2d | 3947 | /******************** Bit definition for LTDC_LxPFCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3948 | |
| rajathr | 0:34ee385f4d2d | 3949 | |
| rajathr | 0:34ee385f4d2d | 3950 | /******************** Bit definition for LTDC_LxCACR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3951 | |
| rajathr | 0:34ee385f4d2d | 3952 | |
| rajathr | 0:34ee385f4d2d | 3953 | /******************** Bit definition for LTDC_LxDCCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3954 | |
| rajathr | 0:34ee385f4d2d | 3955 | |
| rajathr | 0:34ee385f4d2d | 3956 | /******************** Bit definition for LTDC_LxBFCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3957 | |
| rajathr | 0:34ee385f4d2d | 3958 | |
| rajathr | 0:34ee385f4d2d | 3959 | /******************** Bit definition for LTDC_LxCFBAR register **************/ |
| rajathr | 0:34ee385f4d2d | 3960 | |
| rajathr | 0:34ee385f4d2d | 3961 | |
| rajathr | 0:34ee385f4d2d | 3962 | /******************** Bit definition for LTDC_LxCFBLR register **************/ |
| rajathr | 0:34ee385f4d2d | 3963 | |
| rajathr | 0:34ee385f4d2d | 3964 | |
| rajathr | 0:34ee385f4d2d | 3965 | /******************** Bit definition for LTDC_LxCFBLNR register *************/ |
| rajathr | 0:34ee385f4d2d | 3966 | |
| rajathr | 0:34ee385f4d2d | 3967 | |
| rajathr | 0:34ee385f4d2d | 3968 | /******************** Bit definition for LTDC_LxCLUTWR register *************/ |
| rajathr | 0:34ee385f4d2d | 3969 | |
| rajathr | 0:34ee385f4d2d | 3970 | |
| rajathr | 0:34ee385f4d2d | 3971 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 3972 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3973 | /* */ |
| rajathr | 0:34ee385f4d2d | 3974 | /* DSI_MORT */ |
| rajathr | 0:34ee385f4d2d | 3975 | /* */ |
| rajathr | 0:34ee385f4d2d | 3976 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 3977 | /******************* Bit definition for DSI_VR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3978 | |
| rajathr | 0:34ee385f4d2d | 3979 | |
| rajathr | 0:34ee385f4d2d | 3980 | /******************* Bit definition for DSI_CR register *****************/ |
| rajathr | 0:34ee385f4d2d | 3981 | |
| rajathr | 0:34ee385f4d2d | 3982 | |
| rajathr | 0:34ee385f4d2d | 3983 | /******************* Bit definition for DSI_CCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 3984 | |
| rajathr | 0:34ee385f4d2d | 3985 | |
| rajathr | 0:34ee385f4d2d | 3986 | /******************* Bit definition for DSI_LVCIDR register *************/ |
| rajathr | 0:34ee385f4d2d | 3987 | |
| rajathr | 0:34ee385f4d2d | 3988 | |
| rajathr | 0:34ee385f4d2d | 3989 | /******************* Bit definition for DSI_LCOLCR register *************/ |
| rajathr | 0:34ee385f4d2d | 3990 | |
| rajathr | 0:34ee385f4d2d | 3991 | |
| rajathr | 0:34ee385f4d2d | 3992 | |
| rajathr | 0:34ee385f4d2d | 3993 | /******************* Bit definition for DSI_LPCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 3994 | |
| rajathr | 0:34ee385f4d2d | 3995 | |
| rajathr | 0:34ee385f4d2d | 3996 | /******************* Bit definition for DSI_LPMCR register **************/ |
| rajathr | 0:34ee385f4d2d | 3997 | |
| rajathr | 0:34ee385f4d2d | 3998 | |
| rajathr | 0:34ee385f4d2d | 3999 | /******************* Bit definition for DSI_PCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 4000 | |
| rajathr | 0:34ee385f4d2d | 4001 | |
| rajathr | 0:34ee385f4d2d | 4002 | /******************* Bit definition for DSI_GVCIDR register *************/ |
| rajathr | 0:34ee385f4d2d | 4003 | |
| rajathr | 0:34ee385f4d2d | 4004 | |
| rajathr | 0:34ee385f4d2d | 4005 | /******************* Bit definition for DSI_MCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 4006 | |
| rajathr | 0:34ee385f4d2d | 4007 | |
| rajathr | 0:34ee385f4d2d | 4008 | /******************* Bit definition for DSI_VMCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4009 | |
| rajathr | 0:34ee385f4d2d | 4010 | |
| rajathr | 0:34ee385f4d2d | 4011 | /******************* Bit definition for DSI_VPCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4012 | |
| rajathr | 0:34ee385f4d2d | 4013 | |
| rajathr | 0:34ee385f4d2d | 4014 | /******************* Bit definition for DSI_VCCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4015 | |
| rajathr | 0:34ee385f4d2d | 4016 | |
| rajathr | 0:34ee385f4d2d | 4017 | /******************* Bit definition for DSI_VNPCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4018 | |
| rajathr | 0:34ee385f4d2d | 4019 | |
| rajathr | 0:34ee385f4d2d | 4020 | /******************* Bit definition for DSI_VHSACR register *************/ |
| rajathr | 0:34ee385f4d2d | 4021 | |
| rajathr | 0:34ee385f4d2d | 4022 | |
| rajathr | 0:34ee385f4d2d | 4023 | /******************* Bit definition for DSI_VHBPCR register *************/ |
| rajathr | 0:34ee385f4d2d | 4024 | |
| rajathr | 0:34ee385f4d2d | 4025 | |
| rajathr | 0:34ee385f4d2d | 4026 | /******************* Bit definition for DSI_VLCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4027 | |
| rajathr | 0:34ee385f4d2d | 4028 | /******************* Bit definition for DSI_VVSACR register *************/ |
| rajathr | 0:34ee385f4d2d | 4029 | |
| rajathr | 0:34ee385f4d2d | 4030 | |
| rajathr | 0:34ee385f4d2d | 4031 | /******************* Bit definition for DSI_VVBPCR register *************/ |
| rajathr | 0:34ee385f4d2d | 4032 | |
| rajathr | 0:34ee385f4d2d | 4033 | |
| rajathr | 0:34ee385f4d2d | 4034 | /******************* Bit definition for DSI_VVFPCR register *************/ |
| rajathr | 0:34ee385f4d2d | 4035 | |
| rajathr | 0:34ee385f4d2d | 4036 | |
| rajathr | 0:34ee385f4d2d | 4037 | /******************* Bit definition for DSI_VVACR register **************/ |
| rajathr | 0:34ee385f4d2d | 4038 | |
| rajathr | 0:34ee385f4d2d | 4039 | |
| rajathr | 0:34ee385f4d2d | 4040 | /******************* Bit definition for DSI_LCCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4041 | |
| rajathr | 0:34ee385f4d2d | 4042 | |
| rajathr | 0:34ee385f4d2d | 4043 | /******************* Bit definition for DSI_CMCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4044 | |
| rajathr | 0:34ee385f4d2d | 4045 | |
| rajathr | 0:34ee385f4d2d | 4046 | /******************* Bit definition for DSI_GHCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4047 | |
| rajathr | 0:34ee385f4d2d | 4048 | |
| rajathr | 0:34ee385f4d2d | 4049 | /******************* Bit definition for DSI_GPDR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4050 | |
| rajathr | 0:34ee385f4d2d | 4051 | |
| rajathr | 0:34ee385f4d2d | 4052 | /******************* Bit definition for DSI_GPSR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4053 | |
| rajathr | 0:34ee385f4d2d | 4054 | /******************* Bit definition for DSI_TCCR0 register **************/ |
| rajathr | 0:34ee385f4d2d | 4055 | |
| rajathr | 0:34ee385f4d2d | 4056 | |
| rajathr | 0:34ee385f4d2d | 4057 | /******************* Bit definition for DSI_TCCR1 register **************/ |
| rajathr | 0:34ee385f4d2d | 4058 | |
| rajathr | 0:34ee385f4d2d | 4059 | |
| rajathr | 0:34ee385f4d2d | 4060 | /******************* Bit definition for DSI_TCCR2 register **************/ |
| rajathr | 0:34ee385f4d2d | 4061 | |
| rajathr | 0:34ee385f4d2d | 4062 | |
| rajathr | 0:34ee385f4d2d | 4063 | /******************* Bit definition for DSI_TCCR3 register **************/ |
| rajathr | 0:34ee385f4d2d | 4064 | |
| rajathr | 0:34ee385f4d2d | 4065 | |
| rajathr | 0:34ee385f4d2d | 4066 | /******************* Bit definition for DSI_TCCR4 register **************/ |
| rajathr | 0:34ee385f4d2d | 4067 | |
| rajathr | 0:34ee385f4d2d | 4068 | |
| rajathr | 0:34ee385f4d2d | 4069 | /******************* Bit definition for DSI_TCCR5 register **************/ |
| rajathr | 0:34ee385f4d2d | 4070 | |
| rajathr | 0:34ee385f4d2d | 4071 | |
| rajathr | 0:34ee385f4d2d | 4072 | /******************* Bit definition for DSI_TDCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4073 | |
| rajathr | 0:34ee385f4d2d | 4074 | |
| rajathr | 0:34ee385f4d2d | 4075 | /******************* Bit definition for DSI_CLCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4076 | |
| rajathr | 0:34ee385f4d2d | 4077 | |
| rajathr | 0:34ee385f4d2d | 4078 | /******************* Bit definition for DSI_CLTCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4079 | |
| rajathr | 0:34ee385f4d2d | 4080 | |
| rajathr | 0:34ee385f4d2d | 4081 | /******************* Bit definition for DSI_DLTCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4082 | |
| rajathr | 0:34ee385f4d2d | 4083 | |
| rajathr | 0:34ee385f4d2d | 4084 | /******************* Bit definition for DSI_PCTLR register **************/ |
| rajathr | 0:34ee385f4d2d | 4085 | |
| rajathr | 0:34ee385f4d2d | 4086 | |
| rajathr | 0:34ee385f4d2d | 4087 | /******************* Bit definition for DSI_PCONFR register *************/ |
| rajathr | 0:34ee385f4d2d | 4088 | |
| rajathr | 0:34ee385f4d2d | 4089 | |
| rajathr | 0:34ee385f4d2d | 4090 | /******************* Bit definition for DSI_PUCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4091 | |
| rajathr | 0:34ee385f4d2d | 4092 | |
| rajathr | 0:34ee385f4d2d | 4093 | /******************* Bit definition for DSI_PTTCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4094 | |
| rajathr | 0:34ee385f4d2d | 4095 | |
| rajathr | 0:34ee385f4d2d | 4096 | /******************* Bit definition for DSI_PSR register ****************/ |
| rajathr | 0:34ee385f4d2d | 4097 | |
| rajathr | 0:34ee385f4d2d | 4098 | |
| rajathr | 0:34ee385f4d2d | 4099 | /******************* Bit definition for DSI_ISR0 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4100 | |
| rajathr | 0:34ee385f4d2d | 4101 | /******************* Bit definition for DSI_ISR1 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4102 | |
| rajathr | 0:34ee385f4d2d | 4103 | |
| rajathr | 0:34ee385f4d2d | 4104 | /******************* Bit definition for DSI_IER0 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4105 | |
| rajathr | 0:34ee385f4d2d | 4106 | |
| rajathr | 0:34ee385f4d2d | 4107 | /******************* Bit definition for DSI_IER1 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4108 | |
| rajathr | 0:34ee385f4d2d | 4109 | |
| rajathr | 0:34ee385f4d2d | 4110 | /******************* Bit definition for DSI_FIR0 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4111 | |
| rajathr | 0:34ee385f4d2d | 4112 | |
| rajathr | 0:34ee385f4d2d | 4113 | /******************* Bit definition for DSI_FIR1 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4114 | |
| rajathr | 0:34ee385f4d2d | 4115 | |
| rajathr | 0:34ee385f4d2d | 4116 | /******************* Bit definition for DSI_VSCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4117 | |
| rajathr | 0:34ee385f4d2d | 4118 | |
| rajathr | 0:34ee385f4d2d | 4119 | /******************* Bit definition for DSI_LCVCIDR register ************/ |
| rajathr | 0:34ee385f4d2d | 4120 | |
| rajathr | 0:34ee385f4d2d | 4121 | |
| rajathr | 0:34ee385f4d2d | 4122 | /******************* Bit definition for DSI_LCCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4123 | |
| rajathr | 0:34ee385f4d2d | 4124 | |
| rajathr | 0:34ee385f4d2d | 4125 | /******************* Bit definition for DSI_LPMCCR register *************/ |
| rajathr | 0:34ee385f4d2d | 4126 | |
| rajathr | 0:34ee385f4d2d | 4127 | /******************* Bit definition for DSI_VMCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4128 | |
| rajathr | 0:34ee385f4d2d | 4129 | |
| rajathr | 0:34ee385f4d2d | 4130 | /******************* Bit definition for DSI_VPCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4131 | |
| rajathr | 0:34ee385f4d2d | 4132 | |
| rajathr | 0:34ee385f4d2d | 4133 | /******************* Bit definition for DSI_VCCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4134 | |
| rajathr | 0:34ee385f4d2d | 4135 | |
| rajathr | 0:34ee385f4d2d | 4136 | /******************* Bit definition for DSI_VNPCCR register *************/ |
| rajathr | 0:34ee385f4d2d | 4137 | |
| rajathr | 0:34ee385f4d2d | 4138 | |
| rajathr | 0:34ee385f4d2d | 4139 | /******************* Bit definition for DSI_VHSACCR register ************/ |
| rajathr | 0:34ee385f4d2d | 4140 | |
| rajathr | 0:34ee385f4d2d | 4141 | |
| rajathr | 0:34ee385f4d2d | 4142 | /******************* Bit definition for DSI_VHBPCCR register ************/ |
| rajathr | 0:34ee385f4d2d | 4143 | |
| rajathr | 0:34ee385f4d2d | 4144 | |
| rajathr | 0:34ee385f4d2d | 4145 | /******************* Bit definition for DSI_VLCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4146 | |
| rajathr | 0:34ee385f4d2d | 4147 | |
| rajathr | 0:34ee385f4d2d | 4148 | /******************* Bit definition for DSI_VVSACCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4149 | |
| rajathr | 0:34ee385f4d2d | 4150 | |
| rajathr | 0:34ee385f4d2d | 4151 | /******************* Bit definition for DSI_VVBPCCR register ************/ |
| rajathr | 0:34ee385f4d2d | 4152 | |
| rajathr | 0:34ee385f4d2d | 4153 | |
| rajathr | 0:34ee385f4d2d | 4154 | /******************* Bit definition for DSI_VVFPCCR register ************/ |
| rajathr | 0:34ee385f4d2d | 4155 | |
| rajathr | 0:34ee385f4d2d | 4156 | |
| rajathr | 0:34ee385f4d2d | 4157 | /******************* Bit definition for DSI_VVACCR register *************/ |
| rajathr | 0:34ee385f4d2d | 4158 | |
| rajathr | 0:34ee385f4d2d | 4159 | |
| rajathr | 0:34ee385f4d2d | 4160 | /******************* Bit definition for DSI_TDCCR register **************/ |
| rajathr | 0:34ee385f4d2d | 4161 | |
| rajathr | 0:34ee385f4d2d | 4162 | |
| rajathr | 0:34ee385f4d2d | 4163 | /******************* Bit definition for DSI_WCFGR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4164 | |
| rajathr | 0:34ee385f4d2d | 4165 | /******************* Bit definition for DSI_WCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 4166 | |
| rajathr | 0:34ee385f4d2d | 4167 | |
| rajathr | 0:34ee385f4d2d | 4168 | /******************* Bit definition for DSI_WIER register ****************/ |
| rajathr | 0:34ee385f4d2d | 4169 | |
| rajathr | 0:34ee385f4d2d | 4170 | |
| rajathr | 0:34ee385f4d2d | 4171 | /******************* Bit definition for DSI_WISR register ****************/ |
| rajathr | 0:34ee385f4d2d | 4172 | |
| rajathr | 0:34ee385f4d2d | 4173 | /******************* Bit definition for DSI_WIFCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4174 | |
| rajathr | 0:34ee385f4d2d | 4175 | /******************* Bit definition for DSI_WPCR0 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4176 | |
| rajathr | 0:34ee385f4d2d | 4177 | /******************* Bit definition for DSI_WPCR1 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4178 | |
| rajathr | 0:34ee385f4d2d | 4179 | |
| rajathr | 0:34ee385f4d2d | 4180 | /******************* Bit definition for DSI_WPCR2 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4181 | |
| rajathr | 0:34ee385f4d2d | 4182 | |
| rajathr | 0:34ee385f4d2d | 4183 | /******************* Bit definition for DSI_WPCR3 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4184 | |
| rajathr | 0:34ee385f4d2d | 4185 | |
| rajathr | 0:34ee385f4d2d | 4186 | /******************* Bit definition for DSI_WPCR4 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4187 | |
| rajathr | 0:34ee385f4d2d | 4188 | |
| rajathr | 0:34ee385f4d2d | 4189 | /******************* Bit definition for DSI_WRPCR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4190 | |
| rajathr | 0:34ee385f4d2d | 4191 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4192 | |
| rajathr | 0:34ee385f4d2d | 4193 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4194 | /* */ |
| rajathr | 0:34ee385f4d2d | 4195 | /* Power Control */ |
| rajathr | 0:34ee385f4d2d | 4196 | /* */ |
| rajathr | 0:34ee385f4d2d | 4197 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4198 | /******************** Bit definition for PWR_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 4199 | |
| rajathr | 0:34ee385f4d2d | 4200 | /*!< PVD level configuration */ |
| rajathr | 0:34ee385f4d2d | 4201 | |
| rajathr | 0:34ee385f4d2d | 4202 | /* Legacy define */ |
| rajathr | 0:34ee385f4d2d | 4203 | |
| rajathr | 0:34ee385f4d2d | 4204 | /******************* Bit definition for PWR_CSR register ********************/ |
| rajathr | 0:34ee385f4d2d | 4205 | |
| rajathr | 0:34ee385f4d2d | 4206 | /* Legacy define */ |
| rajathr | 0:34ee385f4d2d | 4207 | |
| rajathr | 0:34ee385f4d2d | 4208 | |
| rajathr | 0:34ee385f4d2d | 4209 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4210 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4211 | /* */ |
| rajathr | 0:34ee385f4d2d | 4212 | /* QUADSPI_MORT */ |
| rajathr | 0:34ee385f4d2d | 4213 | /* */ |
| rajathr | 0:34ee385f4d2d | 4214 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4215 | /***************** Bit definition for QUADSPI_CR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4216 | |
| rajathr | 0:34ee385f4d2d | 4217 | /***************** Bit definition for QUADSPI_DCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4218 | |
| rajathr | 0:34ee385f4d2d | 4219 | /****************** Bit definition for QUADSPI_SR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4220 | |
| rajathr | 0:34ee385f4d2d | 4221 | /****************** Bit definition for QUADSPI_FCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4222 | |
| rajathr | 0:34ee385f4d2d | 4223 | /****************** Bit definition for QUADSPI_DLR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4224 | |
| rajathr | 0:34ee385f4d2d | 4225 | /****************** Bit definition for QUADSPI_CCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4226 | |
| rajathr | 0:34ee385f4d2d | 4227 | /****************** Bit definition for QUADSPI_AR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4228 | |
| rajathr | 0:34ee385f4d2d | 4229 | /****************** Bit definition for QUADSPI_ABR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4230 | |
| rajathr | 0:34ee385f4d2d | 4231 | /****************** Bit definition for QUADSPI_DR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4232 | |
| rajathr | 0:34ee385f4d2d | 4233 | /****************** Bit definition for QUADSPI_PSMKR register ****************/ |
| rajathr | 0:34ee385f4d2d | 4234 | |
| rajathr | 0:34ee385f4d2d | 4235 | /****************** Bit definition for QUADSPI_PSMAR register ****************/ |
| rajathr | 0:34ee385f4d2d | 4236 | |
| rajathr | 0:34ee385f4d2d | 4237 | /****************** Bit definition for QUADSPI_PIR register *****************/ |
| rajathr | 0:34ee385f4d2d | 4238 | |
| rajathr | 0:34ee385f4d2d | 4239 | /****************** Bit definition for QUADSPI_LPTR register *****************/ |
| rajathr | 0:34ee385f4d2d | 4240 | |
| rajathr | 0:34ee385f4d2d | 4241 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4242 | |
| rajathr | 0:34ee385f4d2d | 4243 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4244 | /* */ |
| rajathr | 0:34ee385f4d2d | 4245 | /* Reset and Clock Control */ |
| rajathr | 0:34ee385f4d2d | 4246 | /* */ |
| rajathr | 0:34ee385f4d2d | 4247 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4248 | /******************** Bit definition for RCC_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 4249 | #define RCC_CR_HSION_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4250 | #define RCC_CR_HSIRDY_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4251 | |
| rajathr | 0:34ee385f4d2d | 4252 | #define RCC_CR_HSITRIM_MORT ((uint32_t)0x000000F8) |
| rajathr | 0:34ee385f4d2d | 4253 | #define RCC_CR_HSITRIM_0_MORT ((uint32_t)0x00000008)/*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4254 | #define RCC_CR_HSITRIM_1_MORT ((uint32_t)0x00000010)/*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4255 | #define RCC_CR_HSITRIM_2_MORT ((uint32_t)0x00000020)/*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 4256 | #define RCC_CR_HSITRIM_3_MORT ((uint32_t)0x00000040)/*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 4257 | #define RCC_CR_HSITRIM_4_MORT ((uint32_t)0x00000080)/*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 4258 | |
| rajathr | 0:34ee385f4d2d | 4259 | #define RCC_CR_HSICAL_MORT ((uint32_t)0x0000FF00) |
| rajathr | 0:34ee385f4d2d | 4260 | #define RCC_CR_HSICAL_0_MORT ((uint32_t)0x00000100)/*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4261 | #define RCC_CR_HSICAL_1_MORT ((uint32_t)0x00000200)/*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4262 | #define RCC_CR_HSICAL_2_MORT ((uint32_t)0x00000400)/*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 4263 | #define RCC_CR_HSICAL_3_MORT ((uint32_t)0x00000800)/*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 4264 | #define RCC_CR_HSICAL_4_MORT ((uint32_t)0x00001000)/*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 4265 | #define RCC_CR_HSICAL_5_MORT ((uint32_t)0x00002000)/*!<Bit 5 */ |
| rajathr | 0:34ee385f4d2d | 4266 | #define RCC_CR_HSICAL_6_MORT ((uint32_t)0x00004000)/*!<Bit 6 */ |
| rajathr | 0:34ee385f4d2d | 4267 | #define RCC_CR_HSICAL_7_MORT ((uint32_t)0x00008000)/*!<Bit 7 */ |
| rajathr | 0:34ee385f4d2d | 4268 | |
| rajathr | 0:34ee385f4d2d | 4269 | #define RCC_CR_HSEON_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4270 | #define RCC_CR_HSERDY_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4271 | #define RCC_CR_HSEBYP_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4272 | #define RCC_CR_CSSON_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4273 | #define RCC_CR_PLLON_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4274 | #define RCC_CR_PLLRDY_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4275 | #define RCC_CR_PLLI2SON_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4276 | #define RCC_CR_PLLI2SRDY_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4277 | #define RCC_CR_PLLSAION_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4278 | #define RCC_CR_PLLSAIRDY_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4279 | |
| rajathr | 0:34ee385f4d2d | 4280 | /******************** Bit definition for RCC_PLLCFGR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4281 | #define RCC_PLLCFGR_PLLM_MORT ((uint32_t)0x0000003F) |
| rajathr | 0:34ee385f4d2d | 4282 | #define RCC_PLLCFGR_PLLM_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4283 | #define RCC_PLLCFGR_PLLM_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4284 | #define RCC_PLLCFGR_PLLM_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4285 | #define RCC_PLLCFGR_PLLM_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4286 | #define RCC_PLLCFGR_PLLM_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4287 | #define RCC_PLLCFGR_PLLM_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4288 | |
| rajathr | 0:34ee385f4d2d | 4289 | #define RCC_PLLCFGR_PLLN_MORT ((uint32_t)0x00007FC0) |
| rajathr | 0:34ee385f4d2d | 4290 | #define RCC_PLLCFGR_PLLN_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4291 | #define RCC_PLLCFGR_PLLN_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4292 | #define RCC_PLLCFGR_PLLN_2_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4293 | #define RCC_PLLCFGR_PLLN_3_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4294 | #define RCC_PLLCFGR_PLLN_4_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4295 | #define RCC_PLLCFGR_PLLN_5_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4296 | #define RCC_PLLCFGR_PLLN_6_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4297 | #define RCC_PLLCFGR_PLLN_7_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4298 | #define RCC_PLLCFGR_PLLN_8_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4299 | |
| rajathr | 0:34ee385f4d2d | 4300 | #define RCC_PLLCFGR_PLLP_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 4301 | #define RCC_PLLCFGR_PLLP_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4302 | #define RCC_PLLCFGR_PLLP_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4303 | |
| rajathr | 0:34ee385f4d2d | 4304 | #define RCC_PLLCFGR_PLLSRC_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4305 | #define RCC_PLLCFGR_PLLSRC_HSE_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4306 | #define RCC_PLLCFGR_PLLSRC_HSI_MORT ((uint32_t)0x00000000) |
| rajathr | 0:34ee385f4d2d | 4307 | |
| rajathr | 0:34ee385f4d2d | 4308 | #define RCC_PLLCFGR_PLLQ_MORT ((uint32_t)0x0F000000) |
| rajathr | 0:34ee385f4d2d | 4309 | #define RCC_PLLCFGR_PLLQ_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4310 | #define RCC_PLLCFGR_PLLQ_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4311 | #define RCC_PLLCFGR_PLLQ_2_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4312 | #define RCC_PLLCFGR_PLLQ_3_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4313 | |
| rajathr | 0:34ee385f4d2d | 4314 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4315 | #define RCC_PLLCFGR_PLLR_MORT ((uint32_t)0x70000000) |
| rajathr | 0:34ee385f4d2d | 4316 | #define RCC_PLLCFGR_PLLR_0_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4317 | #define RCC_PLLCFGR_PLLR_1_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4318 | #define RCC_PLLCFGR_PLLR_2_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4319 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4320 | |
| rajathr | 0:34ee385f4d2d | 4321 | /******************** Bit definition for RCC_CFGR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4322 | /*!< SW configuration */ |
| rajathr | 0:34ee385f4d2d | 4323 | #define RCC_CFGR_SW_MORT ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
| rajathr | 0:34ee385f4d2d | 4324 | #define RCC_CFGR_SW_0_MORT ((uint32_t)0x00000001) /*!< Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4325 | #define RCC_CFGR_SW_1_MORT ((uint32_t)0x00000002) /*!< Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4326 | |
| rajathr | 0:34ee385f4d2d | 4327 | #define RCC_CFGR_SW_HSI_MORT ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
| rajathr | 0:34ee385f4d2d | 4328 | #define RCC_CFGR_SW_HSE_MORT ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
| rajathr | 0:34ee385f4d2d | 4329 | #define RCC_CFGR_SW_PLL_MORT ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */ |
| rajathr | 0:34ee385f4d2d | 4330 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4331 | #define RCC_CFGR_SW_PLLR_MORT ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */ |
| rajathr | 0:34ee385f4d2d | 4332 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4333 | |
| rajathr | 0:34ee385f4d2d | 4334 | /*!< SWS configuration */ |
| rajathr | 0:34ee385f4d2d | 4335 | #define RCC_CFGR_SWS_MORT ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| rajathr | 0:34ee385f4d2d | 4336 | #define RCC_CFGR_SWS_0_MORT ((uint32_t)0x00000004) /*!< Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4337 | #define RCC_CFGR_SWS_1_MORT ((uint32_t)0x00000008) /*!< Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4338 | |
| rajathr | 0:34ee385f4d2d | 4339 | #define RCC_CFGR_SWS_HSI_MORT ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
| rajathr | 0:34ee385f4d2d | 4340 | #define RCC_CFGR_SWS_HSE_MORT ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
| rajathr | 0:34ee385f4d2d | 4341 | #define RCC_CFGR_SWS_PLL_MORT ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */ |
| rajathr | 0:34ee385f4d2d | 4342 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F469_479xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4343 | #define RCC_CFGR_SWS_PLLR_MORT ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */ |
| rajathr | 0:34ee385f4d2d | 4344 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4345 | |
| rajathr | 0:34ee385f4d2d | 4346 | /*!< HPRE configuration */ |
| rajathr | 0:34ee385f4d2d | 4347 | #define RCC_CFGR_HPRE_MORT ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
| rajathr | 0:34ee385f4d2d | 4348 | #define RCC_CFGR_HPRE_0_MORT ((uint32_t)0x00000010) /*!< Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4349 | #define RCC_CFGR_HPRE_1_MORT ((uint32_t)0x00000020) /*!< Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4350 | #define RCC_CFGR_HPRE_2_MORT ((uint32_t)0x00000040) /*!< Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 4351 | #define RCC_CFGR_HPRE_3_MORT ((uint32_t)0x00000080) /*!< Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 4352 | |
| rajathr | 0:34ee385f4d2d | 4353 | #define RCC_CFGR_HPRE_DIV1_MORT ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
| rajathr | 0:34ee385f4d2d | 4354 | #define RCC_CFGR_HPRE_DIV2_MORT ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
| rajathr | 0:34ee385f4d2d | 4355 | #define RCC_CFGR_HPRE_DIV4_MORT ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
| rajathr | 0:34ee385f4d2d | 4356 | #define RCC_CFGR_HPRE_DIV8_MORT ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
| rajathr | 0:34ee385f4d2d | 4357 | #define RCC_CFGR_HPRE_DIV16_MORT ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
| rajathr | 0:34ee385f4d2d | 4358 | #define RCC_CFGR_HPRE_DIV64_MORT ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
| rajathr | 0:34ee385f4d2d | 4359 | #define RCC_CFGR_HPRE_DIV128_MORT ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
| rajathr | 0:34ee385f4d2d | 4360 | #define RCC_CFGR_HPRE_DIV256_MORT ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
| rajathr | 0:34ee385f4d2d | 4361 | #define RCC_CFGR_HPRE_DIV512_MORT ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
| rajathr | 0:34ee385f4d2d | 4362 | |
| rajathr | 0:34ee385f4d2d | 4363 | #if defined(STM32F410xx) |
| rajathr | 0:34ee385f4d2d | 4364 | /*!< MCO1EN configuration */ |
| rajathr | 0:34ee385f4d2d | 4365 | |
| rajathr | 0:34ee385f4d2d | 4366 | #endif /* STM32F410xx */ |
| rajathr | 0:34ee385f4d2d | 4367 | /*!< PPRE1 configuration */ |
| rajathr | 0:34ee385f4d2d | 4368 | #define RCC_CFGR_PPRE1_MORT ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
| rajathr | 0:34ee385f4d2d | 4369 | #define RCC_CFGR_PPRE1_0_MORT ((uint32_t)0x00000400) /*!< Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4370 | #define RCC_CFGR_PPRE1_1_MORT ((uint32_t)0x00000800) /*!< Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4371 | #define RCC_CFGR_PPRE1_2_MORT ((uint32_t)0x00001000) /*!< Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 4372 | |
| rajathr | 0:34ee385f4d2d | 4373 | #define RCC_CFGR_PPRE1_DIV1_MORT ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| rajathr | 0:34ee385f4d2d | 4374 | #define RCC_CFGR_PPRE1_DIV2_MORT ((uint32_t)0x00001000) /*!< HCLK divided by 2 */ |
| rajathr | 0:34ee385f4d2d | 4375 | #define RCC_CFGR_PPRE1_DIV4_MORT ((uint32_t)0x00001400) /*!< HCLK divided by 4 */ |
| rajathr | 0:34ee385f4d2d | 4376 | #define RCC_CFGR_PPRE1_DIV8_MORT ((uint32_t)0x00001800) /*!< HCLK divided by 8 */ |
| rajathr | 0:34ee385f4d2d | 4377 | #define RCC_CFGR_PPRE1_DIV16_MORT ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */ |
| rajathr | 0:34ee385f4d2d | 4378 | |
| rajathr | 0:34ee385f4d2d | 4379 | /*!< PPRE2 configuration */ |
| rajathr | 0:34ee385f4d2d | 4380 | #define RCC_CFGR_PPRE2_MORT ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| rajathr | 0:34ee385f4d2d | 4381 | #define RCC_CFGR_PPRE2_0_MORT ((uint32_t)0x00002000) /*!< Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 4382 | #define RCC_CFGR_PPRE2_1_MORT ((uint32_t)0x00004000) /*!< Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 4383 | #define RCC_CFGR_PPRE2_2_MORT ((uint32_t)0x00008000) /*!< Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 4384 | |
| rajathr | 0:34ee385f4d2d | 4385 | #define RCC_CFGR_PPRE2_DIV1_MORT ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| rajathr | 0:34ee385f4d2d | 4386 | #define RCC_CFGR_PPRE2_DIV2_MORT ((uint32_t)0x00008000) /*!< HCLK divided by 2 */ |
| rajathr | 0:34ee385f4d2d | 4387 | #define RCC_CFGR_PPRE2_DIV4_MORT ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */ |
| rajathr | 0:34ee385f4d2d | 4388 | #define RCC_CFGR_PPRE2_DIV8_MORT ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */ |
| rajathr | 0:34ee385f4d2d | 4389 | #define RCC_CFGR_PPRE2_DIV16_MORT ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */ |
| rajathr | 0:34ee385f4d2d | 4390 | |
| rajathr | 0:34ee385f4d2d | 4391 | /*!< RTCPRE configuration */ |
| rajathr | 0:34ee385f4d2d | 4392 | #define RCC_CFGR_RTCPRE_MORT ((uint32_t)0x001F0000) |
| rajathr | 0:34ee385f4d2d | 4393 | #define RCC_CFGR_RTCPRE_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4394 | #define RCC_CFGR_RTCPRE_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4395 | #define RCC_CFGR_RTCPRE_2_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4396 | #define RCC_CFGR_RTCPRE_3_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4397 | #define RCC_CFGR_RTCPRE_4_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4398 | |
| rajathr | 0:34ee385f4d2d | 4399 | /*!< MCO1 configuration */ |
| rajathr | 0:34ee385f4d2d | 4400 | #define RCC_CFGR_MCO1_MORT ((uint32_t)0x00600000) |
| rajathr | 0:34ee385f4d2d | 4401 | #define RCC_CFGR_MCO1_0_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4402 | #define RCC_CFGR_MCO1_1_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4403 | |
| rajathr | 0:34ee385f4d2d | 4404 | #define RCC_CFGR_I2SSRC_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4405 | |
| rajathr | 0:34ee385f4d2d | 4406 | #define RCC_CFGR_MCO1PRE_MORT ((uint32_t)0x07000000) |
| rajathr | 0:34ee385f4d2d | 4407 | #define RCC_CFGR_MCO1PRE_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4408 | #define RCC_CFGR_MCO1PRE_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4409 | #define RCC_CFGR_MCO1PRE_2_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4410 | |
| rajathr | 0:34ee385f4d2d | 4411 | #define RCC_CFGR_MCO2PRE_MORT ((uint32_t)0x38000000) |
| rajathr | 0:34ee385f4d2d | 4412 | #define RCC_CFGR_MCO2PRE_0_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4413 | #define RCC_CFGR_MCO2PRE_1_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4414 | #define RCC_CFGR_MCO2PRE_2_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4415 | |
| rajathr | 0:34ee385f4d2d | 4416 | #define RCC_CFGR_MCO2_MORT ((uint32_t)0xC0000000) |
| rajathr | 0:34ee385f4d2d | 4417 | #define RCC_CFGR_MCO2_0_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4418 | #define RCC_CFGR_MCO2_1_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 4419 | |
| rajathr | 0:34ee385f4d2d | 4420 | /******************** Bit definition for RCC_CIR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4421 | #define RCC_CIR_LSIRDYF_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4422 | #define RCC_CIR_LSERDYF_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4423 | #define RCC_CIR_HSIRDYF_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4424 | #define RCC_CIR_HSERDYF_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4425 | #define RCC_CIR_PLLRDYF_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4426 | #define RCC_CIR_PLLI2SRDYF_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4427 | #define RCC_CIR_PLLSAIRDYF_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4428 | #define RCC_CIR_CSSF_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4429 | #define RCC_CIR_LSIRDYIE_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4430 | #define RCC_CIR_LSERDYIE_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4431 | #define RCC_CIR_HSIRDYIE_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4432 | #define RCC_CIR_HSERDYIE_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4433 | #define RCC_CIR_PLLRDYIE_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4434 | #define RCC_CIR_PLLI2SRDYIE_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4435 | #define RCC_CIR_PLLSAIRDYIE_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4436 | #define RCC_CIR_LSIRDYC_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4437 | #define RCC_CIR_LSERDYC_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4438 | #define RCC_CIR_HSIRDYC_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4439 | #define RCC_CIR_HSERDYC_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4440 | #define RCC_CIR_PLLRDYC_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4441 | #define RCC_CIR_PLLI2SRDYC_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4442 | #define RCC_CIR_PLLSAIRDYC_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4443 | #define RCC_CIR_CSSC_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4444 | |
| rajathr | 0:34ee385f4d2d | 4445 | /******************** Bit definition for RCC_AHB1RSTR register **************/ |
| rajathr | 0:34ee385f4d2d | 4446 | #define RCC_AHB1RSTR_GPIOARST_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4447 | #define RCC_AHB1RSTR_GPIOBRST_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4448 | #define RCC_AHB1RSTR_GPIOCRST_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4449 | #define RCC_AHB1RSTR_GPIODRST_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4450 | #define RCC_AHB1RSTR_GPIOERST_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4451 | #define RCC_AHB1RSTR_GPIOFRST_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4452 | #define RCC_AHB1RSTR_GPIOGRST_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4453 | #define RCC_AHB1RSTR_GPIOHRST_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4454 | #define RCC_AHB1RSTR_GPIOIRST_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4455 | #define RCC_AHB1RSTR_GPIOJRST_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4456 | #define RCC_AHB1RSTR_GPIOKRST_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4457 | #define RCC_AHB1RSTR_CRCRST_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4458 | #define RCC_AHB1RSTR_DMA1RST_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4459 | #define RCC_AHB1RSTR_DMA2RST_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4460 | #define RCC_AHB1RSTR_DMA2DRST_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4461 | #define RCC_AHB1RSTR_ETHMACRST_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4462 | #define RCC_AHB1RSTR_OTGHRST_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4463 | |
| rajathr | 0:34ee385f4d2d | 4464 | /******************** Bit definition for RCC_AHB2RSTR register **************/ |
| rajathr | 0:34ee385f4d2d | 4465 | #define RCC_AHB2RSTR_DCMIRST_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4466 | #define RCC_AHB2RSTR_CRYPRST_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4467 | #define RCC_AHB2RSTR_HASHRST_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4468 | /* maintained for legacy purpose */ |
| rajathr | 0:34ee385f4d2d | 4469 | #define RCC_AHB2RSTR_HSAHRST_MORT RCC_AHB2RSTR_HASHRST_MORT |
| rajathr | 0:34ee385f4d2d | 4470 | #define RCC_AHB2RSTR_RNGRST_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4471 | #define RCC_AHB2RSTR_OTGFSRST_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4472 | |
| rajathr | 0:34ee385f4d2d | 4473 | /******************** Bit definition for RCC_AHB3RSTR register **************/ |
| rajathr | 0:34ee385f4d2d | 4474 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4475 | |
| rajathr | 0:34ee385f4d2d | 4476 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4477 | |
| rajathr | 0:34ee385f4d2d | 4478 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4479 | #define RCC_AHB3RSTR_FMCRST_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4480 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4481 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4482 | #define RCC_AHB3RSTR_QSPIRST_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4483 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4484 | |
| rajathr | 0:34ee385f4d2d | 4485 | /******************** Bit definition for RCC_APB1RSTR register **************/ |
| rajathr | 0:34ee385f4d2d | 4486 | #define RCC_APB1RSTR_TIM2RST_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4487 | #define RCC_APB1RSTR_TIM3RST_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4488 | #define RCC_APB1RSTR_TIM4RST_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4489 | #define RCC_APB1RSTR_TIM5RST_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4490 | #define RCC_APB1RSTR_TIM6RST_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4491 | #define RCC_APB1RSTR_TIM7RST_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4492 | #define RCC_APB1RSTR_TIM12RST_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4493 | #define RCC_APB1RSTR_TIM13RST_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4494 | #define RCC_APB1RSTR_TIM14RST_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4495 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4496 | #define RCC_APB1RSTR_LPTIM1RST_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4497 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4498 | #define RCC_APB1RSTR_WWDGRST_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4499 | #define RCC_APB1RSTR_SPI2RST_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4500 | #define RCC_APB1RSTR_SPI3RST_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 4501 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4502 | #define RCC_APB1RSTR_SPDIFRXRST_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4503 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4504 | #define RCC_APB1RSTR_USART2RST_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4505 | #define RCC_APB1RSTR_USART3RST_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4506 | #define RCC_APB1RSTR_UART4RST_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4507 | #define RCC_APB1RSTR_UART5RST_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4508 | #define RCC_APB1RSTR_I2C1RST_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4509 | #define RCC_APB1RSTR_I2C2RST_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4510 | #define RCC_APB1RSTR_I2C3RST_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4511 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4512 | #define RCC_APB1RSTR_FMPI2C1RST_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4513 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4514 | #define RCC_APB1RSTR_CAN1RST_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4515 | #define RCC_APB1RSTR_CAN2RST_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4516 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4517 | #define RCC_APB1RSTR_CECRST_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4518 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4519 | #define RCC_APB1RSTR_PWRRST_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4520 | #define RCC_APB1RSTR_DACRST_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4521 | #define RCC_APB1RSTR_UART7RST_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4522 | #define RCC_APB1RSTR_UART8RST_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 4523 | |
| rajathr | 0:34ee385f4d2d | 4524 | /******************** Bit definition for RCC_APB2RSTR register **************/ |
| rajathr | 0:34ee385f4d2d | 4525 | #define RCC_APB2RSTR_TIM1RST_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4526 | #define RCC_APB2RSTR_TIM8RST_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4527 | #define RCC_APB2RSTR_USART1RST_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4528 | #define RCC_APB2RSTR_USART6RST_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4529 | #define RCC_APB2RSTR_UART9RST_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4530 | #define RCC_APB2RSTR_UART10RST_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4531 | #define RCC_APB2RSTR_ADCRST_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4532 | #define RCC_APB2RSTR_SDIORST_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4533 | #define RCC_APB2RSTR_SPI1RST_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4534 | #define RCC_APB2RSTR_SPI4RST_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4535 | #define RCC_APB2RSTR_SYSCFGRST_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4536 | #define RCC_APB2RSTR_TIM9RST_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4537 | #define RCC_APB2RSTR_TIM10RST_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4538 | #define RCC_APB2RSTR_TIM11RST_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4539 | #define RCC_APB2RSTR_SPI5RST_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4540 | #define RCC_APB2RSTR_SPI6RST_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4541 | #define RCC_APB2RSTR_SAI1RST_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4542 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4543 | #define RCC_APB2RSTR_SAI2RST_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4544 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4545 | #define RCC_APB2RSTR_LTDCRST_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4546 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4547 | #define RCC_APB2RSTR_DSIRST_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4548 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4549 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4550 | #define RCC_APB2RSTR_DFSDM1RST_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4551 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4552 | |
| rajathr | 0:34ee385f4d2d | 4553 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4554 | #define RCC_APB2RSTR_DFSDM2RST_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4555 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4556 | /* Old definitions, maintained for legacy purpose */ |
| rajathr | 0:34ee385f4d2d | 4557 | #define RCC_APB2RSTR_SPI1_MORT RCC_APB2RSTR_SPI1RST_MORT |
| rajathr | 0:34ee385f4d2d | 4558 | #define RCC_APB2RSTR_DFSDMRST RCC_APB2RSTR_DFSDM1RST_MORT |
| rajathr | 0:34ee385f4d2d | 4559 | |
| rajathr | 0:34ee385f4d2d | 4560 | /******************** Bit definition for RCC_AHB1ENR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4561 | #define RCC_AHB1ENR_GPIOAEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4562 | #define RCC_AHB1ENR_GPIOBEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4563 | #define RCC_AHB1ENR_GPIOCEN_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4564 | #define RCC_AHB1ENR_GPIODEN_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4565 | #define RCC_AHB1ENR_GPIOEEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4566 | #define RCC_AHB1ENR_GPIOFEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4567 | #define RCC_AHB1ENR_GPIOGEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4568 | #define RCC_AHB1ENR_GPIOHEN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4569 | #define RCC_AHB1ENR_GPIOIEN_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4570 | #define RCC_AHB1ENR_GPIOJEN_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4571 | #define RCC_AHB1ENR_GPIOKEN_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4572 | #define RCC_AHB1ENR_CRCEN_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4573 | #define RCC_AHB1ENR_BKPSRAMEN_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4574 | #define RCC_AHB1ENR_CCMDATARAMEN_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4575 | #define RCC_AHB1ENR_DMA1EN_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4576 | #define RCC_AHB1ENR_DMA2EN_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4577 | #define RCC_AHB1ENR_DMA2DEN_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4578 | #define RCC_AHB1ENR_ETHMACEN_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4579 | #define RCC_AHB1ENR_ETHMACTXEN_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4580 | #define RCC_AHB1ENR_ETHMACRXEN_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4581 | #define RCC_AHB1ENR_ETHMACPTPEN_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4582 | #define RCC_AHB1ENR_OTGHSEN_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4583 | #define RCC_AHB1ENR_OTGHSULPIEN_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4584 | |
| rajathr | 0:34ee385f4d2d | 4585 | /******************** Bit definition for RCC_AHB2ENR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4586 | #define RCC_AHB2ENR_DCMIEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4587 | #define RCC_AHB2ENR_CRYPEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4588 | #define RCC_AHB2ENR_HASHEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4589 | #define RCC_AHB2ENR_RNGEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4590 | #define RCC_AHB2ENR_OTGFSEN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4591 | |
| rajathr | 0:34ee385f4d2d | 4592 | /******************** Bit definition for RCC_AHB3ENR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4593 | |
| rajathr | 0:34ee385f4d2d | 4594 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4595 | |
| rajathr | 0:34ee385f4d2d | 4596 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4597 | |
| rajathr | 0:34ee385f4d2d | 4598 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4599 | #define RCC_AHB3ENR_FMCEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4600 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4601 | |
| rajathr | 0:34ee385f4d2d | 4602 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4603 | #define RCC_AHB3ENR_QSPIEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4604 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4605 | |
| rajathr | 0:34ee385f4d2d | 4606 | /******************** Bit definition for RCC_APB1ENR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4607 | #define RCC_APB1ENR_TIM2EN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4608 | #define RCC_APB1ENR_TIM3EN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4609 | #define RCC_APB1ENR_TIM4EN_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4610 | #define RCC_APB1ENR_TIM5EN_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4611 | #define RCC_APB1ENR_TIM6EN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4612 | #define RCC_APB1ENR_TIM7EN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4613 | #define RCC_APB1ENR_TIM12EN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4614 | #define RCC_APB1ENR_TIM13EN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4615 | #define RCC_APB1ENR_TIM14EN_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4616 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4617 | |
| rajathr | 0:34ee385f4d2d | 4618 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4619 | #define RCC_APB1ENR_WWDGEN_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4620 | #define RCC_APB1ENR_SPI2EN_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4621 | #define RCC_APB1ENR_SPI3EN_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 4622 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4623 | #define RCC_APB1ENR_SPDIFRXEN_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4624 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4625 | #define RCC_APB1ENR_USART2EN_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4626 | #define RCC_APB1ENR_USART3EN_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4627 | #define RCC_APB1ENR_UART4EN_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4628 | #define RCC_APB1ENR_UART5EN_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4629 | #define RCC_APB1ENR_I2C1EN_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4630 | #define RCC_APB1ENR_I2C2EN_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4631 | #define RCC_APB1ENR_I2C3EN_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4632 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4633 | #define RCC_APB1ENR_FMPI2C1EN_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4634 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4635 | #define RCC_APB1ENR_CAN1EN_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4636 | #define RCC_APB1ENR_CAN2EN_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4637 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4638 | #define RCC_APB1ENR_CECEN_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4639 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4640 | #define RCC_APB1ENR_PWREN_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4641 | #define RCC_APB1ENR_DACEN_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4642 | #define RCC_APB1ENR_UART7EN_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4643 | #define RCC_APB1ENR_UART8EN_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 4644 | |
| rajathr | 0:34ee385f4d2d | 4645 | /******************** Bit definition for RCC_APB2ENR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4646 | #define RCC_APB2ENR_TIM1EN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4647 | #define RCC_APB2ENR_TIM8EN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4648 | #define RCC_APB2ENR_USART1EN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4649 | #define RCC_APB2ENR_USART6EN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4650 | #define RCC_APB2ENR_UART9EN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4651 | #define RCC_APB2ENR_UART10EN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4652 | #define RCC_APB2ENR_ADC1EN_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4653 | #define RCC_APB2ENR_ADC2EN_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4654 | #define RCC_APB2ENR_ADC3EN_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4655 | #define RCC_APB2ENR_SDIOEN_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4656 | #define RCC_APB2ENR_SPI1EN_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4657 | #define RCC_APB2ENR_SPI4EN_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4658 | #define RCC_APB2ENR_SYSCFGEN_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4659 | #define RCC_APB2ENR_EXTIEN_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 4660 | #define RCC_APB2ENR_TIM9EN_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4661 | #define RCC_APB2ENR_TIM10EN_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4662 | #define RCC_APB2ENR_TIM11EN_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4663 | #define RCC_APB2ENR_SPI5EN_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4664 | #define RCC_APB2ENR_SPI6EN_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4665 | #define RCC_APB2ENR_SAI1EN_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4666 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4667 | #define RCC_APB2ENR_SAI2EN_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4668 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4669 | #define RCC_APB2ENR_LTDCEN_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4670 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4671 | #define RCC_APB2ENR_DSIEN_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4672 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4673 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4674 | #define RCC_APB2ENR_DFSDM1EN_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4675 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4676 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4677 | #define RCC_APB2ENR_DFSDM2EN_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4678 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4679 | /******************** Bit definition for RCC_AHB1LPENR register *************/ |
| rajathr | 0:34ee385f4d2d | 4680 | #define RCC_AHB1LPENR_GPIOALPEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4681 | #define RCC_AHB1LPENR_GPIOBLPEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4682 | #define RCC_AHB1LPENR_GPIOCLPEN_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4683 | #define RCC_AHB1LPENR_GPIODLPEN_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4684 | #define RCC_AHB1LPENR_GPIOELPEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4685 | #define RCC_AHB1LPENR_GPIOFLPEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4686 | #define RCC_AHB1LPENR_GPIOGLPEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4687 | #define RCC_AHB1LPENR_GPIOHLPEN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4688 | #define RCC_AHB1LPENR_GPIOILPEN_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4689 | #define RCC_AHB1LPENR_GPIOJLPEN_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4690 | #define RCC_AHB1LPENR_GPIOKLPEN_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4691 | #define RCC_AHB1LPENR_CRCLPEN_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4692 | #define RCC_AHB1LPENR_FLITFLPEN_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 4693 | #define RCC_AHB1LPENR_SRAM1LPEN_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4694 | #define RCC_AHB1LPENR_SRAM2LPEN_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4695 | #define RCC_AHB1LPENR_BKPSRAMLPEN_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4696 | #define RCC_AHB1LPENR_SRAM3LPEN_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4697 | #define RCC_AHB1LPENR_DMA1LPEN_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4698 | #define RCC_AHB1LPENR_DMA2LPEN_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4699 | #define RCC_AHB1LPENR_DMA2DLPEN_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4700 | #define RCC_AHB1LPENR_ETHMACLPEN_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4701 | #define RCC_AHB1LPENR_ETHMACTXLPEN_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4702 | #define RCC_AHB1LPENR_ETHMACRXLPEN_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4703 | #define RCC_AHB1LPENR_ETHMACPTPLPEN_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4704 | #define RCC_AHB1LPENR_OTGHSLPEN_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4705 | #define RCC_AHB1LPENR_OTGHSULPILPEN_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4706 | |
| rajathr | 0:34ee385f4d2d | 4707 | /******************** Bit definition for RCC_AHB2LPENR register *************/ |
| rajathr | 0:34ee385f4d2d | 4708 | #define RCC_AHB2LPENR_DCMILPEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4709 | #define RCC_AHB2LPENR_CRYPLPEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4710 | #define RCC_AHB2LPENR_HASHLPEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4711 | #define RCC_AHB2LPENR_RNGLPEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4712 | #define RCC_AHB2LPENR_OTGFSLPEN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4713 | |
| rajathr | 0:34ee385f4d2d | 4714 | /******************** Bit definition for RCC_AHB3LPENR register *************/ |
| rajathr | 0:34ee385f4d2d | 4715 | #if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4716 | #define RCC_AHB3LPENR_FSMCLPEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4717 | #endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4718 | |
| rajathr | 0:34ee385f4d2d | 4719 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4720 | #define RCC_AHB3LPENR_FMCLPEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4721 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4722 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4723 | #define RCC_AHB3LPENR_QSPILPEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4724 | #endif /* STM32F412xG || STM32F413_423xx || STM32F469_479xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4725 | |
| rajathr | 0:34ee385f4d2d | 4726 | /******************** Bit definition for RCC_APB1LPENR register *************/ |
| rajathr | 0:34ee385f4d2d | 4727 | #define RCC_APB1LPENR_TIM2LPEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4728 | #define RCC_APB1LPENR_TIM3LPEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4729 | #define RCC_APB1LPENR_TIM4LPEN_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4730 | #define RCC_APB1LPENR_TIM5LPEN_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4731 | #define RCC_APB1LPENR_TIM6LPEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4732 | #define RCC_APB1LPENR_TIM7LPEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4733 | #define RCC_APB1LPENR_TIM12LPEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4734 | #define RCC_APB1LPENR_TIM13LPEN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4735 | #define RCC_APB1LPENR_TIM14LPEN_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4736 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4737 | #define RCC_APB1LPENR_LPTIM1LPEN_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4738 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4739 | #define RCC_APB1LPENR_WWDGLPEN_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4740 | #define RCC_APB1LPENR_SPI2LPEN_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4741 | #define RCC_APB1LPENR_SPI3LPEN_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 4742 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4743 | #define RCC_APB1LPENR_SPDIFRXLPEN_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4744 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4745 | #define RCC_APB1LPENR_USART2LPEN_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4746 | #define RCC_APB1LPENR_USART3LPEN_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4747 | #define RCC_APB1LPENR_UART4LPEN_MORT ((uint32_t)0x00080000) |
| rajathr | 0:34ee385f4d2d | 4748 | #define RCC_APB1LPENR_UART5LPEN_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4749 | #define RCC_APB1LPENR_I2C1LPEN_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4750 | #define RCC_APB1LPENR_I2C2LPEN_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4751 | #define RCC_APB1LPENR_I2C3LPEN_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4752 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4753 | #define RCC_APB1LPENR_FMPI2C1LPEN_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4754 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4755 | #define RCC_APB1LPENR_CAN1LPEN_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4756 | #define RCC_APB1LPENR_CAN2LPEN_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4757 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4758 | #define RCC_APB1LPENR_CECLPEN_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4759 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4760 | #define RCC_APB1LPENR_PWRLPEN_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4761 | #define RCC_APB1LPENR_DACLPEN_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4762 | #define RCC_APB1LPENR_UART7LPEN_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4763 | #define RCC_APB1LPENR_UART8LPEN_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 4764 | |
| rajathr | 0:34ee385f4d2d | 4765 | /******************** Bit definition for RCC_APB2LPENR register *************/ |
| rajathr | 0:34ee385f4d2d | 4766 | #define RCC_APB2LPENR_TIM1LPEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4767 | #define RCC_APB2LPENR_TIM8LPEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4768 | #define RCC_APB2LPENR_USART1LPEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4769 | #define RCC_APB2LPENR_USART6LPEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4770 | #define RCC_APB2LPENR_UART9LPEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4771 | #define RCC_APB2LPENR_UART10LPEN_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4772 | #define RCC_APB2LPENR_ADC1LPEN_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4773 | #define RCC_APB2LPENR_ADC2PEN_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4774 | #define RCC_APB2LPENR_ADC3LPEN_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4775 | #define RCC_APB2LPENR_SDIOLPEN_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4776 | #define RCC_APB2LPENR_SPI1LPEN_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4777 | #define RCC_APB2LPENR_SPI4LPEN_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4778 | #define RCC_APB2LPENR_SYSCFGLPEN_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4779 | #define RCC_APB2LPENR_TIM9LPEN_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4780 | #define RCC_APB2LPENR_TIM10LPEN_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4781 | #define RCC_APB2LPENR_TIM11LPEN_MORT ((uint32_t)0x00040000) |
| rajathr | 0:34ee385f4d2d | 4782 | #define RCC_APB2LPENR_SPI5LPEN_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4783 | #define RCC_APB2LPENR_SPI6LPEN_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4784 | #define RCC_APB2LPENR_SAI1LPEN_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4785 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4786 | #define RCC_APB2LPENR_SAI2LPEN_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4787 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4788 | #define RCC_APB2LPENR_LTDCLPEN_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4789 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4790 | |
| rajathr | 0:34ee385f4d2d | 4791 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4792 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4793 | |
| rajathr | 0:34ee385f4d2d | 4794 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4795 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4796 | |
| rajathr | 0:34ee385f4d2d | 4797 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4798 | |
| rajathr | 0:34ee385f4d2d | 4799 | /******************** Bit definition for RCC_BDCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 4800 | #define RCC_BDCR_LSEON_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4801 | #define RCC_BDCR_LSERDY_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4802 | #define RCC_BDCR_LSEBYP_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4803 | #define RCC_BDCR_LSEMOD_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4804 | |
| rajathr | 0:34ee385f4d2d | 4805 | #define RCC_BDCR_RTCSEL_MORT ((uint32_t)0x00000300) |
| rajathr | 0:34ee385f4d2d | 4806 | #define RCC_BDCR_RTCSEL_0_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4807 | #define RCC_BDCR_RTCSEL_1_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4808 | |
| rajathr | 0:34ee385f4d2d | 4809 | #define RCC_BDCR_RTCEN_MORT ((uint32_t)0x00008000) |
| rajathr | 0:34ee385f4d2d | 4810 | #define RCC_BDCR_BDRST_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4811 | |
| rajathr | 0:34ee385f4d2d | 4812 | /******************** Bit definition for RCC_CSR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4813 | #define RCC_CSR_LSION_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4814 | #define RCC_CSR_LSIRDY_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4815 | #define RCC_CSR_RMVF_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4816 | #define RCC_CSR_BORRSTF_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4817 | #define RCC_CSR_PADRSTF_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4818 | #define RCC_CSR_PORRSTF_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4819 | #define RCC_CSR_SFTRSTF_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4820 | #define RCC_CSR_WDGRSTF_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4821 | #define RCC_CSR_WWDGRSTF_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4822 | #define RCC_CSR_LPWRRSTF_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 4823 | |
| rajathr | 0:34ee385f4d2d | 4824 | /******************** Bit definition for RCC_SSCGR register *****************/ |
| rajathr | 0:34ee385f4d2d | 4825 | #define RCC_SSCGR_MODPER_MORT ((uint32_t)0x00001FFF) |
| rajathr | 0:34ee385f4d2d | 4826 | #define RCC_SSCGR_INCSTEP_MORT ((uint32_t)0x0FFFE000) |
| rajathr | 0:34ee385f4d2d | 4827 | #define RCC_SSCGR_SPREADSEL_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4828 | #define RCC_SSCGR_SSCGEN_MORT ((uint32_t)0x80000000) |
| rajathr | 0:34ee385f4d2d | 4829 | |
| rajathr | 0:34ee385f4d2d | 4830 | /******************** Bit definition for RCC_PLLI2SCFGR register ************/ |
| rajathr | 0:34ee385f4d2d | 4831 | #define RCC_PLLI2SCFGR_PLLI2SM_MORT ((uint32_t)0x0000003F) |
| rajathr | 0:34ee385f4d2d | 4832 | #define RCC_PLLI2SCFGR_PLLI2SM_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4833 | #define RCC_PLLI2SCFGR_PLLI2SM_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4834 | #define RCC_PLLI2SCFGR_PLLI2SM_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4835 | #define RCC_PLLI2SCFGR_PLLI2SM_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4836 | #define RCC_PLLI2SCFGR_PLLI2SM_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4837 | #define RCC_PLLI2SCFGR_PLLI2SM_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4838 | |
| rajathr | 0:34ee385f4d2d | 4839 | #define RCC_PLLI2SCFGR_PLLI2SN_MORT ((uint32_t)0x00007FC0) |
| rajathr | 0:34ee385f4d2d | 4840 | #define RCC_PLLI2SCFGR_PLLI2SN_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4841 | #define RCC_PLLI2SCFGR_PLLI2SN_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4842 | #define RCC_PLLI2SCFGR_PLLI2SN_2_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4843 | #define RCC_PLLI2SCFGR_PLLI2SN_3_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4844 | #define RCC_PLLI2SCFGR_PLLI2SN_4_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4845 | #define RCC_PLLI2SCFGR_PLLI2SN_5_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4846 | #define RCC_PLLI2SCFGR_PLLI2SN_6_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4847 | #define RCC_PLLI2SCFGR_PLLI2SN_7_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4848 | #define RCC_PLLI2SCFGR_PLLI2SN_8_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4849 | |
| rajathr | 0:34ee385f4d2d | 4850 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4851 | |
| rajathr | 0:34ee385f4d2d | 4852 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4853 | |
| rajathr | 0:34ee385f4d2d | 4854 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4855 | #define RCC_PLLI2SCFGR_PLLI2SP_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 4856 | #define RCC_PLLI2SCFGR_PLLI2SP_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4857 | #define RCC_PLLI2SCFGR_PLLI2SP_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4858 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4859 | |
| rajathr | 0:34ee385f4d2d | 4860 | #define RCC_PLLI2SCFGR_PLLI2SQ_MORT ((uint32_t)0x0F000000) |
| rajathr | 0:34ee385f4d2d | 4861 | #define RCC_PLLI2SCFGR_PLLI2SQ_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4862 | #define RCC_PLLI2SCFGR_PLLI2SQ_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4863 | #define RCC_PLLI2SCFGR_PLLI2SQ_2_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4864 | #define RCC_PLLI2SCFGR_PLLI2SQ_3_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4865 | |
| rajathr | 0:34ee385f4d2d | 4866 | #define RCC_PLLI2SCFGR_PLLI2SR_MORT ((uint32_t)0x70000000) |
| rajathr | 0:34ee385f4d2d | 4867 | #define RCC_PLLI2SCFGR_PLLI2SR_0_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4868 | #define RCC_PLLI2SCFGR_PLLI2SR_1_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4869 | #define RCC_PLLI2SCFGR_PLLI2SR_2_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4870 | |
| rajathr | 0:34ee385f4d2d | 4871 | /******************** Bit definition for RCC_PLLSAICFGR register ************/ |
| rajathr | 0:34ee385f4d2d | 4872 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4873 | #define RCC_PLLSAICFGR_PLLSAIM_MORT ((uint32_t)0x0000003F) |
| rajathr | 0:34ee385f4d2d | 4874 | #define RCC_PLLSAICFGR_PLLSAIM_0_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4875 | #define RCC_PLLSAICFGR_PLLSAIM_1_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4876 | #define RCC_PLLSAICFGR_PLLSAIM_2_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4877 | #define RCC_PLLSAICFGR_PLLSAIM_3_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4878 | #define RCC_PLLSAICFGR_PLLSAIM_4_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4879 | #define RCC_PLLSAICFGR_PLLSAIM_5_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4880 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4881 | |
| rajathr | 0:34ee385f4d2d | 4882 | #define RCC_PLLSAICFGR_PLLSAIN_MORT ((uint32_t)0x00007FC0) |
| rajathr | 0:34ee385f4d2d | 4883 | #define RCC_PLLSAICFGR_PLLSAIN_0_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4884 | #define RCC_PLLSAICFGR_PLLSAIN_1_MORT ((uint32_t)0x00000080) |
| rajathr | 0:34ee385f4d2d | 4885 | #define RCC_PLLSAICFGR_PLLSAIN_2_MORT ((uint32_t)0x00000100) |
| rajathr | 0:34ee385f4d2d | 4886 | #define RCC_PLLSAICFGR_PLLSAIN_3_MORT ((uint32_t)0x00000200) |
| rajathr | 0:34ee385f4d2d | 4887 | #define RCC_PLLSAICFGR_PLLSAIN_4_MORT ((uint32_t)0x00000400) |
| rajathr | 0:34ee385f4d2d | 4888 | #define RCC_PLLSAICFGR_PLLSAIN_5_MORT ((uint32_t)0x00000800) |
| rajathr | 0:34ee385f4d2d | 4889 | #define RCC_PLLSAICFGR_PLLSAIN_6_MORT ((uint32_t)0x00001000) |
| rajathr | 0:34ee385f4d2d | 4890 | #define RCC_PLLSAICFGR_PLLSAIN_7_MORT ((uint32_t)0x00002000) |
| rajathr | 0:34ee385f4d2d | 4891 | #define RCC_PLLSAICFGR_PLLSAIN_8_MORT ((uint32_t)0x00004000) |
| rajathr | 0:34ee385f4d2d | 4892 | |
| rajathr | 0:34ee385f4d2d | 4893 | #if defined(STM32F446xx_MORT) || defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4894 | #define RCC_PLLSAICFGR_PLLSAIP_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 4895 | #define RCC_PLLSAICFGR_PLLSAIP_0_MORT ((uint32_t)0x00010000) |
| rajathr | 0:34ee385f4d2d | 4896 | #define RCC_PLLSAICFGR_PLLSAIP_1_MORT ((uint32_t)0x00020000) |
| rajathr | 0:34ee385f4d2d | 4897 | #endif /* STM32F446xx_MORT || STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4898 | |
| rajathr | 0:34ee385f4d2d | 4899 | #define RCC_PLLSAICFGR_PLLSAIQ_MORT ((uint32_t)0x0F000000) |
| rajathr | 0:34ee385f4d2d | 4900 | #define RCC_PLLSAICFGR_PLLSAIQ_0_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4901 | #define RCC_PLLSAICFGR_PLLSAIQ_1_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4902 | #define RCC_PLLSAICFGR_PLLSAIQ_2_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4903 | #define RCC_PLLSAICFGR_PLLSAIQ_3_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4904 | |
| rajathr | 0:34ee385f4d2d | 4905 | #define RCC_PLLSAICFGR_PLLSAIR_MORT ((uint32_t)0x70000000) |
| rajathr | 0:34ee385f4d2d | 4906 | #define RCC_PLLSAICFGR_PLLSAIR_0_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4907 | #define RCC_PLLSAICFGR_PLLSAIR_1_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4908 | #define RCC_PLLSAICFGR_PLLSAIR_2_MORT ((uint32_t)0x40000000) |
| rajathr | 0:34ee385f4d2d | 4909 | |
| rajathr | 0:34ee385f4d2d | 4910 | /******************** Bit definition for RCC_DCKCFGR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4911 | #define RCC_DCKCFGR_PLLI2SDIVQ_MORT ((uint32_t)0x0000001F) |
| rajathr | 0:34ee385f4d2d | 4912 | #define RCC_DCKCFGR_PLLSAIDIVQ_MORT ((uint32_t)0x00001F00) |
| rajathr | 0:34ee385f4d2d | 4913 | #define RCC_DCKCFGR_PLLSAIDIVR_MORT ((uint32_t)0x00030000) |
| rajathr | 0:34ee385f4d2d | 4914 | |
| rajathr | 0:34ee385f4d2d | 4915 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4916 | |
| rajathr | 0:34ee385f4d2d | 4917 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4918 | |
| rajathr | 0:34ee385f4d2d | 4919 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4920 | |
| rajathr | 0:34ee385f4d2d | 4921 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4922 | |
| rajathr | 0:34ee385f4d2d | 4923 | #define RCC_DCKCFGR_SAI1ASRC_MORT ((uint32_t)0x00300000) |
| rajathr | 0:34ee385f4d2d | 4924 | #define RCC_DCKCFGR_SAI1ASRC_0_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4925 | #define RCC_DCKCFGR_SAI1ASRC_1_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4926 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4927 | #define RCC_DCKCFGR_SAI1SRC_MORT ((uint32_t)0x00300000) |
| rajathr | 0:34ee385f4d2d | 4928 | #define RCC_DCKCFGR_SAI1SRC_0_MORT ((uint32_t)0x00100000) |
| rajathr | 0:34ee385f4d2d | 4929 | #define RCC_DCKCFGR_SAI1SRC_1_MORT ((uint32_t)0x00200000) |
| rajathr | 0:34ee385f4d2d | 4930 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4931 | |
| rajathr | 0:34ee385f4d2d | 4932 | #define RCC_DCKCFGR_SAI1BSRC_MORT ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 4933 | #define RCC_DCKCFGR_SAI1BSRC_0_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4934 | #define RCC_DCKCFGR_SAI1BSRC_1_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4935 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4936 | #define RCC_DCKCFGR_SAI2SRC_MORT ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 4937 | #define RCC_DCKCFGR_SAI2SRC_0_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4938 | #define RCC_DCKCFGR_SAI2SRC_1_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4939 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4940 | |
| rajathr | 0:34ee385f4d2d | 4941 | #define RCC_DCKCFGR_TIMPRE_MORT ((uint32_t)0x01000000) |
| rajathr | 0:34ee385f4d2d | 4942 | #if defined(STM32F469_479xx) |
| rajathr | 0:34ee385f4d2d | 4943 | |
| rajathr | 0:34ee385f4d2d | 4944 | #endif /* STM32F469_479xx */ |
| rajathr | 0:34ee385f4d2d | 4945 | |
| rajathr | 0:34ee385f4d2d | 4946 | #if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4947 | #define RCC_DCKCFGR_I2S1SRC_MORT ((uint32_t)0x06000000) |
| rajathr | 0:34ee385f4d2d | 4948 | #define RCC_DCKCFGR_I2S1SRC_0_MORT ((uint32_t)0x02000000) |
| rajathr | 0:34ee385f4d2d | 4949 | #define RCC_DCKCFGR_I2S1SRC_1_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4950 | #define RCC_DCKCFGR_I2S2SRC_MORT ((uint32_t)0x18000000) |
| rajathr | 0:34ee385f4d2d | 4951 | #define RCC_DCKCFGR_I2S2SRC_0_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4952 | #define RCC_DCKCFGR_I2S2SRC_1_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4953 | |
| rajathr | 0:34ee385f4d2d | 4954 | /******************** Bit definition for RCC_CKGATENR register ***************/ |
| rajathr | 0:34ee385f4d2d | 4955 | #define RCC_CKGATENR_AHB2APB1_CKEN_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 4956 | #define RCC_CKGATENR_AHB2APB2_CKEN_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 4957 | #define RCC_CKGATENR_CM4DBG_CKEN_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4958 | #define RCC_CKGATENR_SPARE_CKEN_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4959 | #define RCC_CKGATENR_SRAM_CKEN_MORT ((uint32_t)0x00000010) |
| rajathr | 0:34ee385f4d2d | 4960 | #define RCC_CKGATENR_FLITF_CKEN_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 4961 | #define RCC_CKGATENR_RCC_CKEN_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 4962 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4963 | |
| rajathr | 0:34ee385f4d2d | 4964 | #endif /* STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4965 | |
| rajathr | 0:34ee385f4d2d | 4966 | /******************** Bit definition for RCC_DCKCFGR2 register ***************/ |
| rajathr | 0:34ee385f4d2d | 4967 | #define RCC_DCKCFGR2_FMPI2C1SEL_MORT ((uint32_t)0x00C00000) |
| rajathr | 0:34ee385f4d2d | 4968 | #define RCC_DCKCFGR2_FMPI2C1SEL_0_MORT ((uint32_t)0x00400000) |
| rajathr | 0:34ee385f4d2d | 4969 | #define RCC_DCKCFGR2_FMPI2C1SEL_1_MORT ((uint32_t)0x00800000) |
| rajathr | 0:34ee385f4d2d | 4970 | #define RCC_DCKCFGR2_CECSEL_MORT ((uint32_t)0x04000000) |
| rajathr | 0:34ee385f4d2d | 4971 | #define RCC_DCKCFGR2_CK48MSEL_MORT ((uint32_t)0x08000000) |
| rajathr | 0:34ee385f4d2d | 4972 | #define RCC_DCKCFGR2_SDIOSEL_MORT ((uint32_t)0x10000000) |
| rajathr | 0:34ee385f4d2d | 4973 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 4974 | #define RCC_DCKCFGR2_SPDIFRXSEL_MORT ((uint32_t)0x20000000) |
| rajathr | 0:34ee385f4d2d | 4975 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4976 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 4977 | |
| rajathr | 0:34ee385f4d2d | 4978 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 4979 | #endif /* STM32F412xG || STM32F413_423xx || STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 4980 | |
| rajathr | 0:34ee385f4d2d | 4981 | #if defined(STM32F410xx) |
| rajathr | 0:34ee385f4d2d | 4982 | |
| rajathr | 0:34ee385f4d2d | 4983 | #endif /* STM32F410xx */ |
| rajathr | 0:34ee385f4d2d | 4984 | |
| rajathr | 0:34ee385f4d2d | 4985 | #if defined(STM32F410xx) |
| rajathr | 0:34ee385f4d2d | 4986 | /******************** Bit definition for RCC_DCKCFGR2 register **************/ |
| rajathr | 0:34ee385f4d2d | 4987 | |
| rajathr | 0:34ee385f4d2d | 4988 | #endif /* STM32F410xx */ |
| rajathr | 0:34ee385f4d2d | 4989 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4990 | /* */ |
| rajathr | 0:34ee385f4d2d | 4991 | /* RNG_MORT */ |
| rajathr | 0:34ee385f4d2d | 4992 | /* */ |
| rajathr | 0:34ee385f4d2d | 4993 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 4994 | /******************** Bits definition for RNG_CR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4995 | #define RNG_CR_RNGEN_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 4996 | #define RNG_CR_IE_MORT ((uint32_t)0x00000008) |
| rajathr | 0:34ee385f4d2d | 4997 | |
| rajathr | 0:34ee385f4d2d | 4998 | /******************** Bits definition for RNG_SR register *******************/ |
| rajathr | 0:34ee385f4d2d | 4999 | #define RNG_SR_DRDY_MORT ((uint32_t)0x00000001) |
| rajathr | 0:34ee385f4d2d | 5000 | #define RNG_SR_CECS_MORT ((uint32_t)0x00000002) |
| rajathr | 0:34ee385f4d2d | 5001 | #define RNG_SR_SECS_MORT ((uint32_t)0x00000004) |
| rajathr | 0:34ee385f4d2d | 5002 | #define RNG_SR_CEIS_MORT ((uint32_t)0x00000020) |
| rajathr | 0:34ee385f4d2d | 5003 | #define RNG_SR_SEIS_MORT ((uint32_t)0x00000040) |
| rajathr | 0:34ee385f4d2d | 5004 | |
| rajathr | 0:34ee385f4d2d | 5005 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5006 | /* */ |
| rajathr | 0:34ee385f4d2d | 5007 | /* Real-Time Clock (RTC_MORT) */ |
| rajathr | 0:34ee385f4d2d | 5008 | /* */ |
| rajathr | 0:34ee385f4d2d | 5009 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5010 | /******************** Bits definition for RTC_TR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5011 | |
| rajathr | 0:34ee385f4d2d | 5012 | |
| rajathr | 0:34ee385f4d2d | 5013 | /******************** Bits definition for RTC_DR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5014 | |
| rajathr | 0:34ee385f4d2d | 5015 | |
| rajathr | 0:34ee385f4d2d | 5016 | /******************** Bits definition for RTC_CR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5017 | |
| rajathr | 0:34ee385f4d2d | 5018 | |
| rajathr | 0:34ee385f4d2d | 5019 | /******************** Bits definition for RTC_ISR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5020 | |
| rajathr | 0:34ee385f4d2d | 5021 | |
| rajathr | 0:34ee385f4d2d | 5022 | /******************** Bits definition for RTC_PRER register *****************/ |
| rajathr | 0:34ee385f4d2d | 5023 | |
| rajathr | 0:34ee385f4d2d | 5024 | |
| rajathr | 0:34ee385f4d2d | 5025 | /******************** Bits definition for RTC_WUTR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5026 | |
| rajathr | 0:34ee385f4d2d | 5027 | /******************** Bits definition for RTC_CALIBR register ***************/ |
| rajathr | 0:34ee385f4d2d | 5028 | |
| rajathr | 0:34ee385f4d2d | 5029 | |
| rajathr | 0:34ee385f4d2d | 5030 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
| rajathr | 0:34ee385f4d2d | 5031 | |
| rajathr | 0:34ee385f4d2d | 5032 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
| rajathr | 0:34ee385f4d2d | 5033 | |
| rajathr | 0:34ee385f4d2d | 5034 | /******************** Bits definition for RTC_WPR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5035 | |
| rajathr | 0:34ee385f4d2d | 5036 | |
| rajathr | 0:34ee385f4d2d | 5037 | /******************** Bits definition for RTC_SSR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5038 | |
| rajathr | 0:34ee385f4d2d | 5039 | |
| rajathr | 0:34ee385f4d2d | 5040 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
| rajathr | 0:34ee385f4d2d | 5041 | |
| rajathr | 0:34ee385f4d2d | 5042 | |
| rajathr | 0:34ee385f4d2d | 5043 | /******************** Bits definition for RTC_TSTR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5044 | |
| rajathr | 0:34ee385f4d2d | 5045 | |
| rajathr | 0:34ee385f4d2d | 5046 | /******************** Bits definition for RTC_TSDR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5047 | |
| rajathr | 0:34ee385f4d2d | 5048 | /******************** Bits definition for RTC_TSSSR register ****************/ |
| rajathr | 0:34ee385f4d2d | 5049 | |
| rajathr | 0:34ee385f4d2d | 5050 | |
| rajathr | 0:34ee385f4d2d | 5051 | /******************** Bits definition for RTC_CAL register *****************/ |
| rajathr | 0:34ee385f4d2d | 5052 | |
| rajathr | 0:34ee385f4d2d | 5053 | /******************** Bits definition for RTC_TAFCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 5054 | |
| rajathr | 0:34ee385f4d2d | 5055 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
| rajathr | 0:34ee385f4d2d | 5056 | |
| rajathr | 0:34ee385f4d2d | 5057 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
| rajathr | 0:34ee385f4d2d | 5058 | |
| rajathr | 0:34ee385f4d2d | 5059 | /******************** Bits definition for RTC_BKP0R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5060 | |
| rajathr | 0:34ee385f4d2d | 5061 | /******************** Bits definition for RTC_BKP1R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5062 | |
| rajathr | 0:34ee385f4d2d | 5063 | /******************** Bits definition for RTC_BKP2R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5064 | |
| rajathr | 0:34ee385f4d2d | 5065 | /******************** Bits definition for RTC_BKP3R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5066 | |
| rajathr | 0:34ee385f4d2d | 5067 | /******************** Bits definition for RTC_BKP4R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5068 | |
| rajathr | 0:34ee385f4d2d | 5069 | /******************** Bits definition for RTC_BKP5R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5070 | |
| rajathr | 0:34ee385f4d2d | 5071 | /******************** Bits definition for RTC_BKP6R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5072 | |
| rajathr | 0:34ee385f4d2d | 5073 | /******************** Bits definition for RTC_BKP7R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5074 | |
| rajathr | 0:34ee385f4d2d | 5075 | /******************** Bits definition for RTC_BKP8R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5076 | |
| rajathr | 0:34ee385f4d2d | 5077 | |
| rajathr | 0:34ee385f4d2d | 5078 | /******************** Bits definition for RTC_BKP9R register ****************/ |
| rajathr | 0:34ee385f4d2d | 5079 | |
| rajathr | 0:34ee385f4d2d | 5080 | |
| rajathr | 0:34ee385f4d2d | 5081 | /******************** Bits definition for RTC_BKP10R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5082 | |
| rajathr | 0:34ee385f4d2d | 5083 | /******************** Bits definition for RTC_BKP11R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5084 | |
| rajathr | 0:34ee385f4d2d | 5085 | /******************** Bits definition for RTC_BKP12R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5086 | |
| rajathr | 0:34ee385f4d2d | 5087 | /******************** Bits definition for RTC_BKP13R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5088 | |
| rajathr | 0:34ee385f4d2d | 5089 | /******************** Bits definition for RTC_BKP14R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5090 | |
| rajathr | 0:34ee385f4d2d | 5091 | /******************** Bits definition for RTC_BKP15R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5092 | |
| rajathr | 0:34ee385f4d2d | 5093 | /******************** Bits definition for RTC_BKP16R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5094 | |
| rajathr | 0:34ee385f4d2d | 5095 | |
| rajathr | 0:34ee385f4d2d | 5096 | /******************** Bits definition for RTC_BKP17R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5097 | |
| rajathr | 0:34ee385f4d2d | 5098 | /******************** Bits definition for RTC_BKP18R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5099 | |
| rajathr | 0:34ee385f4d2d | 5100 | /******************** Bits definition for RTC_BKP19R register ***************/ |
| rajathr | 0:34ee385f4d2d | 5101 | |
| rajathr | 0:34ee385f4d2d | 5102 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5103 | /* */ |
| rajathr | 0:34ee385f4d2d | 5104 | /* Serial Audio Interface */ |
| rajathr | 0:34ee385f4d2d | 5105 | /* */ |
| rajathr | 0:34ee385f4d2d | 5106 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5107 | /******************** Bit definition for SAI_GCR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5108 | |
| rajathr | 0:34ee385f4d2d | 5109 | /******************* Bit definition for SAI_xCR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5110 | |
| rajathr | 0:34ee385f4d2d | 5111 | /******************* Bit definition for SAI_xCR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5112 | |
| rajathr | 0:34ee385f4d2d | 5113 | /****************** Bit definition for SAI_xFRCR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5114 | |
| rajathr | 0:34ee385f4d2d | 5115 | |
| rajathr | 0:34ee385f4d2d | 5116 | /****************** Bit definition for SAI_xSLOTR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5117 | |
| rajathr | 0:34ee385f4d2d | 5118 | /******************* Bit definition for SAI_xIMR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5119 | |
| rajathr | 0:34ee385f4d2d | 5120 | /******************** Bit definition for SAI_xSR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5121 | |
| rajathr | 0:34ee385f4d2d | 5122 | /****************** Bit definition for SAI_xCLRFR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5123 | |
| rajathr | 0:34ee385f4d2d | 5124 | /****************** Bit definition for SAI_xDR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5125 | |
| rajathr | 0:34ee385f4d2d | 5126 | |
| rajathr | 0:34ee385f4d2d | 5127 | #if defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 5128 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5129 | /* */ |
| rajathr | 0:34ee385f4d2d | 5130 | /* SPDIF-RX Interface */ |
| rajathr | 0:34ee385f4d2d | 5131 | /* */ |
| rajathr | 0:34ee385f4d2d | 5132 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5133 | /******************** Bit definition for SPDIFRX_CR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5134 | |
| rajathr | 0:34ee385f4d2d | 5135 | /******************* Bit definition for SPDIFRX_IMR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5136 | |
| rajathr | 0:34ee385f4d2d | 5137 | /******************* Bit definition for SPDIFRX_SR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5138 | |
| rajathr | 0:34ee385f4d2d | 5139 | /******************* Bit definition for SPDIFRX_IFCR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5140 | |
| rajathr | 0:34ee385f4d2d | 5141 | /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/ |
| rajathr | 0:34ee385f4d2d | 5142 | |
| rajathr | 0:34ee385f4d2d | 5143 | /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/ |
| rajathr | 0:34ee385f4d2d | 5144 | |
| rajathr | 0:34ee385f4d2d | 5145 | /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/ |
| rajathr | 0:34ee385f4d2d | 5146 | |
| rajathr | 0:34ee385f4d2d | 5147 | /******************* Bit definition for SPDIFRX_CSR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5148 | |
| rajathr | 0:34ee385f4d2d | 5149 | /******************* Bit definition for SPDIFRX_DIR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5150 | |
| rajathr | 0:34ee385f4d2d | 5151 | #endif /* STM32F446xx_MORT */ |
| rajathr | 0:34ee385f4d2d | 5152 | |
| rajathr | 0:34ee385f4d2d | 5153 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5154 | /* */ |
| rajathr | 0:34ee385f4d2d | 5155 | /* SD host Interface */ |
| rajathr | 0:34ee385f4d2d | 5156 | /* */ |
| rajathr | 0:34ee385f4d2d | 5157 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5158 | /****************** Bit definition for SDIO_POWER register ******************/ |
| rajathr | 0:34ee385f4d2d | 5159 | |
| rajathr | 0:34ee385f4d2d | 5160 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5161 | |
| rajathr | 0:34ee385f4d2d | 5162 | /******************* Bit definition for SDIO_ARG register *******************/ |
| rajathr | 0:34ee385f4d2d | 5163 | |
| rajathr | 0:34ee385f4d2d | 5164 | /******************* Bit definition for SDIO_CMD register *******************/ |
| rajathr | 0:34ee385f4d2d | 5165 | |
| rajathr | 0:34ee385f4d2d | 5166 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
| rajathr | 0:34ee385f4d2d | 5167 | |
| rajathr | 0:34ee385f4d2d | 5168 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
| rajathr | 0:34ee385f4d2d | 5169 | |
| rajathr | 0:34ee385f4d2d | 5170 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
| rajathr | 0:34ee385f4d2d | 5171 | |
| rajathr | 0:34ee385f4d2d | 5172 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
| rajathr | 0:34ee385f4d2d | 5173 | |
| rajathr | 0:34ee385f4d2d | 5174 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
| rajathr | 0:34ee385f4d2d | 5175 | |
| rajathr | 0:34ee385f4d2d | 5176 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
| rajathr | 0:34ee385f4d2d | 5177 | |
| rajathr | 0:34ee385f4d2d | 5178 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
| rajathr | 0:34ee385f4d2d | 5179 | |
| rajathr | 0:34ee385f4d2d | 5180 | /****************** Bit definition for SDIO_DLEN register *******************/ |
| rajathr | 0:34ee385f4d2d | 5181 | |
| rajathr | 0:34ee385f4d2d | 5182 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
| rajathr | 0:34ee385f4d2d | 5183 | |
| rajathr | 0:34ee385f4d2d | 5184 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
| rajathr | 0:34ee385f4d2d | 5185 | |
| rajathr | 0:34ee385f4d2d | 5186 | /****************** Bit definition for SDIO_STA register ********************/ |
| rajathr | 0:34ee385f4d2d | 5187 | |
| rajathr | 0:34ee385f4d2d | 5188 | /******************* Bit definition for SDIO_ICR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5189 | |
| rajathr | 0:34ee385f4d2d | 5190 | |
| rajathr | 0:34ee385f4d2d | 5191 | /****************** Bit definition for SDIO_MASK register *******************/ |
| rajathr | 0:34ee385f4d2d | 5192 | |
| rajathr | 0:34ee385f4d2d | 5193 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
| rajathr | 0:34ee385f4d2d | 5194 | |
| rajathr | 0:34ee385f4d2d | 5195 | /****************** Bit definition for SDIO_FIFO register *******************/ |
| rajathr | 0:34ee385f4d2d | 5196 | |
| rajathr | 0:34ee385f4d2d | 5197 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5198 | /* */ |
| rajathr | 0:34ee385f4d2d | 5199 | /* Serial Peripheral Interface */ |
| rajathr | 0:34ee385f4d2d | 5200 | /* */ |
| rajathr | 0:34ee385f4d2d | 5201 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5202 | /******************* Bit definition for SPI_CR1 register ********************/ |
| rajathr | 0:34ee385f4d2d | 5203 | #define SPI_CR1_CPHA_MORT ((uint16_t)0x0001) /*!<Clock Phase */ |
| rajathr | 0:34ee385f4d2d | 5204 | #define SPI_CR1_CPOL_MORT ((uint16_t)0x0002) /*!<Clock Polarity */ |
| rajathr | 0:34ee385f4d2d | 5205 | #define SPI_CR1_MSTR_MORT ((uint16_t)0x0004) /*!<Master Selection */ |
| rajathr | 0:34ee385f4d2d | 5206 | |
| rajathr | 0:34ee385f4d2d | 5207 | #define SPI_CR1_BR_MORT ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */ |
| rajathr | 0:34ee385f4d2d | 5208 | #define SPI_CR1_BR_0_MORT ((uint16_t)0x0008) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5209 | #define SPI_CR1_BR_1_MORT ((uint16_t)0x0010) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5210 | #define SPI_CR1_BR_2_MORT ((uint16_t)0x0020) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5211 | |
| rajathr | 0:34ee385f4d2d | 5212 | #define SPI_CR1_SPE_MORT ((uint16_t)0x0040) /*!<SPI Enable */ |
| rajathr | 0:34ee385f4d2d | 5213 | #define SPI_CR1_LSBFIRST_MORT ((uint16_t)0x0080) /*!<Frame Format */ |
| rajathr | 0:34ee385f4d2d | 5214 | #define SPI_CR1_SSI_MORT ((uint16_t)0x0100) /*!<Internal slave select */ |
| rajathr | 0:34ee385f4d2d | 5215 | #define SPI_CR1_SSM_MORT ((uint16_t)0x0200) /*!<Software slave management */ |
| rajathr | 0:34ee385f4d2d | 5216 | #define SPI_CR1_RXONLY_MORT ((uint16_t)0x0400) /*!<Receive only */ |
| rajathr | 0:34ee385f4d2d | 5217 | #define SPI_CR1_DFF_MORT ((uint16_t)0x0800) /*!<Data Frame Format */ |
| rajathr | 0:34ee385f4d2d | 5218 | #define SPI_CR1_CRCNEXT_MORT ((uint16_t)0x1000) /*!<Transmit CRC_MORT next */ |
| rajathr | 0:34ee385f4d2d | 5219 | #define SPI_CR1_CRCEN_MORT ((uint16_t)0x2000) /*!<Hardware CRC_MORT calculation enable */ |
| rajathr | 0:34ee385f4d2d | 5220 | #define SPI_CR1_BIDIOE_MORT ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */ |
| rajathr | 0:34ee385f4d2d | 5221 | #define SPI_CR1_BIDIMODE_MORT ((uint16_t)0x8000) /*!<Bidirectional data mode enable */ |
| rajathr | 0:34ee385f4d2d | 5222 | |
| rajathr | 0:34ee385f4d2d | 5223 | /******************* Bit definition for SPI_CR2 register ********************/ |
| rajathr | 0:34ee385f4d2d | 5224 | #define SPI_CR2_RXDMAEN_MORT ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */ |
| rajathr | 0:34ee385f4d2d | 5225 | #define SPI_CR2_TXDMAEN_MORT ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */ |
| rajathr | 0:34ee385f4d2d | 5226 | #define SPI_CR2_SSOE_MORT ((uint8_t)0x04) /*!<SS Output Enable */ |
| rajathr | 0:34ee385f4d2d | 5227 | #define SPI_CR2_ERRIE_MORT ((uint8_t)0x20) /*!<Error Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 5228 | #define SPI_CR2_RXNEIE_MORT ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 5229 | #define SPI_CR2_TXEIE_MORT ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */ |
| rajathr | 0:34ee385f4d2d | 5230 | |
| rajathr | 0:34ee385f4d2d | 5231 | /******************** Bit definition for SPI_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5232 | #define SPI_SR_RXNE_MORT ((uint8_t)0x01) /*!<Receive buffer Not Empty */ |
| rajathr | 0:34ee385f4d2d | 5233 | #define SPI_SR_TXE_MORT ((uint8_t)0x02) /*!<Transmit buffer Empty */ |
| rajathr | 0:34ee385f4d2d | 5234 | #define SPI_SR_CHSIDE_MORT ((uint8_t)0x04) /*!<Channel side */ |
| rajathr | 0:34ee385f4d2d | 5235 | #define SPI_SR_UDR_MORT ((uint8_t)0x08) /*!<Underrun flag */ |
| rajathr | 0:34ee385f4d2d | 5236 | #define SPI_SR_CRCERR_MORT ((uint8_t)0x10) /*!<CRC_MORT Error flag */ |
| rajathr | 0:34ee385f4d2d | 5237 | #define SPI_SR_MODF_MORT ((uint8_t)0x20) /*!<Mode fault */ |
| rajathr | 0:34ee385f4d2d | 5238 | #define SPI_SR_OVR_MORT ((uint8_t)0x40) /*!<Overrun flag */ |
| rajathr | 0:34ee385f4d2d | 5239 | #define SPI_SR_BSY_MORT ((uint8_t)0x80) /*!<Busy flag */ |
| rajathr | 0:34ee385f4d2d | 5240 | |
| rajathr | 0:34ee385f4d2d | 5241 | /******************** Bit definition for SPI_DR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5242 | #define SPI_DR_DR_MORT ((uint16_t)0xFFFF) /*!<Data Register */ |
| rajathr | 0:34ee385f4d2d | 5243 | |
| rajathr | 0:34ee385f4d2d | 5244 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5245 | #define SPI_CRCPR_CRCPOLY_MORT ((uint16_t)0xFFFF) /*!<CRC_MORT polynomial register */ |
| rajathr | 0:34ee385f4d2d | 5246 | |
| rajathr | 0:34ee385f4d2d | 5247 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5248 | #define SPI_RXCRCR_RXCRC_MORT ((uint16_t)0xFFFF) /*!<Rx CRC_MORT Register */ |
| rajathr | 0:34ee385f4d2d | 5249 | |
| rajathr | 0:34ee385f4d2d | 5250 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5251 | #define SPI_TXCRCR_TXCRC_MORT ((uint16_t)0xFFFF) /*!<Tx CRC_MORT Register */ |
| rajathr | 0:34ee385f4d2d | 5252 | |
| rajathr | 0:34ee385f4d2d | 5253 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5254 | #define SPI_I2SCFGR_CHLEN_MORT ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ |
| rajathr | 0:34ee385f4d2d | 5255 | |
| rajathr | 0:34ee385f4d2d | 5256 | #define SPI_I2SCFGR_DATLEN_MORT ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
| rajathr | 0:34ee385f4d2d | 5257 | #define SPI_I2SCFGR_DATLEN_0_MORT ((uint16_t)0x0002) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5258 | #define SPI_I2SCFGR_DATLEN_1_MORT ((uint16_t)0x0004) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5259 | |
| rajathr | 0:34ee385f4d2d | 5260 | #define SPI_I2SCFGR_CKPOL_MORT ((uint16_t)0x0008) /*!<steady state clock polarity */ |
| rajathr | 0:34ee385f4d2d | 5261 | |
| rajathr | 0:34ee385f4d2d | 5262 | #define SPI_I2SCFGR_I2SSTD_MORT ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
| rajathr | 0:34ee385f4d2d | 5263 | #define SPI_I2SCFGR_I2SSTD_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5264 | #define SPI_I2SCFGR_I2SSTD_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5265 | |
| rajathr | 0:34ee385f4d2d | 5266 | #define SPI_I2SCFGR_PCMSYNC_MORT ((uint16_t)0x0080) /*!<PCM frame synchronization */ |
| rajathr | 0:34ee385f4d2d | 5267 | |
| rajathr | 0:34ee385f4d2d | 5268 | #define SPI_I2SCFGR_I2SCFG_MORT ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
| rajathr | 0:34ee385f4d2d | 5269 | #define SPI_I2SCFGR_I2SCFG_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5270 | #define SPI_I2SCFGR_I2SCFG_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5271 | |
| rajathr | 0:34ee385f4d2d | 5272 | #define SPI_I2SCFGR_I2SE_MORT ((uint16_t)0x0400) /*!<I2S Enable */ |
| rajathr | 0:34ee385f4d2d | 5273 | #define SPI_I2SCFGR_I2SMOD_MORT ((uint16_t)0x0800) /*!<I2S mode selection */ |
| rajathr | 0:34ee385f4d2d | 5274 | #if defined(STM32F413_423xx) || defined(STM32F446xx_MORT) |
| rajathr | 0:34ee385f4d2d | 5275 | #define SPI_I2SCFGR_ASTRTEN_MORT ((uint16_t)0x1000) /*!<Asynchronous start enable */ |
| rajathr | 0:34ee385f4d2d | 5276 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 5277 | |
| rajathr | 0:34ee385f4d2d | 5278 | /****************** Bit definition for SPI_I2SPR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5279 | #define SPI_I2SPR_I2SDIV_MORT ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ |
| rajathr | 0:34ee385f4d2d | 5280 | #define SPI_I2SPR_ODD_MORT ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ |
| rajathr | 0:34ee385f4d2d | 5281 | #define SPI_I2SPR_MCKOE_MORT ((uint16_t)0x0200) /*!<Master Clock Output Enable */ |
| rajathr | 0:34ee385f4d2d | 5282 | |
| rajathr | 0:34ee385f4d2d | 5283 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5284 | /* */ |
| rajathr | 0:34ee385f4d2d | 5285 | /* SYSCFG_MORT */ |
| rajathr | 0:34ee385f4d2d | 5286 | /* */ |
| rajathr | 0:34ee385f4d2d | 5287 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5288 | /****************** Bit definition for SYSCFG_MEMRMP register ***************/ |
| rajathr | 0:34ee385f4d2d | 5289 | |
| rajathr | 0:34ee385f4d2d | 5290 | /****************** Bit definition for SYSCFG_PMC register ******************/ |
| rajathr | 0:34ee385f4d2d | 5291 | |
| rajathr | 0:34ee385f4d2d | 5292 | |
| rajathr | 0:34ee385f4d2d | 5293 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
| rajathr | 0:34ee385f4d2d | 5294 | |
| rajathr | 0:34ee385f4d2d | 5295 | /** |
| rajathr | 0:34ee385f4d2d | 5296 | * @brief EXTI0 configuration |
| rajathr | 0:34ee385f4d2d | 5297 | */ |
| rajathr | 0:34ee385f4d2d | 5298 | |
| rajathr | 0:34ee385f4d2d | 5299 | |
| rajathr | 0:34ee385f4d2d | 5300 | /** |
| rajathr | 0:34ee385f4d2d | 5301 | * @brief EXTI1 configuration |
| rajathr | 0:34ee385f4d2d | 5302 | */ |
| rajathr | 0:34ee385f4d2d | 5303 | |
| rajathr | 0:34ee385f4d2d | 5304 | |
| rajathr | 0:34ee385f4d2d | 5305 | /** |
| rajathr | 0:34ee385f4d2d | 5306 | * @brief EXTI2 configuration |
| rajathr | 0:34ee385f4d2d | 5307 | */ |
| rajathr | 0:34ee385f4d2d | 5308 | |
| rajathr | 0:34ee385f4d2d | 5309 | |
| rajathr | 0:34ee385f4d2d | 5310 | |
| rajathr | 0:34ee385f4d2d | 5311 | /** |
| rajathr | 0:34ee385f4d2d | 5312 | * @brief EXTI3 configuration |
| rajathr | 0:34ee385f4d2d | 5313 | */ |
| rajathr | 0:34ee385f4d2d | 5314 | |
| rajathr | 0:34ee385f4d2d | 5315 | |
| rajathr | 0:34ee385f4d2d | 5316 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
| rajathr | 0:34ee385f4d2d | 5317 | |
| rajathr | 0:34ee385f4d2d | 5318 | /** |
| rajathr | 0:34ee385f4d2d | 5319 | * @brief EXTI4 configuration |
| rajathr | 0:34ee385f4d2d | 5320 | */ |
| rajathr | 0:34ee385f4d2d | 5321 | |
| rajathr | 0:34ee385f4d2d | 5322 | |
| rajathr | 0:34ee385f4d2d | 5323 | /** |
| rajathr | 0:34ee385f4d2d | 5324 | * @brief EXTI5 configuration |
| rajathr | 0:34ee385f4d2d | 5325 | */ |
| rajathr | 0:34ee385f4d2d | 5326 | |
| rajathr | 0:34ee385f4d2d | 5327 | |
| rajathr | 0:34ee385f4d2d | 5328 | /** |
| rajathr | 0:34ee385f4d2d | 5329 | * @brief EXTI6 configuration |
| rajathr | 0:34ee385f4d2d | 5330 | */ |
| rajathr | 0:34ee385f4d2d | 5331 | |
| rajathr | 0:34ee385f4d2d | 5332 | |
| rajathr | 0:34ee385f4d2d | 5333 | /** |
| rajathr | 0:34ee385f4d2d | 5334 | * @brief EXTI7 configuration |
| rajathr | 0:34ee385f4d2d | 5335 | */ |
| rajathr | 0:34ee385f4d2d | 5336 | |
| rajathr | 0:34ee385f4d2d | 5337 | |
| rajathr | 0:34ee385f4d2d | 5338 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
| rajathr | 0:34ee385f4d2d | 5339 | |
| rajathr | 0:34ee385f4d2d | 5340 | /** |
| rajathr | 0:34ee385f4d2d | 5341 | * @brief EXTI8 configuration |
| rajathr | 0:34ee385f4d2d | 5342 | */ |
| rajathr | 0:34ee385f4d2d | 5343 | |
| rajathr | 0:34ee385f4d2d | 5344 | |
| rajathr | 0:34ee385f4d2d | 5345 | /** |
| rajathr | 0:34ee385f4d2d | 5346 | * @brief EXTI9 configuration |
| rajathr | 0:34ee385f4d2d | 5347 | */ |
| rajathr | 0:34ee385f4d2d | 5348 | |
| rajathr | 0:34ee385f4d2d | 5349 | |
| rajathr | 0:34ee385f4d2d | 5350 | /** |
| rajathr | 0:34ee385f4d2d | 5351 | * @brief EXTI10 configuration |
| rajathr | 0:34ee385f4d2d | 5352 | */ |
| rajathr | 0:34ee385f4d2d | 5353 | |
| rajathr | 0:34ee385f4d2d | 5354 | |
| rajathr | 0:34ee385f4d2d | 5355 | /** |
| rajathr | 0:34ee385f4d2d | 5356 | * @brief EXTI11 configuration |
| rajathr | 0:34ee385f4d2d | 5357 | */ |
| rajathr | 0:34ee385f4d2d | 5358 | |
| rajathr | 0:34ee385f4d2d | 5359 | |
| rajathr | 0:34ee385f4d2d | 5360 | /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ |
| rajathr | 0:34ee385f4d2d | 5361 | |
| rajathr | 0:34ee385f4d2d | 5362 | /** |
| rajathr | 0:34ee385f4d2d | 5363 | * @brief EXTI12 configuration |
| rajathr | 0:34ee385f4d2d | 5364 | */ |
| rajathr | 0:34ee385f4d2d | 5365 | |
| rajathr | 0:34ee385f4d2d | 5366 | |
| rajathr | 0:34ee385f4d2d | 5367 | /** |
| rajathr | 0:34ee385f4d2d | 5368 | * @brief EXTI13 configuration |
| rajathr | 0:34ee385f4d2d | 5369 | */ |
| rajathr | 0:34ee385f4d2d | 5370 | |
| rajathr | 0:34ee385f4d2d | 5371 | |
| rajathr | 0:34ee385f4d2d | 5372 | /** |
| rajathr | 0:34ee385f4d2d | 5373 | * @brief EXTI14 configuration |
| rajathr | 0:34ee385f4d2d | 5374 | */ |
| rajathr | 0:34ee385f4d2d | 5375 | |
| rajathr | 0:34ee385f4d2d | 5376 | /** |
| rajathr | 0:34ee385f4d2d | 5377 | * @brief EXTI15 configuration |
| rajathr | 0:34ee385f4d2d | 5378 | */ |
| rajathr | 0:34ee385f4d2d | 5379 | |
| rajathr | 0:34ee385f4d2d | 5380 | |
| rajathr | 0:34ee385f4d2d | 5381 | #if defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 5382 | /****************** Bit definition for SYSCFG_CFGR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5383 | |
| rajathr | 0:34ee385f4d2d | 5384 | #endif /* STM32F412xG || STM32413_423xx */ |
| rajathr | 0:34ee385f4d2d | 5385 | |
| rajathr | 0:34ee385f4d2d | 5386 | #if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 5387 | /****************** Bit definition for SYSCFG_CFGR2 register ****************/ |
| rajathr | 0:34ee385f4d2d | 5388 | |
| rajathr | 0:34ee385f4d2d | 5389 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 5390 | /****************** Bit definition for SYSCFG_CMPCR register ****************/ |
| rajathr | 0:34ee385f4d2d | 5391 | |
| rajathr | 0:34ee385f4d2d | 5392 | #if defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 5393 | /****************** Bit definition for SYSCFG_MCHDLYCR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5394 | |
| rajathr | 0:34ee385f4d2d | 5395 | #endif /* STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 5396 | |
| rajathr | 0:34ee385f4d2d | 5397 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5398 | /* */ |
| rajathr | 0:34ee385f4d2d | 5399 | /* TIM */ |
| rajathr | 0:34ee385f4d2d | 5400 | /* */ |
| rajathr | 0:34ee385f4d2d | 5401 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5402 | /******************* Bit definition for TIM_CR1 register ********************/ |
| rajathr | 0:34ee385f4d2d | 5403 | #define TIM_CR1_CEN_MORT ((uint16_t)0x0001) /*!<Counter enable */ |
| rajathr | 0:34ee385f4d2d | 5404 | #define TIM_CR1_UDIS_MORT ((uint16_t)0x0002) /*!<Update disable */ |
| rajathr | 0:34ee385f4d2d | 5405 | #define TIM_CR1_URS_MORT ((uint16_t)0x0004) /*!<Update request source */ |
| rajathr | 0:34ee385f4d2d | 5406 | #define TIM_CR1_OPM_MORT ((uint16_t)0x0008) /*!<One pulse mode */ |
| rajathr | 0:34ee385f4d2d | 5407 | #define TIM_CR1_DIR_MORT ((uint16_t)0x0010) /*!<Direction */ |
| rajathr | 0:34ee385f4d2d | 5408 | |
| rajathr | 0:34ee385f4d2d | 5409 | #define TIM_CR1_CMS_MORT ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| rajathr | 0:34ee385f4d2d | 5410 | #define TIM_CR1_CMS_0_MORT ((uint16_t)0x0020) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5411 | #define TIM_CR1_CMS_1_MORT ((uint16_t)0x0040) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5412 | |
| rajathr | 0:34ee385f4d2d | 5413 | #define TIM_CR1_ARPE_MORT ((uint16_t)0x0080) /*!<Auto-reload preload enable */ |
| rajathr | 0:34ee385f4d2d | 5414 | |
| rajathr | 0:34ee385f4d2d | 5415 | #define TIM_CR1_CKD_MORT ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ |
| rajathr | 0:34ee385f4d2d | 5416 | #define TIM_CR1_CKD_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5417 | #define TIM_CR1_CKD_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5418 | |
| rajathr | 0:34ee385f4d2d | 5419 | /******************* Bit definition for TIM_CR2 register ********************/ |
| rajathr | 0:34ee385f4d2d | 5420 | #define TIM_CR2_CCPC_MORT ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ |
| rajathr | 0:34ee385f4d2d | 5421 | #define TIM_CR2_CCUS_MORT ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ |
| rajathr | 0:34ee385f4d2d | 5422 | #define TIM_CR2_CCDS_MORT ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ |
| rajathr | 0:34ee385f4d2d | 5423 | |
| rajathr | 0:34ee385f4d2d | 5424 | #define TIM_CR2_MMS_MORT ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
| rajathr | 0:34ee385f4d2d | 5425 | #define TIM_CR2_MMS_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5426 | #define TIM_CR2_MMS_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5427 | #define TIM_CR2_MMS_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5428 | |
| rajathr | 0:34ee385f4d2d | 5429 | #define TIM_CR2_TI1S_MORT ((uint16_t)0x0080) /*!<TI1 Selection */ |
| rajathr | 0:34ee385f4d2d | 5430 | #define TIM_CR2_OIS1_MORT ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ |
| rajathr | 0:34ee385f4d2d | 5431 | #define TIM_CR2_OIS1N_MORT ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ |
| rajathr | 0:34ee385f4d2d | 5432 | #define TIM_CR2_OIS2_MORT ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ |
| rajathr | 0:34ee385f4d2d | 5433 | #define TIM_CR2_OIS2N_MORT ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ |
| rajathr | 0:34ee385f4d2d | 5434 | #define TIM_CR2_OIS3_MORT ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ |
| rajathr | 0:34ee385f4d2d | 5435 | #define TIM_CR2_OIS3N_MORT ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ |
| rajathr | 0:34ee385f4d2d | 5436 | #define TIM_CR2_OIS4_MORT ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ |
| rajathr | 0:34ee385f4d2d | 5437 | |
| rajathr | 0:34ee385f4d2d | 5438 | /******************* Bit definition for TIM_SMCR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5439 | #define TIM_SMCR_SMS_MORT ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ |
| rajathr | 0:34ee385f4d2d | 5440 | #define TIM_SMCR_SMS_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5441 | #define TIM_SMCR_SMS_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5442 | #define TIM_SMCR_SMS_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5443 | |
| rajathr | 0:34ee385f4d2d | 5444 | #define TIM_SMCR_TS_MORT ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ |
| rajathr | 0:34ee385f4d2d | 5445 | #define TIM_SMCR_TS_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5446 | #define TIM_SMCR_TS_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5447 | #define TIM_SMCR_TS_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5448 | |
| rajathr | 0:34ee385f4d2d | 5449 | #define TIM_SMCR_MSM_MORT ((uint16_t)0x0080) /*!<Master/slave mode */ |
| rajathr | 0:34ee385f4d2d | 5450 | |
| rajathr | 0:34ee385f4d2d | 5451 | #define TIM_SMCR_ETF_MORT ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ |
| rajathr | 0:34ee385f4d2d | 5452 | #define TIM_SMCR_ETF_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5453 | #define TIM_SMCR_ETF_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5454 | #define TIM_SMCR_ETF_2_MORT ((uint16_t)0x0400) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5455 | #define TIM_SMCR_ETF_3_MORT ((uint16_t)0x0800) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5456 | |
| rajathr | 0:34ee385f4d2d | 5457 | #define TIM_SMCR_ETPS_MORT ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| rajathr | 0:34ee385f4d2d | 5458 | #define TIM_SMCR_ETPS_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5459 | #define TIM_SMCR_ETPS_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5460 | |
| rajathr | 0:34ee385f4d2d | 5461 | #define TIM_SMCR_ECE_MORT ((uint16_t)0x4000) /*!<External clock enable */ |
| rajathr | 0:34ee385f4d2d | 5462 | #define TIM_SMCR_ETP_MORT ((uint16_t)0x8000) /*!<External trigger polarity */ |
| rajathr | 0:34ee385f4d2d | 5463 | |
| rajathr | 0:34ee385f4d2d | 5464 | /******************* Bit definition for TIM_DIER register *******************/ |
| rajathr | 0:34ee385f4d2d | 5465 | #define TIM_DIER_UIE_MORT ((uint16_t)0x0001) /*!<Update interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5466 | #define TIM_DIER_CC1IE_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5467 | #define TIM_DIER_CC2IE_MORT ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5468 | #define TIM_DIER_CC3IE_MORT ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5469 | #define TIM_DIER_CC4IE_MORT ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5470 | #define TIM_DIER_COMIE_MORT ((uint16_t)0x0020) /*!<COM interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5471 | #define TIM_DIER_TIE_MORT ((uint16_t)0x0040) /*!<Trigger interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5472 | #define TIM_DIER_BIE_MORT ((uint16_t)0x0080) /*!<Break interrupt enable */ |
| rajathr | 0:34ee385f4d2d | 5473 | #define TIM_DIER_UDE_MORT ((uint16_t)0x0100) /*!<Update DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5474 | #define TIM_DIER_CC1DE_MORT ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5475 | #define TIM_DIER_CC2DE_MORT ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5476 | #define TIM_DIER_CC3DE_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5477 | #define TIM_DIER_CC4DE_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5478 | #define TIM_DIER_COMDE_MORT ((uint16_t)0x2000) /*!<COM DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5479 | #define TIM_DIER_TDE_MORT ((uint16_t)0x4000) /*!<Trigger DMA request enable */ |
| rajathr | 0:34ee385f4d2d | 5480 | |
| rajathr | 0:34ee385f4d2d | 5481 | /******************** Bit definition for TIM_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5482 | #define TIM_SR_UIF_MORT ((uint16_t)0x0001) /*!<Update interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5483 | #define TIM_SR_CC1IF_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5484 | #define TIM_SR_CC2IF_MORT ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5485 | #define TIM_SR_CC3IF_MORT ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5486 | #define TIM_SR_CC4IF_MORT ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5487 | #define TIM_SR_COMIF_MORT ((uint16_t)0x0020) /*!<COM interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5488 | #define TIM_SR_TIF_MORT ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5489 | #define TIM_SR_BIF_MORT ((uint16_t)0x0080) /*!<Break interrupt Flag */ |
| rajathr | 0:34ee385f4d2d | 5490 | #define TIM_SR_CC1OF_MORT ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ |
| rajathr | 0:34ee385f4d2d | 5491 | #define TIM_SR_CC2OF_MORT ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ |
| rajathr | 0:34ee385f4d2d | 5492 | #define TIM_SR_CC3OF_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ |
| rajathr | 0:34ee385f4d2d | 5493 | #define TIM_SR_CC4OF_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ |
| rajathr | 0:34ee385f4d2d | 5494 | |
| rajathr | 0:34ee385f4d2d | 5495 | /******************* Bit definition for TIM_EGR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5496 | #define TIM_EGR_UG_MORT ((uint8_t)0x01) /*!<Update Generation */ |
| rajathr | 0:34ee385f4d2d | 5497 | #define TIM_EGR_CC1G_MORT ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ |
| rajathr | 0:34ee385f4d2d | 5498 | #define TIM_EGR_CC2G_MORT ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ |
| rajathr | 0:34ee385f4d2d | 5499 | #define TIM_EGR_CC3G_MORT ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ |
| rajathr | 0:34ee385f4d2d | 5500 | #define TIM_EGR_CC4G_MORT ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ |
| rajathr | 0:34ee385f4d2d | 5501 | #define TIM_EGR_COMG_MORT ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ |
| rajathr | 0:34ee385f4d2d | 5502 | #define TIM_EGR_TG_MORT ((uint8_t)0x40) /*!<Trigger Generation */ |
| rajathr | 0:34ee385f4d2d | 5503 | #define TIM_EGR_BG_MORT ((uint8_t)0x80) /*!<Break Generation */ |
| rajathr | 0:34ee385f4d2d | 5504 | |
| rajathr | 0:34ee385f4d2d | 5505 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5506 | #define TIM_CCMR1_CC1S_MORT ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| rajathr | 0:34ee385f4d2d | 5507 | #define TIM_CCMR1_CC1S_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5508 | #define TIM_CCMR1_CC1S_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5509 | |
| rajathr | 0:34ee385f4d2d | 5510 | #define TIM_CCMR1_OC1FE_MORT ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ |
| rajathr | 0:34ee385f4d2d | 5511 | #define TIM_CCMR1_OC1PE_MORT ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ |
| rajathr | 0:34ee385f4d2d | 5512 | |
| rajathr | 0:34ee385f4d2d | 5513 | #define TIM_CCMR1_OC1M_MORT ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| rajathr | 0:34ee385f4d2d | 5514 | #define TIM_CCMR1_OC1M_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5515 | #define TIM_CCMR1_OC1M_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5516 | #define TIM_CCMR1_OC1M_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5517 | |
| rajathr | 0:34ee385f4d2d | 5518 | #define TIM_CCMR1_OC1CE_MORT ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ |
| rajathr | 0:34ee385f4d2d | 5519 | |
| rajathr | 0:34ee385f4d2d | 5520 | #define TIM_CCMR1_CC2S_MORT ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| rajathr | 0:34ee385f4d2d | 5521 | #define TIM_CCMR1_CC2S_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5522 | #define TIM_CCMR1_CC2S_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5523 | |
| rajathr | 0:34ee385f4d2d | 5524 | #define TIM_CCMR1_OC2FE_MORT ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ |
| rajathr | 0:34ee385f4d2d | 5525 | #define TIM_CCMR1_OC2PE_MORT ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ |
| rajathr | 0:34ee385f4d2d | 5526 | |
| rajathr | 0:34ee385f4d2d | 5527 | #define TIM_CCMR1_OC2M_MORT ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| rajathr | 0:34ee385f4d2d | 5528 | #define TIM_CCMR1_OC2M_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5529 | #define TIM_CCMR1_OC2M_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5530 | #define TIM_CCMR1_OC2M_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5531 | |
| rajathr | 0:34ee385f4d2d | 5532 | #define TIM_CCMR1_OC2CE_MORT ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ |
| rajathr | 0:34ee385f4d2d | 5533 | |
| rajathr | 0:34ee385f4d2d | 5534 | /*----------------------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 5535 | |
| rajathr | 0:34ee385f4d2d | 5536 | #define TIM_CCMR1_IC1PSC_MORT ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| rajathr | 0:34ee385f4d2d | 5537 | #define TIM_CCMR1_IC1PSC_0_MORT ((uint16_t)0x0004) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5538 | #define TIM_CCMR1_IC1PSC_1_MORT ((uint16_t)0x0008) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5539 | |
| rajathr | 0:34ee385f4d2d | 5540 | #define TIM_CCMR1_IC1F_MORT ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| rajathr | 0:34ee385f4d2d | 5541 | #define TIM_CCMR1_IC1F_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5542 | #define TIM_CCMR1_IC1F_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5543 | #define TIM_CCMR1_IC1F_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5544 | #define TIM_CCMR1_IC1F_3_MORT ((uint16_t)0x0080) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5545 | |
| rajathr | 0:34ee385f4d2d | 5546 | #define TIM_CCMR1_IC2PSC_MORT ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| rajathr | 0:34ee385f4d2d | 5547 | #define TIM_CCMR1_IC2PSC_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5548 | #define TIM_CCMR1_IC2PSC_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5549 | |
| rajathr | 0:34ee385f4d2d | 5550 | #define TIM_CCMR1_IC2F_MORT ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| rajathr | 0:34ee385f4d2d | 5551 | #define TIM_CCMR1_IC2F_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5552 | #define TIM_CCMR1_IC2F_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5553 | #define TIM_CCMR1_IC2F_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5554 | #define TIM_CCMR1_IC2F_3_MORT ((uint16_t)0x8000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5555 | |
| rajathr | 0:34ee385f4d2d | 5556 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5557 | #define TIM_CCMR2_CC3S_MORT ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| rajathr | 0:34ee385f4d2d | 5558 | #define TIM_CCMR2_CC3S_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5559 | #define TIM_CCMR2_CC3S_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5560 | |
| rajathr | 0:34ee385f4d2d | 5561 | #define TIM_CCMR2_OC3FE_MORT ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ |
| rajathr | 0:34ee385f4d2d | 5562 | #define TIM_CCMR2_OC3PE_MORT ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ |
| rajathr | 0:34ee385f4d2d | 5563 | |
| rajathr | 0:34ee385f4d2d | 5564 | #define TIM_CCMR2_OC3M_MORT ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| rajathr | 0:34ee385f4d2d | 5565 | #define TIM_CCMR2_OC3M_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5566 | #define TIM_CCMR2_OC3M_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5567 | #define TIM_CCMR2_OC3M_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5568 | |
| rajathr | 0:34ee385f4d2d | 5569 | #define TIM_CCMR2_OC3CE_MORT ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ |
| rajathr | 0:34ee385f4d2d | 5570 | |
| rajathr | 0:34ee385f4d2d | 5571 | #define TIM_CCMR2_CC4S_MORT ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| rajathr | 0:34ee385f4d2d | 5572 | #define TIM_CCMR2_CC4S_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5573 | #define TIM_CCMR2_CC4S_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5574 | |
| rajathr | 0:34ee385f4d2d | 5575 | #define TIM_CCMR2_OC4FE_MORT ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ |
| rajathr | 0:34ee385f4d2d | 5576 | #define TIM_CCMR2_OC4PE_MORT ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ |
| rajathr | 0:34ee385f4d2d | 5577 | |
| rajathr | 0:34ee385f4d2d | 5578 | #define TIM_CCMR2_OC4M_MORT ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| rajathr | 0:34ee385f4d2d | 5579 | #define TIM_CCMR2_OC4M_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5580 | #define TIM_CCMR2_OC4M_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5581 | #define TIM_CCMR2_OC4M_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5582 | |
| rajathr | 0:34ee385f4d2d | 5583 | #define TIM_CCMR2_OC4CE_MORT ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ |
| rajathr | 0:34ee385f4d2d | 5584 | |
| rajathr | 0:34ee385f4d2d | 5585 | /*----------------------------------------------------------------------------*/ |
| rajathr | 0:34ee385f4d2d | 5586 | |
| rajathr | 0:34ee385f4d2d | 5587 | #define TIM_CCMR2_IC3PSC_MORT ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| rajathr | 0:34ee385f4d2d | 5588 | #define TIM_CCMR2_IC3PSC_0_MORT ((uint16_t)0x0004) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5589 | #define TIM_CCMR2_IC3PSC_1_MORT ((uint16_t)0x0008) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5590 | |
| rajathr | 0:34ee385f4d2d | 5591 | #define TIM_CCMR2_IC3F_MORT ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| rajathr | 0:34ee385f4d2d | 5592 | #define TIM_CCMR2_IC3F_0_MORT ((uint16_t)0x0010) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5593 | #define TIM_CCMR2_IC3F_1_MORT ((uint16_t)0x0020) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5594 | #define TIM_CCMR2_IC3F_2_MORT ((uint16_t)0x0040) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5595 | #define TIM_CCMR2_IC3F_3_MORT ((uint16_t)0x0080) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5596 | |
| rajathr | 0:34ee385f4d2d | 5597 | #define TIM_CCMR2_IC4PSC_MORT ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| rajathr | 0:34ee385f4d2d | 5598 | #define TIM_CCMR2_IC4PSC_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5599 | #define TIM_CCMR2_IC4PSC_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5600 | |
| rajathr | 0:34ee385f4d2d | 5601 | #define TIM_CCMR2_IC4F_MORT ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| rajathr | 0:34ee385f4d2d | 5602 | #define TIM_CCMR2_IC4F_0_MORT ((uint16_t)0x1000) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5603 | #define TIM_CCMR2_IC4F_1_MORT ((uint16_t)0x2000) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5604 | #define TIM_CCMR2_IC4F_2_MORT ((uint16_t)0x4000) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5605 | #define TIM_CCMR2_IC4F_3_MORT ((uint16_t)0x8000) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5606 | |
| rajathr | 0:34ee385f4d2d | 5607 | /******************* Bit definition for TIM_CCER register *******************/ |
| rajathr | 0:34ee385f4d2d | 5608 | #define TIM_CCER_CC1E_MORT ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ |
| rajathr | 0:34ee385f4d2d | 5609 | #define TIM_CCER_CC1P_MORT ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5610 | #define TIM_CCER_CC1NE_MORT ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ |
| rajathr | 0:34ee385f4d2d | 5611 | #define TIM_CCER_CC1NP_MORT ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5612 | #define TIM_CCER_CC2E_MORT ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ |
| rajathr | 0:34ee385f4d2d | 5613 | #define TIM_CCER_CC2P_MORT ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5614 | #define TIM_CCER_CC2NE_MORT ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ |
| rajathr | 0:34ee385f4d2d | 5615 | #define TIM_CCER_CC2NP_MORT ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5616 | #define TIM_CCER_CC3E_MORT ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ |
| rajathr | 0:34ee385f4d2d | 5617 | #define TIM_CCER_CC3P_MORT ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5618 | #define TIM_CCER_CC3NE_MORT ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ |
| rajathr | 0:34ee385f4d2d | 5619 | #define TIM_CCER_CC3NP_MORT ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5620 | #define TIM_CCER_CC4E_MORT ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ |
| rajathr | 0:34ee385f4d2d | 5621 | #define TIM_CCER_CC4P_MORT ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5622 | #define TIM_CCER_CC4NP_MORT ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ |
| rajathr | 0:34ee385f4d2d | 5623 | |
| rajathr | 0:34ee385f4d2d | 5624 | /******************* Bit definition for TIM_CNT register ********************/ |
| rajathr | 0:34ee385f4d2d | 5625 | #define TIM_CNT_CNT_MORT ((uint16_t)0xFFFF) /*!<Counter Value */ |
| rajathr | 0:34ee385f4d2d | 5626 | |
| rajathr | 0:34ee385f4d2d | 5627 | /******************* Bit definition for TIM_PSC register ********************/ |
| rajathr | 0:34ee385f4d2d | 5628 | #define TIM_PSC_PSC_MORT ((uint16_t)0xFFFF) /*!<Prescaler Value */ |
| rajathr | 0:34ee385f4d2d | 5629 | |
| rajathr | 0:34ee385f4d2d | 5630 | /******************* Bit definition for TIM_ARR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5631 | #define TIM_ARR_ARR_MORT ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ |
| rajathr | 0:34ee385f4d2d | 5632 | |
| rajathr | 0:34ee385f4d2d | 5633 | /******************* Bit definition for TIM_RCR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5634 | #define TIM_RCR_REP_MORT ((uint8_t)0xFF) /*!<Repetition Counter Value */ |
| rajathr | 0:34ee385f4d2d | 5635 | |
| rajathr | 0:34ee385f4d2d | 5636 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5637 | #define TIM_CCR1_CCR1_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ |
| rajathr | 0:34ee385f4d2d | 5638 | |
| rajathr | 0:34ee385f4d2d | 5639 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5640 | #define TIM_CCR2_CCR2_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ |
| rajathr | 0:34ee385f4d2d | 5641 | |
| rajathr | 0:34ee385f4d2d | 5642 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5643 | #define TIM_CCR3_CCR3_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ |
| rajathr | 0:34ee385f4d2d | 5644 | |
| rajathr | 0:34ee385f4d2d | 5645 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5646 | #define TIM_CCR4_CCR4_MORT ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ |
| rajathr | 0:34ee385f4d2d | 5647 | |
| rajathr | 0:34ee385f4d2d | 5648 | /******************* Bit definition for TIM_BDTR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5649 | #define TIM_BDTR_DTG_MORT ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| rajathr | 0:34ee385f4d2d | 5650 | #define TIM_BDTR_DTG_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5651 | #define TIM_BDTR_DTG_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5652 | #define TIM_BDTR_DTG_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5653 | #define TIM_BDTR_DTG_3_MORT ((uint16_t)0x0008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5654 | #define TIM_BDTR_DTG_4_MORT ((uint16_t)0x0010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 5655 | #define TIM_BDTR_DTG_5_MORT ((uint16_t)0x0020) /*!<Bit 5 */ |
| rajathr | 0:34ee385f4d2d | 5656 | #define TIM_BDTR_DTG_6_MORT ((uint16_t)0x0040) /*!<Bit 6 */ |
| rajathr | 0:34ee385f4d2d | 5657 | #define TIM_BDTR_DTG_7_MORT ((uint16_t)0x0080) /*!<Bit 7 */ |
| rajathr | 0:34ee385f4d2d | 5658 | |
| rajathr | 0:34ee385f4d2d | 5659 | #define TIM_BDTR_LOCK_MORT ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
| rajathr | 0:34ee385f4d2d | 5660 | #define TIM_BDTR_LOCK_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5661 | #define TIM_BDTR_LOCK_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5662 | |
| rajathr | 0:34ee385f4d2d | 5663 | #define TIM_BDTR_OSSI_MORT ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ |
| rajathr | 0:34ee385f4d2d | 5664 | #define TIM_BDTR_OSSR_MORT ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ |
| rajathr | 0:34ee385f4d2d | 5665 | #define TIM_BDTR_BKE_MORT ((uint16_t)0x1000) /*!<Break enable */ |
| rajathr | 0:34ee385f4d2d | 5666 | #define TIM_BDTR_BKP_MORT ((uint16_t)0x2000) /*!<Break Polarity */ |
| rajathr | 0:34ee385f4d2d | 5667 | #define TIM_BDTR_AOE_MORT ((uint16_t)0x4000) /*!<Automatic Output enable */ |
| rajathr | 0:34ee385f4d2d | 5668 | #define TIM_BDTR_MOE_MORT ((uint16_t)0x8000) /*!<Main Output enable */ |
| rajathr | 0:34ee385f4d2d | 5669 | |
| rajathr | 0:34ee385f4d2d | 5670 | /******************* Bit definition for TIM_DCR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5671 | #define TIM_DCR_DBA_MORT ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
| rajathr | 0:34ee385f4d2d | 5672 | #define TIM_DCR_DBA_0_MORT ((uint16_t)0x0001) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5673 | #define TIM_DCR_DBA_1_MORT ((uint16_t)0x0002) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5674 | #define TIM_DCR_DBA_2_MORT ((uint16_t)0x0004) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5675 | #define TIM_DCR_DBA_3_MORT ((uint16_t)0x0008) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5676 | #define TIM_DCR_DBA_4_MORT ((uint16_t)0x0010) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 5677 | |
| rajathr | 0:34ee385f4d2d | 5678 | #define TIM_DCR_DBL_MORT ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
| rajathr | 0:34ee385f4d2d | 5679 | #define TIM_DCR_DBL_0_MORT ((uint16_t)0x0100) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5680 | #define TIM_DCR_DBL_1_MORT ((uint16_t)0x0200) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5681 | #define TIM_DCR_DBL_2_MORT ((uint16_t)0x0400) /*!<Bit 2 */ |
| rajathr | 0:34ee385f4d2d | 5682 | #define TIM_DCR_DBL_3_MORT ((uint16_t)0x0800) /*!<Bit 3 */ |
| rajathr | 0:34ee385f4d2d | 5683 | #define TIM_DCR_DBL_4_MORT ((uint16_t)0x1000) /*!<Bit 4 */ |
| rajathr | 0:34ee385f4d2d | 5684 | |
| rajathr | 0:34ee385f4d2d | 5685 | /******************* Bit definition for TIM_DMAR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5686 | #define TIM_DMAR_DMAB_MORT ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ |
| rajathr | 0:34ee385f4d2d | 5687 | |
| rajathr | 0:34ee385f4d2d | 5688 | /******************* Bit definition for TIM_OR register *********************/ |
| rajathr | 0:34ee385f4d2d | 5689 | #define TIM_OR_TI4_RMP_MORT ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5_MORT Input 4 remap) */ |
| rajathr | 0:34ee385f4d2d | 5690 | #define TIM_OR_TI4_RMP_0_MORT ((uint16_t)0x0040) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5691 | #define TIM_OR_TI4_RMP_1_MORT ((uint16_t)0x0080) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5692 | #define TIM_OR_ITR1_RMP_MORT ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2_MORT Internal trigger 1 remap) */ |
| rajathr | 0:34ee385f4d2d | 5693 | #define TIM_OR_ITR1_RMP_0_MORT ((uint16_t)0x0400) /*!<Bit 0 */ |
| rajathr | 0:34ee385f4d2d | 5694 | #define TIM_OR_ITR1_RMP_1_MORT ((uint16_t)0x0800) /*!<Bit 1 */ |
| rajathr | 0:34ee385f4d2d | 5695 | |
| rajathr | 0:34ee385f4d2d | 5696 | #if defined(STM32F410xx) || defined(STM32F413_423xx) |
| rajathr | 0:34ee385f4d2d | 5697 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5698 | /* */ |
| rajathr | 0:34ee385f4d2d | 5699 | /* Low Power Timer (LPTIM) */ |
| rajathr | 0:34ee385f4d2d | 5700 | /* */ |
| rajathr | 0:34ee385f4d2d | 5701 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5702 | /****************** Bit definition for LPTIM_ISR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5703 | |
| rajathr | 0:34ee385f4d2d | 5704 | /****************** Bit definition for LPTIM_ICR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5705 | |
| rajathr | 0:34ee385f4d2d | 5706 | /****************** Bit definition for LPTIM_IER register ********************/ |
| rajathr | 0:34ee385f4d2d | 5707 | |
| rajathr | 0:34ee385f4d2d | 5708 | /****************** Bit definition for LPTIM_CFGR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5709 | |
| rajathr | 0:34ee385f4d2d | 5710 | |
| rajathr | 0:34ee385f4d2d | 5711 | /****************** Bit definition for LPTIM_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5712 | |
| rajathr | 0:34ee385f4d2d | 5713 | /****************** Bit definition for LPTIM_CMP register *******************/ |
| rajathr | 0:34ee385f4d2d | 5714 | |
| rajathr | 0:34ee385f4d2d | 5715 | /****************** Bit definition for LPTIM_ARR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5716 | |
| rajathr | 0:34ee385f4d2d | 5717 | /****************** Bit definition for LPTIM_CNT register *******************/ |
| rajathr | 0:34ee385f4d2d | 5718 | |
| rajathr | 0:34ee385f4d2d | 5719 | /****************** Bit definition for LPTIM_OR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5720 | |
| rajathr | 0:34ee385f4d2d | 5721 | #endif /* STM32F410xx || STM32F413_423xx */ |
| rajathr | 0:34ee385f4d2d | 5722 | |
| rajathr | 0:34ee385f4d2d | 5723 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5724 | /* */ |
| rajathr | 0:34ee385f4d2d | 5725 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
| rajathr | 0:34ee385f4d2d | 5726 | /* */ |
| rajathr | 0:34ee385f4d2d | 5727 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5728 | /******************* Bit definition for USART_SR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5729 | |
| rajathr | 0:34ee385f4d2d | 5730 | /******************* Bit definition for USART_DR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5731 | |
| rajathr | 0:34ee385f4d2d | 5732 | /****************** Bit definition for USART_BRR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5733 | |
| rajathr | 0:34ee385f4d2d | 5734 | /****************** Bit definition for USART_CR1 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5735 | |
| rajathr | 0:34ee385f4d2d | 5736 | /****************** Bit definition for USART_CR2 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5737 | |
| rajathr | 0:34ee385f4d2d | 5738 | /****************** Bit definition for USART_CR3 register *******************/ |
| rajathr | 0:34ee385f4d2d | 5739 | |
| rajathr | 0:34ee385f4d2d | 5740 | /****************** Bit definition for USART_GTPR register ******************/ |
| rajathr | 0:34ee385f4d2d | 5741 | |
| rajathr | 0:34ee385f4d2d | 5742 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5743 | /* */ |
| rajathr | 0:34ee385f4d2d | 5744 | /* Window WATCHDOG */ |
| rajathr | 0:34ee385f4d2d | 5745 | /* */ |
| rajathr | 0:34ee385f4d2d | 5746 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5747 | /******************* Bit definition for WWDG_CR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5748 | |
| rajathr | 0:34ee385f4d2d | 5749 | /******************* Bit definition for WWDG_CFR register *******************/ |
| rajathr | 0:34ee385f4d2d | 5750 | |
| rajathr | 0:34ee385f4d2d | 5751 | /******************* Bit definition for WWDG_SR register ********************/ |
| rajathr | 0:34ee385f4d2d | 5752 | |
| rajathr | 0:34ee385f4d2d | 5753 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5754 | /* */ |
| rajathr | 0:34ee385f4d2d | 5755 | /* DBG */ |
| rajathr | 0:34ee385f4d2d | 5756 | /* */ |
| rajathr | 0:34ee385f4d2d | 5757 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5758 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
| rajathr | 0:34ee385f4d2d | 5759 | |
| rajathr | 0:34ee385f4d2d | 5760 | /******************** Bit definition for DBGMCU_CR register *****************/ |
| rajathr | 0:34ee385f4d2d | 5761 | |
| rajathr | 0:34ee385f4d2d | 5762 | |
| rajathr | 0:34ee385f4d2d | 5763 | /******************** Bit definition for DBGMCU_APB1_FZ register ************/ |
| rajathr | 0:34ee385f4d2d | 5764 | |
| rajathr | 0:34ee385f4d2d | 5765 | |
| rajathr | 0:34ee385f4d2d | 5766 | /******************** Bit definition for DBGMCU_APB1_FZ register ************/ |
| rajathr | 0:34ee385f4d2d | 5767 | |
| rajathr | 0:34ee385f4d2d | 5768 | |
| rajathr | 0:34ee385f4d2d | 5769 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5770 | /* */ |
| rajathr | 0:34ee385f4d2d | 5771 | /* Ethernet MAC Registers bits definitions */ |
| rajathr | 0:34ee385f4d2d | 5772 | /* */ |
| rajathr | 0:34ee385f4d2d | 5773 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5774 | /* Bit definition for Ethernet MAC Control Register register */ |
| rajathr | 0:34ee385f4d2d | 5775 | |
| rajathr | 0:34ee385f4d2d | 5776 | |
| rajathr | 0:34ee385f4d2d | 5777 | /* Bit definition for Ethernet MAC Frame Filter Register */ |
| rajathr | 0:34ee385f4d2d | 5778 | |
| rajathr | 0:34ee385f4d2d | 5779 | /* Bit definition for Ethernet MAC Flow Control Register */ |
| rajathr | 0:34ee385f4d2d | 5780 | |
| rajathr | 0:34ee385f4d2d | 5781 | |
| rajathr | 0:34ee385f4d2d | 5782 | /* Bit definition for Ethernet MAC Status Register */ |
| rajathr | 0:34ee385f4d2d | 5783 | |
| rajathr | 0:34ee385f4d2d | 5784 | |
| rajathr | 0:34ee385f4d2d | 5785 | /* Bit definition for Ethernet MAC Interrupt Mask Register */ |
| rajathr | 0:34ee385f4d2d | 5786 | |
| rajathr | 0:34ee385f4d2d | 5787 | |
| rajathr | 0:34ee385f4d2d | 5788 | /* Bit definition for Ethernet MAC Address0 High Register */ |
| rajathr | 0:34ee385f4d2d | 5789 | |
| rajathr | 0:34ee385f4d2d | 5790 | |
| rajathr | 0:34ee385f4d2d | 5791 | /* Bit definition for Ethernet MAC Address0 Low Register */ |
| rajathr | 0:34ee385f4d2d | 5792 | |
| rajathr | 0:34ee385f4d2d | 5793 | |
| rajathr | 0:34ee385f4d2d | 5794 | /* Bit definition for Ethernet MAC Address1 High Register */ |
| rajathr | 0:34ee385f4d2d | 5795 | |
| rajathr | 0:34ee385f4d2d | 5796 | /* Bit definition for Ethernet MAC Address1 Low Register */ |
| rajathr | 0:34ee385f4d2d | 5797 | |
| rajathr | 0:34ee385f4d2d | 5798 | |
| rajathr | 0:34ee385f4d2d | 5799 | /* Bit definition for Ethernet MAC Address2 High Register */ |
| rajathr | 0:34ee385f4d2d | 5800 | |
| rajathr | 0:34ee385f4d2d | 5801 | |
| rajathr | 0:34ee385f4d2d | 5802 | /* Bit definition for Ethernet MAC Address2 Low Register */ |
| rajathr | 0:34ee385f4d2d | 5803 | |
| rajathr | 0:34ee385f4d2d | 5804 | |
| rajathr | 0:34ee385f4d2d | 5805 | /* Bit definition for Ethernet MAC Address3 High Register */ |
| rajathr | 0:34ee385f4d2d | 5806 | |
| rajathr | 0:34ee385f4d2d | 5807 | |
| rajathr | 0:34ee385f4d2d | 5808 | /* Bit definition for Ethernet MAC Address3 Low Register */ |
| rajathr | 0:34ee385f4d2d | 5809 | |
| rajathr | 0:34ee385f4d2d | 5810 | |
| rajathr | 0:34ee385f4d2d | 5811 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5812 | /* Ethernet MMC Registers bits definition */ |
| rajathr | 0:34ee385f4d2d | 5813 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5814 | |
| rajathr | 0:34ee385f4d2d | 5815 | /* Bit definition for Ethernet MMC Contol Register */ |
| rajathr | 0:34ee385f4d2d | 5816 | |
| rajathr | 0:34ee385f4d2d | 5817 | |
| rajathr | 0:34ee385f4d2d | 5818 | /* Bit definition for Ethernet MMC Receive Interrupt Register */ |
| rajathr | 0:34ee385f4d2d | 5819 | |
| rajathr | 0:34ee385f4d2d | 5820 | /* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
| rajathr | 0:34ee385f4d2d | 5821 | |
| rajathr | 0:34ee385f4d2d | 5822 | /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
| rajathr | 0:34ee385f4d2d | 5823 | |
| rajathr | 0:34ee385f4d2d | 5824 | /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
| rajathr | 0:34ee385f4d2d | 5825 | |
| rajathr | 0:34ee385f4d2d | 5826 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5827 | /* Ethernet PTP Registers bits definition */ |
| rajathr | 0:34ee385f4d2d | 5828 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5829 | |
| rajathr | 0:34ee385f4d2d | 5830 | /* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
| rajathr | 0:34ee385f4d2d | 5831 | |
| rajathr | 0:34ee385f4d2d | 5832 | |
| rajathr | 0:34ee385f4d2d | 5833 | |
| rajathr | 0:34ee385f4d2d | 5834 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5835 | /* Ethernet DMA Registers bits definition */ |
| rajathr | 0:34ee385f4d2d | 5836 | /******************************************************************************/ |
| rajathr | 0:34ee385f4d2d | 5837 | |
| rajathr | 0:34ee385f4d2d | 5838 | /* Bit definition for Ethernet DMA Bus Mode Register */ |
| rajathr | 0:34ee385f4d2d | 5839 | |
| rajathr | 0:34ee385f4d2d | 5840 | |
| rajathr | 0:34ee385f4d2d | 5841 | /** |
| rajathr | 0:34ee385f4d2d | 5842 | * |
| rajathr | 0:34ee385f4d2d | 5843 | */ |
| rajathr | 0:34ee385f4d2d | 5844 | |
| rajathr | 0:34ee385f4d2d | 5845 | /** |
| rajathr | 0:34ee385f4d2d | 5846 | * @} |
| rajathr | 0:34ee385f4d2d | 5847 | */ |
| rajathr | 0:34ee385f4d2d | 5848 | |
| rajathr | 0:34ee385f4d2d | 5849 | #ifdef USE_STDPERIPH_DRIVER |
| rajathr | 0:34ee385f4d2d | 5850 | #include "stm32f4xx_conf.h" |
| rajathr | 0:34ee385f4d2d | 5851 | #endif /* USE_STDPERIPH_DRIVER */ |
| rajathr | 0:34ee385f4d2d | 5852 | |
| rajathr | 0:34ee385f4d2d | 5853 | /** @addtogroup Exported_macro |
| rajathr | 0:34ee385f4d2d | 5854 | * @{ |
| rajathr | 0:34ee385f4d2d | 5855 | */ |
| rajathr | 0:34ee385f4d2d | 5856 | |
| rajathr | 0:34ee385f4d2d | 5857 | #define SET_BIT_MORT(REG, BIT) ((REG) |= (BIT)) |
| rajathr | 0:34ee385f4d2d | 5858 | |
| rajathr | 0:34ee385f4d2d | 5859 | #define CLEAR_BIT_MORT(REG, BIT) ((REG) &= ~(BIT)) |
| rajathr | 0:34ee385f4d2d | 5860 | |
| rajathr | 0:34ee385f4d2d | 5861 | #define READ_BIT_MORT(REG, BIT) ((REG) & (BIT)) |
| rajathr | 0:34ee385f4d2d | 5862 | |
| rajathr | 0:34ee385f4d2d | 5863 | #define CLEAR_REG_MORT(REG) ((REG) = (0x0)) |
| rajathr | 0:34ee385f4d2d | 5864 | |
| rajathr | 0:34ee385f4d2d | 5865 | #define WRITE_REG_MORT(REG, VAL) ((REG) = (VAL)) |
| rajathr | 0:34ee385f4d2d | 5866 | |
| rajathr | 0:34ee385f4d2d | 5867 | #define READ_REG_MORT(REG) ((REG)) |
| rajathr | 0:34ee385f4d2d | 5868 | |
| rajathr | 0:34ee385f4d2d | 5869 | #define MODIFY_REG_MORT(REG, CLEARMASK, SETMASK) WRITE_REG_MORT((REG), (((READ_REG_MORT(REG)) & (~(CLEARMASK))) | (SETMASK))) |
| rajathr | 0:34ee385f4d2d | 5870 | |
| rajathr | 0:34ee385f4d2d | 5871 | /** |
| rajathr | 0:34ee385f4d2d | 5872 | * @} |
| rajathr | 0:34ee385f4d2d | 5873 | */ |
| rajathr | 0:34ee385f4d2d | 5874 | |
| rajathr | 0:34ee385f4d2d | 5875 | #ifdef __cplusplus |
| rajathr | 0:34ee385f4d2d | 5876 | } |
| rajathr | 0:34ee385f4d2d | 5877 | #endif /* __cplusplus */ |
| rajathr | 0:34ee385f4d2d | 5878 | |
| rajathr | 0:34ee385f4d2d | 5879 | #endif /* __STM32F4xx_H */ |
| rajathr | 0:34ee385f4d2d | 5880 | |
| rajathr | 0:34ee385f4d2d | 5881 | /** |
| rajathr | 0:34ee385f4d2d | 5882 | * @} |
| rajathr | 0:34ee385f4d2d | 5883 | */ |
| rajathr | 0:34ee385f4d2d | 5884 | |
| rajathr | 0:34ee385f4d2d | 5885 | /** |
| rajathr | 0:34ee385f4d2d | 5886 | * @} |
| rajathr | 0:34ee385f4d2d | 5887 | */ |
| rajathr | 0:34ee385f4d2d | 5888 | |
| rajathr | 0:34ee385f4d2d | 5889 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| rajathr | 0:34ee385f4d2d | 5890 | |
| rajathr | 0:34ee385f4d2d | 5891 | |
| rajathr | 0:34ee385f4d2d | 5892 | |
| rajathr | 0:34ee385f4d2d | 5893 | |
| rajathr | 0:34ee385f4d2d | 5894 | |
| rajathr | 0:34ee385f4d2d | 5895 |