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Dependencies:   mbed

interrupt.c@0:34ee385f4d2d, 2021-10-23 (annotated)

Committer:
rajathr
Date:
Sat Oct 23 05:49:09 2021 +0000
Revision:
0:34ee385f4d2d
At 23rd Oct 21 - All Code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:34ee385f4d2d 1 #include "hardware_timer3.h"
rajathr 0:34ee385f4d2d 2 #include "gpio.h"
rajathr 0:34ee385f4d2d 3 #include "stm32f4xx_rcc_mort.h"
rajathr 0:34ee385f4d2d 4 #include "interrupt.h"
rajathr 0:34ee385f4d2d 5
rajathr 0:34ee385f4d2d 6 /*Below are defined all Timers and flags required */ //COPYING ALL VALUES AND DEFINITIONS FROM HARDWARE_TIMER3.C
rajathr 0:34ee385f4d2d 7 #define TIM3_BASE_ADDRESS ((uint32_t)0x40000400)
rajathr 0:34ee385f4d2d 8 #define TIM3_STATUS_REGISTER (TIM3_BASE_ADDRESS + 0x10)
rajathr 0:34ee385f4d2d 9 #define TIM3_PSC_REGISTER (TIM3_BASE_ADDRESS + 0x28)
rajathr 0:34ee385f4d2d 10 #define TIM3_AUTORELOAD_REGISTER (TIM3_BASE_ADDRESS + 0x2C)
rajathr 0:34ee385f4d2d 11 #define TIM3_COUNTER_REGISTER (TIM3_BASE_ADDRESS + 0x24)
rajathr 0:34ee385f4d2d 12 #define TIM3_CAPTURE_COMPARE_MODE_2_REGISTER (TIM3_BASE_ADDRESS + 0x1C)
rajathr 0:34ee385f4d2d 13 #define TIM_CCMR13_OC1M_0 (0b00010000)
rajathr 0:34ee385f4d2d 14 #define TIM_CCMR13_OC1M_1 (0b00100000)
rajathr 0:34ee385f4d2d 15 #define TIM_CCMR13_OC1M_2 (0b01000000)
rajathr 0:34ee385f4d2d 16 #define TIM_CCMR13_OCPE (0b00001000)
rajathr 0:34ee385f4d2d 17 #define TIM_CCMR23_
rajathr 0:34ee385f4d2d 18 #define TIM_CCMR13_OUTPUT 0x00
rajathr 0:34ee385f4d2d 19 #define TIM3_COMPARE3_REGISTER (TIM3_BASE_ADDRESS + 0x3C)
rajathr 0:34ee385f4d2d 20 #define TIM3_CAPTURE_COMPARE_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x20)
rajathr 0:34ee385f4d2d 21 #define TIM3_CR1_REGISTER1 (TIM3_BASE_ADDRESS + 0x00)
rajathr 0:34ee385f4d2d 22 #define TIM3_CAPTURE_COMPARE_MODE_1_REGISTER (TIM3_BASE_ADDRESS + 0x18)
rajathr 0:34ee385f4d2d 23 #define TIM3_CAPTURE_COMPARE_REGISTER_1 (TIM3_BASE_ADDRESS + 0x34)
rajathr 0:34ee385f4d2d 24
rajathr 0:34ee385f4d2d 25 #define TIM3_CCMR2_CC3S_OUTPUT (0b11111100)
rajathr 0:34ee385f4d2d 26 #define TIM3_CCMR2_OC3FE (0b11111011)
rajathr 0:34ee385f4d2d 27 #define TIM3_CCMR2_OC3PE (0b00001000)
rajathr 0:34ee385f4d2d 28 #define TIM3_CCMR2_OC3M1 (0b11101111)
rajathr 0:34ee385f4d2d 29 #define TIM3_CCMR2_OC3M2 (0b01100000)
rajathr 0:34ee385f4d2d 30
rajathr 0:34ee385f4d2d 31 # define TIM3_INTERRUPT_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x0C)
rajathr 0:34ee385f4d2d 32
rajathr 0:34ee385f4d2d 33 /* MACRO definitions----------------------------------------------------------*/
rajathr 0:34ee385f4d2d 34 #define SYSTEM_CONTROL_BASE_ADDRESS (0xE000E000)
rajathr 0:34ee385f4d2d 35 #define NVIC_BASE_ADDRESS (SYSTEM_CONTROL_BASE_ADDRESS + 0x100)
rajathr 0:34ee385f4d2d 36 #define NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31 (NVIC_BASE_ADDRESS)
rajathr 0:34ee385f4d2d 37 #define NVIC_INTERRUPT_SET_ENABLE_REGISTER_32_63 (NVIC_BASE_ADDRESS+0x4)
rajathr 0:34ee385f4d2d 38 #define NVIC_INTERRUPT_SET_ENABLE_REGISTER_64_95 (NVIC_BASE_ADDRESS+0x8)
rajathr 0:34ee385f4d2d 39 #define TIM3_INTERRUPT_BIT (0x20000000)
rajathr 0:34ee385f4d2d 40
rajathr 0:34ee385f4d2d 41 #define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x80)
rajathr 0:34ee385f4d2d 42 #define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_32_63 (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x4)
rajathr 0:34ee385f4d2d 43 #define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_64_95 (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x8)
rajathr 0:34ee385f4d2d 44 #define NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x100)
rajathr 0:34ee385f4d2d 45 #define NVIC_INTERRUPT_SET_PENDING_REGISTER_32_63 (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x4)
rajathr 0:34ee385f4d2d 46 #define NVIC_INTERRUPT_SET_PENDING_REGISTER_64_95 (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x8)
rajathr 0:34ee385f4d2d 47 #define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 (NVIC_BASE_ADDRESS + 0x180)
rajathr 0:34ee385f4d2d 48 #define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_32_63 (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x4)
rajathr 0:34ee385f4d2d 49 #define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_64_95 (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x8)
rajathr 0:34ee385f4d2d 50 #define EXTI9_5_INTERRUPT_BIT (0x800000)
rajathr 0:34ee385f4d2d 51
rajathr 0:34ee385f4d2d 52 //For external interrupts:
rajathr 0:34ee385f4d2d 53 #define SYSCFG_BASE_ADDRESS ((uint32_t)(0x40013800))
rajathr 0:34ee385f4d2d 54 #define SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2 (SYSCFG_BASE_ADDRESS + 0x0C)
rajathr 0:34ee385f4d2d 55 #define SYSCFG_EXTERNAL_INTERRUPT_6_BITS ((uint32_t)0xF00) //flags for External interrupt register 2
rajathr 0:34ee385f4d2d 56 #define SYSCFG_EXTERNAL_INTERRUPT_6_PORTC ((uint32_t)0x200)
rajathr 0:34ee385f4d2d 57 //External interrupt controller :
rajathr 0:34ee385f4d2d 58 #define EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS ((uint32_t)(0x40013C00))
rajathr 0:34ee385f4d2d 59 #define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS)
rajathr 0:34ee385f4d2d 60 #define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6 ((uint32_t)0x40) //flags for external interrupt controller mask register
rajathr 0:34ee385f4d2d 61 #define EXTERNAL_INTERRUPT_CONTROLLER_RTSR (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x08)
rajathr 0:34ee385f4d2d 62 #define EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6 ((uint32_t)0x40)
rajathr 0:34ee385f4d2d 63 #define EXTERNAL_INTERRUPT_CONTROLLER_FTSR (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x0C)
rajathr 0:34ee385f4d2d 64 #define EXTERNAL_INTERRUPT_CONTROLLER_FTSR_EXTI6 ((uint32_t)0x40)
rajathr 0:34ee385f4d2d 65 #define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x14)
rajathr 0:34ee385f4d2d 66 #define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6 ((uint32_t)0x40)
rajathr 0:34ee385f4d2d 67
rajathr 0:34ee385f4d2d 68
rajathr 0:34ee385f4d2d 69 void enableNVIC_Timer3(void)
rajathr 0:34ee385f4d2d 70 {
rajathr 0:34ee385f4d2d 71 uint32_t * reg;
rajathr 0:34ee385f4d2d 72 reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
rajathr 0:34ee385f4d2d 73 *reg = TIM3_INTERRUPT_BIT;
rajathr 0:34ee385f4d2d 74 }
rajathr 0:34ee385f4d2d 75
rajathr 0:34ee385f4d2d 76 void TIM3_IRQHandler(void)
rajathr 0:34ee385f4d2d 77 {
rajathr 0:34ee385f4d2d 78 uint16_t * reg_pointer_16_sr;
rajathr 0:34ee385f4d2d 79 uint16_t * reg_pointer_16_dier;
rajathr 0:34ee385f4d2d 80 reg_pointer_16_sr = (uint16_t *)TIM3_STATUS_REGISTER;
rajathr 0:34ee385f4d2d 81 reg_pointer_16_dier = (uint16_t *)TIM3_INTERRUPT_ENABLE_REGISTER;
rajathr 0:34ee385f4d2d 82 //check which interrupts fired and if they were supposed to fire, then clear the flags so they don’t keep firing,
rajathr 0:34ee385f4d2d 83 // then perform actions according to these interrupts
rajathr 0:34ee385f4d2d 84 //check if Output Compare 3 triggered the interrupt:
rajathr 0:34ee385f4d2d 85 if (( (*reg_pointer_16_sr & 0x8) >0) && ( (*reg_pointer_16_dier & 0x8) >0))
rajathr 0:34ee385f4d2d 86 {
rajathr 0:34ee385f4d2d 87 //clear interrupt
rajathr 0:34ee385f4d2d 88 *reg_pointer_16_sr = ~((uint16_t)0x8);
rajathr 0:34ee385f4d2d 89 //perform action
rajathr 0:34ee385f4d2d 90 clearGPIOB0();
rajathr 0:34ee385f4d2d 91 }
rajathr 0:34ee385f4d2d 92 //check if Overflow triggered the interrupt: I.e. Timer Counter 3 >= Autorreload value
rajathr 0:34ee385f4d2d 93 if (( (*reg_pointer_16_sr & 0x01) >0) && ( (*reg_pointer_16_dier & 0x1) >0))
rajathr 0:34ee385f4d2d 94 {
rajathr 0:34ee385f4d2d 95 //clear interrupt
rajathr 0:34ee385f4d2d 96 *reg_pointer_16_sr = ~((uint16_t)0x01);
rajathr 0:34ee385f4d2d 97 //perform action
rajathr 0:34ee385f4d2d 98 setGPIOB0();
rajathr 0:34ee385f4d2d 99 }
rajathr 0:34ee385f4d2d 100 }
rajathr 0:34ee385f4d2d 101
rajathr 0:34ee385f4d2d 102 void enableEXTI6OnPortC(void)
rajathr 0:34ee385f4d2d 103 {
rajathr 0:34ee385f4d2d 104 uint32_t * reg;
rajathr 0:34ee385f4d2d 105 /*Init GPIO 6 C as input*/
rajathr 0:34ee385f4d2d 106 initGpioC6AsInput();
rajathr 0:34ee385f4d2d 107 /*As a test, Init GPIO B0 as output for debugging*/
rajathr 0:34ee385f4d2d 108 InitPortBPin0asOutput();
rajathr 0:34ee385f4d2d 109 /* Enable SYSCFG clock */
rajathr 0:34ee385f4d2d 110 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
rajathr 0:34ee385f4d2d 111 /*map EXTI6 to port C bit 6*/
rajathr 0:34ee385f4d2d 112 reg = (uint32_t *)SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2;
rajathr 0:34ee385f4d2d 113 //clear EXTI6
rajathr 0:34ee385f4d2d 114 *reg = *reg & ~SYSCFG_EXTERNAL_INTERRUPT_6_BITS;
rajathr 0:34ee385f4d2d 115 //set EXTI6 to Port C
rajathr 0:34ee385f4d2d 116 *reg = *reg | SYSCFG_EXTERNAL_INTERRUPT_6_PORTC;
rajathr 0:34ee385f4d2d 117 /*un-mask EXTI6*/
rajathr 0:34ee385f4d2d 118 reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER;
rajathr 0:34ee385f4d2d 119 *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6;
rajathr 0:34ee385f4d2d 120 /*trigger on rising edge*/
rajathr 0:34ee385f4d2d 121 reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_RTSR;
rajathr 0:34ee385f4d2d 122 *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6;
rajathr 0:34ee385f4d2d 123 /* set the NVIC to respond to EXTI9_5*/
rajathr 0:34ee385f4d2d 124 reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
rajathr 0:34ee385f4d2d 125 *reg = EXTI9_5_INTERRUPT_BIT;
rajathr 0:34ee385f4d2d 126 }
rajathr 0:34ee385f4d2d 127
rajathr 0:34ee385f4d2d 128 void EXTI9_5_IRQHandler(void)
rajathr 0:34ee385f4d2d 129 {
rajathr 0:34ee385f4d2d 130 uint32_t * reg;
rajathr 0:34ee385f4d2d 131 reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER;
rajathr 0:34ee385f4d2d 132 //check which interrupt fired:
rajathr 0:34ee385f4d2d 133 if ((*reg & EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6)>0)
rajathr 0:34ee385f4d2d 134 {
rajathr 0:34ee385f4d2d 135 //clear the interrupt:
rajathr 0:34ee385f4d2d 136 *reg = EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6;
rajathr 0:34ee385f4d2d 137 //toggle the LED
rajathr 0:34ee385f4d2d 138 toggleGPIOB0();
rajathr 0:34ee385f4d2d 139 }
rajathr 0:34ee385f4d2d 140 }
rajathr 0:34ee385f4d2d 141