Diff: hardware_adc.c

Revision:

1:c125f4e65df7

Parent:

0:716b93ab9a58

diff -r 716b93ab9a58 -r c125f4e65df7 hardware_adc.c
--- a/hardware_adc.c	Fri Oct 29 20:56:20 2021 +0000
+++ b/hardware_adc.c	Wed Nov 03 05:31:26 2021 +0000
@@ -60,17 +60,20 @@
      //Initialize GPIO F 7 as Analog
      InitPortFPin7asAnalog();
      
-     initDMAForAdc3_1Channel();              //FUNCTION IS DEFINED
+     initDMAForAdc3_1Channel();              //FUNCTION IS DEFINED // CHECK FOR THIS FUNCTION IN MAIN
      enableDMAForAdc3_1channels();           //FUNCTION IS DEFINED
      
      //Writing Pre Scale Value divided by 4 - 01 in bits 17&16 of CCR Register
      reg = (uint32_t *)ADC_CCR_REGISTER;
      *reg = 0x10000; 
      
-     //Clear Status Register                    //QUESTION - IS THIS ACTION MANDATORY ??
-     reg = (uint32_t *)ADC_3_SR_REGISTER;
-     *reg = 0;
-        
+     //STATUS REGISTER IS CLEARED IN START CONVERSION FUNCTION
+     
+//     //Clear Status Register                    //QUESTION - IS THIS ACTION MANDATORY ??
+//     reg = (uint32_t *)ADC_3_SR_REGISTER;
+//     *reg = 0;
+//        
+
      //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
      reg = (uint32_t *)ADC_3_CR1_REGISTER;
      *reg = 0; //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
@@ -79,13 +82,12 @@
      //Configure ADC External trigger disabled, right data alignment, DMA Enabled ,
      //EOC is set at the end of each regular conversion, continuous conversion enabled 
      reg = (uint32_t *)ADC_3_CR2_REGISTER;
-     *reg = 0;
      *reg = ((uint32_t)0x02) + ((uint32_t)0x100) + ((uint32_t)0x400);
      //*reg = ADC_E0CS + ADC_CONT + ADC_DDS + ADC_DMA;   //DO YOU HAVE TO WRITE TO THIS REGISTER OR READ THE VALUE ???
         
      //There will be 1 Channel (Channel 5) in the sequence of conversions - SQR1
      reg = (uint32_t *)ADC_3_SQR1_REGISTER;
-     *reg = (uint32_t)0x100000;
+     *reg = 0; //1 conversion is 0000
      
      //Configure Channels 5 to max sampling times (480 cycles)
      reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
@@ -95,7 +97,7 @@
      reg = (uint32_t *)ADC_3_SQR3_REGISTER;
      * reg = 0x05; //WRITING 7 TO SQR1 (BITS 0 TO 4) IN SQR3 REGISTER
      
-     enableADC3();
+     enableADC3(); //ADDITIONAL LINE - IT ALREADY IS PRESENT IN START ADC CONVERSION
      
      //Start a software conversion
      //Need to do this separately
@@ -118,27 +120,30 @@
      initDMAForAdc3_3Channels();             //FUNCTION IS DEFINED
      enableDMAForAdc3_3channels();           //FUNCTION IS DEFINED
      
+     //I HAVE NOT CLEARED STATUS REGISTER - NO NEED - STATUS REGISTER IS CLEARED WHILE CALLING FUNCTION - START CONVERSION
+     
      //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED , SCAN MODE ENABLED 
      //TO BE ABLE TO SCAN A GROUP OF CHANNELS
      reg = (uint32_t *)ADC_3_CR1_REGISTER;
-     *reg = ADC_SCAN;
+     //*reg = 0; //IS THIS STATEMENT MANDATORY TO SET 25TH and 24th BIT AS 00
+     *reg = (uint32_t)0x100 ;  //THIS STATEMENT ALSO SETS 25TH and 24th BIT AS 00 but it does set the SCAN MODE ON
      
-     //Configure ADC External trigger dissabled, right data alignment, DMA ,
+     //Configure ADC External trigger dissabled (29th and 28th Bit is set to 0), right data alignment (11th bit is 0), DMA ,
      //EOC is set at the end of each regular conversion, continuous conversion enabled 
      reg = (uint32_t *)ADC_3_CR2_REGISTER;
-     *reg = ADC_E0CS + ADC_CONT + ADC_DDS + ADC_DMA;
+     *reg = (uint32_t)0x100 + (uint32_t)0x02 + (uint32_t)0x400; //Is the 10th bit supposed to be set to 0 - EC0 SET AT THE END OF EACH CONVERSION
      
      //There will be 3 channels in the sequence of conversions
      reg = (uint32_t *)ADC_3_SQR1_REGISTER;
-     *reg = ADC_3_CONVERSIONS;
+     *reg = (uint32_t)0x200000; //0010 3 will be 2 actually
      
      //Configure Channels 5,6,7 to max sampling times (480 cycles)
      reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
-     *reg = ADC_SMP_5_MX + ADC_SMP_6_MX + ADC_SMP_7_MX;
+     *reg = (uint32_t)0x38000 + (uint32_t)0x1C0000 + (uint32_t)0xE00000; //In the order of 5th Channel set to 480 Cycles , 6th Channel set to 480 Cycles , 7th Channel set to 480 Cycles
      
      //Configure the sequence of conversion for the ADC (5,6,7)
      reg = (uint32_t *)ADC_3_SQR3_REGISTER;
-     * reg = (ADC_CHANNEL_5_MORT2<<ADC_SQ1) + (ADC_CHANNEL_6_MORT2<<ADC_SQ2) + (ADC_CHANNEL_7_MORT2<<ADC_SQ3);
+     * reg = (uint32_t)0x05 + (uint32_t)0xC0 + (uint32_t)0x1C00; //In the order of SQ1 written to 5, SQ2 written to 6 . SQ3 writtent to 7
      
      enableADC3();
      
@@ -155,4 +160,16 @@
      reg = (uint32_t *)ADC_3_CR2_REGISTER;
      *reg= *reg | ((uint32_t)0x01);
 }    
-     
\ No newline at end of file
+
+
+//FUNCTION TO START ADC CONVERSION
+void startADCConversion(void)
+{
+     uint32_t * reg;
+     
+     reg = (uint32_t *)ADC_3_SR_REGISTER;
+     *reg = 0;
+     
+     reg = (uint32_t *)ADC_3_CR2_REGISTER;
+     *reg = *reg | 0x01;
+}     
\ No newline at end of file