hardware_timer.c

00001 #include "hardware_timer.h"
00002 #include "gpio.h"
00003 #include "stm32f4xx_rcc_mort.h"
00004 #include "interrupt.h"
00005 
00006 
00007 /*Below are defined all Timers and flags required  //Mort: These should be in a timer.c or something like that file*/
00008 #define TIM3_BASE_ADDRESS                           ((uint32_t)0x40000400)
00009 #define TIM3_STATUS_REGISTER                        (TIM3_BASE_ADDRESS + 0x10)
00010 #define TIM3_PSC_REGISTER                           (TIM3_BASE_ADDRESS + 0x28)
00011 #define TIM3_AUTORELOAD_REGISTER                    (TIM3_BASE_ADDRESS + 0x2C)
00012 #define TIM3_COUNTER_REGISTER                       (TIM3_BASE_ADDRESS + 0x24)
00013 #define TIM3_CAPTURE_COMPARE_MODE_2_REGISTER        (TIM3_BASE_ADDRESS + 0x1C)
00014 #define TIM_CCMR13_OC1M_0                           (0b00010000)
00015 #define TIM_CCMR13_OC1M_1                           (0b00100000)
00016 #define TIM_CCMR13_OC1M_2                           (0b01000000)
00017 #define TIM_CCMR13_OCPE                             (0b00001000)
00018 #define TIM_CCMR13_OUTPUT                           0x00
00019 #define TIM3_COMPARE3_REGISTER                      (TIM3_BASE_ADDRESS + 0x3C)
00020 #define TIM3_CAPTURE_COMPARE_ENABLE_REGISTER        (TIM3_BASE_ADDRESS + 0x20)
00021 #define TIM3_CR1_REGISTER1                          (TIM3_BASE_ADDRESS + 0x00)
00022 #define TIM3_CAPTURE_COMPARE_MODE_1_REGISTER        (TIM3_BASE_ADDRESS + 0x18)
00023 #define TIM3_CAPTURE_COMPARE_REGISTER_1             (TIM3_BASE_ADDRESS + 0x34)
00024 
00025 #define TIM3_CCMR2_CC3S_OUTPUT                      (0b11111100)
00026 #define TIM3_CCMR2_OC3FE                            (0b11111011)
00027 #define TIM3_CCMR2_OC3PE                            (0b00001000)
00028 #define TIM3_CCMR2_OC3M1                            (0b11101111)
00029 #define TIM3_CCMR2_OC3M2                            (0b01100000)
00030 
00031 #define TIM3_INTERRUPT_ENABLE_REGISTER              (TIM3_BASE_ADDRESS + 0x0C)
00032 
00033 
00034 
00035 void TMR3CH3OutputCompare(void)
00036 {
00037     uint16_t *reg;
00038     RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);//Enable Clock - SEE THE BUS UNDER WHICH THE REGISTER OR PERIPHERAL IS PRESENT
00039     
00040     reg = (uint16_t *)TIM3_STATUS_REGISTER; //Read flag value of STATUS REGISTER
00041     *reg = (~((uint16_t)0x01)); //Clear update event flag in STATUS REGISTER 
00042     
00043     reg = (uint16_t *)TIM3_PSC_REGISTER; //Read value of PRESCALER REGISTER
00044     *reg = 8999; //Setting the PRESCALER VALUE TO 899999, CALCULATE BY 90MHz/(Prescale + 1) --> ARR * 1/freq = 1Hz ---> freqcounter = 90MHz/(prescale +1)
00045     
00046     reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER; //Read value of AUTORELOAD REGISTER
00047     *reg = 10000; //Count till 65535 or 2^16-1, DEFINES LIMIT UPTO WHICH COUNTER SHOULD COUNT,POST THIS IT WILL RESET ITSELF
00048     
00049     /*Setup mode resgister 2 to output compare and enable output*/ //(0b00000000 00110000)
00050     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_2_REGISTER; //READ CAPTURE COMPARE MODE REGISTER 
00051     *reg = *reg | TIM_CCMR13_OC1M_1 | TIM_CCMR13_OC1M_0 | TIM_CCMR13_OUTPUT;//Setting the Output Compare to the OC3M bit fields and enabling it as an output
00052     
00053     reg = (uint16_t *)TIM3_COMPARE3_REGISTER; //READ VALUE OF COMPARE REGISTER 
00054     *reg = 2000; //Any value to count between two cycles- this is the value that we want to compare
00055     
00056     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER; //READ VALUE OF CAPTURE COMPARE ENABLE REGISTER
00057     *reg = *reg | 0x0100; // Enabling TIM3 Channel3 - Setting the CC3E (Enable) bit in the CCER REGISTER
00058     
00059     //Also keeping the default configuration for channel polarity
00060     reg = (uint16_t *)TIM3_CR1_REGISTER1;
00061     *reg = *reg | ((uint16_t)0x01);//Enabling the Timer3 subsystem by setting the CEN bit in TIM3_CR1 
00062 }
00063 
00064 
00065 void TMR3CH1GPIOCPin6asInputCapture(void)
00066 {
00067     uint16_t *reg;
00068     RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); //Enable Clock
00069     
00070     /*Clear Status register*/
00071     reg = (uint16_t *)TIM3_STATUS_REGISTER; //Read flag value of STATUS REGISTER
00072     *reg = (~((uint16_t)0x1)); //Clear update event flag in STATUS REGISTER
00073     
00074     reg = (uint16_t *)TIM3_PSC_REGISTER; //Read value of PRESCALER REGISTER
00075     *reg = 9999; //Setting the PRESCALER VALUE TO 9999, CALCULATE BY 90MHz/(Prescale + 1)
00076     
00077     reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER; //Read value of AUTORELOAD REGISTER
00078     *reg = 0xFFFF; //Count till 65535 or 2^16-1, DEFINES LIMIT UPTO WHICH COUNTER SHOULD COUNT,POST THIS IT WILL RESET ITSELF
00079     
00080     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_1_REGISTER; //READ CAPTURE COMPARE MODE REGISTER 
00081     *reg = *reg | 0x01;//Configuring CC1 Channel as Input
00082     //IC1 is mapped on TI1 - Configuring the REGISTER TO INPUT CAPTURE - CC1S BIT - 01
00083     //ALL OTHER BITS TO BE SET FOR INPUT CAPTURE ARE 00's
00084     //IC1PSC - 00 - NO PRESCALER
00085     //IC1F - 0000 - No filter, sampling is done at fDTS - Input Capture 1 Filter 
00086     
00087     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER; //READ VALUE OF CAPTURE COMPARE ENABLE REGISTER
00088     *reg = *reg | 0x01; // Enabling TIM3 Channel1 - Setting the CC3E bit in the CCER REGISTER
00089     //BY DEFAULT TIMER IS SENSITIVE TO RISING EDGE - ENABLE AND KEEP IT AS IT IS 
00090     
00091     reg = (uint16_t *)TIM3_CR1_REGISTER1;
00092     *reg = *reg | ((uint16_t)0x01);//Enabling the Timer3 subsystem by setting the CEN bit in TIM3_CR1 
00093 }
00094 
00095 /* Question - Why dont we initialize or set bits of IC1PSC, IC1F AND IC1  
00096 WHY CAN'T IT BE *reg=0b00000001*/
00097 
00098 uint16_t readCounterValueIfFlagIsSet(void)
00099 {
00100    uint16_t * reg1;
00101    uint16_t * reg2;
00102    uint16_t value;
00103    value=0;
00104    
00105    reg1 = (uint16_t *)TIM3_STATUS_REGISTER;
00106    
00107    if( *reg1 & (uint16_t)0b10 == 0b10 )
00108    {
00109        reg2 = (uint16_t *)TIM3_CAPTURE_COMPARE_REGISTER_1;
00110        value = *reg2;
00111        //Do we need to clear the flag? - The TIM3_STATUS_REGISTER
00112     }
00113     
00114     return value;
00115     
00116 }
00117        
00118    //read status reguster,
00119    //check if CCIF1 flag is set, if it is, you clear it rc_w0
00120                 //Statusregister = ~(CCIF1)
00121    //and also you read the INput caputre register and return the value. 
00122     
00123 
00124     
00125     
00126 uint16_t readCounterRegister(void)
00127 {
00128     uint16_t *reg;
00129     reg = (uint16_t *)TIM3_COUNTER_REGISTER;
00130     return *reg;
00131 }
00132 
00133 
00134 void TMR3CH3OutputPWMMode1(void)
00135 {
00136     uint16_t *reg;
00137     RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);//Enable Clock - SEE THE BUS UNDER WHICH THE REGISTER OR PERIPHERAL IS PRESENT
00138     
00139     reg = (uint16_t *)TIM3_STATUS_REGISTER; //Read flag value of STATUS REGISTER
00140     *reg = (~((uint16_t)0x01)); //Clear update event flag in STATUS REGISTER 
00141     
00142     reg = (uint16_t *)TIM3_PSC_REGISTER; //Read value of PRESCALER REGISTER
00143     *reg = 35999; //Setting the PRESCALER VALUE TO 35999
00144     
00145     reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER; //Read value of AUTORELOAD REGISTER
00146     *reg = 10000; //Count till 65535 or 2^16-1, DEFINES LIMIT UPTO WHICH COUNTER SHOULD COUNT,POST THIS IT WILL RESET ITSELF
00147     
00148     /*Setup mode resgister 2 to output compare and enable output*/ //(0b00000000 01101000)
00149     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_2_REGISTER; //READ CAPTURE COMPARE MODE REGISTER 
00150     *reg = *reg | TIM3_CCMR2_OC3M2 & TIM3_CCMR2_OC3M1 | TIM3_CCMR2_OC3PE & TIM3_CCMR2_OC3FE & TIM3_CCMR2_CC3S_OUTPUT ;//Setting the PWM Mode 1 to the OC3M bit fields and enabling it as an output
00151     
00152     reg = (uint16_t *)TIM3_COMPARE3_REGISTER; //READ VALUE OF COMPARE REGISTER 
00153     *reg = 5000; //We want half of 0.5Hz - Autoreload Register is 0.5Hz and Compare Value is at 0.25Hz
00154     
00155     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER; //READ VALUE OF CAPTURE COMPARE ENABLE REGISTER
00156     *reg = *reg | 0x0100; // Enabling TIM3 Channel3 - Setting the CC3E (Enable) bit in the CCER REGISTER
00157     
00158     //Also keeping the default configuration for channel polarity
00159     reg = (uint16_t *)TIM3_CR1_REGISTER1;
00160     *reg = *reg | ((uint16_t)0x01);//Enabling the Timer3 subsystem by setting the CEN bit in TIM3_CR1 
00161 }
00162 
00163 void initTimer3ToInterrupt(void)
00164 {
00165     uint16_t * reg;
00166     uint16_t prescalervalue2, autoreloadvalue;
00167  /* Timer 3 APB clock enable */
00168     RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
00169  /*enable the interrupt that would go to timer 3*/
00170     enableNVIC_Timer3(); 
00171  /* Compute Prescale and Autorreload */
00172     prescalervalue2 = 35999; //Frequency of clock is 90 MHz
00173     autoreloadvalue = 10000;
00174  /* Clear any pending flags in the status register */
00175     reg = (uint16_t *)TIM3_STATUS_REGISTER;
00176     *reg = 0;
00177  /* Set Prescale and Autorreload */
00178     reg = (uint16_t *)TIM3_PSC_REGISTER;
00179     *reg = prescalervalue2;
00180     reg = (uint16_t *)TIM3_AUTORELOAD_REGISTER;
00181     *reg = autoreloadvalue;
00182  /* Set Compare Value */
00183     reg = (uint16_t *)TIM3_COMPARE3_REGISTER;
00184     *reg = autoreloadvalue/2; 
00185  /* Enable Preload Register (Don’t HAVE to, but good practice) */
00186     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_MODE_2_REGISTER;
00187     *reg = *reg | 0b00001000;
00188  /*enable the TIM3 channel 3 counter and keep the default configuration for channel polarity*/
00189     reg = (uint16_t *)TIM3_CAPTURE_COMPARE_ENABLE_REGISTER;
00190     *reg = *reg | 0x0100;
00191  /*enable interrupt on capture compare channel 3*/
00192     reg = (uint16_t *)TIM3_INTERRUPT_ENABLE_REGISTER;
00193     *reg = (0x8 | 0x1); 
00194  /*enable timer 3*/
00195     reg = (uint16_t *)TIM3_CR1_REGISTER1;
00196     *reg = *reg | (uint16_t)0x01; 
00197 }
00198 
00199