Peripheral clocks configuration functions
[RCC_Private_Functions]

Configures the 48MHz clock Source.

Note:

This feature is only available for STM32F446xx/STM32F469_479xx devices.

Parameters:

RCC_ClockSource,:

specifies the 48MHz clock Source. This parameter can be one of the following values: RCC_48MHZCLKSource_PLL: 48MHz from PLL selected. RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected. RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ

Return values:

None

Definition at line 2794 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB1 clock gating for the specified IPs.

Note:

This feature is only available for STM32F446xx devices.

Parameters:

RCC_AHB1ClockGating,:

specifies the AHB1 clock gating. This parameter can be any combination of the following values: RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock RCC_AHB1ClockGating_SPARE: Spare clock RCC_AHB1ClockGating_SRAM: SRAM controller clock RCC_AHB1ClockGating_FLITF: Flash interface clock RCC_AHB1ClockGating_RCC: RCC clock

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2882 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB1 peripheral clock.

Note:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters:

RCC_AHBPeriph,:

specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_AHB1Periph_GPIOA: GPIOA clock RCC_AHB1Periph_GPIOB: GPIOB clock RCC_AHB1Periph_GPIOC: GPIOC clock RCC_AHB1Periph_GPIOD: GPIOD clock RCC_AHB1Periph_GPIOE: GPIOE clock RCC_AHB1Periph_GPIOF: GPIOF clock RCC_AHB1Periph_GPIOG: GPIOG clock RCC_AHB1Periph_GPIOG: GPIOG clock RCC_AHB1Periph_GPIOI: GPIOI clock RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) RCC_AHB1Periph_CRC: CRC clock RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock RCC_AHB1Periph_DMA1: DMA1_MORT clock RCC_AHB1Periph_DMA2: DMA2_MORT clock RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock RCC_AHB1Periph_OTG_HS: USB OTG HS clock RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2104 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.

Note:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.

After wakeup from SLEEP mode, the peripheral clock is enabled again.

By default, all peripheral clocks are enabled during SLEEP mode.

Parameters:

RCC_AHBPeriph,:

specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_AHB1Periph_GPIOA: GPIOA clock RCC_AHB1Periph_GPIOB: GPIOB clock RCC_AHB1Periph_GPIOC: GPIOC clock RCC_AHB1Periph_GPIOD: GPIOD clock RCC_AHB1Periph_GPIOE: GPIOE clock RCC_AHB1Periph_GPIOF: GPIOF clock RCC_AHB1Periph_GPIOG: GPIOG clock RCC_AHB1Periph_GPIOG: GPIOG clock RCC_AHB1Periph_GPIOI: GPIOI clock RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) RCC_AHB1Periph_CRC: CRC clock RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock RCC_AHB1Periph_DMA1: DMA1_MORT clock RCC_AHB1Periph_DMA2: DMA2_MORT clock RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock RCC_AHB1Periph_OTG_HS: USB OTG HS clock RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2523 of file stm32f4xx_rcc_mort.c.

Forces or releases AHB1 peripheral reset.

Parameters:

RCC_AHB1Periph,:

specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values: RCC_AHB1Periph_GPIOA: GPIOA clock RCC_AHB1Periph_GPIOB: GPIOB clock RCC_AHB1Periph_GPIOC: GPIOC clock RCC_AHB1Periph_GPIOD: GPIOD clock RCC_AHB1Periph_GPIOE: GPIOE clock RCC_AHB1Periph_GPIOF: GPIOF clock RCC_AHB1Periph_GPIOG: GPIOG clock RCC_AHB1Periph_GPIOG: GPIOG clock RCC_AHB1Periph_GPIOI: GPIOI clock RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) RCC_AHB1Periph_CRC: CRC clock RCC_AHB1Periph_DMA1: DMA1_MORT clock RCC_AHB1Periph_DMA2: DMA2_MORT clock RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock RCC_AHB1Periph_OTG_HS: USB OTG HS clock RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices

NewState,:

new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2317 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB2 peripheral clock.

Note:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters:

RCC_AHBPeriph,:	specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_AHB2Periph_DCMI: DCMI clock RCC_AHB2Periph_CRYP: CRYP clock RCC_AHB2Periph_HASH: HASH clock RCC_AHB2Periph_RNG: RNG clock RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,:	new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2136 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.

Note:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.

After wakeup from SLEEP mode, the peripheral clock is enabled again.

By default, all peripheral clocks are enabled during SLEEP mode.

Parameters:

RCC_AHBPeriph,:	specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_AHB2Periph_DCMI: DCMI clock RCC_AHB2Periph_CRYP: CRYP clock RCC_AHB2Periph_HASH: HASH clock RCC_AHB2Periph_RNG: RNG clock RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,:	new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2555 of file stm32f4xx_rcc_mort.c.

Forces or releases AHB2 peripheral reset.

Parameters:

RCC_AHB2Periph,:	specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values: RCC_AHB2Periph_DCMI: DCMI clock RCC_AHB2Periph_CRYP: CRYP clock RCC_AHB2Periph_HASH: HASH clock RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices RCC_AHB2Periph_OTG_FS: USB OTG FS clock
NewState,:	new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2346 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB3 peripheral clock.

Note:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters:

RCC_AHBPeriph,:	specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices) RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
NewState,:	new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2166 of file stm32f4xx_rcc_mort.c.

Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.

Note:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.

After wakeup from SLEEP mode, the peripheral clock is enabled again.

By default, all peripheral clocks are enabled during SLEEP mode.

Parameters:

RCC_AHBPeriph,:	specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices) RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
NewState,:	new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2585 of file stm32f4xx_rcc_mort.c.

Forces or releases AHB3 peripheral reset.

Parameters:

RCC_AHB3Periph,:	specifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices) RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
NewState,:	new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2373 of file stm32f4xx_rcc_mort.c.

Enables or disables the Low Speed APB (APB1) peripheral clock.

Note:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters:

RCC_APB1Periph,:

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB1Periph_TIM2: TIM2 clock RCC_APB1Periph_TIM3: TIM3 clock RCC_APB1Periph_TIM4: TIM4 clock RCC_APB1Periph_TIM5: TIM5 clock RCC_APB1Periph_TIM6: TIM6 clock RCC_APB1Periph_TIM7: TIM7 clock RCC_APB1Periph_TIM12: TIM12 clock RCC_APB1Periph_TIM13: TIM13 clock RCC_APB1Periph_TIM14: TIM14 clock RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) RCC_APB1Periph_WWDG: WWDG clock RCC_APB1Periph_SPI2: SPI2 clock RCC_APB1Periph_SPI3: SPI3 clock RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) RCC_APB1Periph_USART2: USART2 clock RCC_APB1Periph_USART3: USART3 clock RCC_APB1Periph_UART4: UART4 clock RCC_APB1Periph_UART5: UART5 clock RCC_APB1Periph_I2C1: I2C1 clock RCC_APB1Periph_I2C2: I2C2 clock RCC_APB1Periph_I2C3: I2C3 clock RCC_APB1Periph_FMPI2C1:FMPI2C1 clock RCC_APB1Periph_CAN1: CAN1 clock RCC_APB1Periph_CAN2: CAN2 clock RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices) RCC_APB1Periph_PWR: PWR clock RCC_APB1Periph_DAC: DAC clock RCC_APB1Periph_UART7: UART7 clock RCC_APB1Periph_UART8: UART8 clock

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2223 of file stm32f4xx_rcc_mort.c.

Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.

Note:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.

After wakeup from SLEEP mode, the peripheral clock is enabled again.

By default, all peripheral clocks are enabled during SLEEP mode.

Parameters:

RCC_APB1Periph,:

specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB1Periph_TIM2: TIM2 clock RCC_APB1Periph_TIM3: TIM3 clock RCC_APB1Periph_TIM4: TIM4 clock RCC_APB1Periph_TIM5: TIM5 clock RCC_APB1Periph_TIM6: TIM6 clock RCC_APB1Periph_TIM7: TIM7 clock RCC_APB1Periph_TIM12: TIM12 clock RCC_APB1Periph_TIM13: TIM13 clock RCC_APB1Periph_TIM14: TIM14 clock RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) RCC_APB1Periph_WWDG: WWDG clock RCC_APB1Periph_SPI2: SPI2 clock RCC_APB1Periph_SPI3: SPI3 clock RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) RCC_APB1Periph_USART2: USART2 clock RCC_APB1Periph_USART3: USART3 clock RCC_APB1Periph_UART4: UART4 clock RCC_APB1Periph_UART5: UART5 clock RCC_APB1Periph_I2C1: I2C1 clock RCC_APB1Periph_I2C2: I2C2 clock RCC_APB1Periph_I2C3: I2C3 clock RCC_APB1Periph_FMPI2C1: FMPI2C1 clock RCC_APB1Periph_CAN1: CAN1 clock RCC_APB1Periph_CAN2: CAN2 clock RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices) RCC_APB1Periph_PWR: PWR clock RCC_APB1Periph_DAC: DAC clock RCC_APB1Periph_UART7: UART7 clock RCC_APB1Periph_UART8: UART8 clock

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2642 of file stm32f4xx_rcc_mort.c.

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:

RCC_APB1Periph,:

specifies the APB1 peripheral to reset. This parameter can be any combination of the following values: RCC_APB1Periph_TIM2: TIM2 clock RCC_APB1Periph_TIM3: TIM3 clock RCC_APB1Periph_TIM4: TIM4 clock RCC_APB1Periph_TIM5: TIM5 clock RCC_APB1Periph_TIM6: TIM6 clock RCC_APB1Periph_TIM7: TIM7 clock RCC_APB1Periph_TIM12: TIM12 clock RCC_APB1Periph_TIM13: TIM13 clock RCC_APB1Periph_TIM14: TIM14 clock RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) RCC_APB1Periph_WWDG: WWDG clock RCC_APB1Periph_SPI2: SPI2 clock RCC_APB1Periph_SPI3: SPI3 clock RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) RCC_APB1Periph_USART2: USART2 clock RCC_APB1Periph_USART3: USART3 clock RCC_APB1Periph_UART4: UART4 clock RCC_APB1Periph_UART5: UART5 clock RCC_APB1Periph_I2C1: I2C1 clock RCC_APB1Periph_I2C2: I2C2 clock RCC_APB1Periph_I2C3: I2C3 clock RCC_APB1Periph_FMPI2C1:FMPI2C1 clock RCC_APB1Periph_CAN1: CAN1 clock RCC_APB1Periph_CAN2: CAN2 clock RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices) RCC_APB1Periph_PWR: PWR clock RCC_APB1Periph_DAC: DAC clock RCC_APB1Periph_UART7: UART7 clock RCC_APB1Periph_UART8: UART8 clock

NewState,:

new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2427 of file stm32f4xx_rcc_mort.c.

Enables or disables the High Speed APB (APB2) peripheral clock.

Note:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters:

RCC_APB2Periph,:

specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB2Periph_TIM1: TIM1 clock RCC_APB2Periph_TIM8: TIM8 clock RCC_APB2Periph_USART1: USART1 clock RCC_APB2Periph_USART6: USART6 clock RCC_APB2Periph_ADC1: ADC1 clock RCC_APB2Periph_ADC2: ADC2 clock RCC_APB2Periph_ADC3: ADC3 clock RCC_APB2Periph_SDIO: SDIO clock RCC_APB2Periph_SPI1: SPI1 clock RCC_APB2Periph_SPI4: SPI4 clock RCC_APB2Periph_SYSCFG: SYSCFG clock RCC_APB2Periph_EXTIT: EXTIIT clock RCC_APB2Periph_TIM9: TIM9 clock RCC_APB2Periph_TIM10: TIM10 clock RCC_APB2Periph_TIM11: TIM11 clock RCC_APB2Periph_SPI5: SPI5 clock RCC_APB2Periph_SPI6: SPI6 clock RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices) RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices) RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2275 of file stm32f4xx_rcc_mort.c.

Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.

Note:

Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.

After wakeup from SLEEP mode, the peripheral clock is enabled again.

By default, all peripheral clocks are enabled during SLEEP mode.

Parameters:

RCC_APB2Periph,:

specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: RCC_APB2Periph_TIM1: TIM1 clock RCC_APB2Periph_TIM8: TIM8 clock RCC_APB2Periph_USART1: USART1 clock RCC_APB2Periph_USART6: USART6 clock RCC_APB2Periph_ADC1: ADC1 clock RCC_APB2Periph_ADC2: ADC2 clock RCC_APB2Periph_ADC3: ADC3 clock RCC_APB2Periph_SDIO: SDIO clock RCC_APB2Periph_SPI1: SPI1 clock RCC_APB2Periph_SPI4: SPI4 clock RCC_APB2Periph_SYSCFG: SYSCFG clock RCC_APB2Periph_EXTIT: EXTIIT clock RCC_APB2Periph_TIM9: TIM9 clock RCC_APB2Periph_TIM10: TIM10 clock RCC_APB2Periph_TIM11: TIM11 clock RCC_APB2Periph_SPI5: SPI5 clock RCC_APB2Periph_SPI6: SPI6 clock RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices) RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices) RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2694 of file stm32f4xx_rcc_mort.c.

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:

RCC_APB2Periph,:

specifies the APB2 peripheral to reset. This parameter can be any combination of the following values: RCC_APB2Periph_TIM1: TIM1 clock RCC_APB2Periph_TIM8: TIM8 clock RCC_APB2Periph_USART1: USART1 clock RCC_APB2Periph_USART6: USART6 clock RCC_APB2Periph_ADC1: ADC1 clock RCC_APB2Periph_ADC2: ADC2 clock RCC_APB2Periph_ADC3: ADC3 clock RCC_APB2Periph_SDIO: SDIO clock RCC_APB2Periph_SPI1: SPI1 clock RCC_APB2Periph_SPI4: SPI4 clock RCC_APB2Periph_SYSCFG: SYSCFG clock RCC_APB2Periph_TIM9: TIM9 clock RCC_APB2Periph_TIM10: TIM10 clock RCC_APB2Periph_TIM11: TIM11 clock RCC_APB2Periph_SPI5: SPI5 clock RCC_APB2Periph_SPI6: SPI6 clock RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices) RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices) RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)

NewState,:

new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 2474 of file stm32f4xx_rcc_mort.c.

Forces or releases the Backup domain reset.

Note:

This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.

The BKPSRAM is not affected by this reset.

Parameters:

NewState,:

new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1519 of file stm32f4xx_rcc_mort.c.

Configures the CEC clock Source.

Note:

This feature is only available for STM32F446xx devices.

Parameters:

RCC_ClockSource,:

specifies the CEC clock Source. This parameter can be one of the following values: RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected. RCC_CECCLKSource_LSE: CEC clock from LSE selected.

Return values:

None

Definition at line 2931 of file stm32f4xx_rcc_mort.c.

Configures the DFSDM Audio clock source (DFSDMACLK).

Note:

This function must be called before enabling the DFSDM APB clock.

Parameters:

RCC_DFSDM1ACLKSource,:

specifies the DFSDM clock source. This parameter can be one of the following values: RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.

Return values:

None

Definition at line 1993 of file stm32f4xx_rcc_mort.c.

Configures the DFSDM clock source (DFSDMCLK).

Note:

This function must be called before enabling the DFSDM APB clock.

Parameters:

RCC_DFSDMCLKSource,:

specifies the DFSDM clock source. This parameter can be one of the following values: RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source. RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source.

Return values:

None

Definition at line 1964 of file stm32f4xx_rcc_mort.c.

Configures the DFSDM Audio clock source (DFSDMACLK).

Note:

This function must be called before enabling the DFSDM APB clock.

Parameters:

RCC_DFSDM2ACLKSource,:

specifies the DFSDM clock source. This parameter can be one of the following values: RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.

Return values:

None

Definition at line 2023 of file stm32f4xx_rcc_mort.c.

Configures the DSI clock Source.

Note:

This feature is only available for STM32F469_479xx devices.

Parameters:

RCC_ClockSource,:

specifies the DSI clock Source. This parameter can be one of the following values: RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case). RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode).

Return values:

None

Definition at line 2767 of file stm32f4xx_rcc_mort.c.

Configures the FMPI2C1 clock Source.

Note:

This feature is only available for STM32F446xx devices.

Parameters:

RCC_ClockSource,:

specifies the FMPI2C1 clock Source. This parameter can be one of the following values: RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected. RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected. RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.

Return values:

None

Definition at line 2958 of file stm32f4xx_rcc_mort.c.

Configures the I2S clock source (I2SCLK).

Note:

This function must be called before enabling the I2S clock.

Parameters:

RCC_I2SCLKSource,:

specifies the I2S clock source. This parameter can be one of the following values: RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.

Return values:

None

Note:

This function must be called before enabling the I2S APB clock.

Parameters:

RCC_I2SCLKSource,:

specifies the I2S clock source. This parameter can be one of the following values: RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source

Return values:

None

Definition at line 1684 of file stm32f4xx_rcc_mort.c.

Configures the I2S clock source (I2SCLK).

Note:

This function must be called before enabling the I2S APB clock.

Parameters:

RCC_I2SAPBx,:	specifies the APBx I2S clock source. This parameter can be one of the following values: RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
RCC_I2SCLKSource,:	specifies the I2S clock source. This parameter can be one of the following values: RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source

Return values:

None

Definition at line 1545 of file stm32f4xx_rcc_mort.c.

Configures the LPTIM1 clock Source.

Note:

This feature is only available for STM32F410xx devices.

Parameters:

RCC_ClockSource,:

specifies the LPTIM1 clock Source. This parameter can be one of the following values: RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected. RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected. RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected. RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected.

Return values:

None

Definition at line 2745 of file stm32f4xx_rcc_mort.c.

Configures the External Low Speed oscillator mode (LSE mode).

Note:

This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.

Parameters:

Mode,:

specifies the LSE mode. This parameter can be one of the following values: RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.

Return values:

None

Definition at line 2718 of file stm32f4xx_rcc_mort.c.

Configures the LTDC clock Divider coming from PLLSAI.

Note:

The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.

This function must be called before enabling the PLLSAI.

Parameters:

RCC_PLLSAIDivR,:

specifies the PLLSAI division factor for LTDC clock . LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR This parameter can be one of the following values: RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2 RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4 RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8 RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16

Return values:

None

Definition at line 1934 of file stm32f4xx_rcc_mort.c.

Enables or disables the RTC clock.

Note:

This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.

Parameters:

NewState,:

new state of the RTC clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 1502 of file stm32f4xx_rcc_mort.c.

Configures the RTC clock (RTCCLK).

Note:

As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).

Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).

Parameters:

RCC_RTCCLKSource,:

specifies the RTC clock source. This parameter can be one of the following values: RCC_RTCCLKSource_LSE: LSE selected as RTC clock RCC_RTCCLKSource_LSI: LSI selected as RTC clock RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]

Note:

If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.

The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Return values:

None

Definition at line 1470 of file stm32f4xx_rcc_mort.c.

Configures SAI1BlockA clock source selection.

Note:

This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.

Parameters:

RCC_SAIBlockACLKSource,:

specifies the SAI Block A clock source. This parameter can be one of the following values: RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source

Return values:

None

Note:

This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.

This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.

Parameters:

RCC_SAIBlockACLKSource,:

specifies the SAI Block A clock source. This parameter can be one of the following values: RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block A clock RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block A clock RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock

Return values:

None

Definition at line 1620 of file stm32f4xx_rcc_mort.c.

Configures SAI1BlockB clock source selection.

Note:

This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.

Parameters:

RCC_SAIBlockBCLKSource,:

specifies the SAI Block B clock source. This parameter can be one of the following values: RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source

Return values:

None

Note:

This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.

This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.

Parameters:

RCC_SAIBlockBCLKSource,:

specifies the SAI Block B clock source. This parameter can be one of the following values: RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block B clock RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block B clock RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block B clock

Return values:

None

Definition at line 1651 of file stm32f4xx_rcc_mort.c.

Configures the SAIx clock source (SAIxCLK).

Note:

This function must be called before enabling the SAIx APB clock.

Parameters:

RCC_SAIInstance,:	specifies the SAIx clock source. This parameter can be one of the following values: RCC_SAIInstance_SAI1: SAI1 clock source selection RCC_SAIInstance_SAI2: SAI2 clock source selections
RCC_SAICLKSource,:	specifies the SAI clock source. This parameter can be one of the following values: RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source RCC_SAICLKSource_PLL: PLL clock used as SAI clock source RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source

Return values:

None

Definition at line 1584 of file stm32f4xx_rcc_mort.c.

Configures the SAI clock Divider coming from PLLI2S.

Note:

This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.

This function must be called before enabling the PLLI2S.

Parameters:

RCC_PLLI2SDivQ,:

specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ

Return values:

None

Definition at line 1803 of file stm32f4xx_rcc_mort.c.

Configures the SAI clock Divider coming from PLLI2S.

Note:

This function can be used only for STM32F413_423xx

Parameters:

RCC_PLLI2SDivR,:

specifies the PLLI2S division factor for SAI1 clock. This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR

Return values:

None

Definition at line 1865 of file stm32f4xx_rcc_mort.c.

Configures the SAI clock Divider coming from PLL.

Note:

This function can be used only for STM32F413_423xx

This function must be called before enabling the PLLSAI.

Parameters:

RCC_PLLDivR,:

specifies the PLL division factor for SAI1 clock. This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLR) / RCC_PLLDivR

Return values:

None

Definition at line 1897 of file stm32f4xx_rcc_mort.c.

Configures the SAI clock Divider coming from PLLSAI.

Note:

This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.

This function must be called before enabling the PLLSAI.

Parameters:

RCC_PLLSAIDivQ,:

specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ

Return values:

None

Definition at line 1835 of file stm32f4xx_rcc_mort.c.

Configures the SDIO clock Source.

Note:

This feature is only available for STM32F469_479xx/STM32F446xx devices.

Parameters:

RCC_ClockSource,:

specifies the SDIO clock Source. This parameter can be one of the following values: RCC_SDIOCLKSource_48MHZ: 48MHz clock selected. RCC_SDIOCLKSource_SYSCLK: system clock selected.

Return values:

None

Definition at line 2838 of file stm32f4xx_rcc_mort.c.

Configures the SPDIFRX clock Source.

Note:

This feature is only available for STM32F446xx devices.

Parameters:

RCC_ClockSource,:

specifies the SPDIFRX clock Source. This parameter can be one of the following values: RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected. RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.

Return values:

None

Definition at line 2907 of file stm32f4xx_rcc_mort.c.

Configures the Timers clocks prescalers selection.

Note:

This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.

Parameters:

RCC_TIMCLKPrescaler

: specifies the Timers clocks prescalers selection This parameter can be one of the following values: RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more. RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.

Return values:

None

Definition at line 2062 of file stm32f4xx_rcc_mort.c.