hardware_dma_controller.c

00001 #include "gpio.h"
00002 #include "hardware_dma_controller.h"
00003 #include "stm32f4xx_rcc_mort.h"
00004 #include "hardware_adc.h"
00005 
00006 //Defining Base Addresses and Registers
00007 #define DMA2_BASE_ADDRESS               ((uint32_t)0x40026400)
00008 #define DMA2_LISR_REGISTER              (DMA2_BASE_ADDRESS + 0x00)
00009 #define DMA2_HISR_REGISTER              (DMA2_BASE_ADDRESS + 0x04)
00010 #define DMA2_LIFCR_REGISTER             (DMA2_BASE_ADDRESS + 0x08)
00011 #define DMA2_HIFCR_REGISTER             (DMA2_BASE_ADDRESS + 0x0C)
00012 #define DMA2_S0CR_REGISTER              (DMA2_BASE_ADDRESS + 0x10)
00013 #define DMA2_S0NDTR_REGISTER            (DMA2_BASE_ADDRESS + 0x14)
00014 #define DMA2_S0PAR_REGISTER             (DMA2_BASE_ADDRESS + 0x18)
00015 #define DMA2_S0M0AR_REGISTER            (DMA2_BASE_ADDRESS + 0x1C)
00016 #define DMA2_S0M1AR_REGISTER            (DMA2_BASE_ADDRESS + 0x20)
00017 #define DMA2_S0FCR_REGISTER             (DMA2_BASE_ADDRESS + 0x24)
00018 
00019 //Defining bits and flags
00020 //DMA_SxCR: DMA STREAM X CONFIGURATION REGISTER
00021 #define DMA_SxCR_CHANNEL_2_SELECT       (((uint32_t)2)<<25) //To Select Channel 2
00022 #define DMA_SxCR_MSIZE_HALF_WORD        (((uint32_t)1)<<13) //The location memory is 16 bits in length
00023 #define DMA_SxCR_PSIZE_HALF_WORD        (((uint32_t)1)<<11) //The peripheral data size is 16 bits in length
00024 #define DMA_SxCR_MINC_INCREMENT         (((uint32_t)1)<<10) //Increment the place where you store the data each transfer
00025 #define DMA_SxCR_CIRC_ENABLE            (((uint32_t)1)<<8) //Enable circular mode
00026 #define DMA_SxCR_DIR_PERTOMEM           0
00027 #define DMA_SxCR_STREAM_ENABLE          1
00028 
00029 
00030 #define ADC_REGISTER_BASE_ADDRESS   ((uint32_t)0x40012000)
00031 #define ADC_3_BASE_ADDRESS          (ADC_REGISTER_BASE_ADDRESS + 0x200)
00032 #define ADC_3_DR_REGISTER           (ADC_3_BASE_ADDRESS + 0x4C)
00033 
00034 
00035 uint16_t adcDmaDataStorageBuffer_3_Channel[3]; //Variable Definition to store read values
00036 uint16_t adcDmaDataStorageBuffer_1_Channel[1]; //Variable Definition to store read value
00037 
00038 
00039 //FUNCTION GIVEN BY PROFESSOR TO SETUP DMA TO READ VALUES FROM 3 PINS
00040 void initDMAForAdc3_1Channel(void)
00041 {
00042     uint32_t * reg;
00043     RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); /* Enable the clock */
00044     
00045     // Configure Stream 0 to use Channel 2 - ADC3
00046     reg = (uint32_t *)DMA2_S0CR_REGISTER;
00047     *reg = DMA_SxCR_CHANNEL_2_SELECT + DMA_SxCR_MSIZE_HALF_WORD + DMA_SxCR_PSIZE_HALF_WORD + DMA_SxCR_DIR_PERTOMEM +DMA_SxCR_CIRC_ENABLE;
00048     
00049     //We will transfer 1 data registers for 1 channels of ADC
00050     reg = (uint32_t *)DMA2_S0NDTR_REGISTER;
00051     *reg = 1;
00052     
00053     //We will transfer from the ADC3 Data Register
00054     reg = (uint32_t *)DMA2_S0PAR_REGISTER;
00055     *reg = ADC_3_DR_REGISTER; //THIS FUNCTION IS DEFINED IN HARDWARE ADC
00056     
00057     //We will transfer to the adcDmaDataStorageBuffer we created
00058     reg = (uint32_t *)DMA2_S0M0AR_REGISTER;
00059     *reg = (uint32_t)&adcDmaDataStorageBuffer_1_Channel[0]; //QUESTION - WHY IS THIS ZERO??? DIDNT UNDERSTAND THIS STATEMENT
00060     
00061 }
00062 
00063 
00064 
00065 //FUNCTION GIVEN BY PROFESSOR TO SETUP DMA TO READ VALUES FROM 3 PINS
00066 void initDMAForAdc3_3Channels(void)
00067 {
00068     uint32_t * reg;
00069     RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); /* Enable the clock */
00070     
00071     // Configure Stream 0 to use Channel 2 (ADC3)
00072     reg = (uint32_t *)DMA2_S0CR_REGISTER;
00073     *reg = DMA_SxCR_CHANNEL_2_SELECT + DMA_SxCR_MSIZE_HALF_WORD + DMA_SxCR_PSIZE_HALF_WORD + DMA_SxCR_MINC_INCREMENT + DMA_SxCR_DIR_PERTOMEM +DMA_SxCR_CIRC_ENABLE;
00074     
00075     //We will transfer 3 data registers for 3 channels of ADC
00076     reg = (uint32_t *)DMA2_S0NDTR_REGISTER;
00077     *reg = 3;
00078     
00079     //We will transfer from the ADC3 Data Register
00080     reg = (uint32_t *)DMA2_S0PAR_REGISTER;
00081     *reg = ADC_3_DR_REGISTER; //THIS FUNCTION IS DETECTED
00082     
00083     //We will transfer to the adcDmaDataStorageBuffer we just created
00084     reg = (uint32_t *)DMA2_S0M0AR_REGISTER;
00085     *reg = (uint32_t)& adcDmaDataStorageBuffer_3_Channel[0];
00086     
00087 }
00088 
00089 
00090 void enableDMAForAdc3_3channels (void)
00091 {
00092     uint32_t * reg;
00093     reg = (uint32_t *)DMA2_S0CR_REGISTER;
00094     *reg = *reg | DMA_SxCR_STREAM_ENABLE;
00095 }
00096 
00097 void enableDMAForAdc3_1channels (void)
00098 {
00099     uint32_t * reg;
00100     reg = (uint32_t *)DMA2_S0CR_REGISTER;
00101     *reg = *reg | DMA_SxCR_STREAM_ENABLE;
00102 }
00103 
00104 
00105 
00106 uint16_t returnADC3StoredValue3Channel(uint8_t index)
00107 {
00108     return adcDmaDataStorageBuffer_3_Channel[index];
00109 }
00110     
00111     
00112 uint16_t returnADC3StoredValue1Channel(uint8_t index)
00113 {
00114     return adcDmaDataStorageBuffer_1_Channel[index];
00115 }
00116     
00117      
00118      
00119