hardware_adc.c

00001 #include "gpio.h"
00002 #include "hardware_adc.h"
00003 #include "stm32f4xx_rcc_mort.h"
00004 #include "hardware_dma_controller.h"
00005 
00006 //DEFINITION OF BASE ADDRESS FOR ADC1-ADC2-ADC3
00007 #define ADC_REGISTER_BASE_ADDRESS ((uint32_t)0x40012000)
00008 
00009 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR ADC1
00010 #define ADC_1_BASE_ADDRESS          (ADC_REGISTER_BASE_ADDRESS + 0x000)
00011 #define ADC_1_SR_REGISTER           (ADC_1_BASE_ADDRESS + 0x00)
00012 #define ADC_1_CR1_REGISTER          (ADC_1_BASE_ADDRESS + 0x04)
00013 #define ADC_1_CR2_REGISTER          (ADC_1_BASE_ADDRESS + 0x08)
00014 #define ADC_1_SMPR1_REGISTER        (ADC_1_BASE_ADDRESS + 0x0C)
00015 #define ADC_1_SMPR2_REGISTER        (ADC_1_BASE_ADDRESS + 0x10)
00016 #define ADC_1_SQR1_REGISTER         (ADC_1_BASE_ADDRESS + 0x2C)
00017 #define ADC_1_SQR2_REGISTER         (ADC_1_BASE_ADDRESS + 0x30)
00018 #define ADC_1_SQR3_REGISTER         (ADC_1_BASE_ADDRESS + 0x34)
00019 #define ADC_1_DR_REGISTER           (ADC_1_BASE_ADDRESS + 0x4C)
00020 
00021 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR ADC2
00022 #define ADC_2_BASE_ADDRESS          (ADC_REGISTER_BASE_ADDRESS + 0x100)
00023 #define ADC_2_SR_REGISTER           (ADC_2_BASE_ADDRESS + 0x00)
00024 #define ADC_2_CR1_REGISTER          (ADC_2_BASE_ADDRESS + 0x04)
00025 #define ADC_2_CR2_REGISTER          (ADC_2_BASE_ADDRESS + 0x08)
00026 #define ADC_2_SMPR1_REGISTER        (ADC_2_BASE_ADDRESS + 0x0C)
00027 #define ADC_2_SMPR2_REGISTER        (ADC_2_BASE_ADDRESS + 0x10)
00028 #define ADC_2_SQR1_REGISTER         (ADC_2_BASE_ADDRESS + 0x2C)
00029 #define ADC_2_SQR2_REGISTER         (ADC_2_BASE_ADDRESS + 0x30)
00030 #define ADC_2_SQR3_REGISTER         (ADC_2_BASE_ADDRESS + 0x34)
00031 #define ADC_2_DR_REGISTER           (ADC_2_BASE_ADDRESS + 0x4C)
00032 
00033 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR ADC3
00034 #define ADC_3_BASE_ADDRESS          (ADC_REGISTER_BASE_ADDRESS + 0x200)
00035 #define ADC_3_SR_REGISTER           (ADC_3_BASE_ADDRESS + 0x00)
00036 #define ADC_3_CR1_REGISTER          (ADC_3_BASE_ADDRESS + 0x04)
00037 #define ADC_3_CR2_REGISTER          (ADC_3_BASE_ADDRESS + 0x08)
00038 #define ADC_3_SMPR1_REGISTER        (ADC_3_BASE_ADDRESS + 0x0C)
00039 #define ADC_3_SMPR2_REGISTER        (ADC_3_BASE_ADDRESS + 0x10)
00040 #define ADC_3_SQR1_REGISTER         (ADC_3_BASE_ADDRESS + 0x2C)
00041 #define ADC_3_SQR2_REGISTER         (ADC_3_BASE_ADDRESS + 0x30)
00042 #define ADC_3_SQR3_REGISTER         (ADC_3_BASE_ADDRESS + 0x34)
00043 #define ADC_3_DR_REGISTER           (ADC_3_BASE_ADDRESS + 0x4C)
00044 
00045 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR COMMON REGISTERS
00046 #define ADC_COMMON_REGISTERS        (ADC_REGISTER_BASE_ADDRESS + 0x300)
00047 #define ADC_CSR_REGISTER            (ADC_COMMON_REGISTERS + 0x00)
00048 #define ADC_CCR_REGISTER            (ADC_COMMON_REGISTERS + 0x04)
00049 
00050 
00051 
00052 //FUNCTION DEFINED FOR - ADC 3 CONTINUOUS CONVERSION USING CHANNEL 5 
00053 void initADC3_5_withDMA(void)
00054 {
00055      uint32_t * reg;
00056      
00057      //Turn on ADC3 BUS CLOCKS
00058      RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE); /* Enable the clock */
00059      
00060      //Initialize GPIO F 7 as Analog
00061      InitPortFPin7asAnalog();
00062      
00063      initDMAForAdc3_1Channel();              //FUNCTION IS DEFINED // CHECK FOR THIS FUNCTION IN MAIN
00064      enableDMAForAdc3_1channels();           //FUNCTION IS DEFINED
00065      
00066      //Writing Pre Scale Value divided by 4 - 01 in bits 17&16 of CCR Register
00067      reg = (uint32_t *)ADC_CCR_REGISTER;
00068      *reg = 0x10000; 
00069      
00070      //STATUS REGISTER IS CLEARED IN START CONVERSION FUNCTION
00071      
00072 //     //Clear Status Register                    //QUESTION - IS THIS ACTION MANDATORY ??
00073 //     reg = (uint32_t *)ADC_3_SR_REGISTER;
00074 //     *reg = 0;
00075 //        
00076 
00077      //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
00078      reg = (uint32_t *)ADC_3_CR1_REGISTER;
00079      *reg = 0; //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
00080      //*reg = *reg & (~((uint32_t)0x3000000)) & (~((uint32_t)0x20)); //DO YOU HAVE TO WRITE TO THIS REGISTER OR READ THE VALUE ???
00081      
00082      //Configure ADC External trigger disabled, right data alignment, DMA Enabled ,
00083      //EOC is set at the end of each regular conversion, continuous conversion enabled 
00084      reg = (uint32_t *)ADC_3_CR2_REGISTER;
00085      *reg = ((uint32_t)0x02) + ((uint32_t)0x100) + ((uint32_t)0x400);
00086      //*reg = ADC_E0CS + ADC_CONT + ADC_DDS + ADC_DMA;   //DO YOU HAVE TO WRITE TO THIS REGISTER OR READ THE VALUE ???
00087         
00088      //There will be 1 Channel (Channel 5) in the sequence of conversions - SQR1
00089      reg = (uint32_t *)ADC_3_SQR1_REGISTER;
00090      *reg = 0; //1 conversion is 0000
00091      
00092      //Configure Channels 5 to max sampling times (480 cycles)
00093      reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
00094      *reg = 0x38000; //Writing 111 to bits 15,16&17
00095      
00096      //Configure the sequence of conversion for the ADC (7)
00097      reg = (uint32_t *)ADC_3_SQR3_REGISTER;
00098      * reg = 0x05; //WRITING 7 TO SQR1 (BITS 0 TO 4) IN SQR3 REGISTER
00099      
00100      enableADC3(); //ADDITIONAL LINE - IT ALREADY IS PRESENT IN START ADC CONVERSION
00101      
00102      //Start a software conversion
00103      //Need to do this separately
00104      
00105 }
00106 
00107 
00108 
00109 //FUNCTION DEFINED BY PROFESSOR - ADC 3 SCAN CONTINUOUS CONVERSION USING 3 CHANNELS
00110  void initADC3_567_withDMA(void)
00111  {
00112      uint32_t * reg;
00113      
00114      //Turn on ADC3 BUS CLOCKS
00115      RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE); /* Enable the clock */
00116      
00117      //Initialize GPIO F 7 8 9 as Analog
00118      InitPortFPin7Pin8Pin9asAnalog();
00119      
00120      initDMAForAdc3_3Channels();             //FUNCTION IS DEFINED
00121      enableDMAForAdc3_3channels();           //FUNCTION IS DEFINED
00122      
00123      //I HAVE NOT CLEARED STATUS REGISTER - NO NEED - STATUS REGISTER IS CLEARED WHILE CALLING FUNCTION - START CONVERSION
00124      
00125      //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED , SCAN MODE ENABLED 
00126      //TO BE ABLE TO SCAN A GROUP OF CHANNELS
00127      reg = (uint32_t *)ADC_3_CR1_REGISTER;
00128      //*reg = 0; //IS THIS STATEMENT MANDATORY TO SET 25TH and 24th BIT AS 00
00129      *reg = (uint32_t)0x100 ;  //THIS STATEMENT ALSO SETS 25TH and 24th BIT AS 00 but it does set the SCAN MODE ON
00130      
00131      //Configure ADC External trigger dissabled (29th and 28th Bit is set to 0), right data alignment (11th bit is 0), DMA ,
00132      //EOC is set at the end of each regular conversion, continuous conversion enabled 
00133      reg = (uint32_t *)ADC_3_CR2_REGISTER;
00134      *reg = (uint32_t)0x100 + (uint32_t)0x02 + (uint32_t)0x400; //Is the 10th bit supposed to be set to 0 - EC0 SET AT THE END OF EACH CONVERSION
00135      
00136      //There will be 3 channels in the sequence of conversions
00137      reg = (uint32_t *)ADC_3_SQR1_REGISTER;
00138      *reg = (uint32_t)0x200000; //0010 3 will be 2 actually
00139      
00140      //Configure Channels 5,6,7 to max sampling times (480 cycles)
00141      reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
00142      *reg = (uint32_t)0x38000 + (uint32_t)0x1C0000 + (uint32_t)0xE00000; //In the order of 5th Channel set to 480 Cycles , 6th Channel set to 480 Cycles , 7th Channel set to 480 Cycles
00143      
00144      //Configure the sequence of conversion for the ADC (5,6,7)
00145      reg = (uint32_t *)ADC_3_SQR3_REGISTER;
00146      * reg = (uint32_t)0x05 + (uint32_t)0xC0 + (uint32_t)0x1C00; //In the order of SQ1 written to 5, SQ2 written to 6 . SQ3 writtent to 7
00147      
00148      enableADC3();
00149      
00150      //Start a software conversion
00151      //Need to do this separately
00152      
00153 }
00154      
00155 
00156 //FUNCTON TO TURN ON ADC3
00157 void enableADC3(void)
00158 {
00159      uint32_t * reg;
00160      reg = (uint32_t *)ADC_3_CR2_REGISTER;
00161      *reg= *reg | ((uint32_t)0x01);
00162 }    
00163 
00164 
00165 //FUNCTION TO START ADC CONVERSION
00166 void startADCConversion(void)
00167 {
00168      uint32_t * reg;
00169      
00170      reg = (uint32_t *)ADC_3_SR_REGISTER;
00171      *reg = 0;
00172      
00173      reg = (uint32_t *)ADC_3_CR2_REGISTER;
00174      *reg = *reg | 0x01;
00175 }