Rajath Ravi / Mbed 2 deprecated ADC_DMA_POST_LEC12

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Dependencies:   mbed

hardware_dma_controller.c@0:716b93ab9a58, 2021-10-29 (annotated)

Committer:
rajathr
Date:
Fri Oct 29 20:56:20 2021 +0000
Revision:
0:716b93ab9a58
Child:
1:c125f4e65df7
AS ON 29TH OCT AT 5PM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:716b93ab9a58 1 #include "gpio.h"
rajathr 0:716b93ab9a58 2 #include "hardware_dma_controller.h"
rajathr 0:716b93ab9a58 3 #include "stm32f4xx_rcc_mort.h"
rajathr 0:716b93ab9a58 4 #include "hardware_adc.h"
rajathr 0:716b93ab9a58 5
rajathr 0:716b93ab9a58 6 //Defining Base Addresses and Registers
rajathr 0:716b93ab9a58 7 #define DMA2_BASE_ADDRESS ((uint32_t)0x40026400)
rajathr 0:716b93ab9a58 8 #define DMA2_LISR_REGISTER (DMA2_BASE_ADDRESS + 0x00)
rajathr 0:716b93ab9a58 9 #define DMA2_HISR_REGISTER (DMA2_BASE_ADDRESS + 0x04)
rajathr 0:716b93ab9a58 10 #define DMA2_LIFCR_REGISTER (DMA2_BASE_ADDRESS + 0x08)
rajathr 0:716b93ab9a58 11 #define DMA2_HIFCR_REGISTER (DMA2_BASE_ADDRESS + 0x0C)
rajathr 0:716b93ab9a58 12 #define DMA2_S0CR_REGISTER (DMA2_BASE_ADDRESS + 0x10)
rajathr 0:716b93ab9a58 13 #define DMA2_S0NDTR_REGISTER (DMA2_BASE_ADDRESS + 0x14)
rajathr 0:716b93ab9a58 14 #define DMA2_S0PAR_REGISTER (DMA2_BASE_ADDRESS + 0x18)
rajathr 0:716b93ab9a58 15 #define DMA2_S0M0AR_REGISTER (DMA2_BASE_ADDRESS + 0x1C)
rajathr 0:716b93ab9a58 16 #define DMA2_S0M1AR_REGISTER (DMA2_BASE_ADDRESS + 0x20)
rajathr 0:716b93ab9a58 17 #define DMA2_S0FCR_REGISTER (DMA2_BASE_ADDRESS + 0x24)
rajathr 0:716b93ab9a58 18
rajathr 0:716b93ab9a58 19 //Defining bits and flags
rajathr 0:716b93ab9a58 20 //DMA_SxCR: DMA STREAM X CONFIGURATION REGISTER
rajathr 0:716b93ab9a58 21 #define DMA_SxCR_CHANNEL_2_SELECT (((uint32_t)2)<<25) //To Select Channel 2
rajathr 0:716b93ab9a58 22 #define DMA_SxCR_MSIZE_HALF_WORD (((uint32_t)1)<<13) //The location memory is 16 bits in length
rajathr 0:716b93ab9a58 23 #define DMA_SxCR_PSIZE_HALF_WORD (((uint32_t)1)<<11) //The peripheral data size is 16 bits in length
rajathr 0:716b93ab9a58 24 #define DMA_SxCR_MINC_INCREMENT (((uint32_t)1)<<10) //Increment the place where you store the data each transfer
rajathr 0:716b93ab9a58 25 #define DMA_SxCR_CIRC_ENABLE (((uint32_t)1)<<8) //Enable circular mode
rajathr 0:716b93ab9a58 26 #define DMA_SxCR_DIR_PERTOMEM 0
rajathr 0:716b93ab9a58 27 #define DMA_SxCR_STREAM_ENABLE 1
rajathr 0:716b93ab9a58 28
rajathr 0:716b93ab9a58 29 uint16_t adcDmaDataStorageBuffer[3]; //Variable Definition to store read values
rajathr 0:716b93ab9a58 30 uint16_t adcDmaDataStorageBuffer[1]; //Variable Definition to store read value
rajathr 0:716b93ab9a58 31
rajathr 0:716b93ab9a58 32
rajathr 0:716b93ab9a58 33 //FUNCTION GIVEN BY PROFESSOR TO SETUP DMA TO READ VALUES FROM 3 PINS
rajathr 0:716b93ab9a58 34 void initDMAForAdc3_1Channel(void)
rajathr 0:716b93ab9a58 35 {
rajathr 0:716b93ab9a58 36 uint32_t reg;
rajathr 0:716b93ab9a58 37 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); /* Enable the clock */
rajathr 0:716b93ab9a58 38
rajathr 0:716b93ab9a58 39 // Configure Stream 0 to use Channel 2 - ADC3
rajathr 0:716b93ab9a58 40 reg = (uint32_t *)DMA2_S0CR_REGISTER;
rajathr 0:716b93ab9a58 41 *reg = DMA_SxCR_CHANNEL_2_SELECT + DMA_SxCR_MSIZE_HALF_WORD + DMA_SxCR_PSIZE_HALF_WORD + DMA_SxCR_DIR_PERTOMEM +DMA_SxCR_CIRC_ENABLE;
rajathr 0:716b93ab9a58 42
rajathr 0:716b93ab9a58 43 //We will transfer 1 data registers for 1 channels of ADC
rajathr 0:716b93ab9a58 44 reg = (uint32_t *)DMA2_S0NDTR_REGISTER;
rajathr 0:716b93ab9a58 45 *reg = 1;
rajathr 0:716b93ab9a58 46
rajathr 0:716b93ab9a58 47 //We will transfer from the ADC3 Data Register
rajathr 0:716b93ab9a58 48 reg = (uint32_t *)DMA2_S0PAR_REGISTER;
rajathr 0:716b93ab9a58 49 *reg = ADC_3_DR_REGISTER; //THIS FUNCTION IS DEFINED IN HARDWARE ADC
rajathr 0:716b93ab9a58 50
rajathr 0:716b93ab9a58 51 //We will transfer to the adcDmaDataStorageBuffer we created
rajathr 0:716b93ab9a58 52 reg = (uint32_t *)DMA2_S0M0AR_REGISTER;
rajathr 0:716b93ab9a58 53 *reg = (uint32_t)&adcDmaDataStorageBuffer[0]; //QUESTION - WHY IS THIS ZERO??? DIDNT UNDERSTAND THIS STATEMENT
rajathr 0:716b93ab9a58 54
rajathr 0:716b93ab9a58 55 }
rajathr 0:716b93ab9a58 56
rajathr 0:716b93ab9a58 57
rajathr 0:716b93ab9a58 58
rajathr 0:716b93ab9a58 59 //FUNCTION GIVEN BY PROFESSOR TO SETUP DMA TO READ VALUES FROM 3 PINS
rajathr 0:716b93ab9a58 60 void initDMAForAdc3_3Channels(void)
rajathr 0:716b93ab9a58 61 {
rajathr 0:716b93ab9a58 62 uint32_t reg;
rajathr 0:716b93ab9a58 63 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); /* Enable the clock */
rajathr 0:716b93ab9a58 64
rajathr 0:716b93ab9a58 65 // Configure Stream 0 to use Channel 2 (ADC3)
rajathr 0:716b93ab9a58 66 reg = (uint32_t *)DMA2_S0CR_REGISTER;
rajathr 0:716b93ab9a58 67 *reg = DMA_SxCR_CHANNEL_2_SELECT + DMA_SxCR_MSIZE_HALF_WORD + DMA_SxCR_PSIZE_HALF_WORD + DMA_SxCR_MINC_INCREMENT + DMA_SxCR_DIR_PERTOMEM +DMA_SxCR_CIRC_ENABLE;
rajathr 0:716b93ab9a58 68
rajathr 0:716b93ab9a58 69 //We will transfer 3 data registers for 3 channels of ADC
rajathr 0:716b93ab9a58 70 reg = (uint32_t *)DMA2_S0NDTR_REGISTER;
rajathr 0:716b93ab9a58 71 *reg = 3;
rajathr 0:716b93ab9a58 72
rajathr 0:716b93ab9a58 73 //We will transfer from the ADC3 Data Register
rajathr 0:716b93ab9a58 74 reg = (uint32_t *)DMA2_S0PAR_REGISTER;
rajathr 0:716b93ab9a58 75 *reg = ADC_3_DR_REGISTER; //THIS FUNCTION IS NOT DETECTED
rajathr 0:716b93ab9a58 76
rajathr 0:716b93ab9a58 77 //We will transfer to the adcDmaDataStorageBuffer we just created
rajathr 0:716b93ab9a58 78 reg = (uint32_t *)DMA2_S0M0AR_REGISTER;
rajathr 0:716b93ab9a58 79 *reg = (uint32_t)& adcDmaDataStorageBuffer[0];
rajathr 0:716b93ab9a58 80
rajathr 0:716b93ab9a58 81 }
rajathr 0:716b93ab9a58 82
rajathr 0:716b93ab9a58 83
rajathr 0:716b93ab9a58 84 void enableDMAForAdc3_3channels (void)
rajathr 0:716b93ab9a58 85 {
rajathr 0:716b93ab9a58 86 uint32_t * reg;
rajathr 0:716b93ab9a58 87 reg = (uint32_t *)DMA2_S0CR_REGISTER;
rajathr 0:716b93ab9a58 88 *reg = *reg | DMA_SxCR_STREAM_ENABLE;
rajathr 0:716b93ab9a58 89 }
rajathr 0:716b93ab9a58 90
rajathr 0:716b93ab9a58 91 void enableDMAForAdc3_1channels (void)
rajathr 0:716b93ab9a58 92 {
rajathr 0:716b93ab9a58 93 uint32_t * reg;
rajathr 0:716b93ab9a58 94 reg = (uint32_t *)DMA2_S0CR_REGISTER;
rajathr 0:716b93ab9a58 95 *reg = *reg | DMA_SxCR_STREAM_ENABLE;
rajathr 0:716b93ab9a58 96 }
rajathr 0:716b93ab9a58 97
rajathr 0:716b93ab9a58 98
rajathr 0:716b93ab9a58 99
rajathr 0:716b93ab9a58 100 uint16_t returnADC3StoredValue(uint8_t index)
rajathr 0:716b93ab9a58 101 {
rajathr 0:716b93ab9a58 102 return adcDmaDataStorageBuffer[index];
rajathr 0:716b93ab9a58 103 }
rajathr 0:716b93ab9a58 104
rajathr 0:716b93ab9a58 105
rajathr 0:716b93ab9a58 106
rajathr 0:716b93ab9a58 107
rajathr 0:716b93ab9a58 108