Antonio Quevedo / TSIHW

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Revision 1:532aa572220b, committed 2014-09-26

Comitter:
quevedo
Date:
Fri Sep 26 17:25:06 2014 +0000
Parent:
0:b39f4f954a9b
Commit message:
Corrected to activate clock gating on PORTs A, B, and C so all electrodes can work

Changed in this revision

TSIHW.cpp Show annotated file Show diff for this revision Revisions of this file 
--- a/TSIHW.cpp	Wed Sep 24 18:48:10 2014 +0000
+++ b/TSIHW.cpp	Fri Sep 26 17:25:06 2014 +0000
@@ -7,7 +7,7 @@
 */
 TSI::TSI(char rchg, char echg, char dvolt, char ps, char nscn) {
     // The first version is preconfigured for non-noise detection, no interrupts, not running on stop modes, software trigger
-    SIM->SCGC5 |= 0x00000020; // clock gate for TSI
+    SIM->SCGC5 |= 0x00000E20; // clock gate for TSI and PORTS A, B, and C
     TSI0->GENCS = 0xC0000080 | ((rchg & 0x07) << 21) | ((echg & 0x07) << 16) | ((dvolt & 0x03) << 19) | ((ps & 0x07) << 13) | ((nscn & 0x1F) << 8);
 }