Zheng Ping / LoRaMacLib

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board/NVIC_set_all_priorities.h@0:9be122c18509, 2015-08-12 (annotated)

Committer:
GregCr
Date:
Wed Aug 12 14:08:29 2015 +0000
Revision:
0:9be122c18509
First Implementation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:9be122c18509 1 #ifndef SET_ALL_PRIO
GregCr 0:9be122c18509 2 #define SET_ALL_PRIO
GregCr 0:9be122c18509 3
GregCr 0:9be122c18509 4 #include "mbed.h"
GregCr 0:9be122c18509 5
GregCr 0:9be122c18509 6 /*
GregCr 0:9be122c18509 7 NOTE
GregCr 0:9be122c18509 8 ----
GregCr 0:9be122c18509 9 SysTick_IRQn is vector -1.
GregCr 0:9be122c18509 10 The vector mentioned in the comment after SysTick_IRQn is vector 0
GregCr 0:9be122c18509 11 */
GregCr 0:9be122c18509 12
GregCr 0:9be122c18509 13 enum FIRST_LAST_IRQ {
GregCr 0:9be122c18509 14 // ************************** Freescale **************************
GregCr 0:9be122c18509 15 // --------- TARGET_K20XX
GregCr 0:9be122c18509 16 #ifdef TARGET_K20D50M
GregCr 0:9be122c18509 17 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 18 last_IRQ_number = SWI_IRQn,
GregCr 0:9be122c18509 19 #elif defined TARGET_TEENSY3_1
GregCr 0:9be122c18509 20 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 21 last_IRQ_number = SWI_IRQn,
GregCr 0:9be122c18509 22
GregCr 0:9be122c18509 23 // --------- TARGET_K22F
GregCr 0:9be122c18509 24 #elif defined TARGET_K22F
GregCr 0:9be122c18509 25 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 26 last_IRQ_number = Reserved101_IRQn,
GregCr 0:9be122c18509 27
GregCr 0:9be122c18509 28 // --------- TARGET_KLXX
GregCr 0:9be122c18509 29 #elif defined TARGET_KL05Z
GregCr 0:9be122c18509 30 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 31 last_IRQ_number = PORTB_IRQn,
GregCr 0:9be122c18509 32 #elif defined TARGET_KL25Z
GregCr 0:9be122c18509 33 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 34 last_IRQ_number = PORTD_IRQn,
GregCr 0:9be122c18509 35 #elif defined TARGET_KL43Z
GregCr 0:9be122c18509 36 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 37 last_IRQ_number = PORTCD_IRQn,
GregCr 0:9be122c18509 38 #elif defined TARGET_KL46Z
GregCr 0:9be122c18509 39 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 40 last_IRQ_number = PORTC_PORTD_IRQn,
GregCr 0:9be122c18509 41
GregCr 0:9be122c18509 42 // --------- TARGET_MCU_K64F
GregCr 0:9be122c18509 43 #elif defined TARGET_MCU_K64F
GregCr 0:9be122c18509 44 first_IRQ_number = SysTick_IRQn, // DMA0_IRQn
GregCr 0:9be122c18509 45 last_IRQ_number = ENET_Error_IRQn,
GregCr 0:9be122c18509 46
GregCr 0:9be122c18509 47 // ************************** Nordic **************************
GregCr 0:9be122c18509 48 // --------- TARGET_MCU_NRF51822
GregCr 0:9be122c18509 49 #elif defined TARGET_MCU_NRF51822
GregCr 0:9be122c18509 50 first_IRQ_number = SysTick_IRQn, // POWER_CLOCK_IRQn
GregCr 0:9be122c18509 51 last_IRQ_number = SWI5_IRQn,
GregCr 0:9be122c18509 52
GregCr 0:9be122c18509 53 // ************************** NXP **************************
GregCr 0:9be122c18509 54 #elif defined TARGET_LPC11U6X
GregCr 0:9be122c18509 55 first_IRQ_number = SysTick_IRQn, // PIN_INT0_IRQn
GregCr 0:9be122c18509 56 last_IRQ_number = USBWAKEUP_IRQn,
GregCr 0:9be122c18509 57 #elif defined TARGET_LPC11UXX
GregCr 0:9be122c18509 58 first_IRQ_number = SysTick_IRQn, // FLEX_INT0_IRQn
GregCr 0:9be122c18509 59 last_IRQ_number = Reserved6_IRQn,
GregCr 0:9be122c18509 60 #elif defined TARGET_LPC11XX_11CXX
GregCr 0:9be122c18509 61 first_IRQ_number = SysTick_IRQn, // WAKEUP0_IRQn
GregCr 0:9be122c18509 62 last_IRQ_number = EINT0_IRQn,
GregCr 0:9be122c18509 63 #elif defined TARGET_LPC13XX
GregCr 0:9be122c18509 64 first_IRQ_number = SysTick_IRQn, // PIN_INT0_IRQn
GregCr 0:9be122c18509 65 last_IRQ_number = Reserved5_IRQn,
GregCr 0:9be122c18509 66 #elif defined TARGET_LPC15XX
GregCr 0:9be122c18509 67 first_IRQ_number = SysTick_IRQn, // WDT_IRQn
GregCr 0:9be122c18509 68 last_IRQ_number = RTC_WAKE_IRQn,
GregCr 0:9be122c18509 69 #elif defined TARGET_LPC176X
GregCr 0:9be122c18509 70 first_IRQ_number = SysTick_IRQn, // WDT_IRQn
GregCr 0:9be122c18509 71 last_IRQ_number = CANActivity_IRQn,
GregCr 0:9be122c18509 72 #elif defined TARGET_LPC23XX
GregCr 0:9be122c18509 73 first_IRQ_number = TIMER0_IRQn,
GregCr 0:9be122c18509 74 last_IRQ_number = I2S_IRQn,
GregCr 0:9be122c18509 75 #elif defined TARGET_LPC408X
GregCr 0:9be122c18509 76 first_IRQ_number = SysTick_IRQn, // WDT_IRQn
GregCr 0:9be122c18509 77 last_IRQ_number = CMP1_IRQn,
GregCr 0:9be122c18509 78 #elif defined TARGET_LPC43XX
GregCr 0:9be122c18509 79 first_IRQ_number = SysTick_IRQn, // DAC_IRQn
GregCr 0:9be122c18509 80 last_IRQ_number = QEI_IRQn,
GregCr 0:9be122c18509 81 #elif defined TARGET_LPC81X
GregCr 0:9be122c18509 82 first_IRQ_number = SysTick_IRQn, // SPI0_IRQn
GregCr 0:9be122c18509 83 last_IRQ_number = PININT7_IRQn,
GregCr 0:9be122c18509 84 #elif defined TARGET_LPC82X
GregCr 0:9be122c18509 85 first_IRQ_number = SysTick_IRQn, // SPI0_IRQn
GregCr 0:9be122c18509 86 last_IRQ_number = PININT7_IRQn,
GregCr 0:9be122c18509 87
GregCr 0:9be122c18509 88 // ************************** Renesas **************************
GregCr 0:9be122c18509 89 // --------- TARGET_RZ_A1H
GregCr 0:9be122c18509 90 #elif defined TARGET_RZ_A1H
GregCr 0:9be122c18509 91 first_IRQ_number = SGI0_IRQn,
GregCr 0:9be122c18509 92 last_IRQ_number = TINT170_IRQn,
GregCr 0:9be122c18509 93
GregCr 0:9be122c18509 94 // ************************** STM **************************
GregCr 0:9be122c18509 95 // --------- TARGET_DISCO_F100RB
GregCr 0:9be122c18509 96 #elif defined TARGET_DISCO_F100RB
GregCr 0:9be122c18509 97 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 98 last_IRQ_number = DMA1_Channel7_IRQn,
GregCr 0:9be122c18509 99 #ifdef STM32F10X_LD
GregCr 0:9be122c18509 100 last_IRQ_number = USBWakeUp_IRQn,
GregCr 0:9be122c18509 101 #endif /* STM32F10X_LD */
GregCr 0:9be122c18509 102 #ifdef STM32F10X_LD_VL
GregCr 0:9be122c18509 103 last_IRQ_number = TIM7_IRQn,
GregCr 0:9be122c18509 104 #endif /* STM32F10X_LD_VL */
GregCr 0:9be122c18509 105 #ifdef STM32F10X_MD
GregCr 0:9be122c18509 106 last_IRQ_number = USBWakeUp_IRQn,
GregCr 0:9be122c18509 107 #endif /* STM32F10X_MD */
GregCr 0:9be122c18509 108 #ifdef STM32F10X_MD_VL
GregCr 0:9be122c18509 109 last_IRQ_number = TIM7_IRQn,
GregCr 0:9be122c18509 110 #endif /* STM32F10X_MD_VL */
GregCr 0:9be122c18509 111 #ifdef STM32F10X_HD
GregCr 0:9be122c18509 112 last_IRQ_number = DMA2_Channel4_5_IRQn,
GregCr 0:9be122c18509 113 #endif /* STM32F10X_HD */
GregCr 0:9be122c18509 114 #ifdef STM32F10X_HD_VL
GregCr 0:9be122c18509 115 last_IRQ_number = DMA2_Channel5_IRQn,
GregCr 0:9be122c18509 116 #endif /* STM32F10X_HD_VL */
GregCr 0:9be122c18509 117 #ifdef STM32F10X_XL
GregCr 0:9be122c18509 118 last_IRQ_number = DMA2_Channel4_5_IRQn,
GregCr 0:9be122c18509 119 #endif /* STM32F10X_XL */
GregCr 0:9be122c18509 120 #ifdef STM32F10X_CL
GregCr 0:9be122c18509 121 last_IRQ_number = OTG_FS_IRQn,
GregCr 0:9be122c18509 122 #endif /* STM32F10X_CL */
GregCr 0:9be122c18509 123
GregCr 0:9be122c18509 124 // --------- TARGET_NUCLEO_F103RB
GregCr 0:9be122c18509 125 #elif defined TARGET_NUCLEO_F103RB
GregCr 0:9be122c18509 126 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 127 last_IRQ_number = DMA1_Channel7_IRQn,
GregCr 0:9be122c18509 128 #ifdef STM32F10X_LD
GregCr 0:9be122c18509 129 last_IRQ_number = USBWakeUp_IRQn,
GregCr 0:9be122c18509 130 #endif /* STM32F10X_LD */
GregCr 0:9be122c18509 131 #ifdef STM32F10X_LD_VL
GregCr 0:9be122c18509 132 last_IRQ_number = TIM7_IRQn,
GregCr 0:9be122c18509 133 #endif /* STM32F10X_LD_VL */
GregCr 0:9be122c18509 134 #ifdef STM32F10X_MD
GregCr 0:9be122c18509 135 last_IRQ_number = USBWakeUp_IRQn,
GregCr 0:9be122c18509 136 #endif /* STM32F10X_MD */
GregCr 0:9be122c18509 137 #ifdef STM32F10X_MD_VL
GregCr 0:9be122c18509 138 last_IRQ_number = TIM7_IRQn,
GregCr 0:9be122c18509 139 #endif /* STM32F10X_MD_VL */
GregCr 0:9be122c18509 140 #ifdef STM32F10X_HD
GregCr 0:9be122c18509 141 last_IRQ_number = DMA2_Channel4_5_IRQn,
GregCr 0:9be122c18509 142 #endif /* STM32F10X_HD */
GregCr 0:9be122c18509 143 #ifdef STM32F10X_HD_VL
GregCr 0:9be122c18509 144 last_IRQ_number = DMA2_Channel5_IRQn,
GregCr 0:9be122c18509 145 #endif /* STM32F10X_HD_VL */
GregCr 0:9be122c18509 146 #ifdef STM32F10X_XL
GregCr 0:9be122c18509 147 last_IRQ_number = DMA2_Channel4_5_IRQn,
GregCr 0:9be122c18509 148 #endif /* STM32F10X_XL */
GregCr 0:9be122c18509 149 #ifdef STM32F10X_CL
GregCr 0:9be122c18509 150 last_IRQ_number = OTG_FS_IRQn,
GregCr 0:9be122c18509 151 #endif /* STM32F10X_CL */
GregCr 0:9be122c18509 152
GregCr 0:9be122c18509 153 // --------- TARGET_STM32F0
GregCr 0:9be122c18509 154 #elif defined TARGET_DISCO_F051R8
GregCr 0:9be122c18509 155 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 156 last_IRQ_number = CEC_CAN_IRQn,
GregCr 0:9be122c18509 157 #elif defined TARGET_NUCLEO_F030R8
GregCr 0:9be122c18509 158 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 159 last_IRQ_number = USART2_IRQn,
GregCr 0:9be122c18509 160 #elif defined TARGET_NUCLEO_F070RB
GregCr 0:9be122c18509 161 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 162 last_IRQ_number = USB_IRQn,
GregCr 0:9be122c18509 163 #elif defined TARGET_NUCLEO_F072RB
GregCr 0:9be122c18509 164 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 165 last_IRQ_number = USB_IRQn,
GregCr 0:9be122c18509 166 #elif defined TARGET_NUCLEO_F091RC
GregCr 0:9be122c18509 167 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 168 last_IRQ_number = CEC_CAN_IRQn,
GregCr 0:9be122c18509 169
GregCr 0:9be122c18509 170 // --------- TARGET_STM32F3
GregCr 0:9be122c18509 171 #elif defined TARGET_DISCO_F303VC
GregCr 0:9be122c18509 172 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 173 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 174 #elif defined TARGET_DISCO_F334C8
GregCr 0:9be122c18509 175 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 176 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 177 #elif defined TARGET_NUCLEO_F302R8
GregCr 0:9be122c18509 178 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 179 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 180 #elif defined TARGET_NUCLEO_F303RE
GregCr 0:9be122c18509 181 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 182 last_IRQ_number = SPI4_IRQn,
GregCr 0:9be122c18509 183 #elif defined TARGET_NUCLEO_F334R8
GregCr 0:9be122c18509 184 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 185 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 186
GregCr 0:9be122c18509 187 // --------- TARGET_STM32F3XX
GregCr 0:9be122c18509 188 #elif defined TARGET_STM32F3XX
GregCr 0:9be122c18509 189 first_IRQ_number = WWDG_IRQn,
GregCr 0:9be122c18509 190 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 191 #ifdef STM32F303xC
GregCr 0:9be122c18509 192 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 193 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 194 #endif /* STM32F303xC */
GregCr 0:9be122c18509 195 #ifdef STM32F334x8
GregCr 0:9be122c18509 196 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 197 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 198 #endif /* STM32F334x8 */
GregCr 0:9be122c18509 199 #ifdef STM32F302x8
GregCr 0:9be122c18509 200 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 201 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 202 #endif /* STM32F302x8 */
GregCr 0:9be122c18509 203
GregCr 0:9be122c18509 204 // --------- TARGET_STM32F4
GregCr 0:9be122c18509 205 #elif defined TARGET_DISCO_F401VC
GregCr 0:9be122c18509 206 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 207 last_IRQ_number = SPI4_IRQn,
GregCr 0:9be122c18509 208 #elif defined TARGET_DISCO_F429ZI
GregCr 0:9be122c18509 209 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 210 last_IRQ_number = DMA2D_IRQn,
GregCr 0:9be122c18509 211 #elif defined TARGET_MTS_DRAGONFLY_F411RE
GregCr 0:9be122c18509 212 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 213 last_IRQ_number = SPI5_IRQn,
GregCr 0:9be122c18509 214 #elif defined TARGET_MTS_MDOT_F405RG
GregCr 0:9be122c18509 215 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 216 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 217 #elif defined TARGET_MTS_MDOT_F411RE
GregCr 0:9be122c18509 218 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 219 last_IRQ_number = SPI5_IRQn,
GregCr 0:9be122c18509 220 #elif defined TARGET_NUCLEO_F401RE
GregCr 0:9be122c18509 221 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 222 last_IRQ_number = SPI4_IRQn,
GregCr 0:9be122c18509 223 #elif defined TARGET_NUCLEO_F411RE
GregCr 0:9be122c18509 224 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 225 last_IRQ_number = SPI5_IRQn,
GregCr 0:9be122c18509 226 #elif defined TARGET_STM32F407VG
GregCr 0:9be122c18509 227 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 228 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 229
GregCr 0:9be122c18509 230 // --------- TARGET_STM32F4XX
GregCr 0:9be122c18509 231 #elif defined TARGET_STM32F4XX
GregCr 0:9be122c18509 232 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 233 last_IRQ_number = HASH_RNG_IRQn,
GregCr 0:9be122c18509 234 #ifdef STM32F40XX
GregCr 0:9be122c18509 235 last_IRQ_number = FPU_IRQn,
GregCr 0:9be122c18509 236 #endif /* STM32F40XX */
GregCr 0:9be122c18509 237 #ifdef STM32F427X
GregCr 0:9be122c18509 238 last_IRQ_number = SPI6_IRQn,
GregCr 0:9be122c18509 239 #endif /* STM32F427X */
GregCr 0:9be122c18509 240
GregCr 0:9be122c18509 241 // --------- TARGET_STM32L0
GregCr 0:9be122c18509 242 #elif defined TARGET_DISCO_L053C8
GregCr 0:9be122c18509 243 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 244 last_IRQ_number = USB_IRQn,
GregCr 0:9be122c18509 245 #elif defined TARGET_NUCLEO_L053R8
GregCr 0:9be122c18509 246 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 247 last_IRQ_number = USB_IRQn,
GregCr 0:9be122c18509 248
GregCr 0:9be122c18509 249 // --------- TARGET_STM32L1
GregCr 0:9be122c18509 250 #elif defined TARGET_NUCLEO_L152RE
GregCr 0:9be122c18509 251 first_IRQ_number = SysTick_IRQn, // WWDG_IRQn
GregCr 0:9be122c18509 252 last_IRQ_number = COMP_ACQ_IRQn,
GregCr 0:9be122c18509 253 #endif
GregCr 0:9be122c18509 254 };
GregCr 0:9be122c18509 255
GregCr 0:9be122c18509 256 void NVIC_set_all_irq_priorities(int priority);
GregCr 0:9be122c18509 257
GregCr 0:9be122c18509 258 #endif // SET_ALL_PRIO