pyonta cansat / Mbed 2 deprecated FM_integration_off

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Dependencies:   HMC5883 MPL3115A MPU605 MU2Class SDFileSystem mbed

PowerControl/EthernetPowerControl.cpp@0:ac7a5495d95c, 2017-09-09 (annotated)

Committer:
pyonta2017
Date:
Sat Sep 09 23:18:12 2017 +0000
Revision:
0:ac7a5495d95c
a

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pyonta2017 0:ac7a5495d95c 1 #include "EthernetPowerControl.h"
pyonta2017 0:ac7a5495d95c 2
pyonta2017 0:ac7a5495d95c 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
pyonta2017 0:ac7a5495d95c 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
pyonta2017 0:ac7a5495d95c 5 unsigned int tout;
pyonta2017 0:ac7a5495d95c 6 /* Hardware MII Management for LPC176x devices. */
pyonta2017 0:ac7a5495d95c 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
pyonta2017 0:ac7a5495d95c 8 LPC_EMAC->MWTD = Value;
pyonta2017 0:ac7a5495d95c 9
pyonta2017 0:ac7a5495d95c 10 /* Wait utill operation completed */
pyonta2017 0:ac7a5495d95c 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
pyonta2017 0:ac7a5495d95c 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
pyonta2017 0:ac7a5495d95c 13 break;
pyonta2017 0:ac7a5495d95c 14 }
pyonta2017 0:ac7a5495d95c 15 }
pyonta2017 0:ac7a5495d95c 16 }
pyonta2017 0:ac7a5495d95c 17
pyonta2017 0:ac7a5495d95c 18 static unsigned short read_PHY (unsigned int PhyReg) {
pyonta2017 0:ac7a5495d95c 19 /* Read a PHY register 'PhyReg'. */
pyonta2017 0:ac7a5495d95c 20 unsigned int tout, val;
pyonta2017 0:ac7a5495d95c 21
pyonta2017 0:ac7a5495d95c 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
pyonta2017 0:ac7a5495d95c 23 LPC_EMAC->MCMD = MCMD_READ;
pyonta2017 0:ac7a5495d95c 24
pyonta2017 0:ac7a5495d95c 25 /* Wait until operation completed */
pyonta2017 0:ac7a5495d95c 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
pyonta2017 0:ac7a5495d95c 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
pyonta2017 0:ac7a5495d95c 28 break;
pyonta2017 0:ac7a5495d95c 29 }
pyonta2017 0:ac7a5495d95c 30 }
pyonta2017 0:ac7a5495d95c 31 LPC_EMAC->MCMD = 0;
pyonta2017 0:ac7a5495d95c 32 val = LPC_EMAC->MRDD;
pyonta2017 0:ac7a5495d95c 33
pyonta2017 0:ac7a5495d95c 34 return (val);
pyonta2017 0:ac7a5495d95c 35 }
pyonta2017 0:ac7a5495d95c 36
pyonta2017 0:ac7a5495d95c 37 void EMAC_Init()
pyonta2017 0:ac7a5495d95c 38 {
pyonta2017 0:ac7a5495d95c 39 unsigned int tout,regv;
pyonta2017 0:ac7a5495d95c 40 /* Power Up the EMAC controller. */
pyonta2017 0:ac7a5495d95c 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
pyonta2017 0:ac7a5495d95c 42
pyonta2017 0:ac7a5495d95c 43 LPC_PINCON->PINSEL2 = 0x50150105;
pyonta2017 0:ac7a5495d95c 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
pyonta2017 0:ac7a5495d95c 45 LPC_PINCON->PINSEL3 |= 0x00000005;
pyonta2017 0:ac7a5495d95c 46
pyonta2017 0:ac7a5495d95c 47 /* Reset all EMAC internal modules. */
pyonta2017 0:ac7a5495d95c 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
pyonta2017 0:ac7a5495d95c 49 MAC1_SIM_RES | MAC1_SOFT_RES;
pyonta2017 0:ac7a5495d95c 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
pyonta2017 0:ac7a5495d95c 51
pyonta2017 0:ac7a5495d95c 52 /* A short delay after reset. */
pyonta2017 0:ac7a5495d95c 53 for (tout = 100; tout; tout--);
pyonta2017 0:ac7a5495d95c 54
pyonta2017 0:ac7a5495d95c 55 /* Initialize MAC control registers. */
pyonta2017 0:ac7a5495d95c 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
pyonta2017 0:ac7a5495d95c 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
pyonta2017 0:ac7a5495d95c 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
pyonta2017 0:ac7a5495d95c 59 LPC_EMAC->CLRT = CLRT_DEF;
pyonta2017 0:ac7a5495d95c 60 LPC_EMAC->IPGR = IPGR_DEF;
pyonta2017 0:ac7a5495d95c 61
pyonta2017 0:ac7a5495d95c 62 /* Enable Reduced MII interface. */
pyonta2017 0:ac7a5495d95c 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
pyonta2017 0:ac7a5495d95c 64
pyonta2017 0:ac7a5495d95c 65 /* Reset Reduced MII Logic. */
pyonta2017 0:ac7a5495d95c 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
pyonta2017 0:ac7a5495d95c 67 for (tout = 100; tout; tout--);
pyonta2017 0:ac7a5495d95c 68 LPC_EMAC->SUPP = 0;
pyonta2017 0:ac7a5495d95c 69
pyonta2017 0:ac7a5495d95c 70 /* Put the DP83848C in reset mode */
pyonta2017 0:ac7a5495d95c 71 write_PHY (PHY_REG_BMCR, 0x8000);
pyonta2017 0:ac7a5495d95c 72
pyonta2017 0:ac7a5495d95c 73 /* Wait for hardware reset to end. */
pyonta2017 0:ac7a5495d95c 74 for (tout = 0; tout < 0x100000; tout++) {
pyonta2017 0:ac7a5495d95c 75 regv = read_PHY (PHY_REG_BMCR);
pyonta2017 0:ac7a5495d95c 76 if (!(regv & 0x8000)) {
pyonta2017 0:ac7a5495d95c 77 /* Reset complete */
pyonta2017 0:ac7a5495d95c 78 break;
pyonta2017 0:ac7a5495d95c 79 }
pyonta2017 0:ac7a5495d95c 80 }
pyonta2017 0:ac7a5495d95c 81 }
pyonta2017 0:ac7a5495d95c 82
pyonta2017 0:ac7a5495d95c 83
pyonta2017 0:ac7a5495d95c 84 void PHY_PowerDown()
pyonta2017 0:ac7a5495d95c 85 {
pyonta2017 0:ac7a5495d95c 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:ac7a5495d95c 87 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:ac7a5495d95c 88
pyonta2017 0:ac7a5495d95c 89 unsigned int regv;
pyonta2017 0:ac7a5495d95c 90 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:ac7a5495d95c 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
pyonta2017 0:ac7a5495d95c 92 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:ac7a5495d95c 93
pyonta2017 0:ac7a5495d95c 94 //shouldn't need the EMAC now.
pyonta2017 0:ac7a5495d95c 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
pyonta2017 0:ac7a5495d95c 96
pyonta2017 0:ac7a5495d95c 97 //and turn off the PHY OSC
pyonta2017 0:ac7a5495d95c 98 LPC_GPIO1->FIODIR |= 0x8000000;
pyonta2017 0:ac7a5495d95c 99 LPC_GPIO1->FIOCLR = 0x8000000;
pyonta2017 0:ac7a5495d95c 100 }
pyonta2017 0:ac7a5495d95c 101
pyonta2017 0:ac7a5495d95c 102 void PHY_PowerUp()
pyonta2017 0:ac7a5495d95c 103 {
pyonta2017 0:ac7a5495d95c 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:ac7a5495d95c 105 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:ac7a5495d95c 106
pyonta2017 0:ac7a5495d95c 107 LPC_GPIO1->FIODIR |= 0x8000000;
pyonta2017 0:ac7a5495d95c 108 LPC_GPIO1->FIOSET = 0x8000000;
pyonta2017 0:ac7a5495d95c 109
pyonta2017 0:ac7a5495d95c 110 //wait for osc to be stable
pyonta2017 0:ac7a5495d95c 111 wait_ms(200);
pyonta2017 0:ac7a5495d95c 112
pyonta2017 0:ac7a5495d95c 113 unsigned int regv;
pyonta2017 0:ac7a5495d95c 114 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:ac7a5495d95c 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
pyonta2017 0:ac7a5495d95c 116 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:ac7a5495d95c 117 }
pyonta2017 0:ac7a5495d95c 118
pyonta2017 0:ac7a5495d95c 119 void PHY_EnergyDetect_Enable()
pyonta2017 0:ac7a5495d95c 120 {
pyonta2017 0:ac7a5495d95c 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:ac7a5495d95c 122 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:ac7a5495d95c 123
pyonta2017 0:ac7a5495d95c 124 unsigned int regv;
pyonta2017 0:ac7a5495d95c 125 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:ac7a5495d95c 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
pyonta2017 0:ac7a5495d95c 127 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:ac7a5495d95c 128 }
pyonta2017 0:ac7a5495d95c 129
pyonta2017 0:ac7a5495d95c 130 void PHY_EnergyDetect_Disable()
pyonta2017 0:ac7a5495d95c 131 {
pyonta2017 0:ac7a5495d95c 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:ac7a5495d95c 133 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:ac7a5495d95c 134 unsigned int regv;
pyonta2017 0:ac7a5495d95c 135 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:ac7a5495d95c 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
pyonta2017 0:ac7a5495d95c 137 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:ac7a5495d95c 138 }