pyonta cansat / Mbed 2 deprecated FM_integration_copy

test

Dependencies:   HMC5883L MPL3115 MPU6050 MU2Class SDFileSystem mbed

PowerControl/EthernetPowerControl.cpp@0:1f956fab4d28, 2017-09-06 (annotated)

Committer:
pyonta2017
Date:
Wed Sep 06 15:13:08 2017 +0000
Revision:
0:1f956fab4d28
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
pyonta2017 0:1f956fab4d28 1 #include "EthernetPowerControl.h"
pyonta2017 0:1f956fab4d28 2
pyonta2017 0:1f956fab4d28 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
pyonta2017 0:1f956fab4d28 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
pyonta2017 0:1f956fab4d28 5 unsigned int tout;
pyonta2017 0:1f956fab4d28 6 /* Hardware MII Management for LPC176x devices. */
pyonta2017 0:1f956fab4d28 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
pyonta2017 0:1f956fab4d28 8 LPC_EMAC->MWTD = Value;
pyonta2017 0:1f956fab4d28 9
pyonta2017 0:1f956fab4d28 10 /* Wait utill operation completed */
pyonta2017 0:1f956fab4d28 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
pyonta2017 0:1f956fab4d28 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
pyonta2017 0:1f956fab4d28 13 break;
pyonta2017 0:1f956fab4d28 14 }
pyonta2017 0:1f956fab4d28 15 }
pyonta2017 0:1f956fab4d28 16 }
pyonta2017 0:1f956fab4d28 17
pyonta2017 0:1f956fab4d28 18 static unsigned short read_PHY (unsigned int PhyReg) {
pyonta2017 0:1f956fab4d28 19 /* Read a PHY register 'PhyReg'. */
pyonta2017 0:1f956fab4d28 20 unsigned int tout, val;
pyonta2017 0:1f956fab4d28 21
pyonta2017 0:1f956fab4d28 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
pyonta2017 0:1f956fab4d28 23 LPC_EMAC->MCMD = MCMD_READ;
pyonta2017 0:1f956fab4d28 24
pyonta2017 0:1f956fab4d28 25 /* Wait until operation completed */
pyonta2017 0:1f956fab4d28 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
pyonta2017 0:1f956fab4d28 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
pyonta2017 0:1f956fab4d28 28 break;
pyonta2017 0:1f956fab4d28 29 }
pyonta2017 0:1f956fab4d28 30 }
pyonta2017 0:1f956fab4d28 31 LPC_EMAC->MCMD = 0;
pyonta2017 0:1f956fab4d28 32 val = LPC_EMAC->MRDD;
pyonta2017 0:1f956fab4d28 33
pyonta2017 0:1f956fab4d28 34 return (val);
pyonta2017 0:1f956fab4d28 35 }
pyonta2017 0:1f956fab4d28 36
pyonta2017 0:1f956fab4d28 37 void EMAC_Init()
pyonta2017 0:1f956fab4d28 38 {
pyonta2017 0:1f956fab4d28 39 unsigned int tout,regv;
pyonta2017 0:1f956fab4d28 40 /* Power Up the EMAC controller. */
pyonta2017 0:1f956fab4d28 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
pyonta2017 0:1f956fab4d28 42
pyonta2017 0:1f956fab4d28 43 LPC_PINCON->PINSEL2 = 0x50150105;
pyonta2017 0:1f956fab4d28 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
pyonta2017 0:1f956fab4d28 45 LPC_PINCON->PINSEL3 |= 0x00000005;
pyonta2017 0:1f956fab4d28 46
pyonta2017 0:1f956fab4d28 47 /* Reset all EMAC internal modules. */
pyonta2017 0:1f956fab4d28 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
pyonta2017 0:1f956fab4d28 49 MAC1_SIM_RES | MAC1_SOFT_RES;
pyonta2017 0:1f956fab4d28 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
pyonta2017 0:1f956fab4d28 51
pyonta2017 0:1f956fab4d28 52 /* A short delay after reset. */
pyonta2017 0:1f956fab4d28 53 for (tout = 100; tout; tout--);
pyonta2017 0:1f956fab4d28 54
pyonta2017 0:1f956fab4d28 55 /* Initialize MAC control registers. */
pyonta2017 0:1f956fab4d28 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
pyonta2017 0:1f956fab4d28 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
pyonta2017 0:1f956fab4d28 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
pyonta2017 0:1f956fab4d28 59 LPC_EMAC->CLRT = CLRT_DEF;
pyonta2017 0:1f956fab4d28 60 LPC_EMAC->IPGR = IPGR_DEF;
pyonta2017 0:1f956fab4d28 61
pyonta2017 0:1f956fab4d28 62 /* Enable Reduced MII interface. */
pyonta2017 0:1f956fab4d28 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
pyonta2017 0:1f956fab4d28 64
pyonta2017 0:1f956fab4d28 65 /* Reset Reduced MII Logic. */
pyonta2017 0:1f956fab4d28 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
pyonta2017 0:1f956fab4d28 67 for (tout = 100; tout; tout--);
pyonta2017 0:1f956fab4d28 68 LPC_EMAC->SUPP = 0;
pyonta2017 0:1f956fab4d28 69
pyonta2017 0:1f956fab4d28 70 /* Put the DP83848C in reset mode */
pyonta2017 0:1f956fab4d28 71 write_PHY (PHY_REG_BMCR, 0x8000);
pyonta2017 0:1f956fab4d28 72
pyonta2017 0:1f956fab4d28 73 /* Wait for hardware reset to end. */
pyonta2017 0:1f956fab4d28 74 for (tout = 0; tout < 0x100000; tout++) {
pyonta2017 0:1f956fab4d28 75 regv = read_PHY (PHY_REG_BMCR);
pyonta2017 0:1f956fab4d28 76 if (!(regv & 0x8000)) {
pyonta2017 0:1f956fab4d28 77 /* Reset complete */
pyonta2017 0:1f956fab4d28 78 break;
pyonta2017 0:1f956fab4d28 79 }
pyonta2017 0:1f956fab4d28 80 }
pyonta2017 0:1f956fab4d28 81 }
pyonta2017 0:1f956fab4d28 82
pyonta2017 0:1f956fab4d28 83
pyonta2017 0:1f956fab4d28 84 void PHY_PowerDown()
pyonta2017 0:1f956fab4d28 85 {
pyonta2017 0:1f956fab4d28 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:1f956fab4d28 87 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:1f956fab4d28 88
pyonta2017 0:1f956fab4d28 89 unsigned int regv;
pyonta2017 0:1f956fab4d28 90 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:1f956fab4d28 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
pyonta2017 0:1f956fab4d28 92 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:1f956fab4d28 93
pyonta2017 0:1f956fab4d28 94 //shouldn't need the EMAC now.
pyonta2017 0:1f956fab4d28 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
pyonta2017 0:1f956fab4d28 96
pyonta2017 0:1f956fab4d28 97 //and turn off the PHY OSC
pyonta2017 0:1f956fab4d28 98 LPC_GPIO1->FIODIR |= 0x8000000;
pyonta2017 0:1f956fab4d28 99 LPC_GPIO1->FIOCLR = 0x8000000;
pyonta2017 0:1f956fab4d28 100 }
pyonta2017 0:1f956fab4d28 101
pyonta2017 0:1f956fab4d28 102 void PHY_PowerUp()
pyonta2017 0:1f956fab4d28 103 {
pyonta2017 0:1f956fab4d28 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:1f956fab4d28 105 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:1f956fab4d28 106
pyonta2017 0:1f956fab4d28 107 LPC_GPIO1->FIODIR |= 0x8000000;
pyonta2017 0:1f956fab4d28 108 LPC_GPIO1->FIOSET = 0x8000000;
pyonta2017 0:1f956fab4d28 109
pyonta2017 0:1f956fab4d28 110 //wait for osc to be stable
pyonta2017 0:1f956fab4d28 111 wait_ms(200);
pyonta2017 0:1f956fab4d28 112
pyonta2017 0:1f956fab4d28 113 unsigned int regv;
pyonta2017 0:1f956fab4d28 114 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:1f956fab4d28 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
pyonta2017 0:1f956fab4d28 116 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:1f956fab4d28 117 }
pyonta2017 0:1f956fab4d28 118
pyonta2017 0:1f956fab4d28 119 void PHY_EnergyDetect_Enable()
pyonta2017 0:1f956fab4d28 120 {
pyonta2017 0:1f956fab4d28 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:1f956fab4d28 122 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:1f956fab4d28 123
pyonta2017 0:1f956fab4d28 124 unsigned int regv;
pyonta2017 0:1f956fab4d28 125 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:1f956fab4d28 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
pyonta2017 0:1f956fab4d28 127 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:1f956fab4d28 128 }
pyonta2017 0:1f956fab4d28 129
pyonta2017 0:1f956fab4d28 130 void PHY_EnergyDetect_Disable()
pyonta2017 0:1f956fab4d28 131 {
pyonta2017 0:1f956fab4d28 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:1f956fab4d28 133 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:1f956fab4d28 134 unsigned int regv;
pyonta2017 0:1f956fab4d28 135 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:1f956fab4d28 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
pyonta2017 0:1f956fab4d28 137 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:1f956fab4d28 138 }