pyonta cansat / Mbed 2 deprecated FM_integration

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Dependencies:   Hm MPL MPU60580 MU2Class SDFileSystem mbed

PowerControl/EthernetPowerControl.cpp@1:8a25883c423c, 2017-09-13 (annotated)

Committer:
pyonta2017
Date:
Wed Sep 13 09:44:08 2017 +0000
Revision:
1:8a25883c423c
Parent:
0:6ddf1386e71d 
aa

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pyonta2017 0:6ddf1386e71d 1 #include "EthernetPowerControl.h"
pyonta2017 0:6ddf1386e71d 2
pyonta2017 0:6ddf1386e71d 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
pyonta2017 0:6ddf1386e71d 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
pyonta2017 0:6ddf1386e71d 5 unsigned int tout;
pyonta2017 0:6ddf1386e71d 6 /* Hardware MII Management for LPC176x devices. */
pyonta2017 0:6ddf1386e71d 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
pyonta2017 0:6ddf1386e71d 8 LPC_EMAC->MWTD = Value;
pyonta2017 0:6ddf1386e71d 9
pyonta2017 0:6ddf1386e71d 10 /* Wait utill operation completed */
pyonta2017 0:6ddf1386e71d 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
pyonta2017 0:6ddf1386e71d 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
pyonta2017 0:6ddf1386e71d 13 break;
pyonta2017 0:6ddf1386e71d 14 }
pyonta2017 0:6ddf1386e71d 15 }
pyonta2017 0:6ddf1386e71d 16 }
pyonta2017 0:6ddf1386e71d 17
pyonta2017 0:6ddf1386e71d 18 static unsigned short read_PHY (unsigned int PhyReg) {
pyonta2017 0:6ddf1386e71d 19 /* Read a PHY register 'PhyReg'. */
pyonta2017 0:6ddf1386e71d 20 unsigned int tout, val;
pyonta2017 0:6ddf1386e71d 21
pyonta2017 0:6ddf1386e71d 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
pyonta2017 0:6ddf1386e71d 23 LPC_EMAC->MCMD = MCMD_READ;
pyonta2017 0:6ddf1386e71d 24
pyonta2017 0:6ddf1386e71d 25 /* Wait until operation completed */
pyonta2017 0:6ddf1386e71d 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
pyonta2017 0:6ddf1386e71d 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
pyonta2017 0:6ddf1386e71d 28 break;
pyonta2017 0:6ddf1386e71d 29 }
pyonta2017 0:6ddf1386e71d 30 }
pyonta2017 0:6ddf1386e71d 31 LPC_EMAC->MCMD = 0;
pyonta2017 0:6ddf1386e71d 32 val = LPC_EMAC->MRDD;
pyonta2017 0:6ddf1386e71d 33
pyonta2017 0:6ddf1386e71d 34 return (val);
pyonta2017 0:6ddf1386e71d 35 }
pyonta2017 0:6ddf1386e71d 36
pyonta2017 0:6ddf1386e71d 37 void EMAC_Init()
pyonta2017 0:6ddf1386e71d 38 {
pyonta2017 0:6ddf1386e71d 39 unsigned int tout,regv;
pyonta2017 0:6ddf1386e71d 40 /* Power Up the EMAC controller. */
pyonta2017 0:6ddf1386e71d 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
pyonta2017 0:6ddf1386e71d 42
pyonta2017 0:6ddf1386e71d 43 LPC_PINCON->PINSEL2 = 0x50150105;
pyonta2017 0:6ddf1386e71d 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
pyonta2017 0:6ddf1386e71d 45 LPC_PINCON->PINSEL3 |= 0x00000005;
pyonta2017 0:6ddf1386e71d 46
pyonta2017 0:6ddf1386e71d 47 /* Reset all EMAC internal modules. */
pyonta2017 0:6ddf1386e71d 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
pyonta2017 0:6ddf1386e71d 49 MAC1_SIM_RES | MAC1_SOFT_RES;
pyonta2017 0:6ddf1386e71d 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
pyonta2017 0:6ddf1386e71d 51
pyonta2017 0:6ddf1386e71d 52 /* A short delay after reset. */
pyonta2017 0:6ddf1386e71d 53 for (tout = 100; tout; tout--);
pyonta2017 0:6ddf1386e71d 54
pyonta2017 0:6ddf1386e71d 55 /* Initialize MAC control registers. */
pyonta2017 0:6ddf1386e71d 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
pyonta2017 0:6ddf1386e71d 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
pyonta2017 0:6ddf1386e71d 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
pyonta2017 0:6ddf1386e71d 59 LPC_EMAC->CLRT = CLRT_DEF;
pyonta2017 0:6ddf1386e71d 60 LPC_EMAC->IPGR = IPGR_DEF;
pyonta2017 0:6ddf1386e71d 61
pyonta2017 0:6ddf1386e71d 62 /* Enable Reduced MII interface. */
pyonta2017 0:6ddf1386e71d 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
pyonta2017 0:6ddf1386e71d 64
pyonta2017 0:6ddf1386e71d 65 /* Reset Reduced MII Logic. */
pyonta2017 0:6ddf1386e71d 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
pyonta2017 0:6ddf1386e71d 67 for (tout = 100; tout; tout--);
pyonta2017 0:6ddf1386e71d 68 LPC_EMAC->SUPP = 0;
pyonta2017 0:6ddf1386e71d 69
pyonta2017 0:6ddf1386e71d 70 /* Put the DP83848C in reset mode */
pyonta2017 0:6ddf1386e71d 71 write_PHY (PHY_REG_BMCR, 0x8000);
pyonta2017 0:6ddf1386e71d 72
pyonta2017 0:6ddf1386e71d 73 /* Wait for hardware reset to end. */
pyonta2017 0:6ddf1386e71d 74 for (tout = 0; tout < 0x100000; tout++) {
pyonta2017 0:6ddf1386e71d 75 regv = read_PHY (PHY_REG_BMCR);
pyonta2017 0:6ddf1386e71d 76 if (!(regv & 0x8000)) {
pyonta2017 0:6ddf1386e71d 77 /* Reset complete */
pyonta2017 0:6ddf1386e71d 78 break;
pyonta2017 0:6ddf1386e71d 79 }
pyonta2017 0:6ddf1386e71d 80 }
pyonta2017 0:6ddf1386e71d 81 }
pyonta2017 0:6ddf1386e71d 82
pyonta2017 0:6ddf1386e71d 83
pyonta2017 0:6ddf1386e71d 84 void PHY_PowerDown()
pyonta2017 0:6ddf1386e71d 85 {
pyonta2017 0:6ddf1386e71d 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:6ddf1386e71d 87 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:6ddf1386e71d 88
pyonta2017 0:6ddf1386e71d 89 unsigned int regv;
pyonta2017 0:6ddf1386e71d 90 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:6ddf1386e71d 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
pyonta2017 0:6ddf1386e71d 92 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:6ddf1386e71d 93
pyonta2017 0:6ddf1386e71d 94 //shouldn't need the EMAC now.
pyonta2017 0:6ddf1386e71d 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
pyonta2017 0:6ddf1386e71d 96
pyonta2017 0:6ddf1386e71d 97 //and turn off the PHY OSC
pyonta2017 0:6ddf1386e71d 98 LPC_GPIO1->FIODIR |= 0x8000000;
pyonta2017 0:6ddf1386e71d 99 LPC_GPIO1->FIOCLR = 0x8000000;
pyonta2017 0:6ddf1386e71d 100 }
pyonta2017 0:6ddf1386e71d 101
pyonta2017 0:6ddf1386e71d 102 void PHY_PowerUp()
pyonta2017 0:6ddf1386e71d 103 {
pyonta2017 0:6ddf1386e71d 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:6ddf1386e71d 105 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:6ddf1386e71d 106
pyonta2017 0:6ddf1386e71d 107 LPC_GPIO1->FIODIR |= 0x8000000;
pyonta2017 0:6ddf1386e71d 108 LPC_GPIO1->FIOSET = 0x8000000;
pyonta2017 0:6ddf1386e71d 109
pyonta2017 0:6ddf1386e71d 110 //wait for osc to be stable
pyonta2017 0:6ddf1386e71d 111 wait_ms(200);
pyonta2017 0:6ddf1386e71d 112
pyonta2017 0:6ddf1386e71d 113 unsigned int regv;
pyonta2017 0:6ddf1386e71d 114 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:6ddf1386e71d 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
pyonta2017 0:6ddf1386e71d 116 regv = read_PHY(PHY_REG_BMCR);
pyonta2017 0:6ddf1386e71d 117 }
pyonta2017 0:6ddf1386e71d 118
pyonta2017 0:6ddf1386e71d 119 void PHY_EnergyDetect_Enable()
pyonta2017 0:6ddf1386e71d 120 {
pyonta2017 0:6ddf1386e71d 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:6ddf1386e71d 122 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:6ddf1386e71d 123
pyonta2017 0:6ddf1386e71d 124 unsigned int regv;
pyonta2017 0:6ddf1386e71d 125 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:6ddf1386e71d 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
pyonta2017 0:6ddf1386e71d 127 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:6ddf1386e71d 128 }
pyonta2017 0:6ddf1386e71d 129
pyonta2017 0:6ddf1386e71d 130 void PHY_EnergyDetect_Disable()
pyonta2017 0:6ddf1386e71d 131 {
pyonta2017 0:6ddf1386e71d 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
pyonta2017 0:6ddf1386e71d 133 EMAC_Init(); //init EMAC if it is not already init'd
pyonta2017 0:6ddf1386e71d 134 unsigned int regv;
pyonta2017 0:6ddf1386e71d 135 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:6ddf1386e71d 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
pyonta2017 0:6ddf1386e71d 137 regv = read_PHY(PHY_REG_EDCR);
pyonta2017 0:6ddf1386e71d 138 }