mbed library sources, include can_api for nucleo-f091rc
Dependents: CanNucleoF0_example
Fork of mbed-src by
targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c@320:be04b2b1e3f2, 2014-09-11 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 11 17:00:08 2014 +0100
- Revision:
- 320:be04b2b1e3f2
- Parent:
- targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c@146:f64d43ff0c18
- Child:
- 324:406fd2029f23
Synchronized with git revision c372035d60ac16c22e1313348a9e3f47293dc6b8
Full URL: https://github.com/mbedmicro/mbed/commit/c372035d60ac16c22e1313348a9e3f47293dc6b8/
Add derivative support to K64F and updates for MTS_GAMBIT
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 146:f64d43ff0c18 | 1 | /* |
mbed_official | 146:f64d43ff0c18 | 2 | ** ################################################################### |
mbed_official | 146:f64d43ff0c18 | 3 | ** Processor: MK64FN1M0VMD12 |
mbed_official | 146:f64d43ff0c18 | 4 | ** Compilers: ARM Compiler |
mbed_official | 146:f64d43ff0c18 | 5 | ** Freescale C/C++ for Embedded ARM |
mbed_official | 146:f64d43ff0c18 | 6 | ** GNU C Compiler |
mbed_official | 146:f64d43ff0c18 | 7 | ** GNU C Compiler - CodeSourcery Sourcery G++ |
mbed_official | 146:f64d43ff0c18 | 8 | ** IAR ANSI C/C++ Compiler for ARM |
mbed_official | 146:f64d43ff0c18 | 9 | ** |
mbed_official | 146:f64d43ff0c18 | 10 | ** Reference manual: K64P144M120SF5RM, Rev.1, July 2013 |
mbed_official | 146:f64d43ff0c18 | 11 | ** Version: rev. 2.1, 2013-10-29 |
mbed_official | 146:f64d43ff0c18 | 12 | ** |
mbed_official | 146:f64d43ff0c18 | 13 | ** Abstract: |
mbed_official | 146:f64d43ff0c18 | 14 | ** Provides a system configuration function and a global variable that |
mbed_official | 146:f64d43ff0c18 | 15 | ** contains the system frequency. It configures the device and initializes |
mbed_official | 146:f64d43ff0c18 | 16 | ** the oscillator (PLL) that is part of the microcontroller device. |
mbed_official | 146:f64d43ff0c18 | 17 | ** |
mbed_official | 146:f64d43ff0c18 | 18 | ** Copyright: 2013 Freescale, Inc. All Rights Reserved. |
mbed_official | 146:f64d43ff0c18 | 19 | ** |
mbed_official | 146:f64d43ff0c18 | 20 | ** http: www.freescale.com |
mbed_official | 146:f64d43ff0c18 | 21 | ** mail: support@freescale.com |
mbed_official | 146:f64d43ff0c18 | 22 | ** |
mbed_official | 146:f64d43ff0c18 | 23 | ** Revisions: |
mbed_official | 146:f64d43ff0c18 | 24 | ** - rev. 1.0 (2013-08-12) |
mbed_official | 146:f64d43ff0c18 | 25 | ** Initial version. |
mbed_official | 146:f64d43ff0c18 | 26 | ** - rev. 2.0 (2013-10-29) |
mbed_official | 146:f64d43ff0c18 | 27 | ** Register accessor macros added to the memory map. |
mbed_official | 146:f64d43ff0c18 | 28 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
mbed_official | 146:f64d43ff0c18 | 29 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
mbed_official | 146:f64d43ff0c18 | 30 | ** System initialization updated. |
mbed_official | 146:f64d43ff0c18 | 31 | ** MCG - registers updated. |
mbed_official | 146:f64d43ff0c18 | 32 | ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. |
mbed_official | 146:f64d43ff0c18 | 33 | ** - rev. 2.1 (2013-10-29) |
mbed_official | 146:f64d43ff0c18 | 34 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
mbed_official | 146:f64d43ff0c18 | 35 | ** |
mbed_official | 146:f64d43ff0c18 | 36 | ** ################################################################### |
mbed_official | 146:f64d43ff0c18 | 37 | */ |
mbed_official | 146:f64d43ff0c18 | 38 | |
mbed_official | 146:f64d43ff0c18 | 39 | /*! |
mbed_official | 146:f64d43ff0c18 | 40 | * @file MK64F12 |
mbed_official | 146:f64d43ff0c18 | 41 | * @version 2.1 |
mbed_official | 146:f64d43ff0c18 | 42 | * @date 2013-10-29 |
mbed_official | 146:f64d43ff0c18 | 43 | * @brief Device specific configuration file for MK64F12 (implementation file) |
mbed_official | 146:f64d43ff0c18 | 44 | * |
mbed_official | 146:f64d43ff0c18 | 45 | * Provides a system configuration function and a global variable that contains |
mbed_official | 146:f64d43ff0c18 | 46 | * the system frequency. It configures the device and initializes the oscillator |
mbed_official | 146:f64d43ff0c18 | 47 | * (PLL) that is part of the microcontroller device. |
mbed_official | 146:f64d43ff0c18 | 48 | */ |
mbed_official | 146:f64d43ff0c18 | 49 | |
mbed_official | 146:f64d43ff0c18 | 50 | #include <stdint.h> |
mbed_official | 146:f64d43ff0c18 | 51 | #include "MK64F12.h" |
mbed_official | 146:f64d43ff0c18 | 52 | |
mbed_official | 146:f64d43ff0c18 | 53 | #define DISABLE_WDOG 1 |
mbed_official | 146:f64d43ff0c18 | 54 | |
mbed_official | 146:f64d43ff0c18 | 55 | #ifndef CLOCK_SETUP |
mbed_official | 146:f64d43ff0c18 | 56 | #define CLOCK_SETUP 4 |
mbed_official | 146:f64d43ff0c18 | 57 | #endif |
mbed_official | 146:f64d43ff0c18 | 58 | /* Predefined clock setups |
mbed_official | 146:f64d43ff0c18 | 59 | 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode |
mbed_official | 146:f64d43ff0c18 | 60 | Default part configuration. |
mbed_official | 146:f64d43ff0c18 | 61 | Reference clock source for MCG module is the slow internal clock source 32.768kHz |
mbed_official | 146:f64d43ff0c18 | 62 | Core clock = 20.97MHz, BusClock = 20.97MHz |
mbed_official | 146:f64d43ff0c18 | 63 | 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
mbed_official | 146:f64d43ff0c18 | 64 | Maximum achievable clock frequency configuration. |
mbed_official | 146:f64d43ff0c18 | 65 | Reference clock source for MCG module is an external clock source 50MHz |
mbed_official | 146:f64d43ff0c18 | 66 | Core clock = 120MHz, BusClock = 60MHz |
mbed_official | 146:f64d43ff0c18 | 67 | 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode |
mbed_official | 146:f64d43ff0c18 | 68 | Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication |
mbed_official | 146:f64d43ff0c18 | 69 | The clock settings is ready for Very Low Power Run mode. |
mbed_official | 146:f64d43ff0c18 | 70 | Core clock = 4MHz, BusClock = 4MHz |
mbed_official | 146:f64d43ff0c18 | 71 | 3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode |
mbed_official | 146:f64d43ff0c18 | 72 | Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz |
mbed_official | 146:f64d43ff0c18 | 73 | The clock settings is ready for Very Low Power Run mode. |
mbed_official | 146:f64d43ff0c18 | 74 | Core clock = 32.768kHz, BusClock = 32.768kHz |
mbed_official | 146:f64d43ff0c18 | 75 | 4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
mbed_official | 146:f64d43ff0c18 | 76 | USB clock setup |
mbed_official | 146:f64d43ff0c18 | 77 | USB clock divider is set for USB to receive 48MHz input clock. |
mbed_official | 146:f64d43ff0c18 | 78 | Reference clock source for MCG module is an external clock source 50MHz |
mbed_official | 146:f64d43ff0c18 | 79 | USB clock divider is set for USB to receive 48MHz input clock. |
mbed_official | 146:f64d43ff0c18 | 80 | Core clock = 120MHz, BusClock = 60MHz |
mbed_official | 146:f64d43ff0c18 | 81 | */ |
mbed_official | 146:f64d43ff0c18 | 82 | |
mbed_official | 146:f64d43ff0c18 | 83 | /*---------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 84 | Define clock source values |
mbed_official | 146:f64d43ff0c18 | 85 | *----------------------------------------------------------------------------*/ |
mbed_official | 146:f64d43ff0c18 | 86 | #if (CLOCK_SETUP == 0) |
mbed_official | 146:f64d43ff0c18 | 87 | #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 88 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 89 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 90 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 91 | #define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */ |
mbed_official | 146:f64d43ff0c18 | 92 | #elif (CLOCK_SETUP == 1) |
mbed_official | 146:f64d43ff0c18 | 93 | #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 94 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 95 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 96 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 97 | #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ |
mbed_official | 146:f64d43ff0c18 | 98 | #elif (CLOCK_SETUP == 2) |
mbed_official | 146:f64d43ff0c18 | 99 | #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 100 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 101 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 102 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 103 | #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */ |
mbed_official | 146:f64d43ff0c18 | 104 | #elif (CLOCK_SETUP == 3) |
mbed_official | 146:f64d43ff0c18 | 105 | #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 106 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 107 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 108 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 109 | #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */ |
mbed_official | 146:f64d43ff0c18 | 110 | #elif (CLOCK_SETUP == 4) |
mbed_official | 146:f64d43ff0c18 | 111 | #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 112 | #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 113 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 114 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
mbed_official | 146:f64d43ff0c18 | 115 | #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */ |
mbed_official | 146:f64d43ff0c18 | 116 | #endif /* (CLOCK_SETUP == 4) */ |
mbed_official | 146:f64d43ff0c18 | 117 | |
mbed_official | 146:f64d43ff0c18 | 118 | |
mbed_official | 146:f64d43ff0c18 | 119 | /* ---------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 120 | -- Core clock |
mbed_official | 146:f64d43ff0c18 | 121 | ---------------------------------------------------------------------------- */ |
mbed_official | 146:f64d43ff0c18 | 122 | |
mbed_official | 146:f64d43ff0c18 | 123 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
mbed_official | 146:f64d43ff0c18 | 124 | |
mbed_official | 146:f64d43ff0c18 | 125 | /* ---------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 126 | -- SystemInit() |
mbed_official | 146:f64d43ff0c18 | 127 | ---------------------------------------------------------------------------- */ |
mbed_official | 146:f64d43ff0c18 | 128 | |
mbed_official | 146:f64d43ff0c18 | 129 | void SystemInit (void) { |
mbed_official | 146:f64d43ff0c18 | 130 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) |
mbed_official | 146:f64d43ff0c18 | 131 | SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ |
mbed_official | 146:f64d43ff0c18 | 132 | #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ |
mbed_official | 146:f64d43ff0c18 | 133 | #if (DISABLE_WDOG) |
mbed_official | 146:f64d43ff0c18 | 134 | /* Disable the WDOG module */ |
mbed_official | 146:f64d43ff0c18 | 135 | /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ |
mbed_official | 146:f64d43ff0c18 | 136 | WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ |
mbed_official | 146:f64d43ff0c18 | 137 | /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ |
mbed_official | 146:f64d43ff0c18 | 138 | WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ |
mbed_official | 146:f64d43ff0c18 | 139 | /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ |
mbed_official | 146:f64d43ff0c18 | 140 | WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | |
mbed_official | 146:f64d43ff0c18 | 141 | WDOG_STCTRLH_WAITEN_MASK | |
mbed_official | 146:f64d43ff0c18 | 142 | WDOG_STCTRLH_STOPEN_MASK | |
mbed_official | 146:f64d43ff0c18 | 143 | WDOG_STCTRLH_ALLOWUPDATE_MASK | |
mbed_official | 146:f64d43ff0c18 | 144 | WDOG_STCTRLH_CLKSRC_MASK | |
mbed_official | 146:f64d43ff0c18 | 145 | 0x0100U; |
mbed_official | 146:f64d43ff0c18 | 146 | #endif /* (DISABLE_WDOG) */ |
mbed_official | 146:f64d43ff0c18 | 147 | |
mbed_official | 146:f64d43ff0c18 | 148 | /* |
mbed_official | 146:f64d43ff0c18 | 149 | * Release hold with ACKISO: Only has an effect if recovering from VLLSx. |
mbed_official | 146:f64d43ff0c18 | 150 | * if ACKISO is set you must clear ackiso before initializing the PLL |
mbed_official | 146:f64d43ff0c18 | 151 | * if osc enabled in low power modes - enable it first before ack |
mbed_official | 146:f64d43ff0c18 | 152 | */ |
mbed_official | 146:f64d43ff0c18 | 153 | if (PMC->REGSC & PMC_REGSC_ACKISO_MASK) |
mbed_official | 146:f64d43ff0c18 | 154 | { |
mbed_official | 146:f64d43ff0c18 | 155 | PMC->REGSC |= PMC_REGSC_ACKISO_MASK; |
mbed_official | 146:f64d43ff0c18 | 156 | } |
mbed_official | 146:f64d43ff0c18 | 157 | |
mbed_official | 146:f64d43ff0c18 | 158 | #if (CLOCK_SETUP == 0) |
mbed_official | 146:f64d43ff0c18 | 159 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ |
mbed_official | 146:f64d43ff0c18 | 160 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | |
mbed_official | 146:f64d43ff0c18 | 161 | SIM_CLKDIV1_OUTDIV2(0x00) | |
mbed_official | 146:f64d43ff0c18 | 162 | SIM_CLKDIV1_OUTDIV3(0x01) | |
mbed_official | 146:f64d43ff0c18 | 163 | SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */ |
mbed_official | 146:f64d43ff0c18 | 164 | /* SIM->SOPT2: PLLFLLSEL=0 */ |
mbed_official | 146:f64d43ff0c18 | 165 | SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 166 | /* SIM->SOPT1: OSC32KSEL=3 */ |
mbed_official | 146:f64d43ff0c18 | 167 | SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 168 | /* Switch to FEI Mode */ |
mbed_official | 146:f64d43ff0c18 | 169 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 146:f64d43ff0c18 | 170 | MCG->C1 = MCG_C1_CLKS(0x00) | |
mbed_official | 146:f64d43ff0c18 | 171 | MCG_C1_FRDIV(0x00) | |
mbed_official | 146:f64d43ff0c18 | 172 | MCG_C1_IREFS_MASK | |
mbed_official | 146:f64d43ff0c18 | 173 | MCG_C1_IRCLKEN_MASK; |
mbed_official | 146:f64d43ff0c18 | 174 | /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ |
mbed_official | 146:f64d43ff0c18 | 175 | MCG->C2 = MCG_C2_RANGE0(0x00); |
mbed_official | 146:f64d43ff0c18 | 176 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 146:f64d43ff0c18 | 177 | MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); |
mbed_official | 146:f64d43ff0c18 | 178 | /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 146:f64d43ff0c18 | 179 | OSC->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 146:f64d43ff0c18 | 180 | /* MCG->C7: OSCSEL=0 */ |
mbed_official | 146:f64d43ff0c18 | 181 | MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); |
mbed_official | 146:f64d43ff0c18 | 182 | /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
mbed_official | 146:f64d43ff0c18 | 183 | MCG->C5 = MCG_C5_PRDIV0(0x00); |
mbed_official | 146:f64d43ff0c18 | 184 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
mbed_official | 146:f64d43ff0c18 | 185 | MCG->C6 = MCG_C6_VDIV0(0x00); |
mbed_official | 146:f64d43ff0c18 | 186 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 146:f64d43ff0c18 | 187 | } |
mbed_official | 146:f64d43ff0c18 | 188 | while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ |
mbed_official | 146:f64d43ff0c18 | 189 | } |
mbed_official | 146:f64d43ff0c18 | 190 | #elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4) |
mbed_official | 146:f64d43ff0c18 | 191 | /* SIM->SCGC5: PORTA=1 */ |
mbed_official | 146:f64d43ff0c18 | 192 | SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ |
mbed_official | 146:f64d43ff0c18 | 193 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ |
mbed_official | 146:f64d43ff0c18 | 194 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | |
mbed_official | 146:f64d43ff0c18 | 195 | SIM_CLKDIV1_OUTDIV2(0x01) | |
mbed_official | 146:f64d43ff0c18 | 196 | SIM_CLKDIV1_OUTDIV3(0x02) | |
mbed_official | 146:f64d43ff0c18 | 197 | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ |
mbed_official | 146:f64d43ff0c18 | 198 | /* SIM->SOPT2: PLLFLLSEL=1 */ |
mbed_official | 146:f64d43ff0c18 | 199 | SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 200 | /* SIM->SOPT1: OSC32KSEL=3 */ |
mbed_official | 146:f64d43ff0c18 | 201 | SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 202 | /* PORTA->PCR[18]: ISF=0,MUX=0 */ |
mbed_official | 146:f64d43ff0c18 | 203 | PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); |
mbed_official | 146:f64d43ff0c18 | 204 | /* Switch to FBE Mode */ |
mbed_official | 146:f64d43ff0c18 | 205 | /* MCG->C2: LOCRE0=0,?=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ |
mbed_official | 146:f64d43ff0c18 | 206 | MCG->C2 = MCG_C2_RANGE0(0x02); |
mbed_official | 146:f64d43ff0c18 | 207 | /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 146:f64d43ff0c18 | 208 | OSC->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 146:f64d43ff0c18 | 209 | /* MCG->C7: OSCSEL=0 */ |
mbed_official | 146:f64d43ff0c18 | 210 | MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); |
mbed_official | 146:f64d43ff0c18 | 211 | /* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 146:f64d43ff0c18 | 212 | MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x07) | MCG_C1_IRCLKEN_MASK); |
mbed_official | 146:f64d43ff0c18 | 213 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 146:f64d43ff0c18 | 214 | MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); |
mbed_official | 146:f64d43ff0c18 | 215 | /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */ |
mbed_official | 146:f64d43ff0c18 | 216 | MCG->C5 = MCG_C5_PRDIV0(0x13); |
mbed_official | 146:f64d43ff0c18 | 217 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */ |
mbed_official | 146:f64d43ff0c18 | 218 | MCG->C6 = MCG_C6_VDIV0(0x18); |
mbed_official | 146:f64d43ff0c18 | 219 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
mbed_official | 146:f64d43ff0c18 | 220 | } |
mbed_official | 146:f64d43ff0c18 | 221 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
mbed_official | 146:f64d43ff0c18 | 222 | } |
mbed_official | 146:f64d43ff0c18 | 223 | /* Switch to PBE Mode */ |
mbed_official | 146:f64d43ff0c18 | 224 | /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */ |
mbed_official | 146:f64d43ff0c18 | 225 | MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18)); |
mbed_official | 146:f64d43ff0c18 | 226 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
mbed_official | 146:f64d43ff0c18 | 227 | } |
mbed_official | 146:f64d43ff0c18 | 228 | while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ |
mbed_official | 146:f64d43ff0c18 | 229 | } |
mbed_official | 146:f64d43ff0c18 | 230 | /* Switch to PEE Mode */ |
mbed_official | 146:f64d43ff0c18 | 231 | /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 146:f64d43ff0c18 | 232 | MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK); |
mbed_official | 146:f64d43ff0c18 | 233 | while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ |
mbed_official | 146:f64d43ff0c18 | 234 | } |
mbed_official | 146:f64d43ff0c18 | 235 | #if (CLOCK_SETUP == 4) |
mbed_official | 146:f64d43ff0c18 | 236 | /* Set USB input clock to 48MHz */ |
mbed_official | 146:f64d43ff0c18 | 237 | /* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */ |
mbed_official | 146:f64d43ff0c18 | 238 | SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)( |
mbed_official | 146:f64d43ff0c18 | 239 | SIM_CLKDIV2_USBDIV(0x03) |
mbed_official | 146:f64d43ff0c18 | 240 | )) | (uint32_t)( |
mbed_official | 146:f64d43ff0c18 | 241 | SIM_CLKDIV2_USBDIV(0x04) | |
mbed_official | 146:f64d43ff0c18 | 242 | SIM_CLKDIV2_USBFRAC_MASK |
mbed_official | 146:f64d43ff0c18 | 243 | )); |
mbed_official | 146:f64d43ff0c18 | 244 | #endif |
mbed_official | 146:f64d43ff0c18 | 245 | #elif (CLOCK_SETUP == 2) |
mbed_official | 146:f64d43ff0c18 | 246 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ |
mbed_official | 146:f64d43ff0c18 | 247 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | |
mbed_official | 146:f64d43ff0c18 | 248 | SIM_CLKDIV1_OUTDIV2(0x00) | |
mbed_official | 146:f64d43ff0c18 | 249 | SIM_CLKDIV1_OUTDIV3(0x00) | |
mbed_official | 146:f64d43ff0c18 | 250 | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ |
mbed_official | 146:f64d43ff0c18 | 251 | /* SIM->SOPT2: PLLFLLSEL=0 */ |
mbed_official | 146:f64d43ff0c18 | 252 | SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 253 | /* SIM->SOPT1: OSC32KSEL=3 */ |
mbed_official | 146:f64d43ff0c18 | 254 | SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 255 | /* MCG->SC: FCRDIV=0 */ |
mbed_official | 146:f64d43ff0c18 | 256 | MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07)); |
mbed_official | 146:f64d43ff0c18 | 257 | /* Switch to FBI Mode */ |
mbed_official | 146:f64d43ff0c18 | 258 | /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 146:f64d43ff0c18 | 259 | MCG->C1 = MCG_C1_CLKS(0x01) | |
mbed_official | 146:f64d43ff0c18 | 260 | MCG_C1_FRDIV(0x00) | |
mbed_official | 146:f64d43ff0c18 | 261 | MCG_C1_IREFS_MASK | |
mbed_official | 146:f64d43ff0c18 | 262 | MCG_C1_IRCLKEN_MASK; |
mbed_official | 146:f64d43ff0c18 | 263 | /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */ |
mbed_official | 146:f64d43ff0c18 | 264 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK); |
mbed_official | 146:f64d43ff0c18 | 265 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 146:f64d43ff0c18 | 266 | MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); |
mbed_official | 146:f64d43ff0c18 | 267 | /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 146:f64d43ff0c18 | 268 | OSC->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 146:f64d43ff0c18 | 269 | /* MCG->C7: OSCSEL=0 */ |
mbed_official | 146:f64d43ff0c18 | 270 | MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); |
mbed_official | 146:f64d43ff0c18 | 271 | /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
mbed_official | 146:f64d43ff0c18 | 272 | MCG->C5 = MCG_C5_PRDIV0(0x00); |
mbed_official | 146:f64d43ff0c18 | 273 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
mbed_official | 146:f64d43ff0c18 | 274 | MCG->C6 = MCG_C6_VDIV0(0x00); |
mbed_official | 146:f64d43ff0c18 | 275 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 146:f64d43ff0c18 | 276 | } |
mbed_official | 146:f64d43ff0c18 | 277 | while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */ |
mbed_official | 146:f64d43ff0c18 | 278 | } |
mbed_official | 146:f64d43ff0c18 | 279 | /* Switch to BLPI Mode */ |
mbed_official | 146:f64d43ff0c18 | 280 | /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */ |
mbed_official | 146:f64d43ff0c18 | 281 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK); |
mbed_official | 146:f64d43ff0c18 | 282 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
mbed_official | 146:f64d43ff0c18 | 283 | } |
mbed_official | 146:f64d43ff0c18 | 284 | while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */ |
mbed_official | 146:f64d43ff0c18 | 285 | } |
mbed_official | 146:f64d43ff0c18 | 286 | #elif (CLOCK_SETUP == 3) |
mbed_official | 146:f64d43ff0c18 | 287 | /* SIM->SCGC6: RTC=1 */ |
mbed_official | 146:f64d43ff0c18 | 288 | SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; |
mbed_official | 146:f64d43ff0c18 | 289 | if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */ |
mbed_official | 146:f64d43ff0c18 | 290 | /* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 146:f64d43ff0c18 | 291 | RTC->CR &= (uint32_t)~(uint32_t)( |
mbed_official | 146:f64d43ff0c18 | 292 | RTC_CR_SC2P_MASK | |
mbed_official | 146:f64d43ff0c18 | 293 | RTC_CR_SC4P_MASK | |
mbed_official | 146:f64d43ff0c18 | 294 | RTC_CR_SC8P_MASK | |
mbed_official | 146:f64d43ff0c18 | 295 | RTC_CR_SC16P_MASK |
mbed_official | 146:f64d43ff0c18 | 296 | ); |
mbed_official | 146:f64d43ff0c18 | 297 | /* RTC->CR: OSCE=1 */ |
mbed_official | 146:f64d43ff0c18 | 298 | RTC->CR |= RTC_CR_OSCE_MASK; |
mbed_official | 146:f64d43ff0c18 | 299 | /* RTC->CR: CLKO=0 */ |
mbed_official | 146:f64d43ff0c18 | 300 | RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK); |
mbed_official | 146:f64d43ff0c18 | 301 | } |
mbed_official | 146:f64d43ff0c18 | 302 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */ |
mbed_official | 146:f64d43ff0c18 | 303 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | |
mbed_official | 146:f64d43ff0c18 | 304 | SIM_CLKDIV1_OUTDIV2(0x00) | |
mbed_official | 146:f64d43ff0c18 | 305 | SIM_CLKDIV1_OUTDIV3(0x00) | |
mbed_official | 146:f64d43ff0c18 | 306 | SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */ |
mbed_official | 146:f64d43ff0c18 | 307 | /* SIM->SOPT1: OSC32KSEL=2 */ |
mbed_official | 146:f64d43ff0c18 | 308 | SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)( |
mbed_official | 146:f64d43ff0c18 | 309 | SIM_SOPT1_OSC32KSEL(0x01) |
mbed_official | 146:f64d43ff0c18 | 310 | )) | (uint32_t)( |
mbed_official | 146:f64d43ff0c18 | 311 | SIM_SOPT1_OSC32KSEL(0x02) |
mbed_official | 146:f64d43ff0c18 | 312 | )); /* System oscillator drives 32 kHz clock for various peripherals */ |
mbed_official | 146:f64d43ff0c18 | 313 | /* Switch to FBE Mode */ |
mbed_official | 146:f64d43ff0c18 | 314 | /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ |
mbed_official | 146:f64d43ff0c18 | 315 | MCG->C2 = MCG_C2_RANGE0(0x00); |
mbed_official | 146:f64d43ff0c18 | 316 | /* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
mbed_official | 146:f64d43ff0c18 | 317 | OSC->CR = OSC_CR_ERCLKEN_MASK; |
mbed_official | 146:f64d43ff0c18 | 318 | /* MCG->C7: OSCSEL=1 */ |
mbed_official | 146:f64d43ff0c18 | 319 | MCG->C7 |= MCG_C7_OSCSEL_MASK; |
mbed_official | 146:f64d43ff0c18 | 320 | /* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
mbed_official | 146:f64d43ff0c18 | 321 | MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK); |
mbed_official | 146:f64d43ff0c18 | 322 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
mbed_official | 146:f64d43ff0c18 | 323 | MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); |
mbed_official | 146:f64d43ff0c18 | 324 | /* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
mbed_official | 146:f64d43ff0c18 | 325 | MCG->C5 = MCG_C5_PRDIV0(0x00); |
mbed_official | 146:f64d43ff0c18 | 326 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
mbed_official | 146:f64d43ff0c18 | 327 | MCG->C6 = MCG_C6_VDIV0(0x00); |
mbed_official | 146:f64d43ff0c18 | 328 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
mbed_official | 146:f64d43ff0c18 | 329 | } |
mbed_official | 146:f64d43ff0c18 | 330 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
mbed_official | 146:f64d43ff0c18 | 331 | } |
mbed_official | 146:f64d43ff0c18 | 332 | /* Switch to BLPE Mode */ |
mbed_official | 146:f64d43ff0c18 | 333 | /* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=0 */ |
mbed_official | 146:f64d43ff0c18 | 334 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK); |
mbed_official | 146:f64d43ff0c18 | 335 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
mbed_official | 146:f64d43ff0c18 | 336 | } |
mbed_official | 146:f64d43ff0c18 | 337 | #endif |
mbed_official | 146:f64d43ff0c18 | 338 | } |
mbed_official | 146:f64d43ff0c18 | 339 | |
mbed_official | 146:f64d43ff0c18 | 340 | /* ---------------------------------------------------------------------------- |
mbed_official | 146:f64d43ff0c18 | 341 | -- SystemCoreClockUpdate() |
mbed_official | 146:f64d43ff0c18 | 342 | ---------------------------------------------------------------------------- */ |
mbed_official | 146:f64d43ff0c18 | 343 | |
mbed_official | 146:f64d43ff0c18 | 344 | void SystemCoreClockUpdate (void) { |
mbed_official | 146:f64d43ff0c18 | 345 | uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ |
mbed_official | 146:f64d43ff0c18 | 346 | uint8_t Divider; |
mbed_official | 146:f64d43ff0c18 | 347 | |
mbed_official | 146:f64d43ff0c18 | 348 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 349 | /* Output of FLL or PLL is selected */ |
mbed_official | 146:f64d43ff0c18 | 350 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 351 | /* FLL is selected */ |
mbed_official | 146:f64d43ff0c18 | 352 | if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 353 | /* External reference clock is selected */ |
mbed_official | 146:f64d43ff0c18 | 354 | if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 355 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
mbed_official | 146:f64d43ff0c18 | 356 | } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 357 | MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
mbed_official | 146:f64d43ff0c18 | 358 | } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 359 | Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
mbed_official | 146:f64d43ff0c18 | 360 | MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ |
mbed_official | 146:f64d43ff0c18 | 361 | if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 362 | MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */ |
mbed_official | 146:f64d43ff0c18 | 363 | } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */ |
mbed_official | 146:f64d43ff0c18 | 364 | } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 365 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ |
mbed_official | 146:f64d43ff0c18 | 366 | } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 367 | /* Select correct multiplier to calculate the MCG output clock */ |
mbed_official | 146:f64d43ff0c18 | 368 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
mbed_official | 146:f64d43ff0c18 | 369 | case 0x0u: |
mbed_official | 146:f64d43ff0c18 | 370 | MCGOUTClock *= 640u; |
mbed_official | 146:f64d43ff0c18 | 371 | break; |
mbed_official | 146:f64d43ff0c18 | 372 | case 0x20u: |
mbed_official | 146:f64d43ff0c18 | 373 | MCGOUTClock *= 1280u; |
mbed_official | 146:f64d43ff0c18 | 374 | break; |
mbed_official | 146:f64d43ff0c18 | 375 | case 0x40u: |
mbed_official | 146:f64d43ff0c18 | 376 | MCGOUTClock *= 1920u; |
mbed_official | 146:f64d43ff0c18 | 377 | break; |
mbed_official | 146:f64d43ff0c18 | 378 | case 0x60u: |
mbed_official | 146:f64d43ff0c18 | 379 | MCGOUTClock *= 2560u; |
mbed_official | 146:f64d43ff0c18 | 380 | break; |
mbed_official | 146:f64d43ff0c18 | 381 | case 0x80u: |
mbed_official | 146:f64d43ff0c18 | 382 | MCGOUTClock *= 732u; |
mbed_official | 146:f64d43ff0c18 | 383 | break; |
mbed_official | 146:f64d43ff0c18 | 384 | case 0xA0u: |
mbed_official | 146:f64d43ff0c18 | 385 | MCGOUTClock *= 1464u; |
mbed_official | 146:f64d43ff0c18 | 386 | break; |
mbed_official | 146:f64d43ff0c18 | 387 | case 0xC0u: |
mbed_official | 146:f64d43ff0c18 | 388 | MCGOUTClock *= 2197u; |
mbed_official | 146:f64d43ff0c18 | 389 | break; |
mbed_official | 146:f64d43ff0c18 | 390 | case 0xE0u: |
mbed_official | 146:f64d43ff0c18 | 391 | MCGOUTClock *= 2929u; |
mbed_official | 146:f64d43ff0c18 | 392 | break; |
mbed_official | 146:f64d43ff0c18 | 393 | default: |
mbed_official | 146:f64d43ff0c18 | 394 | break; |
mbed_official | 146:f64d43ff0c18 | 395 | } |
mbed_official | 146:f64d43ff0c18 | 396 | } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 397 | /* PLL is selected */ |
mbed_official | 146:f64d43ff0c18 | 398 | Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); |
mbed_official | 146:f64d43ff0c18 | 399 | MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ |
mbed_official | 146:f64d43ff0c18 | 400 | Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); |
mbed_official | 146:f64d43ff0c18 | 401 | MCGOUTClock *= Divider; /* Calculate the MCG output clock */ |
mbed_official | 146:f64d43ff0c18 | 402 | } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 403 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) { |
mbed_official | 146:f64d43ff0c18 | 404 | /* Internal reference clock is selected */ |
mbed_official | 146:f64d43ff0c18 | 405 | if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 406 | MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ |
mbed_official | 146:f64d43ff0c18 | 407 | } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 408 | MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ |
mbed_official | 146:f64d43ff0c18 | 409 | } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 410 | } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { |
mbed_official | 146:f64d43ff0c18 | 411 | /* External reference clock is selected */ |
mbed_official | 146:f64d43ff0c18 | 412 | if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) { |
mbed_official | 146:f64d43ff0c18 | 413 | MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ |
mbed_official | 146:f64d43ff0c18 | 414 | } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 415 | MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ |
mbed_official | 146:f64d43ff0c18 | 416 | } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */ |
mbed_official | 146:f64d43ff0c18 | 417 | } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
mbed_official | 146:f64d43ff0c18 | 418 | /* Reserved value */ |
mbed_official | 146:f64d43ff0c18 | 419 | return; |
mbed_official | 146:f64d43ff0c18 | 420 | } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */ |
mbed_official | 146:f64d43ff0c18 | 421 | SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); |
mbed_official | 146:f64d43ff0c18 | 422 | } |