mbed library sources, include can_api for nucleo-f091rc
Dependents: CanNucleoF0_example
Fork of mbed-src by
targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c@227:7bd0639b8911, 2014-06-11 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jun 11 16:00:09 2014 +0100
- Revision:
- 227:7bd0639b8911
- Parent:
- 81:a9456fdf72fa
- Child:
- 250:a49055e7a707
Synchronized with git revision d58d532ebc0e0a96f4fffb8edefc082b71b964af
Full URL: https://github.com/mbedmicro/mbed/commit/d58d532ebc0e0a96f4fffb8edefc082b71b964af/
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 46:bebbbd80dd87 | 1 | /* mbed Microcontroller Library |
mbed_official | 46:bebbbd80dd87 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 46:bebbbd80dd87 | 3 | * |
mbed_official | 46:bebbbd80dd87 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 46:bebbbd80dd87 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 46:bebbbd80dd87 | 6 | * You may obtain a copy of the License at |
mbed_official | 46:bebbbd80dd87 | 7 | * |
mbed_official | 46:bebbbd80dd87 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 46:bebbbd80dd87 | 9 | * |
mbed_official | 46:bebbbd80dd87 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 46:bebbbd80dd87 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 46:bebbbd80dd87 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 46:bebbbd80dd87 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 46:bebbbd80dd87 | 14 | * limitations under the License. |
mbed_official | 46:bebbbd80dd87 | 15 | */ |
mbed_official | 227:7bd0639b8911 | 16 | #include "mbed_assert.h" |
mbed_official | 46:bebbbd80dd87 | 17 | #include <math.h> |
mbed_official | 46:bebbbd80dd87 | 18 | |
mbed_official | 46:bebbbd80dd87 | 19 | #include "spi_api.h" |
mbed_official | 46:bebbbd80dd87 | 20 | #include "cmsis.h" |
mbed_official | 46:bebbbd80dd87 | 21 | #include "pinmap.h" |
mbed_official | 46:bebbbd80dd87 | 22 | #include "error.h" |
mbed_official | 46:bebbbd80dd87 | 23 | |
mbed_official | 46:bebbbd80dd87 | 24 | static const SWM_Map SWM_SPI_SSEL[] = { |
mbed_official | 46:bebbbd80dd87 | 25 | {4, 16}, |
mbed_official | 46:bebbbd80dd87 | 26 | {5, 16}, |
mbed_official | 46:bebbbd80dd87 | 27 | }; |
mbed_official | 46:bebbbd80dd87 | 28 | |
mbed_official | 46:bebbbd80dd87 | 29 | static const SWM_Map SWM_SPI_SCLK[] = { |
mbed_official | 46:bebbbd80dd87 | 30 | {3, 24}, |
mbed_official | 46:bebbbd80dd87 | 31 | {4, 24}, |
mbed_official | 46:bebbbd80dd87 | 32 | }; |
mbed_official | 46:bebbbd80dd87 | 33 | |
mbed_official | 46:bebbbd80dd87 | 34 | static const SWM_Map SWM_SPI_MOSI[] = { |
mbed_official | 46:bebbbd80dd87 | 35 | {4, 0}, |
mbed_official | 46:bebbbd80dd87 | 36 | {5, 0}, |
mbed_official | 46:bebbbd80dd87 | 37 | }; |
mbed_official | 46:bebbbd80dd87 | 38 | |
mbed_official | 46:bebbbd80dd87 | 39 | static const SWM_Map SWM_SPI_MISO[] = { |
mbed_official | 46:bebbbd80dd87 | 40 | {4, 8}, |
mbed_official | 46:bebbbd80dd87 | 41 | {5, 16}, |
mbed_official | 46:bebbbd80dd87 | 42 | }; |
mbed_official | 46:bebbbd80dd87 | 43 | |
mbed_official | 46:bebbbd80dd87 | 44 | // bit flags for used SPIs |
mbed_official | 46:bebbbd80dd87 | 45 | static unsigned char spi_used = 0; |
mbed_official | 46:bebbbd80dd87 | 46 | static int get_available_spi(void) { |
mbed_official | 46:bebbbd80dd87 | 47 | int i; |
mbed_official | 46:bebbbd80dd87 | 48 | for (i=0; i<2; i++) { |
mbed_official | 46:bebbbd80dd87 | 49 | if ((spi_used & (1 << i)) == 0) |
mbed_official | 46:bebbbd80dd87 | 50 | return i; |
mbed_official | 46:bebbbd80dd87 | 51 | } |
mbed_official | 46:bebbbd80dd87 | 52 | return -1; |
mbed_official | 46:bebbbd80dd87 | 53 | } |
mbed_official | 46:bebbbd80dd87 | 54 | |
mbed_official | 46:bebbbd80dd87 | 55 | static inline int ssp_disable(spi_t *obj); |
mbed_official | 46:bebbbd80dd87 | 56 | static inline int ssp_enable(spi_t *obj); |
mbed_official | 46:bebbbd80dd87 | 57 | |
mbed_official | 46:bebbbd80dd87 | 58 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { |
mbed_official | 46:bebbbd80dd87 | 59 | int spi_n = get_available_spi(); |
mbed_official | 46:bebbbd80dd87 | 60 | if (spi_n == -1) { |
mbed_official | 46:bebbbd80dd87 | 61 | error("No available SPI"); |
mbed_official | 46:bebbbd80dd87 | 62 | } |
mbed_official | 46:bebbbd80dd87 | 63 | obj->spi_n = spi_n; |
mbed_official | 46:bebbbd80dd87 | 64 | spi_used |= (1 << spi_n); |
mbed_official | 46:bebbbd80dd87 | 65 | |
mbed_official | 46:bebbbd80dd87 | 66 | obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE); |
mbed_official | 46:bebbbd80dd87 | 67 | |
mbed_official | 46:bebbbd80dd87 | 68 | const SWM_Map *swm; |
mbed_official | 46:bebbbd80dd87 | 69 | uint32_t regVal; |
mbed_official | 46:bebbbd80dd87 | 70 | |
mbed_official | 46:bebbbd80dd87 | 71 | swm = &SWM_SPI_SCLK[obj->spi_n]; |
mbed_official | 46:bebbbd80dd87 | 72 | regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 73 | LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 74 | |
mbed_official | 46:bebbbd80dd87 | 75 | swm = &SWM_SPI_MOSI[obj->spi_n]; |
mbed_official | 46:bebbbd80dd87 | 76 | regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 77 | LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 78 | |
mbed_official | 46:bebbbd80dd87 | 79 | swm = &SWM_SPI_MISO[obj->spi_n]; |
mbed_official | 46:bebbbd80dd87 | 80 | regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 81 | LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 82 | |
mbed_official | 46:bebbbd80dd87 | 83 | swm = &SWM_SPI_SSEL[obj->spi_n]; |
mbed_official | 46:bebbbd80dd87 | 84 | regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 85 | LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset); |
mbed_official | 46:bebbbd80dd87 | 86 | |
mbed_official | 46:bebbbd80dd87 | 87 | // clear interrupts |
mbed_official | 46:bebbbd80dd87 | 88 | obj->spi->INTENCLR = 0x3f; |
mbed_official | 46:bebbbd80dd87 | 89 | |
mbed_official | 46:bebbbd80dd87 | 90 | // enable power and clocking |
mbed_official | 46:bebbbd80dd87 | 91 | switch (obj->spi_n) { |
mbed_official | 46:bebbbd80dd87 | 92 | case 0: |
mbed_official | 46:bebbbd80dd87 | 93 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11); |
mbed_official | 46:bebbbd80dd87 | 94 | LPC_SYSCON->PRESETCTRL &= ~(0x1<<0); |
mbed_official | 46:bebbbd80dd87 | 95 | LPC_SYSCON->PRESETCTRL |= (0x1<<0); |
mbed_official | 46:bebbbd80dd87 | 96 | break; |
mbed_official | 46:bebbbd80dd87 | 97 | case 1: |
mbed_official | 46:bebbbd80dd87 | 98 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); |
mbed_official | 46:bebbbd80dd87 | 99 | LPC_SYSCON->PRESETCTRL &= ~(0x1<<1); |
mbed_official | 46:bebbbd80dd87 | 100 | LPC_SYSCON->PRESETCTRL |= (0x1<<1); |
mbed_official | 46:bebbbd80dd87 | 101 | break; |
mbed_official | 46:bebbbd80dd87 | 102 | } |
mbed_official | 46:bebbbd80dd87 | 103 | |
mbed_official | 46:bebbbd80dd87 | 104 | // set default format and frequency |
mbed_official | 46:bebbbd80dd87 | 105 | if (ssel == NC) { |
mbed_official | 46:bebbbd80dd87 | 106 | spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master |
mbed_official | 46:bebbbd80dd87 | 107 | } else { |
mbed_official | 46:bebbbd80dd87 | 108 | spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave |
mbed_official | 46:bebbbd80dd87 | 109 | } |
mbed_official | 46:bebbbd80dd87 | 110 | spi_frequency(obj, 1000000); |
mbed_official | 46:bebbbd80dd87 | 111 | |
mbed_official | 46:bebbbd80dd87 | 112 | // enable the ssp channel |
mbed_official | 46:bebbbd80dd87 | 113 | ssp_enable(obj); |
mbed_official | 46:bebbbd80dd87 | 114 | } |
mbed_official | 46:bebbbd80dd87 | 115 | |
mbed_official | 46:bebbbd80dd87 | 116 | void spi_free(spi_t *obj) {} |
mbed_official | 46:bebbbd80dd87 | 117 | |
mbed_official | 46:bebbbd80dd87 | 118 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
mbed_official | 227:7bd0639b8911 | 119 | MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); |
mbed_official | 46:bebbbd80dd87 | 120 | ssp_disable(obj); |
mbed_official | 46:bebbbd80dd87 | 121 | |
mbed_official | 46:bebbbd80dd87 | 122 | int polarity = (mode & 0x2) ? 1 : 0; |
mbed_official | 46:bebbbd80dd87 | 123 | int phase = (mode & 0x1) ? 1 : 0; |
mbed_official | 46:bebbbd80dd87 | 124 | |
mbed_official | 46:bebbbd80dd87 | 125 | // set it up |
mbed_official | 46:bebbbd80dd87 | 126 | int DSS = bits - 1; // DSS (data select size) |
mbed_official | 46:bebbbd80dd87 | 127 | int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity |
mbed_official | 46:bebbbd80dd87 | 128 | int SPH = (phase) ? 1 : 0; // SPH - clock out phase |
mbed_official | 46:bebbbd80dd87 | 129 | |
mbed_official | 46:bebbbd80dd87 | 130 | uint32_t tmp = obj->spi->CFG; |
mbed_official | 46:bebbbd80dd87 | 131 | tmp &= ~((1 << 2) | (1 << 4) | (1 << 5)); |
mbed_official | 46:bebbbd80dd87 | 132 | tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2); |
mbed_official | 46:bebbbd80dd87 | 133 | obj->spi->CFG = tmp; |
mbed_official | 46:bebbbd80dd87 | 134 | |
mbed_official | 46:bebbbd80dd87 | 135 | // select frame length |
mbed_official | 46:bebbbd80dd87 | 136 | tmp = obj->spi->TXDATCTL; |
mbed_official | 46:bebbbd80dd87 | 137 | tmp &= ~(0xf << 24); |
mbed_official | 46:bebbbd80dd87 | 138 | tmp |= (DSS << 24); |
mbed_official | 46:bebbbd80dd87 | 139 | obj->spi->TXDATCTL = tmp; |
mbed_official | 46:bebbbd80dd87 | 140 | |
mbed_official | 46:bebbbd80dd87 | 141 | ssp_enable(obj); |
mbed_official | 46:bebbbd80dd87 | 142 | } |
mbed_official | 46:bebbbd80dd87 | 143 | |
mbed_official | 46:bebbbd80dd87 | 144 | void spi_frequency(spi_t *obj, int hz) { |
mbed_official | 46:bebbbd80dd87 | 145 | ssp_disable(obj); |
mbed_official | 46:bebbbd80dd87 | 146 | |
mbed_official | 46:bebbbd80dd87 | 147 | uint32_t PCLK = SystemCoreClock; |
mbed_official | 46:bebbbd80dd87 | 148 | |
mbed_official | 46:bebbbd80dd87 | 149 | obj->spi->DIV = PCLK/hz - 1; |
mbed_official | 46:bebbbd80dd87 | 150 | obj->spi->DLY = 0; |
mbed_official | 46:bebbbd80dd87 | 151 | ssp_enable(obj); |
mbed_official | 46:bebbbd80dd87 | 152 | } |
mbed_official | 46:bebbbd80dd87 | 153 | |
mbed_official | 46:bebbbd80dd87 | 154 | static inline int ssp_disable(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 155 | return obj->spi->CFG &= ~(1 << 0); |
mbed_official | 46:bebbbd80dd87 | 156 | } |
mbed_official | 46:bebbbd80dd87 | 157 | |
mbed_official | 46:bebbbd80dd87 | 158 | static inline int ssp_enable(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 159 | return obj->spi->CFG |= (1 << 0); |
mbed_official | 46:bebbbd80dd87 | 160 | } |
mbed_official | 46:bebbbd80dd87 | 161 | |
mbed_official | 46:bebbbd80dd87 | 162 | static inline int ssp_readable(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 163 | return obj->spi->STAT & (1 << 0); |
mbed_official | 46:bebbbd80dd87 | 164 | } |
mbed_official | 46:bebbbd80dd87 | 165 | |
mbed_official | 46:bebbbd80dd87 | 166 | static inline int ssp_writeable(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 167 | return obj->spi->STAT & (1 << 1); |
mbed_official | 46:bebbbd80dd87 | 168 | } |
mbed_official | 46:bebbbd80dd87 | 169 | |
mbed_official | 46:bebbbd80dd87 | 170 | static inline void ssp_write(spi_t *obj, int value) { |
mbed_official | 46:bebbbd80dd87 | 171 | while (!ssp_writeable(obj)); |
mbed_official | 46:bebbbd80dd87 | 172 | // end of transfer |
mbed_official | 46:bebbbd80dd87 | 173 | obj->spi->TXDATCTL |= (1 << 20); |
mbed_official | 46:bebbbd80dd87 | 174 | obj->spi->TXDAT = value; |
mbed_official | 46:bebbbd80dd87 | 175 | } |
mbed_official | 46:bebbbd80dd87 | 176 | |
mbed_official | 46:bebbbd80dd87 | 177 | static inline int ssp_read(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 178 | while (!ssp_readable(obj)); |
mbed_official | 46:bebbbd80dd87 | 179 | return obj->spi->RXDAT; |
mbed_official | 46:bebbbd80dd87 | 180 | } |
mbed_official | 46:bebbbd80dd87 | 181 | |
mbed_official | 46:bebbbd80dd87 | 182 | static inline int ssp_busy(spi_t *obj) { |
mbed_official | 69:49e45cb70de1 | 183 | // checking RXOV(Receiver Overrun interrupt flag) |
mbed_official | 69:49e45cb70de1 | 184 | return obj->spi->STAT & (1 << 2); |
mbed_official | 69:49e45cb70de1 | 185 | } |
mbed_official | 46:bebbbd80dd87 | 186 | |
mbed_official | 46:bebbbd80dd87 | 187 | int spi_master_write(spi_t *obj, int value) { |
mbed_official | 46:bebbbd80dd87 | 188 | ssp_write(obj, value); |
mbed_official | 46:bebbbd80dd87 | 189 | return ssp_read(obj); |
mbed_official | 46:bebbbd80dd87 | 190 | } |
mbed_official | 46:bebbbd80dd87 | 191 | |
mbed_official | 46:bebbbd80dd87 | 192 | int spi_slave_receive(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 193 | return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); |
mbed_official | 81:a9456fdf72fa | 194 | } |
mbed_official | 46:bebbbd80dd87 | 195 | |
mbed_official | 46:bebbbd80dd87 | 196 | int spi_slave_read(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 197 | return obj->spi->RXDAT; |
mbed_official | 46:bebbbd80dd87 | 198 | } |
mbed_official | 46:bebbbd80dd87 | 199 | |
mbed_official | 46:bebbbd80dd87 | 200 | void spi_slave_write(spi_t *obj, int value) { |
mbed_official | 46:bebbbd80dd87 | 201 | while (ssp_writeable(obj) == 0) ; |
mbed_official | 46:bebbbd80dd87 | 202 | obj->spi->TXDAT = value; |
mbed_official | 46:bebbbd80dd87 | 203 | } |
mbed_official | 46:bebbbd80dd87 | 204 | |
mbed_official | 46:bebbbd80dd87 | 205 | int spi_busy(spi_t *obj) { |
mbed_official | 46:bebbbd80dd87 | 206 | return ssp_busy(obj); |
mbed_official | 46:bebbbd80dd87 | 207 | } |