mbed library sources, include can_api for nucleo-f091rc
Dependents: CanNucleoF0_example
Fork of mbed-src by
targets/hal/TARGET_NXP/TARGET_LPC43XX/gpio_irq_api.c@35:371630885ad6, 2013-10-21 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Oct 21 11:45:04 2013 +0100
- Revision:
- 35:371630885ad6
- Parent:
- 20:4263a77256ae
- Child:
- 250:a49055e7a707
Synchronized with git revision 38eb79e9cce7811dee9a4d2b30c4bba468323393
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bogdanm | 20:4263a77256ae | 1 | /* mbed Microcontroller Library |
bogdanm | 20:4263a77256ae | 2 | * Copyright (c) 2006-2013 ARM Limited |
bogdanm | 20:4263a77256ae | 3 | * |
bogdanm | 20:4263a77256ae | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 20:4263a77256ae | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 20:4263a77256ae | 6 | * You may obtain a copy of the License at |
bogdanm | 20:4263a77256ae | 7 | * |
bogdanm | 20:4263a77256ae | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 20:4263a77256ae | 9 | * |
bogdanm | 20:4263a77256ae | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 20:4263a77256ae | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 20:4263a77256ae | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 20:4263a77256ae | 13 | * See the License for the specific language governing permissions and |
bogdanm | 20:4263a77256ae | 14 | * limitations under the License. |
bogdanm | 20:4263a77256ae | 15 | * |
bogdanm | 20:4263a77256ae | 16 | * Ported to NXP LPC43XX by Micromint USA <support@micromint.com> |
bogdanm | 20:4263a77256ae | 17 | */ |
bogdanm | 20:4263a77256ae | 18 | #include <stddef.h> |
bogdanm | 20:4263a77256ae | 19 | #include "gpio_irq_api.h" |
bogdanm | 20:4263a77256ae | 20 | #include "error.h" |
bogdanm | 20:4263a77256ae | 21 | #include "cmsis.h" |
bogdanm | 20:4263a77256ae | 22 | |
bogdanm | 20:4263a77256ae | 23 | /* The LPC43xx implements GPIO pin and group interrupts. Any pin in the |
bogdanm | 20:4263a77256ae | 24 | * 8 32-bit GPIO ports can interrupt. On group interrupts a pin can |
bogdanm | 20:4263a77256ae | 25 | * only interrupt on the rising or falling edge, not both as required |
bogdanm | 20:4263a77256ae | 26 | * by mbed. Also, group interrupts can't be cleared individually. |
bogdanm | 20:4263a77256ae | 27 | * This implementation uses pin interrupts (8 on M4/M3, 1 on M0). |
bogdanm | 20:4263a77256ae | 28 | * A future implementation may provide group interrupt support. |
bogdanm | 20:4263a77256ae | 29 | */ |
bogdanm | 20:4263a77256ae | 30 | #if !defined(CORE_M0) |
bogdanm | 20:4263a77256ae | 31 | #define CHANNEL_NUM 8 |
bogdanm | 20:4263a77256ae | 32 | #else |
bogdanm | 20:4263a77256ae | 33 | #define CHANNEL_NUM 1 |
bogdanm | 20:4263a77256ae | 34 | #endif |
bogdanm | 20:4263a77256ae | 35 | |
bogdanm | 20:4263a77256ae | 36 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
bogdanm | 20:4263a77256ae | 37 | static uint32_t channel = 0; |
bogdanm | 20:4263a77256ae | 38 | static gpio_irq_handler irq_handler; |
bogdanm | 20:4263a77256ae | 39 | |
bogdanm | 20:4263a77256ae | 40 | static void handle_interrupt_in(void) { |
bogdanm | 20:4263a77256ae | 41 | uint32_t rise = LPC_GPIO_PIN_INT->RISE; |
bogdanm | 20:4263a77256ae | 42 | uint32_t fall = LPC_GPIO_PIN_INT->FALL; |
bogdanm | 20:4263a77256ae | 43 | uint32_t pmask; |
bogdanm | 20:4263a77256ae | 44 | int i; |
bogdanm | 20:4263a77256ae | 45 | |
bogdanm | 20:4263a77256ae | 46 | for (i = 0; i < CHANNEL_NUM; i++) { |
bogdanm | 20:4263a77256ae | 47 | pmask = (1 << i); |
bogdanm | 20:4263a77256ae | 48 | if (rise & pmask) { |
bogdanm | 20:4263a77256ae | 49 | /* Rising edge interrupts */ |
bogdanm | 20:4263a77256ae | 50 | if (channel_ids[i] != 0) |
bogdanm | 20:4263a77256ae | 51 | irq_handler(channel_ids[i], IRQ_RISE); |
bogdanm | 20:4263a77256ae | 52 | /* Clear rising edge detected */ |
bogdanm | 20:4263a77256ae | 53 | LPC_GPIO_PIN_INT->RISE = pmask; |
bogdanm | 20:4263a77256ae | 54 | } |
bogdanm | 20:4263a77256ae | 55 | if (fall & pmask) { |
bogdanm | 20:4263a77256ae | 56 | /* Falling edge interrupts */ |
bogdanm | 20:4263a77256ae | 57 | if (channel_ids[i] != 0) |
bogdanm | 20:4263a77256ae | 58 | irq_handler(channel_ids[i], IRQ_FALL); |
bogdanm | 20:4263a77256ae | 59 | /* Clear falling edge detected */ |
bogdanm | 20:4263a77256ae | 60 | LPC_GPIO_PIN_INT->FALL = pmask; |
bogdanm | 20:4263a77256ae | 61 | } |
bogdanm | 20:4263a77256ae | 62 | } |
bogdanm | 20:4263a77256ae | 63 | } |
bogdanm | 20:4263a77256ae | 64 | |
bogdanm | 20:4263a77256ae | 65 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
bogdanm | 20:4263a77256ae | 66 | uint32_t portnum, pinnum; //, pmask; |
bogdanm | 20:4263a77256ae | 67 | |
bogdanm | 20:4263a77256ae | 68 | if (pin == NC) return -1; |
bogdanm | 20:4263a77256ae | 69 | |
bogdanm | 20:4263a77256ae | 70 | irq_handler = handler; |
bogdanm | 20:4263a77256ae | 71 | |
bogdanm | 20:4263a77256ae | 72 | /* Set port and pin numbers */ |
bogdanm | 20:4263a77256ae | 73 | obj->port = portnum = MBED_GPIO_PORT(pin); |
bogdanm | 20:4263a77256ae | 74 | obj->pin = pinnum = MBED_GPIO_PIN(pin); |
bogdanm | 20:4263a77256ae | 75 | |
bogdanm | 20:4263a77256ae | 76 | /* Add to channel table */ |
bogdanm | 20:4263a77256ae | 77 | channel_ids[channel] = id; |
bogdanm | 20:4263a77256ae | 78 | obj->ch = channel; |
bogdanm | 20:4263a77256ae | 79 | |
bogdanm | 20:4263a77256ae | 80 | /* Clear rising and falling edge detection */ |
bogdanm | 20:4263a77256ae | 81 | //pmask = (1 << channel); |
bogdanm | 20:4263a77256ae | 82 | //LPC_GPIO_PIN_INT->IST = pmask; |
bogdanm | 20:4263a77256ae | 83 | |
bogdanm | 20:4263a77256ae | 84 | /* Set SCU */ |
bogdanm | 20:4263a77256ae | 85 | if (channel < 4) { |
bogdanm | 20:4263a77256ae | 86 | LPC_SCU->PINTSEL0 &= ~(0xFF << (portnum << 3)); |
bogdanm | 20:4263a77256ae | 87 | LPC_SCU->PINTSEL0 |= (((portnum << 5) | pinnum) << (channel << 3)); |
bogdanm | 20:4263a77256ae | 88 | } else { |
bogdanm | 20:4263a77256ae | 89 | LPC_SCU->PINTSEL1 &= ~(0xFF << ((portnum - 4) << 3)); |
bogdanm | 20:4263a77256ae | 90 | LPC_SCU->PINTSEL1 |= (((portnum << 5) | pinnum) << ((channel - 4) << 3)); |
bogdanm | 20:4263a77256ae | 91 | } |
bogdanm | 20:4263a77256ae | 92 | |
bogdanm | 20:4263a77256ae | 93 | #if !defined(CORE_M0) |
bogdanm | 20:4263a77256ae | 94 | NVIC_SetVector((IRQn_Type)(PIN_INT0_IRQn + channel), (uint32_t)handle_interrupt_in); |
bogdanm | 20:4263a77256ae | 95 | NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + channel)); |
bogdanm | 20:4263a77256ae | 96 | #else |
bogdanm | 20:4263a77256ae | 97 | NVIC_SetVector((IRQn_Type)PIN_INT4_IRQn, (uint32_t)handle_interrupt_in); |
bogdanm | 20:4263a77256ae | 98 | NVIC_EnableIRQ((IRQn_Type)PIN_INT4_IRQn); |
bogdanm | 20:4263a77256ae | 99 | #endif |
bogdanm | 20:4263a77256ae | 100 | |
bogdanm | 20:4263a77256ae | 101 | // Increment channel number |
bogdanm | 20:4263a77256ae | 102 | channel++; |
bogdanm | 20:4263a77256ae | 103 | channel %= CHANNEL_NUM; |
bogdanm | 20:4263a77256ae | 104 | |
bogdanm | 20:4263a77256ae | 105 | return 0; |
bogdanm | 20:4263a77256ae | 106 | } |
bogdanm | 20:4263a77256ae | 107 | |
bogdanm | 20:4263a77256ae | 108 | void gpio_irq_free(gpio_irq_t *obj) { |
bogdanm | 20:4263a77256ae | 109 | channel_ids[obj->ch] = 0; |
bogdanm | 20:4263a77256ae | 110 | } |
bogdanm | 20:4263a77256ae | 111 | |
bogdanm | 20:4263a77256ae | 112 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
bogdanm | 20:4263a77256ae | 113 | uint32_t pmask; |
bogdanm | 20:4263a77256ae | 114 | |
bogdanm | 20:4263a77256ae | 115 | /* Clear pending interrupts */ |
bogdanm | 20:4263a77256ae | 116 | pmask = (1 << obj->ch); |
bogdanm | 20:4263a77256ae | 117 | LPC_GPIO_PIN_INT->IST = pmask; |
bogdanm | 20:4263a77256ae | 118 | |
bogdanm | 20:4263a77256ae | 119 | /* Configure pin interrupt */ |
bogdanm | 20:4263a77256ae | 120 | LPC_GPIO_PIN_INT->ISEL &= ~pmask; |
bogdanm | 20:4263a77256ae | 121 | if (event == IRQ_RISE) { |
bogdanm | 20:4263a77256ae | 122 | /* Rising edge interrupts */ |
bogdanm | 20:4263a77256ae | 123 | if (enable) { |
bogdanm | 20:4263a77256ae | 124 | LPC_GPIO_PIN_INT->SIENR |= pmask; |
bogdanm | 20:4263a77256ae | 125 | } else { |
bogdanm | 20:4263a77256ae | 126 | LPC_GPIO_PIN_INT->CIENR |= pmask; |
bogdanm | 20:4263a77256ae | 127 | } |
bogdanm | 20:4263a77256ae | 128 | } else { |
bogdanm | 20:4263a77256ae | 129 | /* Falling edge interrupts */ |
bogdanm | 20:4263a77256ae | 130 | if (enable) { |
bogdanm | 20:4263a77256ae | 131 | LPC_GPIO_PIN_INT->SIENF |= pmask; |
bogdanm | 20:4263a77256ae | 132 | } else { |
bogdanm | 20:4263a77256ae | 133 | LPC_GPIO_PIN_INT->CIENF |= pmask; |
bogdanm | 20:4263a77256ae | 134 | } |
bogdanm | 20:4263a77256ae | 135 | } |
bogdanm | 20:4263a77256ae | 136 | } |
mbed_official | 35:371630885ad6 | 137 | |
mbed_official | 35:371630885ad6 | 138 | void gpio_irq_enable(gpio_irq_t *obj) { |
mbed_official | 35:371630885ad6 | 139 | #if !defined(CORE_M0) |
mbed_official | 35:371630885ad6 | 140 | NVIC_EnableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch)); |
mbed_official | 35:371630885ad6 | 141 | #else |
mbed_official | 35:371630885ad6 | 142 | NVIC_EnableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch)); |
mbed_official | 35:371630885ad6 | 143 | #endif |
mbed_official | 35:371630885ad6 | 144 | } |
mbed_official | 35:371630885ad6 | 145 | |
mbed_official | 35:371630885ad6 | 146 | void gpio_irq_disable(gpio_irq_t *obj) { |
mbed_official | 35:371630885ad6 | 147 | #if !defined(CORE_M0) |
mbed_official | 35:371630885ad6 | 148 | NVIC_DisableIRQ((IRQn_Type)(PIN_INT0_IRQn + obj->ch)); |
mbed_official | 35:371630885ad6 | 149 | #else |
mbed_official | 35:371630885ad6 | 150 | NVIC_DisableIRQ((IRQn_Type)(PIN_INT4_IRQn + obj->ch)); |
mbed_official | 35:371630885ad6 | 151 | #endif |
mbed_official | 35:371630885ad6 | 152 | } |