Diff: targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c

Revision:

417:39e86d6263aa

Parent:

390:35c2c1cf29cd

Child:

441:d2c15dda23c1

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c	Tue Nov 25 11:45:06 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c	Wed Nov 26 08:00:09 2014 +0000
@@ -160,12 +160,12 @@
     GPIOPFCE1   |=  0x4000;
     GPIOPFC1    |=  0x4000;
 
-    /* P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
-    GPIOPMC3    |=  0x0078;
-    GPIOPFCAE3  &= ~0x0078;
-    GPIOPFCE3   &= ~0x0078;
-    GPIOPFC3    |=  0x0078;
-    GPIOPIPC3   |=  0x0078;
+    /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
+    GPIOPMC3    |=  0x0079;
+    GPIOPFCAE3  &= ~0x0079;
+    GPIOPFCE3   &= ~0x0079;
+    GPIOPFC3    |=  0x0079;
+    GPIOPIPC3   |=  0x0079;
 
     /* P5_9(ET_MDC) */
     GPIOPMC5    |=  0x0200;
@@ -174,13 +174,13 @@
     GPIOPFC5    |=  0x0200;
     GPIOPIPC5   |=  0x0200;
 
-    /* P10_0(ET_TXCLK), P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
+    /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
     /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
-    GPIOPMC10   |=  0x0FFF;
-    GPIOPFCAE10 &= ~0x0FFF;
-    GPIOPFCE10  |=  0x0FFF;
-    GPIOPFC10   |=  0x0FFF;
-    GPIOPIPC10  |=  0x0FFF;
+    GPIOPMC10   |=  0x0FFE;
+    GPIOPFCAE10 &= ~0x0FFE;
+    GPIOPFCE10  |=  0x0FFE;
+    GPIOPFC10   |=  0x0FFE;
+    GPIOPIPC10  |=  0x0FFE;
 
     /* Resets the E-MAC,E-DMAC */
     lan_reg_reset();
@@ -446,8 +446,7 @@
     ethernetext_set_link_mode(link);
 }
 
-void INT_Ether(void)
-{
+void INT_Ether(void) {
     uint32_t stat_edmac;
     uint32_t stat_etherc;