Paul Paterson / mbed-src-CanNucleoF0

mbed library sources, include can_api for nucleo-f091rc

Dependents:   CanNucleoF0_example

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c@445:3312ed629f01, 2015-01-15 (annotated)

Committer:
mbed_official
Date:
Thu Jan 15 19:30:07 2015 +0000
Revision:
445:3312ed629f01
Synchronized with git revision e21c65041d9a718f866ed6438e5791b13f9c6d91



Full URL: https://github.com/mbedmicro/mbed/commit/e21c65041d9a718f866ed6438e5791b13f9c6d91/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 445:3312ed629f01 1 /*
mbed_official 445:3312ed629f01 2 ** ###################################################################
mbed_official 445:3312ed629f01 3 ** Compilers: ARM Compiler
mbed_official 445:3312ed629f01 4 ** Freescale C/C++ for Embedded ARM
mbed_official 445:3312ed629f01 5 ** GNU C Compiler
mbed_official 445:3312ed629f01 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 445:3312ed629f01 7 **
mbed_official 445:3312ed629f01 8 ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
mbed_official 445:3312ed629f01 9 ** K20P32M50SF0RM Rev. 1, Oct 2011
mbed_official 445:3312ed629f01 10 ** K20P48M50SF0RM Rev. 1, Oct 2011
mbed_official 445:3312ed629f01 11 **
mbed_official 445:3312ed629f01 12 ** Version: rev. 1.0, 2011-12-15
mbed_official 445:3312ed629f01 13 **
mbed_official 445:3312ed629f01 14 ** Abstract:
mbed_official 445:3312ed629f01 15 ** Provides a system configuration function and a global variable that
mbed_official 445:3312ed629f01 16 ** contains the system frequency. It configures the device and initializes
mbed_official 445:3312ed629f01 17 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 445:3312ed629f01 18 **
mbed_official 445:3312ed629f01 19 ** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
mbed_official 445:3312ed629f01 20 **
mbed_official 445:3312ed629f01 21 ** http: www.freescale.com
mbed_official 445:3312ed629f01 22 ** mail: support@freescale.com
mbed_official 445:3312ed629f01 23 **
mbed_official 445:3312ed629f01 24 ** Revisions:
mbed_official 445:3312ed629f01 25 ** - rev. 1.0 (2011-12-15)
mbed_official 445:3312ed629f01 26 ** Initial version
mbed_official 445:3312ed629f01 27 **
mbed_official 445:3312ed629f01 28 ** ###################################################################
mbed_official 445:3312ed629f01 29 */
mbed_official 445:3312ed629f01 30
mbed_official 445:3312ed629f01 31 /**
mbed_official 445:3312ed629f01 32 * @file MK20D5
mbed_official 445:3312ed629f01 33 * @version 1.0
mbed_official 445:3312ed629f01 34 * @date 2011-12-15
mbed_official 445:3312ed629f01 35 * @brief Device specific configuration file for MK20D5 (implementation file)
mbed_official 445:3312ed629f01 36 *
mbed_official 445:3312ed629f01 37 * Provides a system configuration function and a global variable that contains
mbed_official 445:3312ed629f01 38 * the system frequency. It configures the device and initializes the oscillator
mbed_official 445:3312ed629f01 39 * (PLL) that is part of the microcontroller device.
mbed_official 445:3312ed629f01 40 */
mbed_official 445:3312ed629f01 41
mbed_official 445:3312ed629f01 42 #include <stdint.h>
mbed_official 445:3312ed629f01 43 #include "MK20D5.h"
mbed_official 445:3312ed629f01 44
mbed_official 445:3312ed629f01 45 #define DISABLE_WDOG 1
mbed_official 445:3312ed629f01 46
mbed_official 445:3312ed629f01 47 #define CLOCK_SETUP 1
mbed_official 445:3312ed629f01 48 /* Predefined clock setups
mbed_official 445:3312ed629f01 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
mbed_official 445:3312ed629f01 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
mbed_official 445:3312ed629f01 51 Core clock = 41.94MHz, BusClock = 41.94MHz
mbed_official 445:3312ed629f01 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
mbed_official 445:3312ed629f01 53 Reference clock source for MCG module is an external crystal 8MHz
mbed_official 445:3312ed629f01 54 Core clock = 48MHz, BusClock = 48MHz
mbed_official 445:3312ed629f01 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
mbed_official 445:3312ed629f01 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
mbed_official 445:3312ed629f01 57 Core clock = 8MHz, BusClock = 8MHz
mbed_official 445:3312ed629f01 58 */
mbed_official 445:3312ed629f01 59
mbed_official 445:3312ed629f01 60 /*----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 61 Define clock source values
mbed_official 445:3312ed629f01 62 *----------------------------------------------------------------------------*/
mbed_official 445:3312ed629f01 63 #if (CLOCK_SETUP == 0)
mbed_official 445:3312ed629f01 64 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 65 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 66 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 67 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 68 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
mbed_official 445:3312ed629f01 69 #elif (CLOCK_SETUP == 1)
mbed_official 445:3312ed629f01 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 71 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 72 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 73 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 74 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
mbed_official 445:3312ed629f01 75 #elif (CLOCK_SETUP == 2)
mbed_official 445:3312ed629f01 76 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 77 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 78 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 79 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 445:3312ed629f01 80 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
mbed_official 445:3312ed629f01 81 #endif /* (CLOCK_SETUP == 2) */
mbed_official 445:3312ed629f01 82
mbed_official 445:3312ed629f01 83
mbed_official 445:3312ed629f01 84 /* ----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 85 -- Core clock
mbed_official 445:3312ed629f01 86 ---------------------------------------------------------------------------- */
mbed_official 445:3312ed629f01 87
mbed_official 445:3312ed629f01 88 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 445:3312ed629f01 89
mbed_official 445:3312ed629f01 90 /* ----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 91 -- SystemInit()
mbed_official 445:3312ed629f01 92 ---------------------------------------------------------------------------- */
mbed_official 445:3312ed629f01 93
mbed_official 445:3312ed629f01 94 void SystemInit (void) {
mbed_official 445:3312ed629f01 95 #if (DISABLE_WDOG)
mbed_official 445:3312ed629f01 96 /* Disable the WDOG module */
mbed_official 445:3312ed629f01 97 /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
mbed_official 445:3312ed629f01 98 WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
mbed_official 445:3312ed629f01 99 /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
mbed_official 445:3312ed629f01 100 WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
mbed_official 445:3312ed629f01 101 /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
mbed_official 445:3312ed629f01 102 WDOG->STCTRLH = (uint16_t)0x01D2u;
mbed_official 445:3312ed629f01 103 #endif /* (DISABLE_WDOG) */
mbed_official 445:3312ed629f01 104 #if (CLOCK_SETUP == 0)
mbed_official 445:3312ed629f01 105 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 445:3312ed629f01 106 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
mbed_official 445:3312ed629f01 107 /* Switch to FEI Mode */
mbed_official 445:3312ed629f01 108 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 445:3312ed629f01 109 MCG->C1 = (uint8_t)0x06u;
mbed_official 445:3312ed629f01 110 /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
mbed_official 445:3312ed629f01 111 MCG->C2 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 112 /* MCG_C4: DMX32=0,DRST_DRS=1 */
mbed_official 445:3312ed629f01 113 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
mbed_official 445:3312ed629f01 114 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
mbed_official 445:3312ed629f01 115 MCG->C5 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 116 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 117 MCG->C6 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 118 while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
mbed_official 445:3312ed629f01 119 }
mbed_official 445:3312ed629f01 120 while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
mbed_official 445:3312ed629f01 121 }
mbed_official 445:3312ed629f01 122 #elif (CLOCK_SETUP == 1)
mbed_official 445:3312ed629f01 123 /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 445:3312ed629f01 124 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
mbed_official 445:3312ed629f01 125 /* Switch to FBE Mode */
mbed_official 445:3312ed629f01 126 /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 445:3312ed629f01 127 OSC0->CR = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 128 /* MCG->C7: OSCSEL=0 */
mbed_official 445:3312ed629f01 129 MCG->C7 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 130 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
mbed_official 445:3312ed629f01 131 MCG->C2 = (uint8_t)0x24u;
mbed_official 445:3312ed629f01 132 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 445:3312ed629f01 133 MCG->C1 = (uint8_t)0x9Au;
mbed_official 445:3312ed629f01 134 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 445:3312ed629f01 135 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
mbed_official 445:3312ed629f01 136 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
mbed_official 445:3312ed629f01 137 MCG->C5 = (uint8_t)0x03u;
mbed_official 445:3312ed629f01 138 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 139 MCG->C6 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 140 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
mbed_official 445:3312ed629f01 141 }
mbed_official 445:3312ed629f01 142 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
mbed_official 445:3312ed629f01 143 while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 445:3312ed629f01 144 }
mbed_official 445:3312ed629f01 145 #endif
mbed_official 445:3312ed629f01 146 while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
mbed_official 445:3312ed629f01 147 }
mbed_official 445:3312ed629f01 148 /* Switch to PBE Mode */
mbed_official 445:3312ed629f01 149 /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
mbed_official 445:3312ed629f01 150 MCG->C5 = (uint8_t)0x03u;
mbed_official 445:3312ed629f01 151 /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 152 MCG->C6 = (uint8_t)0x40u;
mbed_official 445:3312ed629f01 153 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
mbed_official 445:3312ed629f01 154 }
mbed_official 445:3312ed629f01 155 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
mbed_official 445:3312ed629f01 156 }
mbed_official 445:3312ed629f01 157 /* Switch to PEE Mode */
mbed_official 445:3312ed629f01 158 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 445:3312ed629f01 159 MCG->C1 = (uint8_t)0x1Au;
mbed_official 445:3312ed629f01 160 while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
mbed_official 445:3312ed629f01 161 }
mbed_official 445:3312ed629f01 162 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
mbed_official 445:3312ed629f01 163 }
mbed_official 445:3312ed629f01 164 #elif (CLOCK_SETUP == 2)
mbed_official 445:3312ed629f01 165 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
mbed_official 445:3312ed629f01 166 SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
mbed_official 445:3312ed629f01 167 /* Switch to FBE Mode */
mbed_official 445:3312ed629f01 168 /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 445:3312ed629f01 169 OSC0->CR = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 170 /* MCG->C7: OSCSEL=0 */
mbed_official 445:3312ed629f01 171 MCG->C7 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 172 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
mbed_official 445:3312ed629f01 173 MCG->C2 = (uint8_t)0x24u;
mbed_official 445:3312ed629f01 174 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 445:3312ed629f01 175 MCG->C1 = (uint8_t)0x9Au;
mbed_official 445:3312ed629f01 176 /* MCG->C4: DMX32=0,DRST_DRS=0 */
mbed_official 445:3312ed629f01 177 MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
mbed_official 445:3312ed629f01 178 /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
mbed_official 445:3312ed629f01 179 MCG->C5 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 180 /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
mbed_official 445:3312ed629f01 181 MCG->C6 = (uint8_t)0x00u;
mbed_official 445:3312ed629f01 182 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
mbed_official 445:3312ed629f01 183 }
mbed_official 445:3312ed629f01 184 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
mbed_official 445:3312ed629f01 185 while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
mbed_official 445:3312ed629f01 186 }
mbed_official 445:3312ed629f01 187 #endif
mbed_official 445:3312ed629f01 188 while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
mbed_official 445:3312ed629f01 189 }
mbed_official 445:3312ed629f01 190 /* Switch to BLPE Mode */
mbed_official 445:3312ed629f01 191 /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
mbed_official 445:3312ed629f01 192 MCG->C2 = (uint8_t)0x24u;
mbed_official 445:3312ed629f01 193 #endif /* (CLOCK_SETUP == 2) */
mbed_official 445:3312ed629f01 194 }
mbed_official 445:3312ed629f01 195
mbed_official 445:3312ed629f01 196 /* ----------------------------------------------------------------------------
mbed_official 445:3312ed629f01 197 -- SystemCoreClockUpdate()
mbed_official 445:3312ed629f01 198 ---------------------------------------------------------------------------- */
mbed_official 445:3312ed629f01 199
mbed_official 445:3312ed629f01 200 void SystemCoreClockUpdate (void) {
mbed_official 445:3312ed629f01 201 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 445:3312ed629f01 202 uint8_t Divider;
mbed_official 445:3312ed629f01 203
mbed_official 445:3312ed629f01 204 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 205 /* Output of FLL or PLL is selected */
mbed_official 445:3312ed629f01 206 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 207 /* FLL is selected */
mbed_official 445:3312ed629f01 208 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 209 /* External reference clock is selected */
mbed_official 445:3312ed629f01 210 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 211 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 445:3312ed629f01 212 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 213 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 445:3312ed629f01 214 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 215 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 445:3312ed629f01 216 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 445:3312ed629f01 217 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
mbed_official 445:3312ed629f01 218 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
mbed_official 445:3312ed629f01 219 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
mbed_official 445:3312ed629f01 220 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 221 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 445:3312ed629f01 222 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 223 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 445:3312ed629f01 224 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 445:3312ed629f01 225 case 0x0u:
mbed_official 445:3312ed629f01 226 MCGOUTClock *= 640u;
mbed_official 445:3312ed629f01 227 break;
mbed_official 445:3312ed629f01 228 case 0x20u:
mbed_official 445:3312ed629f01 229 MCGOUTClock *= 1280u;
mbed_official 445:3312ed629f01 230 break;
mbed_official 445:3312ed629f01 231 case 0x40u:
mbed_official 445:3312ed629f01 232 MCGOUTClock *= 1920u;
mbed_official 445:3312ed629f01 233 break;
mbed_official 445:3312ed629f01 234 case 0x60u:
mbed_official 445:3312ed629f01 235 MCGOUTClock *= 2560u;
mbed_official 445:3312ed629f01 236 break;
mbed_official 445:3312ed629f01 237 case 0x80u:
mbed_official 445:3312ed629f01 238 MCGOUTClock *= 732u;
mbed_official 445:3312ed629f01 239 break;
mbed_official 445:3312ed629f01 240 case 0xA0u:
mbed_official 445:3312ed629f01 241 MCGOUTClock *= 1464u;
mbed_official 445:3312ed629f01 242 break;
mbed_official 445:3312ed629f01 243 case 0xC0u:
mbed_official 445:3312ed629f01 244 MCGOUTClock *= 2197u;
mbed_official 445:3312ed629f01 245 break;
mbed_official 445:3312ed629f01 246 case 0xE0u:
mbed_official 445:3312ed629f01 247 MCGOUTClock *= 2929u;
mbed_official 445:3312ed629f01 248 break;
mbed_official 445:3312ed629f01 249 default:
mbed_official 445:3312ed629f01 250 break;
mbed_official 445:3312ed629f01 251 }
mbed_official 445:3312ed629f01 252 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 253 /* PLL is selected */
mbed_official 445:3312ed629f01 254 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 445:3312ed629f01 255 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 445:3312ed629f01 256 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 445:3312ed629f01 257 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 445:3312ed629f01 258 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 259 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
mbed_official 445:3312ed629f01 260 /* Internal reference clock is selected */
mbed_official 445:3312ed629f01 261 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 262 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 445:3312ed629f01 263 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 264 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
mbed_official 445:3312ed629f01 265 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 266 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
mbed_official 445:3312ed629f01 267 /* External reference clock is selected */
mbed_official 445:3312ed629f01 268 if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
mbed_official 445:3312ed629f01 269 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 445:3312ed629f01 270 } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 271 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 445:3312ed629f01 272 } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
mbed_official 445:3312ed629f01 273 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 445:3312ed629f01 274 /* Reserved value */
mbed_official 445:3312ed629f01 275 return;
mbed_official 445:3312ed629f01 276 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
mbed_official 445:3312ed629f01 277 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 445:3312ed629f01 278 }