mbed library sources, include can_api for nucleo-f091rc
Dependents: CanNucleoF0_example
Fork of mbed-src by
targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c@645:13c87cbecd54, 2016-01-07 (annotated)
- Committer:
- ptpaterson
- Date:
- Thu Jan 07 05:49:05 2016 +0000
- Revision:
- 645:13c87cbecd54
- Parent:
- 482:d9a48e768ce0
corrected freeze on CAN_RECEIVE_IT
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 390:35c2c1cf29cd | 1 | /* mbed Microcontroller Library |
mbed_official | 390:35c2c1cf29cd | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 390:35c2c1cf29cd | 3 | * |
mbed_official | 390:35c2c1cf29cd | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 390:35c2c1cf29cd | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 390:35c2c1cf29cd | 6 | * You may obtain a copy of the License at |
mbed_official | 390:35c2c1cf29cd | 7 | * |
mbed_official | 390:35c2c1cf29cd | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 390:35c2c1cf29cd | 9 | * |
mbed_official | 390:35c2c1cf29cd | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 390:35c2c1cf29cd | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 390:35c2c1cf29cd | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 390:35c2c1cf29cd | 13 | * See the License for the specific language governing permissions and |
mbed_official | 390:35c2c1cf29cd | 14 | * limitations under the License. |
mbed_official | 390:35c2c1cf29cd | 15 | */ |
mbed_official | 390:35c2c1cf29cd | 16 | #include <string.h> |
mbed_official | 390:35c2c1cf29cd | 17 | #include "ethernet_api.h" |
mbed_official | 390:35c2c1cf29cd | 18 | #include "cmsis.h" |
mbed_official | 390:35c2c1cf29cd | 19 | #include "mbed_interface.h" |
mbed_official | 390:35c2c1cf29cd | 20 | #include "toolchain.h" |
mbed_official | 390:35c2c1cf29cd | 21 | #include "mbed_error.h" |
mbed_official | 390:35c2c1cf29cd | 22 | #include "ether_iodefine.h" |
mbed_official | 390:35c2c1cf29cd | 23 | #include "ethernetext_api.h" |
mbed_official | 390:35c2c1cf29cd | 24 | |
mbed_official | 390:35c2c1cf29cd | 25 | /* Descriptor info */ |
mbed_official | 390:35c2c1cf29cd | 26 | #define NUM_OF_TX_DESCRIPTOR (16) |
mbed_official | 390:35c2c1cf29cd | 27 | #define NUM_OF_RX_DESCRIPTOR (16) |
mbed_official | 390:35c2c1cf29cd | 28 | #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ |
mbed_official | 390:35c2c1cf29cd | 29 | #define MAX_SEND_SIZE (1514) |
mbed_official | 390:35c2c1cf29cd | 30 | /* Ethernet Descriptor Value Define */ |
mbed_official | 390:35c2c1cf29cd | 31 | #define TD0_TFP_TOP_BOTTOM (0x30000000) |
mbed_official | 390:35c2c1cf29cd | 32 | #define TD0_TACT (0x80000000) |
mbed_official | 390:35c2c1cf29cd | 33 | #define TD0_TDLE (0x40000000) |
mbed_official | 390:35c2c1cf29cd | 34 | #define RD0_RACT (0x80000000) |
mbed_official | 390:35c2c1cf29cd | 35 | #define RD0_RDLE (0x40000000) |
mbed_official | 390:35c2c1cf29cd | 36 | #define RD0_RFE (0x08000000) |
mbed_official | 390:35c2c1cf29cd | 37 | #define RD0_RCSE (0x04000000) |
mbed_official | 390:35c2c1cf29cd | 38 | #define RD0_RFS (0x03FF0000) |
mbed_official | 390:35c2c1cf29cd | 39 | #define RD0_RCS (0x0000FFFF) |
mbed_official | 390:35c2c1cf29cd | 40 | #define RD0_RFS_RFOF (0x02000000) |
mbed_official | 390:35c2c1cf29cd | 41 | #define RD0_RFS_RUAF (0x00400000) |
mbed_official | 390:35c2c1cf29cd | 42 | #define RD0_RFS_RRF (0x00100000) |
mbed_official | 390:35c2c1cf29cd | 43 | #define RD0_RFS_RTLF (0x00080000) |
mbed_official | 390:35c2c1cf29cd | 44 | #define RD0_RFS_RTSF (0x00040000) |
mbed_official | 390:35c2c1cf29cd | 45 | #define RD0_RFS_PRE (0x00020000) |
mbed_official | 390:35c2c1cf29cd | 46 | #define RD0_RFS_CERF (0x00010000) |
mbed_official | 390:35c2c1cf29cd | 47 | #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ |
mbed_official | 390:35c2c1cf29cd | 48 | RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) |
mbed_official | 390:35c2c1cf29cd | 49 | #define RD1_RDL_MSK (0x0000FFFF) |
mbed_official | 390:35c2c1cf29cd | 50 | /* PHY Register */ |
mbed_official | 390:35c2c1cf29cd | 51 | #define BASIC_MODE_CONTROL_REG (0) |
mbed_official | 390:35c2c1cf29cd | 52 | #define BASIC_MODE_STATUS_REG (1) |
mbed_official | 390:35c2c1cf29cd | 53 | #define PHY_IDENTIFIER1_REG (2) |
mbed_official | 390:35c2c1cf29cd | 54 | #define PHY_IDENTIFIER2_REG (3) |
mbed_official | 390:35c2c1cf29cd | 55 | #define PHY_SP_CTL_STS_REG (31) |
mbed_official | 390:35c2c1cf29cd | 56 | /* MII management interface access */ |
mbed_official | 390:35c2c1cf29cd | 57 | #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ |
mbed_official | 390:35c2c1cf29cd | 58 | #define PHY_ST (1) |
mbed_official | 390:35c2c1cf29cd | 59 | #define PHY_WRITE (1) |
mbed_official | 390:35c2c1cf29cd | 60 | #define PHY_READ (2) |
mbed_official | 390:35c2c1cf29cd | 61 | #define MDC_WAIT (6) /* 400ns/4 */ |
mbed_official | 390:35c2c1cf29cd | 62 | #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ |
mbed_official | 390:35c2c1cf29cd | 63 | #define BASIC_STS_MSK_AUTO_CMP (0x0010) /* Auto-Negotiate Complete */ |
mbed_official | 390:35c2c1cf29cd | 64 | #define M_PHY_ID (0xFFFFFFF0) |
mbed_official | 390:35c2c1cf29cd | 65 | #define PHY_ID_LAN8710A (0x0007C0F0) |
mbed_official | 390:35c2c1cf29cd | 66 | /* ETHERPIR0 */ |
mbed_official | 390:35c2c1cf29cd | 67 | #define PIR0_MDI (0x00000008) |
mbed_official | 390:35c2c1cf29cd | 68 | #define PIR0_MDO (0x00000004) |
mbed_official | 390:35c2c1cf29cd | 69 | #define PIR0_MMD (0x00000002) |
mbed_official | 390:35c2c1cf29cd | 70 | #define PIR0_MDC (0x00000001) |
mbed_official | 390:35c2c1cf29cd | 71 | #define PIR0_MDC_HIGH (0x00000001) |
mbed_official | 390:35c2c1cf29cd | 72 | #define PIR0_MDC_LOW (0x00000000) |
mbed_official | 390:35c2c1cf29cd | 73 | /* ETHEREDRRR0 */ |
mbed_official | 390:35c2c1cf29cd | 74 | #define EDRRR0_RR (0x00000001) |
mbed_official | 390:35c2c1cf29cd | 75 | /* ETHEREDTRR0 */ |
mbed_official | 390:35c2c1cf29cd | 76 | #define EDTRR0_TR (0x00000003) |
mbed_official | 390:35c2c1cf29cd | 77 | /* software wait */ |
mbed_official | 390:35c2c1cf29cd | 78 | #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ |
mbed_official | 390:35c2c1cf29cd | 79 | |
mbed_official | 390:35c2c1cf29cd | 80 | #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ |
mbed_official | 390:35c2c1cf29cd | 81 | /* 0x00040000 : Detect frame reception */ |
mbed_official | 390:35c2c1cf29cd | 82 | /* 0x00010000 : Receive FIFO overflow */ |
mbed_official | 390:35c2c1cf29cd | 83 | /* 0x00000010 : Residual bit frame reception */ |
mbed_official | 390:35c2c1cf29cd | 84 | /* 0x00000008 : Long frame reception */ |
mbed_official | 390:35c2c1cf29cd | 85 | /* 0x00000004 : Short frame reception */ |
mbed_official | 390:35c2c1cf29cd | 86 | /* 0x00000002 : PHY-LSI reception error */ |
mbed_official | 390:35c2c1cf29cd | 87 | /* 0x00000001 : Receive frame CRC error */ |
mbed_official | 390:35c2c1cf29cd | 88 | #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ |
mbed_official | 390:35c2c1cf29cd | 89 | |
mbed_official | 390:35c2c1cf29cd | 90 | /* Send descriptor */ |
mbed_official | 390:35c2c1cf29cd | 91 | typedef struct tag_edmac_send_desc { |
mbed_official | 390:35c2c1cf29cd | 92 | uint32_t td0; |
mbed_official | 390:35c2c1cf29cd | 93 | uint32_t td1; |
mbed_official | 390:35c2c1cf29cd | 94 | uint8_t *td2; |
mbed_official | 390:35c2c1cf29cd | 95 | uint32_t padding4; |
mbed_official | 390:35c2c1cf29cd | 96 | } edmac_send_desc_t; |
mbed_official | 390:35c2c1cf29cd | 97 | |
mbed_official | 390:35c2c1cf29cd | 98 | /* Receive descriptor */ |
mbed_official | 390:35c2c1cf29cd | 99 | typedef struct tag_edmac_recv_desc { |
mbed_official | 390:35c2c1cf29cd | 100 | uint32_t rd0; |
mbed_official | 390:35c2c1cf29cd | 101 | uint32_t rd1; |
mbed_official | 390:35c2c1cf29cd | 102 | uint8_t *rd2; |
mbed_official | 390:35c2c1cf29cd | 103 | uint32_t padding4; |
mbed_official | 390:35c2c1cf29cd | 104 | } edmac_recv_desc_t; |
mbed_official | 390:35c2c1cf29cd | 105 | |
mbed_official | 390:35c2c1cf29cd | 106 | /* memory */ |
mbed_official | 390:35c2c1cf29cd | 107 | /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ |
mbed_official | 390:35c2c1cf29cd | 108 | /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ |
mbed_official | 390:35c2c1cf29cd | 109 | static uint8_t ehernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + |
mbed_official | 390:35c2c1cf29cd | 110 | (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + |
mbed_official | 390:35c2c1cf29cd | 111 | (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + |
mbed_official | 482:d9a48e768ce0 | 112 | (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] |
mbed_official | 482:d9a48e768ce0 | 113 | __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! |
mbed_official | 390:35c2c1cf29cd | 114 | static int32_t rx_read_offset; /* read offset */ |
mbed_official | 390:35c2c1cf29cd | 115 | static int32_t tx_wite_offset; /* write offset */ |
mbed_official | 390:35c2c1cf29cd | 116 | static uint32_t send_top_index; |
mbed_official | 390:35c2c1cf29cd | 117 | static uint32_t recv_top_index; |
mbed_official | 390:35c2c1cf29cd | 118 | static int32_t Interrupt_priority; |
mbed_official | 390:35c2c1cf29cd | 119 | static edmac_send_desc_t *p_eth_desc_dsend = NULL; |
mbed_official | 390:35c2c1cf29cd | 120 | static edmac_recv_desc_t *p_eth_desc_drecv = NULL; |
mbed_official | 390:35c2c1cf29cd | 121 | static edmac_recv_desc_t *p_recv_end_desc = NULL; |
mbed_official | 390:35c2c1cf29cd | 122 | static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; |
mbed_official | 390:35c2c1cf29cd | 123 | static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ |
mbed_official | 390:35c2c1cf29cd | 124 | static uint32_t phy_id = 0; |
mbed_official | 390:35c2c1cf29cd | 125 | static uint32_t start_stop = 1; /* 0:stop 1:start */ |
mbed_official | 390:35c2c1cf29cd | 126 | |
mbed_official | 390:35c2c1cf29cd | 127 | /* function */ |
mbed_official | 390:35c2c1cf29cd | 128 | static void lan_reg_reset(void); |
mbed_official | 390:35c2c1cf29cd | 129 | static void lan_desc_create(void); |
mbed_official | 390:35c2c1cf29cd | 130 | static void lan_reg_set(int32_t link); |
mbed_official | 390:35c2c1cf29cd | 131 | static uint16_t phy_reg_read(uint16_t reg_addr); |
mbed_official | 390:35c2c1cf29cd | 132 | static void phy_reg_write(uint16_t reg_addr, uint16_t data); |
mbed_official | 390:35c2c1cf29cd | 133 | static void mii_preamble(void); |
mbed_official | 390:35c2c1cf29cd | 134 | static void mii_cmd(uint16_t reg_addr, uint32_t option); |
mbed_official | 390:35c2c1cf29cd | 135 | static void mii_reg_read(uint16_t *data); |
mbed_official | 390:35c2c1cf29cd | 136 | static void mii_reg_write(uint16_t data); |
mbed_official | 390:35c2c1cf29cd | 137 | static void mii_z(void); |
mbed_official | 390:35c2c1cf29cd | 138 | static void mii_write_1(void); |
mbed_official | 390:35c2c1cf29cd | 139 | static void mii_write_0(void); |
mbed_official | 390:35c2c1cf29cd | 140 | static void set_ether_pir(uint32_t set_data); |
mbed_official | 390:35c2c1cf29cd | 141 | static void wait_100us(int32_t wait_cnt); |
mbed_official | 390:35c2c1cf29cd | 142 | |
mbed_official | 390:35c2c1cf29cd | 143 | |
mbed_official | 390:35c2c1cf29cd | 144 | int ethernetext_init(ethernet_cfg_t *p_ethcfg) { |
mbed_official | 390:35c2c1cf29cd | 145 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 146 | uint16_t val; |
mbed_official | 390:35c2c1cf29cd | 147 | |
mbed_official | 390:35c2c1cf29cd | 148 | CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ |
mbed_official | 390:35c2c1cf29cd | 149 | |
mbed_official | 390:35c2c1cf29cd | 150 | /* P4_2(PHY Reset) */ |
mbed_official | 390:35c2c1cf29cd | 151 | GPIOP4 &= ~0x0004; /* Outputs low level */ |
mbed_official | 390:35c2c1cf29cd | 152 | GPIOPMC4 &= ~0x0004; /* Port mode */ |
mbed_official | 390:35c2c1cf29cd | 153 | GPIOPM4 &= ~0x0004; /* Output mode */ |
mbed_official | 390:35c2c1cf29cd | 154 | |
mbed_official | 390:35c2c1cf29cd | 155 | /* GPIO P1 P1_14(ET_COL) */ |
mbed_official | 390:35c2c1cf29cd | 156 | GPIOPMC1 |= 0x4000; |
mbed_official | 390:35c2c1cf29cd | 157 | GPIOPFCAE1 &= ~0x4000; |
mbed_official | 390:35c2c1cf29cd | 158 | GPIOPFCE1 |= 0x4000; |
mbed_official | 390:35c2c1cf29cd | 159 | GPIOPFC1 |= 0x4000; |
mbed_official | 390:35c2c1cf29cd | 160 | |
mbed_official | 417:39e86d6263aa | 161 | /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ |
mbed_official | 417:39e86d6263aa | 162 | GPIOPMC3 |= 0x0079; |
mbed_official | 417:39e86d6263aa | 163 | GPIOPFCAE3 &= ~0x0079; |
mbed_official | 417:39e86d6263aa | 164 | GPIOPFCE3 &= ~0x0079; |
mbed_official | 417:39e86d6263aa | 165 | GPIOPFC3 |= 0x0079; |
mbed_official | 417:39e86d6263aa | 166 | GPIOPIPC3 |= 0x0079; |
mbed_official | 390:35c2c1cf29cd | 167 | |
mbed_official | 390:35c2c1cf29cd | 168 | /* P5_9(ET_MDC) */ |
mbed_official | 390:35c2c1cf29cd | 169 | GPIOPMC5 |= 0x0200; |
mbed_official | 390:35c2c1cf29cd | 170 | GPIOPFCAE5 &= ~0x0200; |
mbed_official | 390:35c2c1cf29cd | 171 | GPIOPFCE5 &= ~0x0200; |
mbed_official | 390:35c2c1cf29cd | 172 | GPIOPFC5 |= 0x0200; |
mbed_official | 390:35c2c1cf29cd | 173 | GPIOPIPC5 |= 0x0200; |
mbed_official | 390:35c2c1cf29cd | 174 | |
mbed_official | 417:39e86d6263aa | 175 | /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */ |
mbed_official | 390:35c2c1cf29cd | 176 | /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */ |
mbed_official | 417:39e86d6263aa | 177 | GPIOPMC10 |= 0x0FFE; |
mbed_official | 417:39e86d6263aa | 178 | GPIOPFCAE10 &= ~0x0FFE; |
mbed_official | 417:39e86d6263aa | 179 | GPIOPFCE10 |= 0x0FFE; |
mbed_official | 417:39e86d6263aa | 180 | GPIOPFC10 |= 0x0FFE; |
mbed_official | 417:39e86d6263aa | 181 | GPIOPIPC10 |= 0x0FFE; |
mbed_official | 390:35c2c1cf29cd | 182 | |
mbed_official | 390:35c2c1cf29cd | 183 | /* Resets the E-MAC,E-DMAC */ |
mbed_official | 390:35c2c1cf29cd | 184 | lan_reg_reset(); |
mbed_official | 390:35c2c1cf29cd | 185 | |
mbed_official | 390:35c2c1cf29cd | 186 | /* PHY Reset */ |
mbed_official | 390:35c2c1cf29cd | 187 | GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */ |
mbed_official | 390:35c2c1cf29cd | 188 | wait_100us(250); /* 25msec */ |
mbed_official | 390:35c2c1cf29cd | 189 | GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ |
mbed_official | 390:35c2c1cf29cd | 190 | wait_100us(100); /* 10msec */ |
mbed_official | 390:35c2c1cf29cd | 191 | |
mbed_official | 390:35c2c1cf29cd | 192 | /* Resets the PHY-LSI */ |
mbed_official | 390:35c2c1cf29cd | 193 | phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); |
mbed_official | 390:35c2c1cf29cd | 194 | for (i = 10000; i > 0; i--) { |
mbed_official | 390:35c2c1cf29cd | 195 | val = phy_reg_read(BASIC_MODE_CONTROL_REG); |
mbed_official | 390:35c2c1cf29cd | 196 | if (((uint32_t)val & 0x8000uL) == 0) { |
mbed_official | 390:35c2c1cf29cd | 197 | break; /* Reset complete */ |
mbed_official | 390:35c2c1cf29cd | 198 | } |
mbed_official | 390:35c2c1cf29cd | 199 | } |
mbed_official | 390:35c2c1cf29cd | 200 | |
mbed_official | 390:35c2c1cf29cd | 201 | phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) |
mbed_official | 390:35c2c1cf29cd | 202 | | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); |
mbed_official | 390:35c2c1cf29cd | 203 | |
mbed_official | 390:35c2c1cf29cd | 204 | Interrupt_priority = p_ethcfg->int_priority; |
mbed_official | 390:35c2c1cf29cd | 205 | p_recv_cb_fnc = p_ethcfg->recv_cb; |
mbed_official | 390:35c2c1cf29cd | 206 | start_stop = 1; |
mbed_official | 390:35c2c1cf29cd | 207 | |
mbed_official | 390:35c2c1cf29cd | 208 | if (p_ethcfg->ether_mac != NULL) { |
mbed_official | 390:35c2c1cf29cd | 209 | (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); |
mbed_official | 390:35c2c1cf29cd | 210 | } else { |
mbed_official | 390:35c2c1cf29cd | 211 | ethernet_address(mac_addr); /* Get MAC Address */ |
mbed_official | 390:35c2c1cf29cd | 212 | } |
mbed_official | 390:35c2c1cf29cd | 213 | |
mbed_official | 390:35c2c1cf29cd | 214 | return 0; |
mbed_official | 390:35c2c1cf29cd | 215 | } |
mbed_official | 390:35c2c1cf29cd | 216 | |
mbed_official | 390:35c2c1cf29cd | 217 | void ethernetext_start_stop(int32_t mode) { |
mbed_official | 390:35c2c1cf29cd | 218 | if (mode == 1) { |
mbed_official | 390:35c2c1cf29cd | 219 | /* start */ |
mbed_official | 390:35c2c1cf29cd | 220 | ETHEREDTRR0 |= EDTRR0_TR; |
mbed_official | 390:35c2c1cf29cd | 221 | ETHEREDRRR0 |= EDRRR0_RR; |
mbed_official | 390:35c2c1cf29cd | 222 | start_stop = 1; |
mbed_official | 390:35c2c1cf29cd | 223 | } else { |
mbed_official | 390:35c2c1cf29cd | 224 | /* stop */ |
mbed_official | 390:35c2c1cf29cd | 225 | ETHEREDTRR0 &= ~EDTRR0_TR; |
mbed_official | 390:35c2c1cf29cd | 226 | ETHEREDRRR0 &= ~EDRRR0_RR; |
mbed_official | 390:35c2c1cf29cd | 227 | start_stop = 0; |
mbed_official | 390:35c2c1cf29cd | 228 | } |
mbed_official | 390:35c2c1cf29cd | 229 | } |
mbed_official | 390:35c2c1cf29cd | 230 | |
mbed_official | 390:35c2c1cf29cd | 231 | int ethernetext_chk_link_mode(void) { |
mbed_official | 390:35c2c1cf29cd | 232 | int32_t link; |
mbed_official | 390:35c2c1cf29cd | 233 | uint16_t data; |
mbed_official | 390:35c2c1cf29cd | 234 | |
mbed_official | 390:35c2c1cf29cd | 235 | if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { |
mbed_official | 390:35c2c1cf29cd | 236 | data = phy_reg_read(PHY_SP_CTL_STS_REG); |
mbed_official | 390:35c2c1cf29cd | 237 | switch (((uint32_t)data >> 2) & 0x00000007) { |
mbed_official | 390:35c2c1cf29cd | 238 | case 0x0001: |
mbed_official | 390:35c2c1cf29cd | 239 | link = HALF_10M; |
mbed_official | 390:35c2c1cf29cd | 240 | break; |
mbed_official | 390:35c2c1cf29cd | 241 | case 0x0005: |
mbed_official | 390:35c2c1cf29cd | 242 | link = FULL_10M; |
mbed_official | 390:35c2c1cf29cd | 243 | break; |
mbed_official | 390:35c2c1cf29cd | 244 | case 0x0002: |
mbed_official | 390:35c2c1cf29cd | 245 | link = HALF_TX; |
mbed_official | 390:35c2c1cf29cd | 246 | break; |
mbed_official | 390:35c2c1cf29cd | 247 | case 0x0006: |
mbed_official | 390:35c2c1cf29cd | 248 | link = FULL_TX; |
mbed_official | 390:35c2c1cf29cd | 249 | break; |
mbed_official | 390:35c2c1cf29cd | 250 | default: |
mbed_official | 390:35c2c1cf29cd | 251 | link = NEGO_FAIL; |
mbed_official | 390:35c2c1cf29cd | 252 | break; |
mbed_official | 390:35c2c1cf29cd | 253 | } |
mbed_official | 390:35c2c1cf29cd | 254 | } else { |
mbed_official | 390:35c2c1cf29cd | 255 | link = NEGO_FAIL; |
mbed_official | 390:35c2c1cf29cd | 256 | } |
mbed_official | 390:35c2c1cf29cd | 257 | |
mbed_official | 390:35c2c1cf29cd | 258 | return link; |
mbed_official | 390:35c2c1cf29cd | 259 | } |
mbed_official | 390:35c2c1cf29cd | 260 | |
mbed_official | 390:35c2c1cf29cd | 261 | void ethernetext_set_link_mode(int32_t link) { |
mbed_official | 390:35c2c1cf29cd | 262 | lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ |
mbed_official | 390:35c2c1cf29cd | 263 | lan_desc_create(); /* Initialize of buffer memory */ |
mbed_official | 390:35c2c1cf29cd | 264 | lan_reg_set(link); /* E-DMAC, E-MAC initialization */ |
mbed_official | 390:35c2c1cf29cd | 265 | } |
mbed_official | 390:35c2c1cf29cd | 266 | |
mbed_official | 390:35c2c1cf29cd | 267 | int ethernet_init() { |
mbed_official | 390:35c2c1cf29cd | 268 | ethernet_cfg_t ethcfg; |
mbed_official | 390:35c2c1cf29cd | 269 | |
mbed_official | 441:d2c15dda23c1 | 270 | ethcfg.int_priority = 5; |
mbed_official | 390:35c2c1cf29cd | 271 | ethcfg.recv_cb = NULL; |
mbed_official | 390:35c2c1cf29cd | 272 | ethcfg.ether_mac = NULL; |
mbed_official | 390:35c2c1cf29cd | 273 | ethernetext_init(ðcfg); |
mbed_official | 390:35c2c1cf29cd | 274 | ethernet_set_link(-1, 0); /* Auto-Negotiation */ |
mbed_official | 390:35c2c1cf29cd | 275 | |
mbed_official | 390:35c2c1cf29cd | 276 | return 0; |
mbed_official | 390:35c2c1cf29cd | 277 | } |
mbed_official | 390:35c2c1cf29cd | 278 | |
mbed_official | 390:35c2c1cf29cd | 279 | void ethernet_free() { |
mbed_official | 390:35c2c1cf29cd | 280 | ETHERARSTR |= 0x00000001; /* ETHER software reset */ |
mbed_official | 390:35c2c1cf29cd | 281 | CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ |
mbed_official | 390:35c2c1cf29cd | 282 | } |
mbed_official | 390:35c2c1cf29cd | 283 | |
mbed_official | 390:35c2c1cf29cd | 284 | int ethernet_write(const char *data, int slen) { |
mbed_official | 390:35c2c1cf29cd | 285 | edmac_send_desc_t *p_send_desc; |
mbed_official | 390:35c2c1cf29cd | 286 | int32_t copy_size; |
mbed_official | 390:35c2c1cf29cd | 287 | |
mbed_official | 390:35c2c1cf29cd | 288 | if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) |
mbed_official | 390:35c2c1cf29cd | 289 | || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { |
mbed_official | 390:35c2c1cf29cd | 290 | copy_size = 0; |
mbed_official | 390:35c2c1cf29cd | 291 | } else { |
mbed_official | 390:35c2c1cf29cd | 292 | p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ |
mbed_official | 390:35c2c1cf29cd | 293 | if ((p_send_desc->td0 & TD0_TACT) != 0) { |
mbed_official | 390:35c2c1cf29cd | 294 | copy_size = 0; |
mbed_official | 390:35c2c1cf29cd | 295 | } else { |
mbed_official | 390:35c2c1cf29cd | 296 | copy_size = MAX_SEND_SIZE - tx_wite_offset; |
mbed_official | 390:35c2c1cf29cd | 297 | if (copy_size > slen) { |
mbed_official | 390:35c2c1cf29cd | 298 | copy_size = slen; |
mbed_official | 390:35c2c1cf29cd | 299 | } |
mbed_official | 390:35c2c1cf29cd | 300 | (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); |
mbed_official | 390:35c2c1cf29cd | 301 | tx_wite_offset += copy_size; |
mbed_official | 390:35c2c1cf29cd | 302 | } |
mbed_official | 390:35c2c1cf29cd | 303 | } |
mbed_official | 390:35c2c1cf29cd | 304 | |
mbed_official | 390:35c2c1cf29cd | 305 | return copy_size; |
mbed_official | 390:35c2c1cf29cd | 306 | } |
mbed_official | 390:35c2c1cf29cd | 307 | |
mbed_official | 390:35c2c1cf29cd | 308 | int ethernet_send() { |
mbed_official | 390:35c2c1cf29cd | 309 | edmac_send_desc_t *p_send_desc; |
mbed_official | 390:35c2c1cf29cd | 310 | int32_t ret; |
mbed_official | 390:35c2c1cf29cd | 311 | |
mbed_official | 390:35c2c1cf29cd | 312 | if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { |
mbed_official | 390:35c2c1cf29cd | 313 | ret = 0; |
mbed_official | 390:35c2c1cf29cd | 314 | } else { |
mbed_official | 390:35c2c1cf29cd | 315 | /* Transfer 1 frame */ |
mbed_official | 390:35c2c1cf29cd | 316 | p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ |
mbed_official | 390:35c2c1cf29cd | 317 | |
mbed_official | 390:35c2c1cf29cd | 318 | /* Sets the frame length */ |
mbed_official | 390:35c2c1cf29cd | 319 | p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); |
mbed_official | 390:35c2c1cf29cd | 320 | tx_wite_offset = 0; |
mbed_official | 390:35c2c1cf29cd | 321 | |
mbed_official | 390:35c2c1cf29cd | 322 | /* Sets the transmit descriptor to transmit again */ |
mbed_official | 390:35c2c1cf29cd | 323 | p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); |
mbed_official | 390:35c2c1cf29cd | 324 | p_send_desc->td0 |= TD0_TACT; |
mbed_official | 390:35c2c1cf29cd | 325 | if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { |
mbed_official | 390:35c2c1cf29cd | 326 | ETHEREDTRR0 |= EDTRR0_TR; |
mbed_official | 390:35c2c1cf29cd | 327 | } |
mbed_official | 390:35c2c1cf29cd | 328 | |
mbed_official | 390:35c2c1cf29cd | 329 | /* Update the current descriptor */ |
mbed_official | 390:35c2c1cf29cd | 330 | send_top_index++; |
mbed_official | 390:35c2c1cf29cd | 331 | if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { |
mbed_official | 390:35c2c1cf29cd | 332 | send_top_index = 0; |
mbed_official | 390:35c2c1cf29cd | 333 | } |
mbed_official | 390:35c2c1cf29cd | 334 | ret = 1; |
mbed_official | 390:35c2c1cf29cd | 335 | } |
mbed_official | 390:35c2c1cf29cd | 336 | |
mbed_official | 390:35c2c1cf29cd | 337 | return ret; |
mbed_official | 390:35c2c1cf29cd | 338 | } |
mbed_official | 390:35c2c1cf29cd | 339 | |
mbed_official | 390:35c2c1cf29cd | 340 | int ethernet_receive() { |
mbed_official | 390:35c2c1cf29cd | 341 | edmac_recv_desc_t *p_recv_desc; |
mbed_official | 390:35c2c1cf29cd | 342 | int32_t receive_size = 0; |
mbed_official | 390:35c2c1cf29cd | 343 | |
mbed_official | 390:35c2c1cf29cd | 344 | if (p_eth_desc_drecv != NULL) { |
mbed_official | 390:35c2c1cf29cd | 345 | if (p_recv_end_desc != NULL) { |
mbed_official | 390:35c2c1cf29cd | 346 | /* Sets the receive descriptor to receive again */ |
mbed_official | 390:35c2c1cf29cd | 347 | p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); |
mbed_official | 390:35c2c1cf29cd | 348 | p_recv_end_desc->rd0 |= RD0_RACT; |
mbed_official | 390:35c2c1cf29cd | 349 | if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { |
mbed_official | 390:35c2c1cf29cd | 350 | ETHEREDRRR0 |= EDRRR0_RR; |
mbed_official | 390:35c2c1cf29cd | 351 | } |
mbed_official | 390:35c2c1cf29cd | 352 | p_recv_end_desc = NULL; |
mbed_official | 390:35c2c1cf29cd | 353 | } |
mbed_official | 390:35c2c1cf29cd | 354 | |
mbed_official | 390:35c2c1cf29cd | 355 | p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ |
mbed_official | 390:35c2c1cf29cd | 356 | if ((p_recv_desc->rd0 & RD0_RACT) == 0) { |
mbed_official | 390:35c2c1cf29cd | 357 | /* Receives 1 frame */ |
mbed_official | 390:35c2c1cf29cd | 358 | if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { |
mbed_official | 390:35c2c1cf29cd | 359 | /* Receive frame error */ |
mbed_official | 390:35c2c1cf29cd | 360 | /* Sets the receive descriptor to receive again */ |
mbed_official | 390:35c2c1cf29cd | 361 | p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); |
mbed_official | 390:35c2c1cf29cd | 362 | p_recv_desc->rd0 |= RD0_RACT; |
mbed_official | 390:35c2c1cf29cd | 363 | if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { |
mbed_official | 390:35c2c1cf29cd | 364 | ETHEREDRRR0 |= EDRRR0_RR; |
mbed_official | 390:35c2c1cf29cd | 365 | } |
mbed_official | 390:35c2c1cf29cd | 366 | } else { |
mbed_official | 390:35c2c1cf29cd | 367 | /* Copies the received frame */ |
mbed_official | 390:35c2c1cf29cd | 368 | rx_read_offset = 0; |
mbed_official | 390:35c2c1cf29cd | 369 | p_recv_end_desc = p_recv_desc; |
mbed_official | 390:35c2c1cf29cd | 370 | receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ |
mbed_official | 390:35c2c1cf29cd | 371 | } |
mbed_official | 390:35c2c1cf29cd | 372 | |
mbed_official | 390:35c2c1cf29cd | 373 | /* Update the current descriptor */ |
mbed_official | 390:35c2c1cf29cd | 374 | recv_top_index++; |
mbed_official | 390:35c2c1cf29cd | 375 | if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { |
mbed_official | 390:35c2c1cf29cd | 376 | recv_top_index = 0; |
mbed_official | 390:35c2c1cf29cd | 377 | } |
mbed_official | 390:35c2c1cf29cd | 378 | } |
mbed_official | 390:35c2c1cf29cd | 379 | } |
mbed_official | 390:35c2c1cf29cd | 380 | |
mbed_official | 390:35c2c1cf29cd | 381 | return receive_size; |
mbed_official | 390:35c2c1cf29cd | 382 | } |
mbed_official | 390:35c2c1cf29cd | 383 | |
mbed_official | 390:35c2c1cf29cd | 384 | int ethernet_read(char *data, int dlen) { |
mbed_official | 390:35c2c1cf29cd | 385 | edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ |
mbed_official | 390:35c2c1cf29cd | 386 | int32_t copy_size; |
mbed_official | 390:35c2c1cf29cd | 387 | |
mbed_official | 390:35c2c1cf29cd | 388 | if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { |
mbed_official | 390:35c2c1cf29cd | 389 | copy_size = 0; |
mbed_official | 390:35c2c1cf29cd | 390 | } else { |
mbed_official | 390:35c2c1cf29cd | 391 | copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; |
mbed_official | 390:35c2c1cf29cd | 392 | if (copy_size > dlen) { |
mbed_official | 390:35c2c1cf29cd | 393 | copy_size = dlen; |
mbed_official | 390:35c2c1cf29cd | 394 | } |
mbed_official | 390:35c2c1cf29cd | 395 | (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); |
mbed_official | 390:35c2c1cf29cd | 396 | rx_read_offset += copy_size; |
mbed_official | 390:35c2c1cf29cd | 397 | } |
mbed_official | 390:35c2c1cf29cd | 398 | |
mbed_official | 390:35c2c1cf29cd | 399 | return copy_size; |
mbed_official | 390:35c2c1cf29cd | 400 | } |
mbed_official | 390:35c2c1cf29cd | 401 | |
mbed_official | 390:35c2c1cf29cd | 402 | void ethernet_address(char *mac) { |
mbed_official | 390:35c2c1cf29cd | 403 | if (mac != NULL) { |
mbed_official | 390:35c2c1cf29cd | 404 | mbed_mac_address(mac); /* Get MAC Address */ |
mbed_official | 390:35c2c1cf29cd | 405 | } |
mbed_official | 390:35c2c1cf29cd | 406 | } |
mbed_official | 390:35c2c1cf29cd | 407 | |
mbed_official | 390:35c2c1cf29cd | 408 | int ethernet_link(void) { |
mbed_official | 390:35c2c1cf29cd | 409 | int32_t ret; |
mbed_official | 390:35c2c1cf29cd | 410 | uint16_t data; |
mbed_official | 390:35c2c1cf29cd | 411 | |
mbed_official | 390:35c2c1cf29cd | 412 | data = phy_reg_read(BASIC_MODE_STATUS_REG); |
mbed_official | 390:35c2c1cf29cd | 413 | if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { |
mbed_official | 390:35c2c1cf29cd | 414 | ret = 1; |
mbed_official | 390:35c2c1cf29cd | 415 | } else { |
mbed_official | 390:35c2c1cf29cd | 416 | ret = 0; |
mbed_official | 390:35c2c1cf29cd | 417 | } |
mbed_official | 390:35c2c1cf29cd | 418 | |
mbed_official | 390:35c2c1cf29cd | 419 | return ret; |
mbed_official | 390:35c2c1cf29cd | 420 | } |
mbed_official | 390:35c2c1cf29cd | 421 | |
mbed_official | 390:35c2c1cf29cd | 422 | void ethernet_set_link(int speed, int duplex) { |
mbed_official | 390:35c2c1cf29cd | 423 | uint16_t data; |
mbed_official | 390:35c2c1cf29cd | 424 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 425 | int32_t link; |
mbed_official | 390:35c2c1cf29cd | 426 | |
mbed_official | 390:35c2c1cf29cd | 427 | if ((speed < 0) || (speed > 1)) { |
mbed_official | 390:35c2c1cf29cd | 428 | data = 0x1000; /* Auto-Negotiation Enable */ |
mbed_official | 390:35c2c1cf29cd | 429 | phy_reg_write(BASIC_MODE_CONTROL_REG, data); |
mbed_official | 390:35c2c1cf29cd | 430 | data = phy_reg_read(BASIC_MODE_STATUS_REG); |
mbed_official | 390:35c2c1cf29cd | 431 | for (i = 0; i < 1000; i++) { |
mbed_official | 390:35c2c1cf29cd | 432 | if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { |
mbed_official | 390:35c2c1cf29cd | 433 | break; |
mbed_official | 390:35c2c1cf29cd | 434 | } |
mbed_official | 390:35c2c1cf29cd | 435 | wait_100us(10); |
mbed_official | 390:35c2c1cf29cd | 436 | } |
mbed_official | 390:35c2c1cf29cd | 437 | } else { |
mbed_official | 390:35c2c1cf29cd | 438 | data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); |
mbed_official | 390:35c2c1cf29cd | 439 | phy_reg_write(BASIC_MODE_CONTROL_REG, data); |
mbed_official | 390:35c2c1cf29cd | 440 | wait_100us(1); |
mbed_official | 390:35c2c1cf29cd | 441 | } |
mbed_official | 390:35c2c1cf29cd | 442 | |
mbed_official | 390:35c2c1cf29cd | 443 | link = ethernetext_chk_link_mode(); |
mbed_official | 390:35c2c1cf29cd | 444 | ethernetext_set_link_mode(link); |
mbed_official | 390:35c2c1cf29cd | 445 | } |
mbed_official | 390:35c2c1cf29cd | 446 | |
mbed_official | 417:39e86d6263aa | 447 | void INT_Ether(void) { |
mbed_official | 390:35c2c1cf29cd | 448 | uint32_t stat_edmac; |
mbed_official | 390:35c2c1cf29cd | 449 | uint32_t stat_etherc; |
mbed_official | 390:35c2c1cf29cd | 450 | |
mbed_official | 390:35c2c1cf29cd | 451 | /* Clear the interrupt request flag */ |
mbed_official | 390:35c2c1cf29cd | 452 | stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ |
mbed_official | 390:35c2c1cf29cd | 453 | ETHEREESR0 = stat_edmac; |
mbed_official | 390:35c2c1cf29cd | 454 | /* Reception-related */ |
mbed_official | 390:35c2c1cf29cd | 455 | if (stat_edmac & EDMAC_EESIPR_INI_RECV) { |
mbed_official | 390:35c2c1cf29cd | 456 | if (p_recv_cb_fnc != NULL) { |
mbed_official | 390:35c2c1cf29cd | 457 | p_recv_cb_fnc(); |
mbed_official | 390:35c2c1cf29cd | 458 | } |
mbed_official | 390:35c2c1cf29cd | 459 | } |
mbed_official | 390:35c2c1cf29cd | 460 | /* E-MAC-related */ |
mbed_official | 390:35c2c1cf29cd | 461 | if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { |
mbed_official | 390:35c2c1cf29cd | 462 | /* Clear the interrupt request flag */ |
mbed_official | 390:35c2c1cf29cd | 463 | stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ |
mbed_official | 390:35c2c1cf29cd | 464 | ETHERECSR0 = stat_etherc; |
mbed_official | 390:35c2c1cf29cd | 465 | } |
mbed_official | 390:35c2c1cf29cd | 466 | } |
mbed_official | 390:35c2c1cf29cd | 467 | |
mbed_official | 390:35c2c1cf29cd | 468 | static void lan_reg_reset(void) { |
mbed_official | 390:35c2c1cf29cd | 469 | volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ |
mbed_official | 390:35c2c1cf29cd | 470 | |
mbed_official | 390:35c2c1cf29cd | 471 | ETHERARSTR |= 0x00000001; /* ETHER software reset */ |
mbed_official | 390:35c2c1cf29cd | 472 | while (j--) { |
mbed_official | 390:35c2c1cf29cd | 473 | /* Do Nothing */ |
mbed_official | 390:35c2c1cf29cd | 474 | } |
mbed_official | 390:35c2c1cf29cd | 475 | |
mbed_official | 390:35c2c1cf29cd | 476 | ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ |
mbed_official | 390:35c2c1cf29cd | 477 | ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ |
mbed_official | 390:35c2c1cf29cd | 478 | |
mbed_official | 390:35c2c1cf29cd | 479 | /* Check clear software reset */ |
mbed_official | 390:35c2c1cf29cd | 480 | while ((ETHEREDMR0 & 0x00000003) != 0) { |
mbed_official | 390:35c2c1cf29cd | 481 | /* Do Nothing */ |
mbed_official | 390:35c2c1cf29cd | 482 | } |
mbed_official | 390:35c2c1cf29cd | 483 | } |
mbed_official | 390:35c2c1cf29cd | 484 | |
mbed_official | 390:35c2c1cf29cd | 485 | static void lan_desc_create(void) { |
mbed_official | 390:35c2c1cf29cd | 486 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 487 | uint8_t *p_memory_top; |
mbed_official | 390:35c2c1cf29cd | 488 | |
mbed_official | 390:35c2c1cf29cd | 489 | (void)memset((void *)ehernet_nc_memory, 0, sizeof(ehernet_nc_memory)); |
mbed_official | 482:d9a48e768ce0 | 490 | p_memory_top = ehernet_nc_memory; |
mbed_official | 390:35c2c1cf29cd | 491 | |
mbed_official | 390:35c2c1cf29cd | 492 | /* Descriptor area configuration */ |
mbed_official | 390:35c2c1cf29cd | 493 | p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; |
mbed_official | 390:35c2c1cf29cd | 494 | p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); |
mbed_official | 390:35c2c1cf29cd | 495 | p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; |
mbed_official | 390:35c2c1cf29cd | 496 | p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); |
mbed_official | 390:35c2c1cf29cd | 497 | |
mbed_official | 390:35c2c1cf29cd | 498 | /* Transmit descriptor */ |
mbed_official | 390:35c2c1cf29cd | 499 | for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { |
mbed_official | 390:35c2c1cf29cd | 500 | p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ |
mbed_official | 390:35c2c1cf29cd | 501 | p_memory_top += SIZE_OF_BUFFER; |
mbed_official | 390:35c2c1cf29cd | 502 | p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ |
mbed_official | 390:35c2c1cf29cd | 503 | p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ |
mbed_official | 390:35c2c1cf29cd | 504 | } |
mbed_official | 390:35c2c1cf29cd | 505 | p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ |
mbed_official | 390:35c2c1cf29cd | 506 | |
mbed_official | 390:35c2c1cf29cd | 507 | /* Receive descriptor */ |
mbed_official | 390:35c2c1cf29cd | 508 | for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { |
mbed_official | 390:35c2c1cf29cd | 509 | p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ |
mbed_official | 390:35c2c1cf29cd | 510 | p_memory_top += SIZE_OF_BUFFER; |
mbed_official | 390:35c2c1cf29cd | 511 | p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ |
mbed_official | 390:35c2c1cf29cd | 512 | p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ |
mbed_official | 390:35c2c1cf29cd | 513 | } |
mbed_official | 390:35c2c1cf29cd | 514 | p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ |
mbed_official | 390:35c2c1cf29cd | 515 | |
mbed_official | 390:35c2c1cf29cd | 516 | /* Initialize descriptor management information */ |
mbed_official | 390:35c2c1cf29cd | 517 | send_top_index = 0; |
mbed_official | 390:35c2c1cf29cd | 518 | recv_top_index = 0; |
mbed_official | 390:35c2c1cf29cd | 519 | rx_read_offset = 0; |
mbed_official | 390:35c2c1cf29cd | 520 | tx_wite_offset = 0; |
mbed_official | 390:35c2c1cf29cd | 521 | p_recv_end_desc = NULL; |
mbed_official | 390:35c2c1cf29cd | 522 | } |
mbed_official | 390:35c2c1cf29cd | 523 | |
mbed_official | 390:35c2c1cf29cd | 524 | static void lan_reg_set(int32_t link) { |
mbed_official | 390:35c2c1cf29cd | 525 | /* MAC address setting */ |
mbed_official | 390:35c2c1cf29cd | 526 | ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24) |
mbed_official | 390:35c2c1cf29cd | 527 | | ((uint32_t)mac_addr[1] << 16) |
mbed_official | 390:35c2c1cf29cd | 528 | | ((uint32_t)mac_addr[2] << 8) |
mbed_official | 390:35c2c1cf29cd | 529 | | (uint32_t)mac_addr[3]; |
mbed_official | 390:35c2c1cf29cd | 530 | ETHERMALR0 = ((uint32_t)mac_addr[4] << 8) |
mbed_official | 390:35c2c1cf29cd | 531 | | (uint32_t)mac_addr[5]; |
mbed_official | 390:35c2c1cf29cd | 532 | |
mbed_official | 390:35c2c1cf29cd | 533 | /* E-DMAC */ |
mbed_official | 390:35c2c1cf29cd | 534 | ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; |
mbed_official | 390:35c2c1cf29cd | 535 | ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; |
mbed_official | 390:35c2c1cf29cd | 536 | ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; |
mbed_official | 390:35c2c1cf29cd | 537 | ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; |
mbed_official | 390:35c2c1cf29cd | 538 | ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; |
mbed_official | 390:35c2c1cf29cd | 539 | ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; |
mbed_official | 390:35c2c1cf29cd | 540 | ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ |
mbed_official | 390:35c2c1cf29cd | 541 | ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ |
mbed_official | 390:35c2c1cf29cd | 542 | ETHEREDMR0 |= 0x00000040; /* Little endian */ |
mbed_official | 390:35c2c1cf29cd | 543 | ETHERTRSCER0 &= ~0x0003009F; /* All clear */ |
mbed_official | 390:35c2c1cf29cd | 544 | ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ |
mbed_official | 390:35c2c1cf29cd | 545 | ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ |
mbed_official | 390:35c2c1cf29cd | 546 | ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ |
mbed_official | 390:35c2c1cf29cd | 547 | ETHERFCFTR0 &= ~0x001F00FF; |
mbed_official | 390:35c2c1cf29cd | 548 | ETHERFCFTR0 |= 0x00070007; |
mbed_official | 390:35c2c1cf29cd | 549 | ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ |
mbed_official | 390:35c2c1cf29cd | 550 | |
mbed_official | 390:35c2c1cf29cd | 551 | /* E-MAC */ |
mbed_official | 390:35c2c1cf29cd | 552 | ETHERECMR0 &= ~0x04BF2063; /* All clear */ |
mbed_official | 390:35c2c1cf29cd | 553 | ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ |
mbed_official | 390:35c2c1cf29cd | 554 | ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ |
mbed_official | 390:35c2c1cf29cd | 555 | ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ |
mbed_official | 390:35c2c1cf29cd | 556 | ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ |
mbed_official | 390:35c2c1cf29cd | 557 | ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ |
mbed_official | 390:35c2c1cf29cd | 558 | if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { |
mbed_official | 390:35c2c1cf29cd | 559 | ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ |
mbed_official | 390:35c2c1cf29cd | 560 | } else { |
mbed_official | 390:35c2c1cf29cd | 561 | ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ |
mbed_official | 390:35c2c1cf29cd | 562 | } |
mbed_official | 390:35c2c1cf29cd | 563 | |
mbed_official | 390:35c2c1cf29cd | 564 | /* Interrupt-related */ |
mbed_official | 390:35c2c1cf29cd | 565 | if (p_recv_cb_fnc != NULL) { |
mbed_official | 390:35c2c1cf29cd | 566 | ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ |
mbed_official | 390:35c2c1cf29cd | 567 | ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ |
mbed_official | 390:35c2c1cf29cd | 568 | ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ |
mbed_official | 390:35c2c1cf29cd | 569 | ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ |
mbed_official | 390:35c2c1cf29cd | 570 | InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ |
mbed_official | 390:35c2c1cf29cd | 571 | GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ |
mbed_official | 390:35c2c1cf29cd | 572 | GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ |
mbed_official | 390:35c2c1cf29cd | 573 | } |
mbed_official | 390:35c2c1cf29cd | 574 | |
mbed_official | 390:35c2c1cf29cd | 575 | ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ |
mbed_official | 390:35c2c1cf29cd | 576 | |
mbed_official | 390:35c2c1cf29cd | 577 | /* Enable transmission/reception */ |
mbed_official | 390:35c2c1cf29cd | 578 | if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { |
mbed_official | 390:35c2c1cf29cd | 579 | ETHEREDRRR0 |= 0x00000001; /* RR */ |
mbed_official | 390:35c2c1cf29cd | 580 | } |
mbed_official | 390:35c2c1cf29cd | 581 | } |
mbed_official | 390:35c2c1cf29cd | 582 | |
mbed_official | 390:35c2c1cf29cd | 583 | static uint16_t phy_reg_read(uint16_t reg_addr) { |
mbed_official | 390:35c2c1cf29cd | 584 | uint16_t data; |
mbed_official | 390:35c2c1cf29cd | 585 | |
mbed_official | 390:35c2c1cf29cd | 586 | mii_preamble(); |
mbed_official | 390:35c2c1cf29cd | 587 | mii_cmd(reg_addr, PHY_READ); |
mbed_official | 390:35c2c1cf29cd | 588 | mii_z(); |
mbed_official | 390:35c2c1cf29cd | 589 | mii_reg_read(&data); |
mbed_official | 390:35c2c1cf29cd | 590 | mii_z(); |
mbed_official | 390:35c2c1cf29cd | 591 | |
mbed_official | 390:35c2c1cf29cd | 592 | return data; |
mbed_official | 390:35c2c1cf29cd | 593 | } |
mbed_official | 390:35c2c1cf29cd | 594 | |
mbed_official | 390:35c2c1cf29cd | 595 | static void phy_reg_write(uint16_t reg_addr, uint16_t data) { |
mbed_official | 390:35c2c1cf29cd | 596 | mii_preamble(); |
mbed_official | 390:35c2c1cf29cd | 597 | mii_cmd(reg_addr, PHY_WRITE); |
mbed_official | 390:35c2c1cf29cd | 598 | mii_write_1(); |
mbed_official | 390:35c2c1cf29cd | 599 | mii_write_0(); |
mbed_official | 390:35c2c1cf29cd | 600 | mii_reg_write(data); |
mbed_official | 390:35c2c1cf29cd | 601 | mii_z(); |
mbed_official | 390:35c2c1cf29cd | 602 | } |
mbed_official | 390:35c2c1cf29cd | 603 | |
mbed_official | 390:35c2c1cf29cd | 604 | static void mii_preamble(void) { |
mbed_official | 390:35c2c1cf29cd | 605 | int32_t i = 32; |
mbed_official | 390:35c2c1cf29cd | 606 | |
mbed_official | 390:35c2c1cf29cd | 607 | for (i = 32; i > 0; i--) { |
mbed_official | 390:35c2c1cf29cd | 608 | /* 1 is output via the MII (Media Independent Interface) block. */ |
mbed_official | 390:35c2c1cf29cd | 609 | mii_write_1(); |
mbed_official | 390:35c2c1cf29cd | 610 | } |
mbed_official | 390:35c2c1cf29cd | 611 | } |
mbed_official | 390:35c2c1cf29cd | 612 | |
mbed_official | 390:35c2c1cf29cd | 613 | static void mii_cmd(uint16_t reg_addr, uint32_t option) { |
mbed_official | 390:35c2c1cf29cd | 614 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 615 | uint16_t data = 0; |
mbed_official | 390:35c2c1cf29cd | 616 | |
mbed_official | 390:35c2c1cf29cd | 617 | data |= (PHY_ST << 14); /* ST code */ |
mbed_official | 390:35c2c1cf29cd | 618 | data |= (option << 12); /* OP code */ |
mbed_official | 390:35c2c1cf29cd | 619 | data |= (PHY_ADDR << 7); /* PHY Address */ |
mbed_official | 390:35c2c1cf29cd | 620 | data |= (uint16_t)(reg_addr << 2); /* Reg Address */ |
mbed_official | 390:35c2c1cf29cd | 621 | for (i = 14; i > 0; i--) { |
mbed_official | 390:35c2c1cf29cd | 622 | if ((data & 0x8000) == 0) { |
mbed_official | 390:35c2c1cf29cd | 623 | mii_write_0(); |
mbed_official | 390:35c2c1cf29cd | 624 | } else { |
mbed_official | 390:35c2c1cf29cd | 625 | mii_write_1(); |
mbed_official | 390:35c2c1cf29cd | 626 | } |
mbed_official | 390:35c2c1cf29cd | 627 | data <<= 1; |
mbed_official | 390:35c2c1cf29cd | 628 | } |
mbed_official | 390:35c2c1cf29cd | 629 | } |
mbed_official | 390:35c2c1cf29cd | 630 | |
mbed_official | 390:35c2c1cf29cd | 631 | static void mii_reg_read(uint16_t *data) { |
mbed_official | 390:35c2c1cf29cd | 632 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 633 | uint16_t reg_data = 0; |
mbed_official | 390:35c2c1cf29cd | 634 | |
mbed_official | 390:35c2c1cf29cd | 635 | /* Data are read in one bit at a time */ |
mbed_official | 390:35c2c1cf29cd | 636 | for (i = 16; i > 0; i--) { |
mbed_official | 390:35c2c1cf29cd | 637 | set_ether_pir(PIR0_MDC_LOW); |
mbed_official | 390:35c2c1cf29cd | 638 | set_ether_pir(PIR0_MDC_HIGH); |
mbed_official | 390:35c2c1cf29cd | 639 | reg_data <<= 1; |
mbed_official | 390:35c2c1cf29cd | 640 | reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ |
mbed_official | 390:35c2c1cf29cd | 641 | set_ether_pir(PIR0_MDC_HIGH); |
mbed_official | 390:35c2c1cf29cd | 642 | set_ether_pir(PIR0_MDC_LOW); |
mbed_official | 390:35c2c1cf29cd | 643 | } |
mbed_official | 390:35c2c1cf29cd | 644 | *data = reg_data; |
mbed_official | 390:35c2c1cf29cd | 645 | } |
mbed_official | 390:35c2c1cf29cd | 646 | |
mbed_official | 390:35c2c1cf29cd | 647 | static void mii_reg_write(uint16_t data) { |
mbed_official | 390:35c2c1cf29cd | 648 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 649 | |
mbed_official | 390:35c2c1cf29cd | 650 | /* Data are written one bit at a time */ |
mbed_official | 390:35c2c1cf29cd | 651 | for (i = 16; i > 0; i--) { |
mbed_official | 390:35c2c1cf29cd | 652 | if ((data & 0x8000) == 0) { |
mbed_official | 390:35c2c1cf29cd | 653 | mii_write_0(); |
mbed_official | 390:35c2c1cf29cd | 654 | } else { |
mbed_official | 390:35c2c1cf29cd | 655 | mii_write_1(); |
mbed_official | 390:35c2c1cf29cd | 656 | } |
mbed_official | 390:35c2c1cf29cd | 657 | data <<= 1; |
mbed_official | 390:35c2c1cf29cd | 658 | } |
mbed_official | 390:35c2c1cf29cd | 659 | } |
mbed_official | 390:35c2c1cf29cd | 660 | |
mbed_official | 390:35c2c1cf29cd | 661 | static void mii_z(void) { |
mbed_official | 390:35c2c1cf29cd | 662 | set_ether_pir(PIR0_MDC_LOW); |
mbed_official | 390:35c2c1cf29cd | 663 | set_ether_pir(PIR0_MDC_HIGH); |
mbed_official | 390:35c2c1cf29cd | 664 | set_ether_pir(PIR0_MDC_HIGH); |
mbed_official | 390:35c2c1cf29cd | 665 | set_ether_pir(PIR0_MDC_LOW); |
mbed_official | 390:35c2c1cf29cd | 666 | } |
mbed_official | 390:35c2c1cf29cd | 667 | |
mbed_official | 390:35c2c1cf29cd | 668 | static void mii_write_1(void) { |
mbed_official | 390:35c2c1cf29cd | 669 | set_ether_pir(PIR0_MDO | PIR0_MMD); |
mbed_official | 390:35c2c1cf29cd | 670 | set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); |
mbed_official | 390:35c2c1cf29cd | 671 | set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); |
mbed_official | 390:35c2c1cf29cd | 672 | set_ether_pir(PIR0_MDO | PIR0_MMD); |
mbed_official | 390:35c2c1cf29cd | 673 | } |
mbed_official | 390:35c2c1cf29cd | 674 | |
mbed_official | 390:35c2c1cf29cd | 675 | static void mii_write_0(void) { |
mbed_official | 390:35c2c1cf29cd | 676 | set_ether_pir(PIR0_MMD); |
mbed_official | 390:35c2c1cf29cd | 677 | set_ether_pir(PIR0_MMD | PIR0_MDC); |
mbed_official | 390:35c2c1cf29cd | 678 | set_ether_pir(PIR0_MMD | PIR0_MDC); |
mbed_official | 390:35c2c1cf29cd | 679 | set_ether_pir(PIR0_MMD); |
mbed_official | 390:35c2c1cf29cd | 680 | } |
mbed_official | 390:35c2c1cf29cd | 681 | |
mbed_official | 390:35c2c1cf29cd | 682 | static void set_ether_pir(uint32_t set_data) { |
mbed_official | 390:35c2c1cf29cd | 683 | int32_t i; |
mbed_official | 390:35c2c1cf29cd | 684 | |
mbed_official | 390:35c2c1cf29cd | 685 | for (i = MDC_WAIT; i > 0; i--) { |
mbed_official | 390:35c2c1cf29cd | 686 | ETHERPIR0 = set_data; |
mbed_official | 390:35c2c1cf29cd | 687 | } |
mbed_official | 390:35c2c1cf29cd | 688 | } |
mbed_official | 390:35c2c1cf29cd | 689 | |
mbed_official | 390:35c2c1cf29cd | 690 | static void wait_100us(int32_t wait_cnt) { |
mbed_official | 390:35c2c1cf29cd | 691 | volatile int32_t j = LOOP_100us * wait_cnt; |
mbed_official | 390:35c2c1cf29cd | 692 | |
mbed_official | 390:35c2c1cf29cd | 693 | while (--j) { |
mbed_official | 390:35c2c1cf29cd | 694 | /* Do Nothing */ |
mbed_official | 390:35c2c1cf29cd | 695 | } |
mbed_official | 390:35c2c1cf29cd | 696 | } |