mbed library sources, include can_api for nucleo-f091rc
Dependents: CanNucleoF0_example
Fork of mbed-src by
targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c@363:12a245e5c745, 2014-10-23 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Oct 23 09:45:08 2014 +0100
- Revision:
- 363:12a245e5c745
- Parent:
- 82:0b31dbcd4769
- Child:
- 499:d0e9408fd176
Synchronized with git revision 6ff7dfe464a15417f666938479c7860707707331
Full URL: https://github.com/mbedmicro/mbed/commit/6ff7dfe464a15417f666938479c7860707707331/
Target: Freescale FRDM-KL43Z addition
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 82:0b31dbcd4769 | 1 | /* mbed Microcontroller Library |
mbed_official | 82:0b31dbcd4769 | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 82:0b31dbcd4769 | 3 | * |
mbed_official | 82:0b31dbcd4769 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 82:0b31dbcd4769 | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 82:0b31dbcd4769 | 6 | * You may obtain a copy of the License at |
mbed_official | 82:0b31dbcd4769 | 7 | * |
mbed_official | 82:0b31dbcd4769 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 82:0b31dbcd4769 | 9 | * |
mbed_official | 82:0b31dbcd4769 | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 82:0b31dbcd4769 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 82:0b31dbcd4769 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 82:0b31dbcd4769 | 13 | * See the License for the specific language governing permissions and |
mbed_official | 82:0b31dbcd4769 | 14 | * limitations under the License. |
mbed_official | 82:0b31dbcd4769 | 15 | */ |
mbed_official | 82:0b31dbcd4769 | 16 | #include "sleep_api.h" |
mbed_official | 82:0b31dbcd4769 | 17 | #include "cmsis.h" |
mbed_official | 82:0b31dbcd4769 | 18 | #include "PeripheralPins.h" |
mbed_official | 82:0b31dbcd4769 | 19 | |
mbed_official | 82:0b31dbcd4769 | 20 | //Normal wait mode |
mbed_official | 82:0b31dbcd4769 | 21 | void sleep(void) |
mbed_official | 82:0b31dbcd4769 | 22 | { |
mbed_official | 82:0b31dbcd4769 | 23 | SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; |
mbed_official | 82:0b31dbcd4769 | 24 | |
mbed_official | 82:0b31dbcd4769 | 25 | //Normal sleep mode for ARM core: |
mbed_official | 82:0b31dbcd4769 | 26 | SCB->SCR = 0; |
mbed_official | 82:0b31dbcd4769 | 27 | __WFI(); |
mbed_official | 82:0b31dbcd4769 | 28 | } |
mbed_official | 82:0b31dbcd4769 | 29 | |
mbed_official | 82:0b31dbcd4769 | 30 | //Very low-power stop mode |
mbed_official | 82:0b31dbcd4769 | 31 | void deepsleep(void) |
mbed_official | 82:0b31dbcd4769 | 32 | { |
mbed_official | 363:12a245e5c745 | 33 | #if ! defined(TARGET_KL43Z) |
mbed_official | 82:0b31dbcd4769 | 34 | //Check if PLL/FLL is enabled: |
mbed_official | 82:0b31dbcd4769 | 35 | uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); |
mbed_official | 363:12a245e5c745 | 36 | #endif |
mbed_official | 363:12a245e5c745 | 37 | |
mbed_official | 82:0b31dbcd4769 | 38 | SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; |
mbed_official | 82:0b31dbcd4769 | 39 | SMC->PMCTRL = SMC_PMCTRL_STOPM(2); |
mbed_official | 82:0b31dbcd4769 | 40 | |
mbed_official | 82:0b31dbcd4769 | 41 | //Deep sleep for ARM core: |
mbed_official | 82:0b31dbcd4769 | 42 | SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos; |
mbed_official | 82:0b31dbcd4769 | 43 | |
mbed_official | 82:0b31dbcd4769 | 44 | __WFI(); |
mbed_official | 82:0b31dbcd4769 | 45 | |
mbed_official | 363:12a245e5c745 | 46 | #if ! defined(TARGET_KL43Z) |
mbed_official | 82:0b31dbcd4769 | 47 | //Switch back to PLL as clock source if needed |
mbed_official | 82:0b31dbcd4769 | 48 | //The interrupt that woke up the device will run at reduced speed |
mbed_official | 82:0b31dbcd4769 | 49 | if (PLL_FLL_en) { |
mbed_official | 82:0b31dbcd4769 | 50 | #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available |
mbed_official | 82:0b31dbcd4769 | 51 | if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */ |
mbed_official | 82:0b31dbcd4769 | 52 | while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ |
mbed_official | 82:0b31dbcd4769 | 53 | #endif |
mbed_official | 82:0b31dbcd4769 | 54 | MCG->C1 &= ~MCG_C1_CLKS_MASK; |
mbed_official | 82:0b31dbcd4769 | 55 | } |
mbed_official | 363:12a245e5c745 | 56 | #endif |
mbed_official | 82:0b31dbcd4769 | 57 | } |