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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
113:b3775bf36a83 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2S HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The I2S HAL driver can be used as follow:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
<> 144:ef7eb2e8f9f7 22 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 23 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 24 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 25 (+++) Configure these I2S pins as alternate function.
<> 144:ef7eb2e8f9f7 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 27 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 28 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 29 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 31 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 32 (+++) Declare a DMA handle structure for the Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 38 DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 41 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 44 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 46 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 47 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 48 the define constant HSE_VALUE in the stm32l0xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (#) Three mode of operations are available within this driver :
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 53 =================================
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 56 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 59 ===================================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 62 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 63 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 64 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 65 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 66 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 67 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 69 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 70 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 71 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 72 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 75 ==============================
<> 144:ef7eb2e8f9f7 76 [..]
<> 144:ef7eb2e8f9f7 77 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 78 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 79 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 80 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 81 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 82 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 83 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 84 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 85 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 86 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 87 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 88 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 89 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 90 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 91 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 94 ===================================
<> 144:ef7eb2e8f9f7 95 [..]
<> 144:ef7eb2e8f9f7 96 Below the list of most used macros in USART HAL driver.
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 99 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 100 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 101 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 102 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 [..]
<> 144:ef7eb2e8f9f7 105 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 @endverbatim
<> 144:ef7eb2e8f9f7 108 ******************************************************************************
<> 144:ef7eb2e8f9f7 109 * @attention
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 114 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 115 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 116 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 117 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 118 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 119 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 120 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 121 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 122 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 125 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 126 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 127 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 128 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 129 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 130 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 131 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 132 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 133 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 134 *
<> 144:ef7eb2e8f9f7 135 ******************************************************************************
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
<> 144:ef7eb2e8f9f7 139 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @addtogroup I2S I2S
<> 144:ef7eb2e8f9f7 149 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 160 /** @addtogroup I2S_Private
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 166 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 167 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 168 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 169 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 170 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @}
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 176 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @addtogroup I2S_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 181 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 182 *
<> 144:ef7eb2e8f9f7 183 @verbatim
<> 144:ef7eb2e8f9f7 184 ===============================================================================
<> 144:ef7eb2e8f9f7 185 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 186 ===============================================================================
<> 144:ef7eb2e8f9f7 187 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 188 de-initialiaze the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 191 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 194 the selected configuration:
<> 144:ef7eb2e8f9f7 195 (++) Mode
<> 144:ef7eb2e8f9f7 196 (++) Standard
<> 144:ef7eb2e8f9f7 197 (++) Data Format
<> 144:ef7eb2e8f9f7 198 (++) MCLK Output
<> 144:ef7eb2e8f9f7 199 (++) Audio frequency
<> 144:ef7eb2e8f9f7 200 (++) Polarity
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 203 of the selected I2Sx periperal.
<> 144:ef7eb2e8f9f7 204 @endverbatim
<> 144:ef7eb2e8f9f7 205 * @{
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 210 * in the I2S_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 211 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 212 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 213 * @retval HAL status
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
<> 144:ef7eb2e8f9f7 218 uint32_t tmp = 0, i2sclk = 0, tmpreg = 0;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 221 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Check the I2S parameters */
<> 144:ef7eb2e8f9f7 227 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 228 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
<> 144:ef7eb2e8f9f7 229 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
<> 144:ef7eb2e8f9f7 230 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
<> 144:ef7eb2e8f9f7 231 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 232 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
<> 144:ef7eb2e8f9f7 233 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 if(hi2s->State == HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 238 hi2s->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 241 HAL_I2S_MspInit(hi2s);
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
<> 144:ef7eb2e8f9f7 247 if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 i2sodd = (uint32_t)0;
<> 144:ef7eb2e8f9f7 250 i2sdiv = (uint32_t)2;
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252 /* If the requested audio frequency is not the default, compute the prescaler */
<> 144:ef7eb2e8f9f7 253 else
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /* Check the frame length (For the Prescaler computing) *******************/
<> 144:ef7eb2e8f9f7 256 if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 /* Packet length is 16 bits */
<> 144:ef7eb2e8f9f7 259 packetlength = 1;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 else
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 /* Packet length is 32 bits */
<> 144:ef7eb2e8f9f7 264 packetlength = 2;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Get the source clock value: based on System Clock value */
<> 144:ef7eb2e8f9f7 268 i2sclk = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Compute the Real divider depending on the MCLK output state, with a floating point */
<> 144:ef7eb2e8f9f7 271 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 /* MCLK output is enabled */
<> 144:ef7eb2e8f9f7 274 tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 else
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* MCLK output is disabled */
<> 144:ef7eb2e8f9f7 279 tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Remove the flatting point */
<> 144:ef7eb2e8f9f7 283 tmp = tmp / 10;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Check the parity of the divider */
<> 144:ef7eb2e8f9f7 286 i2sodd = (uint32_t)(tmp & (uint32_t)1);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Compute the i2sdiv prescaler */
<> 144:ef7eb2e8f9f7 289 i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 144:ef7eb2e8f9f7 292 i2sodd = (uint32_t) (i2sodd << 8);
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 144:ef7eb2e8f9f7 296 if((i2sdiv < 2) || (i2sdiv > 0xFF))
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Set the default values */
<> 144:ef7eb2e8f9f7 299 i2sdiv = 2;
<> 144:ef7eb2e8f9f7 300 i2sodd = 0;
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Write to SPIx I2SPR register the computed value */
<> 144:ef7eb2e8f9f7 306 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
<> 144:ef7eb2e8f9f7 309 /* And configure the I2S with the I2S_InitStruct values */
<> 144:ef7eb2e8f9f7 310 MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
<> 144:ef7eb2e8f9f7 311 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
<> 144:ef7eb2e8f9f7 312 SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
<> 144:ef7eb2e8f9f7 313 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\
<> 144:ef7eb2e8f9f7 314 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
<> 144:ef7eb2e8f9f7 315 hi2s->Init.Standard | hi2s->Init.DataFormat |\
<> 144:ef7eb2e8f9f7 316 hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Get the I2SCFGR register value */
<> 144:ef7eb2e8f9f7 319 tmpreg = hi2s->Instance->I2SCFGR;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #if defined(SPI_I2SCFGR_ASTRTEN)
<> 144:ef7eb2e8f9f7 322 if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Write to SPIx I2SCFGR */
<> 144:ef7eb2e8f9f7 325 hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 else
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 /* Write to SPIx I2SCFGR */
<> 144:ef7eb2e8f9f7 330 hi2s->Instance->I2SCFGR = tmpreg;
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332 #else
<> 144:ef7eb2e8f9f7 333 /* Write to SPIx I2SCFGR */
<> 144:ef7eb2e8f9f7 334 hi2s->Instance->I2SCFGR = tmpreg;
<> 144:ef7eb2e8f9f7 335 #endif
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 338 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 return HAL_OK;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @brief DeInitializes the I2S peripheral
<> 144:ef7eb2e8f9f7 345 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 346 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 347 * @retval HAL status
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 352 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Disable the I2S Peripheral Clock */
<> 144:ef7eb2e8f9f7 360 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 363 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 366 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Release Lock */
<> 144:ef7eb2e8f9f7 369 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 return HAL_OK;
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief I2S MSP Init
<> 144:ef7eb2e8f9f7 376 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 377 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 378 * @retval None
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 383 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 386 the HAL_I2S_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief I2S MSP DeInit
<> 144:ef7eb2e8f9f7 392 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 393 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 394 * @retval None
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 399 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 402 the HAL_I2S_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /** @addtogroup I2S_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 411 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 412 *
<> 144:ef7eb2e8f9f7 413 @verbatim
<> 144:ef7eb2e8f9f7 414 ===============================================================================
<> 144:ef7eb2e8f9f7 415 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 416 ===============================================================================
<> 144:ef7eb2e8f9f7 417 [..]
<> 144:ef7eb2e8f9f7 418 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 419 transfers.
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 422 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 423 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 424 after finishing transfer.
<> 144:ef7eb2e8f9f7 425 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 426 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 427 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 428 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 429 using DMA mode.
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 432 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 433 (++) HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 436 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 437 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 440 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 441 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 444 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 445 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 446 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 @endverbatim
<> 144:ef7eb2e8f9f7 449 * @{
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 454 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 455 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 456 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 457 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 458 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 459 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 460 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 461 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 462 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 463 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 464 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 465 * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
<> 144:ef7eb2e8f9f7 466 * @retval HAL status
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Process Locked */
<> 144:ef7eb2e8f9f7 476 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 481 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 484 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486 else
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 489 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Set state and reset error code */
<> 144:ef7eb2e8f9f7 493 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 494 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 495 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 498 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 501 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 while(hi2s->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Wait until TXE flag is set */
<> 144:ef7eb2e8f9f7 507 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 512 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Wait until TXE flag is set, to confirm the end of the transaction */
<> 144:ef7eb2e8f9f7 516 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Check if Slave mode is selected */
<> 144:ef7eb2e8f9f7 522 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* Wait until Busy flag is reset */
<> 144:ef7eb2e8f9f7 525 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 533 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 return HAL_OK;
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 else
<> 144:ef7eb2e8f9f7 538 {
<> 144:ef7eb2e8f9f7 539 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 540 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 541 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 547 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 548 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 549 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 550 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 551 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 552 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 553 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 554 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 555 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 556 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 557 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 558 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
<> 144:ef7eb2e8f9f7 559 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
<> 144:ef7eb2e8f9f7 560 * @note This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz
<> 144:ef7eb2e8f9f7 561 * @retval HAL status
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Process Locked */
<> 144:ef7eb2e8f9f7 571 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 576 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 579 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581 else
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 584 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Set state and reset error code */
<> 144:ef7eb2e8f9f7 588 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 589 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 590 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 593 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 594 {
<> 144:ef7eb2e8f9f7 595 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 596 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 600 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 603 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 604 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Receive data */
<> 144:ef7eb2e8f9f7 608 while(hi2s->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 611 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 617 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 623 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 return HAL_OK;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 else
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 630 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 631 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 637 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 638 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 639 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 640 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 641 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 642 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 643 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 644 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 645 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 646 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 647 * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
<> 144:ef7eb2e8f9f7 648 * @retval HAL status
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Process Locked */
<> 144:ef7eb2e8f9f7 658 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 663 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 664 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 667 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 670 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672 else
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 675 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 679 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 682 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 685 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 689 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 return HAL_OK;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 else
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 696 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 697 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 703 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 704 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 705 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 706 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 707 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 708 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 709 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 710 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 711 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 712 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 713 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
<> 144:ef7eb2e8f9f7 714 * between Master and Slave otherwise the I2S interrupt should be optimized.
<> 144:ef7eb2e8f9f7 715 * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
<> 144:ef7eb2e8f9f7 716 * @retval HAL status
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Process Locked */
<> 144:ef7eb2e8f9f7 726 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 731 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 732 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 735 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 738 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 739 }
<> 144:ef7eb2e8f9f7 740 else
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 743 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Enable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 747 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 750 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 753 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 757 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 return HAL_OK;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 else
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 764 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 765 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief Transmit an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 771 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 772 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 773 * @param pData: a 16-bit pointer to the Transmit data buffer.
<> 144:ef7eb2e8f9f7 774 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 775 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 776 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 777 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 778 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 779 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 780 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 781 * @retval HAL status
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Process Locked */
<> 144:ef7eb2e8f9f7 791 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 796 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 797 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 800 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 803 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805 else
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 808 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Set the I2S Tx DMA Half transfert complete callback */
<> 144:ef7eb2e8f9f7 812 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Set the I2S Tx DMA transfert complete callback */
<> 144:ef7eb2e8f9f7 815 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 818 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 821 HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 824 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 827 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* Check if the I2S Tx request is already enabled */
<> 144:ef7eb2e8f9f7 831 if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 834 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 838 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 return HAL_OK;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 else
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 845 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 846 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @brief Receive an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 852 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 853 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 854 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 855 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 856 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 857 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 858 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 859 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 860 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 861 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 862 * @retval HAL status
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 867 {
<> 144:ef7eb2e8f9f7 868 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Process Locked */
<> 144:ef7eb2e8f9f7 872 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 877 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 878 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 881 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 884 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886 else
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 889 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Set the I2S Rx DMA Half transfert complete callback */
<> 144:ef7eb2e8f9f7 894 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /* Set the I2S Rx DMA transfert complete callback */
<> 144:ef7eb2e8f9f7 897 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 900 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 903 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 906 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 907 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 908 }
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 911 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 914 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 917 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Check if the I2S Rx request is already enabled */
<> 144:ef7eb2e8f9f7 921 if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
<> 144:ef7eb2e8f9f7 922 {
<> 144:ef7eb2e8f9f7 923 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 924 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 928 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 return HAL_OK;
<> 144:ef7eb2e8f9f7 931 }
<> 144:ef7eb2e8f9f7 932 else
<> 144:ef7eb2e8f9f7 933 {
<> 144:ef7eb2e8f9f7 934 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 935 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 936 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939
<> 144:ef7eb2e8f9f7 940 /**
<> 144:ef7eb2e8f9f7 941 * @brief Pauses the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 942 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 943 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 944 * @retval HAL status
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 /* Process Locked */
<> 144:ef7eb2e8f9f7 949 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 954 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 959 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 960 }
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 963 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 return HAL_OK;
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /**
<> 144:ef7eb2e8f9f7 969 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 970 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 971 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 972 * @retval HAL status
<> 144:ef7eb2e8f9f7 973 */
<> 144:ef7eb2e8f9f7 974 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 /* Process Locked */
<> 144:ef7eb2e8f9f7 977 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 980 {
<> 144:ef7eb2e8f9f7 981 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 982 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 987 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /* If the I2S peripheral is still not enabled, enable it */
<> 144:ef7eb2e8f9f7 991 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 994 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 998 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 return HAL_OK;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Stops the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 1005 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1006 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1007 * @retval HAL status
<> 144:ef7eb2e8f9f7 1008 */
<> 144:ef7eb2e8f9f7 1009 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 /* Process Locked */
<> 144:ef7eb2e8f9f7 1012 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Disable the I2S Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 1015 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1016 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Abort the I2S DMA Channel tx */
<> 144:ef7eb2e8f9f7 1019 if(hi2s->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1020 {
<> 144:ef7eb2e8f9f7 1021 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1022 __HAL_DMA_DISABLE(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1023 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 /* Abort the I2S DMA Channel rx */
<> 144:ef7eb2e8f9f7 1026 if(hi2s->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1027 {
<> 144:ef7eb2e8f9f7 1028 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1029 __HAL_DMA_DISABLE(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1030 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 1034 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1039 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 return HAL_OK;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /**
<> 144:ef7eb2e8f9f7 1045 * @brief This function handles I2S interrupt request.
<> 144:ef7eb2e8f9f7 1046 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1047 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1048 * @retval None
<> 144:ef7eb2e8f9f7 1049 */
<> 144:ef7eb2e8f9f7 1050 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1051 {
<> 144:ef7eb2e8f9f7 1052 uint32_t i2ssr = hi2s->Instance->SR;
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* I2S in mode Receiver ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1055 if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
<> 144:ef7eb2e8f9f7 1056 ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 1057 {
<> 144:ef7eb2e8f9f7 1058 I2S_Receive_IT(hi2s);
<> 144:ef7eb2e8f9f7 1059 return;
<> 144:ef7eb2e8f9f7 1060 }
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /* I2S in mode Tramitter -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1063 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1064 {
<> 144:ef7eb2e8f9f7 1065 I2S_Transmit_IT(hi2s);
<> 144:ef7eb2e8f9f7 1066 return;
<> 144:ef7eb2e8f9f7 1067 }
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 /* I2S interrupt error -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1070 if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 /* I2S Overrun error interrupt occured ---------------------------------*/
<> 144:ef7eb2e8f9f7 1073 if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1076 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1079 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /* I2S Underrun error interrupt occured --------------------------------*/
<> 144:ef7eb2e8f9f7 1083 if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1086 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1089 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1093 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1094 /* Call the Error Callback */
<> 144:ef7eb2e8f9f7 1095 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1096 }
<> 144:ef7eb2e8f9f7 1097 }
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /**
<> 144:ef7eb2e8f9f7 1100 * @brief Tx Transfer Half completed callbacks
<> 144:ef7eb2e8f9f7 1101 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1102 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1103 * @retval None
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1108 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1111 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1112 */
<> 144:ef7eb2e8f9f7 1113 }
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /**
<> 144:ef7eb2e8f9f7 1116 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1117 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1118 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1119 * @retval None
<> 144:ef7eb2e8f9f7 1120 */
<> 144:ef7eb2e8f9f7 1121 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1122 {
<> 144:ef7eb2e8f9f7 1123 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1124 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1127 the HAL_I2S_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1128 */
<> 144:ef7eb2e8f9f7 1129 }
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /**
<> 144:ef7eb2e8f9f7 1132 * @brief Rx Transfer half completed callbacks
<> 144:ef7eb2e8f9f7 1133 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1134 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1135 * @retval None
<> 144:ef7eb2e8f9f7 1136 */
<> 144:ef7eb2e8f9f7 1137 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1138 {
<> 144:ef7eb2e8f9f7 1139 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1140 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1143 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1144 */
<> 144:ef7eb2e8f9f7 1145 }
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /**
<> 144:ef7eb2e8f9f7 1148 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1149 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1150 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1151 * @retval None
<> 144:ef7eb2e8f9f7 1152 */
<> 144:ef7eb2e8f9f7 1153 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1154 {
<> 144:ef7eb2e8f9f7 1155 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1156 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1159 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /**
<> 144:ef7eb2e8f9f7 1164 * @brief I2S error callbacks
<> 144:ef7eb2e8f9f7 1165 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1166 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1167 * @retval None
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1172 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1175 the HAL_I2S_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1176 */
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /**
<> 144:ef7eb2e8f9f7 1180 * @}
<> 144:ef7eb2e8f9f7 1181 */
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /** @addtogroup I2S_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1184 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1185 *
<> 144:ef7eb2e8f9f7 1186 @verbatim
<> 144:ef7eb2e8f9f7 1187 ===============================================================================
<> 144:ef7eb2e8f9f7 1188 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1189 ===============================================================================
<> 144:ef7eb2e8f9f7 1190 [..]
<> 144:ef7eb2e8f9f7 1191 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1192 and the data flow.
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 @endverbatim
<> 144:ef7eb2e8f9f7 1195 * @{
<> 144:ef7eb2e8f9f7 1196 */
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /**
<> 144:ef7eb2e8f9f7 1199 * @brief Return the I2S state
<> 144:ef7eb2e8f9f7 1200 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1201 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1202 * @retval HAL state
<> 144:ef7eb2e8f9f7 1203 */
<> 144:ef7eb2e8f9f7 1204 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1205 {
<> 144:ef7eb2e8f9f7 1206 return hi2s->State;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @brief Return the I2S error code
<> 144:ef7eb2e8f9f7 1211 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1212 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1213 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1214 */
<> 144:ef7eb2e8f9f7 1215 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1216 {
<> 144:ef7eb2e8f9f7 1217 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1218 }
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @}
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /**
<> 144:ef7eb2e8f9f7 1224 * @}
<> 144:ef7eb2e8f9f7 1225 */
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1228 /** @addtogroup I2S_Private
<> 144:ef7eb2e8f9f7 1229 * @{
<> 144:ef7eb2e8f9f7 1230 */
<> 144:ef7eb2e8f9f7 1231 /**
<> 144:ef7eb2e8f9f7 1232 * @brief DMA I2S transmit process complete callback
<> 144:ef7eb2e8f9f7 1233 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1234 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1235 * @retval None
<> 144:ef7eb2e8f9f7 1236 */
<> 144:ef7eb2e8f9f7 1237 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1238 {
<> 144:ef7eb2e8f9f7 1239 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1244 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1247 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1248 }
<> 144:ef7eb2e8f9f7 1249 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1250 }
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /**
<> 144:ef7eb2e8f9f7 1253 * @brief DMA I2S transmit process half complete callback
<> 144:ef7eb2e8f9f7 1254 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1255 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1256 * @retval None
<> 144:ef7eb2e8f9f7 1257 */
<> 144:ef7eb2e8f9f7 1258 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /**
<> 144:ef7eb2e8f9f7 1266 * @brief DMA I2S receive process complete callback
<> 144:ef7eb2e8f9f7 1267 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1268 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1269 * @retval None
<> 144:ef7eb2e8f9f7 1270 */
<> 144:ef7eb2e8f9f7 1271 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1272 {
<> 144:ef7eb2e8f9f7 1273 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 1276 {
<> 144:ef7eb2e8f9f7 1277 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1278 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1279 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1280 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1283 }
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /**
<> 144:ef7eb2e8f9f7 1286 * @brief DMA I2S receive process half complete callback
<> 144:ef7eb2e8f9f7 1287 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1288 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1289 * @retval None
<> 144:ef7eb2e8f9f7 1290 */
<> 144:ef7eb2e8f9f7 1291 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /**
<> 144:ef7eb2e8f9f7 1299 * @brief DMA I2S communication error callback
<> 144:ef7eb2e8f9f7 1300 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1301 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1302 * @retval None
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* Disable Rx and Tx DMA Request */
<> 144:ef7eb2e8f9f7 1309 CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
<> 144:ef7eb2e8f9f7 1310 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1311 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1316 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1317 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 /**
<> 144:ef7eb2e8f9f7 1321 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1322 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1323 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1324 * @retval None
<> 144:ef7eb2e8f9f7 1325 */
<> 144:ef7eb2e8f9f7 1326 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1327 {
<> 144:ef7eb2e8f9f7 1328 /* Transmit data */
<> 144:ef7eb2e8f9f7 1329 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1330 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 if(hi2s->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1333 {
<> 144:ef7eb2e8f9f7 1334 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1335 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1338 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1339 }
<> 144:ef7eb2e8f9f7 1340 }
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 /**
<> 144:ef7eb2e8f9f7 1343 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1344 * @param hi2s: I2S handle
<> 144:ef7eb2e8f9f7 1345 * @retval None
<> 144:ef7eb2e8f9f7 1346 */
<> 144:ef7eb2e8f9f7 1347 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 /* Receive data */
<> 144:ef7eb2e8f9f7 1350 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1351 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 if(hi2s->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 1354 {
<> 144:ef7eb2e8f9f7 1355 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1356 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1359 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1360 }
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /**
<> 144:ef7eb2e8f9f7 1365 * @brief This function handles I2S Communication Timeout.
<> 144:ef7eb2e8f9f7 1366 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1367 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1368 * @param Flag: Flag checked
<> 144:ef7eb2e8f9f7 1369 * @param Status: Value of the flag expected
<> 144:ef7eb2e8f9f7 1370 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 1371 * @retval HAL status
<> 144:ef7eb2e8f9f7 1372 */
<> 144:ef7eb2e8f9f7 1373 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /* Get tick */
<> 144:ef7eb2e8f9f7 1378 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1381 if(Status == RESET)
<> 144:ef7eb2e8f9f7 1382 {
<> 144:ef7eb2e8f9f7 1383 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1384 {
<> 144:ef7eb2e8f9f7 1385 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1388 {
<> 144:ef7eb2e8f9f7 1389 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1390 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1393 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1396 }
<> 144:ef7eb2e8f9f7 1397 }
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399 }
<> 144:ef7eb2e8f9f7 1400 else
<> 144:ef7eb2e8f9f7 1401 {
<> 144:ef7eb2e8f9f7 1402 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1405 {
<> 144:ef7eb2e8f9f7 1406 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1407 {
<> 144:ef7eb2e8f9f7 1408 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1409 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1412 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1415 }
<> 144:ef7eb2e8f9f7 1416 }
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418 }
<> 144:ef7eb2e8f9f7 1419 return HAL_OK;
<> 144:ef7eb2e8f9f7 1420 }
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /**
<> 144:ef7eb2e8f9f7 1423 * @}
<> 144:ef7eb2e8f9f7 1424 */
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 /**
<> 144:ef7eb2e8f9f7 1427 * @}
<> 144:ef7eb2e8f9f7 1428 */
<> 144:ef7eb2e8f9f7 1429 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /**
<> 144:ef7eb2e8f9f7 1432 * @}
<> 144:ef7eb2e8f9f7 1433 */
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 #endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) */
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1438