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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr.h@150:cd63f849362a, 2016-11-03 (annotated)

Committer:
ptpaterson
Date:
Thu Nov 03 16:21:53 2016 +0000
Revision:
150:cd63f849362a
Parent:
149:156823d33999 
targets LPC11Cxx, LPC15xx:  can_api can_filter function properly returns 0 if handle argument is out of bounds (handle > 32).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_pwr.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief Header file of PWR HAL module.
<> 149:156823d33999 8 ******************************************************************************
<> 149:156823d33999 9 * @attention
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 12 *
<> 149:156823d33999 13 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 14 * are permitted provided that the following conditions are met:
<> 149:156823d33999 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer.
<> 149:156823d33999 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 18 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 19 * and/or other materials provided with the distribution.
<> 149:156823d33999 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 21 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 22 * without specific prior written permission.
<> 149:156823d33999 23 *
<> 149:156823d33999 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 34 *
<> 149:156823d33999 35 ******************************************************************************
<> 149:156823d33999 36 */
<> 149:156823d33999 37
<> 149:156823d33999 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 39 #ifndef __STM32L1xx_HAL_PWR_H
<> 149:156823d33999 40 #define __STM32L1xx_HAL_PWR_H
<> 149:156823d33999 41
<> 149:156823d33999 42 #ifdef __cplusplus
<> 149:156823d33999 43 extern "C" {
<> 149:156823d33999 44 #endif
<> 149:156823d33999 45
<> 149:156823d33999 46 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 47 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 48
<> 149:156823d33999 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 50 * @{
<> 149:156823d33999 51 */
<> 149:156823d33999 52
<> 149:156823d33999 53 /** @addtogroup PWR
<> 149:156823d33999 54 * @{
<> 149:156823d33999 55 */
<> 149:156823d33999 56
<> 149:156823d33999 57 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 58
<> 149:156823d33999 59 /** @defgroup PWR_Exported_Types PWR Exported Types
<> 149:156823d33999 60 * @{
<> 149:156823d33999 61 */
<> 149:156823d33999 62
<> 149:156823d33999 63 /**
<> 149:156823d33999 64 * @brief PWR PVD configuration structure definition
<> 149:156823d33999 65 */
<> 149:156823d33999 66 typedef struct
<> 149:156823d33999 67 {
<> 149:156823d33999 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
<> 149:156823d33999 69 This parameter can be a value of @ref PWR_PVD_detection_level */
<> 149:156823d33999 70
<> 149:156823d33999 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 149:156823d33999 72 This parameter can be a value of @ref PWR_PVD_Mode */
<> 149:156823d33999 73 }PWR_PVDTypeDef;
<> 149:156823d33999 74
<> 149:156823d33999 75 /**
<> 149:156823d33999 76 * @}
<> 149:156823d33999 77 */
<> 149:156823d33999 78
<> 149:156823d33999 79 /* Internal constants --------------------------------------------------------*/
<> 149:156823d33999 80
<> 149:156823d33999 81 /** @addtogroup PWR_Private_Constants
<> 149:156823d33999 82 * @{
<> 149:156823d33999 83 */
<> 149:156823d33999 84 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 149:156823d33999 85
<> 149:156823d33999 86 /**
<> 149:156823d33999 87 * @}
<> 149:156823d33999 88 */
<> 149:156823d33999 89
<> 149:156823d33999 90
<> 149:156823d33999 91
<> 149:156823d33999 92 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 93
<> 149:156823d33999 94 /** @defgroup PWR_Exported_Constants PWR Exported Constants
<> 149:156823d33999 95 * @{
<> 149:156823d33999 96 */
<> 149:156823d33999 97
<> 149:156823d33999 98 /** @defgroup PWR_register_alias_address PWR Register alias address
<> 149:156823d33999 99 * @{
<> 149:156823d33999 100 */
<> 149:156823d33999 101 /* ------------- PWR registers bit address in the alias region ---------------*/
<> 149:156823d33999 102 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
<> 149:156823d33999 103 #define PWR_CR_OFFSET 0x00
<> 149:156823d33999 104 #define PWR_CSR_OFFSET 0x04
<> 149:156823d33999 105 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
<> 149:156823d33999 106 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
<> 149:156823d33999 107 /**
<> 149:156823d33999 108 * @}
<> 149:156823d33999 109 */
<> 149:156823d33999 110
<> 149:156823d33999 111 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
<> 149:156823d33999 112 * @{
<> 149:156823d33999 113 */
<> 149:156823d33999 114 /* --- CR Register ---*/
<> 149:156823d33999 115 /* Alias word address of LPSDSR bit */
<> 149:156823d33999 116 #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR)
<> 149:156823d33999 117 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
<> 149:156823d33999 118
<> 149:156823d33999 119 /* Alias word address of DBP bit */
<> 149:156823d33999 120 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
<> 149:156823d33999 121 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
<> 149:156823d33999 122
<> 149:156823d33999 123 /* Alias word address of LPRUN bit */
<> 149:156823d33999 124 #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN)
<> 149:156823d33999 125 #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
<> 149:156823d33999 126
<> 149:156823d33999 127 /* Alias word address of PVDE bit */
<> 149:156823d33999 128 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
<> 149:156823d33999 129 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
<> 149:156823d33999 130
<> 149:156823d33999 131 /* Alias word address of FWU bit */
<> 149:156823d33999 132 #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU)
<> 149:156823d33999 133 #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
<> 149:156823d33999 134
<> 149:156823d33999 135 /* Alias word address of ULP bit */
<> 149:156823d33999 136 #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP)
<> 149:156823d33999 137 #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
<> 149:156823d33999 138 /**
<> 149:156823d33999 139 * @}
<> 149:156823d33999 140 */
<> 149:156823d33999 141
<> 149:156823d33999 142 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
<> 149:156823d33999 143 * @{
<> 149:156823d33999 144 */
<> 149:156823d33999 145
<> 149:156823d33999 146 /* --- CSR Register ---*/
<> 149:156823d33999 147 /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
<> 149:156823d33999 148 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
<> 149:156823d33999 149 /**
<> 149:156823d33999 150 * @}
<> 149:156823d33999 151 */
<> 149:156823d33999 152
<> 149:156823d33999 153 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
<> 149:156823d33999 154 * @{
<> 149:156823d33999 155 */
<> 149:156823d33999 156 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
<> 149:156823d33999 157 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
<> 149:156823d33999 158 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
<> 149:156823d33999 159 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
<> 149:156823d33999 160 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
<> 149:156823d33999 161 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
<> 149:156823d33999 162 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
<> 149:156823d33999 163 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
<> 149:156823d33999 164 (Compare internally to VREFINT) */
<> 149:156823d33999 165
<> 149:156823d33999 166 /**
<> 149:156823d33999 167 * @}
<> 149:156823d33999 168 */
<> 149:156823d33999 169
<> 149:156823d33999 170 /** @defgroup PWR_PVD_Mode PWR PVD Mode
<> 149:156823d33999 171 * @{
<> 149:156823d33999 172 */
<> 149:156823d33999 173 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
<> 149:156823d33999 174 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 149:156823d33999 175 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 149:156823d33999 176 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 149:156823d33999 177 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 149:156823d33999 178 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 149:156823d33999 179 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 149:156823d33999 180
<> 149:156823d33999 181 /**
<> 149:156823d33999 182 * @}
<> 149:156823d33999 183 */
<> 149:156823d33999 184
<> 149:156823d33999 185 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
<> 149:156823d33999 186 * @{
<> 149:156823d33999 187 */
<> 149:156823d33999 188 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
<> 149:156823d33999 189 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
<> 149:156823d33999 190
<> 149:156823d33999 191 /**
<> 149:156823d33999 192 * @}
<> 149:156823d33999 193 */
<> 149:156823d33999 194
<> 149:156823d33999 195 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
<> 149:156823d33999 196 * @{
<> 149:156823d33999 197 */
<> 149:156823d33999 198 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
<> 149:156823d33999 199 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
<> 149:156823d33999 200
<> 149:156823d33999 201 /**
<> 149:156823d33999 202 * @}
<> 149:156823d33999 203 */
<> 149:156823d33999 204
<> 149:156823d33999 205 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
<> 149:156823d33999 206 * @{
<> 149:156823d33999 207 */
<> 149:156823d33999 208 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
<> 149:156823d33999 209 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
<> 149:156823d33999 210
<> 149:156823d33999 211 /**
<> 149:156823d33999 212 * @}
<> 149:156823d33999 213 */
<> 149:156823d33999 214
<> 149:156823d33999 215 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
<> 149:156823d33999 216 * @{
<> 149:156823d33999 217 */
<> 149:156823d33999 218
<> 149:156823d33999 219 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
<> 149:156823d33999 220 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
<> 149:156823d33999 221 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
<> 149:156823d33999 222
<> 149:156823d33999 223
<> 149:156823d33999 224 /**
<> 149:156823d33999 225 * @}
<> 149:156823d33999 226 */
<> 149:156823d33999 227
<> 149:156823d33999 228 /** @defgroup PWR_Flag PWR Flag
<> 149:156823d33999 229 * @{
<> 149:156823d33999 230 */
<> 149:156823d33999 231 #define PWR_FLAG_WU PWR_CSR_WUF
<> 149:156823d33999 232 #define PWR_FLAG_SB PWR_CSR_SBF
<> 149:156823d33999 233 #define PWR_FLAG_PVDO PWR_CSR_PVDO
<> 149:156823d33999 234 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
<> 149:156823d33999 235 #define PWR_FLAG_VOS PWR_CSR_VOSF
<> 149:156823d33999 236 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
<> 149:156823d33999 237
<> 149:156823d33999 238 /**
<> 149:156823d33999 239 * @}
<> 149:156823d33999 240 */
<> 149:156823d33999 241
<> 149:156823d33999 242 /**
<> 149:156823d33999 243 * @}
<> 149:156823d33999 244 */
<> 149:156823d33999 245
<> 149:156823d33999 246 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 247 /** @defgroup PWR_Exported_Macros PWR Exported Macros
<> 149:156823d33999 248 * @{
<> 149:156823d33999 249 */
<> 149:156823d33999 250
<> 149:156823d33999 251 /** @brief macros configure the main internal regulator output voltage.
<> 149:156823d33999 252 * @param __REGULATOR__: specifies the regulator output voltage to achieve
<> 149:156823d33999 253 * a tradeoff between performance and power consumption when the device does
<> 149:156823d33999 254 * not operate at the maximum frequency (refer to the datasheets for more details).
<> 149:156823d33999 255 * This parameter can be one of the following values:
<> 149:156823d33999 256 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
<> 149:156823d33999 257 * System frequency up to 32 MHz.
<> 149:156823d33999 258 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
<> 149:156823d33999 259 * System frequency up to 16 MHz.
<> 149:156823d33999 260 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
<> 149:156823d33999 261 * System frequency up to 4.2 MHz
<> 149:156823d33999 262 * @retval None
<> 149:156823d33999 263 */
<> 149:156823d33999 264 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
<> 149:156823d33999 265
<> 149:156823d33999 266 /** @brief Check PWR flag is set or not.
<> 149:156823d33999 267 * @param __FLAG__: specifies the flag to check.
<> 149:156823d33999 268 * This parameter can be one of the following values:
<> 149:156823d33999 269 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
<> 149:156823d33999 270 * was received from the WKUP pin or from the RTC alarm (Alarm B),
<> 149:156823d33999 271 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
<> 149:156823d33999 272 * An additional wakeup event is detected if the WKUP pin is enabled
<> 149:156823d33999 273 * (by setting the EWUP bit) when the WKUP pin level is already high.
<> 149:156823d33999 274 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
<> 149:156823d33999 275 * resumed from StandBy mode.
<> 149:156823d33999 276 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
<> 149:156823d33999 277 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
<> 149:156823d33999 278 * For this reason, this bit is equal to 0 after Standby or reset
<> 149:156823d33999 279 * until the PVDE bit is set.
<> 149:156823d33999 280 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
<> 149:156823d33999 281 * This bit indicates the state of the internal voltage reference, VREFINT.
<> 149:156823d33999 282 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
<> 149:156823d33999 283 * the internal regulator to be ready after the voltage range is changed.
<> 149:156823d33999 284 * The VOSF bit indicates that the regulator has reached the voltage level
<> 149:156823d33999 285 * defined with bits VOS of PWR_CR register.
<> 149:156823d33999 286 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
<> 149:156823d33999 287 * mode, this bit stays at 1 until the regulator is ready in main mode.
<> 149:156823d33999 288 * A polling on this bit is recommended to wait for the regulator main mode.
<> 149:156823d33999 289 * This bit is reset by hardware when the regulator is ready.
<> 149:156823d33999 290 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 149:156823d33999 291 */
<> 149:156823d33999 292 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
<> 149:156823d33999 293
<> 149:156823d33999 294 /** @brief Clear the PWR's pending flags.
<> 149:156823d33999 295 * @param __FLAG__: specifies the flag to clear.
<> 149:156823d33999 296 * This parameter can be one of the following values:
<> 149:156823d33999 297 * @arg PWR_FLAG_WU: Wake Up flag
<> 149:156823d33999 298 * @arg PWR_FLAG_SB: StandBy flag
<> 149:156823d33999 299 */
<> 149:156823d33999 300 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
<> 149:156823d33999 301
<> 149:156823d33999 302 /**
<> 149:156823d33999 303 * @brief Enable interrupt on PVD Exti Line 16.
<> 149:156823d33999 304 * @retval None.
<> 149:156823d33999 305 */
<> 149:156823d33999 306 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 307
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @brief Disable interrupt on PVD Exti Line 16.
<> 149:156823d33999 310 * @retval None.
<> 149:156823d33999 311 */
<> 149:156823d33999 312 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 313
<> 149:156823d33999 314 /**
<> 149:156823d33999 315 * @brief Enable event on PVD Exti Line 16.
<> 149:156823d33999 316 * @retval None.
<> 149:156823d33999 317 */
<> 149:156823d33999 318 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 319
<> 149:156823d33999 320 /**
<> 149:156823d33999 321 * @brief Disable event on PVD Exti Line 16.
<> 149:156823d33999 322 * @retval None.
<> 149:156823d33999 323 */
<> 149:156823d33999 324 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 325
<> 149:156823d33999 326
<> 149:156823d33999 327 /**
<> 149:156823d33999 328 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 149:156823d33999 329 * @retval None.
<> 149:156823d33999 330 */
<> 149:156823d33999 331 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 332
<> 149:156823d33999 333
<> 149:156823d33999 334 /**
<> 149:156823d33999 335 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 149:156823d33999 336 * @retval None.
<> 149:156823d33999 337 */
<> 149:156823d33999 338 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 339
<> 149:156823d33999 340
<> 149:156823d33999 341 /**
<> 149:156823d33999 342 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 149:156823d33999 343 * @retval None.
<> 149:156823d33999 344 */
<> 149:156823d33999 345 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 346
<> 149:156823d33999 347 /**
<> 149:156823d33999 348 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 149:156823d33999 349 * @retval None.
<> 149:156823d33999 350 */
<> 149:156823d33999 351 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 352
<> 149:156823d33999 353 /**
<> 149:156823d33999 354 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
<> 149:156823d33999 355 * @retval None.
<> 149:156823d33999 356 */
<> 149:156823d33999 357 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 149:156823d33999 358 do { \
<> 149:156823d33999 359 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
<> 149:156823d33999 360 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
<> 149:156823d33999 361 } while(0)
<> 149:156823d33999 362
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 149:156823d33999 365 * @retval None.
<> 149:156823d33999 366 */
<> 149:156823d33999 367 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
<> 149:156823d33999 368 do { \
<> 149:156823d33999 369 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
<> 149:156823d33999 370 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
<> 149:156823d33999 371 } while(0)
<> 149:156823d33999 372
<> 149:156823d33999 373
<> 149:156823d33999 374
<> 149:156823d33999 375 /**
<> 149:156823d33999 376 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 149:156823d33999 377 * @retval EXTI PVD Line Status.
<> 149:156823d33999 378 */
<> 149:156823d33999 379 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 149:156823d33999 380
<> 149:156823d33999 381 /**
<> 149:156823d33999 382 * @brief Clear the PVD EXTI flag.
<> 149:156823d33999 383 * @retval None.
<> 149:156823d33999 384 */
<> 149:156823d33999 385 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 149:156823d33999 386
<> 149:156823d33999 387 /**
<> 149:156823d33999 388 * @brief Generate a Software interrupt on selected EXTI line.
<> 149:156823d33999 389 * @retval None.
<> 149:156823d33999 390 */
<> 149:156823d33999 391 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
<> 149:156823d33999 392
<> 149:156823d33999 393 /**
<> 149:156823d33999 394 * @}
<> 149:156823d33999 395 */
<> 149:156823d33999 396
<> 149:156823d33999 397 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 398 /** @defgroup PWR_Private_Macros PWR Private Macros
<> 149:156823d33999 399 * @{
<> 149:156823d33999 400 */
<> 149:156823d33999 401
<> 149:156823d33999 402 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 149:156823d33999 403 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 149:156823d33999 404 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 149:156823d33999 405 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 149:156823d33999 406
<> 149:156823d33999 407
<> 149:156823d33999 408 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 149:156823d33999 409 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 149:156823d33999 410 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 149:156823d33999 411 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 149:156823d33999 412
<> 149:156823d33999 413 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
<> 149:156823d33999 414 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
<> 149:156823d33999 415
<> 149:156823d33999 416
<> 149:156823d33999 417 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
<> 149:156823d33999 418
<> 149:156823d33999 419 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
<> 149:156823d33999 420
<> 149:156823d33999 421 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
<> 149:156823d33999 422 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
<> 149:156823d33999 423 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
<> 149:156823d33999 424
<> 149:156823d33999 425
<> 149:156823d33999 426 /**
<> 149:156823d33999 427 * @}
<> 149:156823d33999 428 */
<> 149:156823d33999 429
<> 149:156823d33999 430
<> 149:156823d33999 431
<> 149:156823d33999 432 /* Include PWR HAL Extension module */
<> 149:156823d33999 433 #include "stm32l1xx_hal_pwr_ex.h"
<> 149:156823d33999 434
<> 149:156823d33999 435 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 436
<> 149:156823d33999 437 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
<> 149:156823d33999 438 * @{
<> 149:156823d33999 439 */
<> 149:156823d33999 440
<> 149:156823d33999 441 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 149:156823d33999 442 * @{
<> 149:156823d33999 443 */
<> 149:156823d33999 444
<> 149:156823d33999 445 /* Initialization and de-initialization functions *******************************/
<> 149:156823d33999 446 void HAL_PWR_DeInit(void);
<> 149:156823d33999 447 void HAL_PWR_EnableBkUpAccess(void);
<> 149:156823d33999 448 void HAL_PWR_DisableBkUpAccess(void);
<> 149:156823d33999 449
<> 149:156823d33999 450 /**
<> 149:156823d33999 451 * @}
<> 149:156823d33999 452 */
<> 149:156823d33999 453
<> 149:156823d33999 454 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 149:156823d33999 455 * @{
<> 149:156823d33999 456 */
<> 149:156823d33999 457
<> 149:156823d33999 458 /* Peripheral Control functions ************************************************/
<> 149:156823d33999 459 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 149:156823d33999 460 void HAL_PWR_EnablePVD(void);
<> 149:156823d33999 461 void HAL_PWR_DisablePVD(void);
<> 149:156823d33999 462
<> 149:156823d33999 463 /* WakeUp pins configuration functions ****************************************/
<> 149:156823d33999 464 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
<> 149:156823d33999 465 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
<> 149:156823d33999 466
<> 149:156823d33999 467 /* Low Power modes configuration functions ************************************/
<> 149:156823d33999 468 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
<> 149:156823d33999 469 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
<> 149:156823d33999 470 void HAL_PWR_EnterSTANDBYMode(void);
<> 149:156823d33999 471
<> 149:156823d33999 472 void HAL_PWR_EnableSleepOnExit(void);
<> 149:156823d33999 473 void HAL_PWR_DisableSleepOnExit(void);
<> 149:156823d33999 474 void HAL_PWR_EnableSEVOnPend(void);
<> 149:156823d33999 475 void HAL_PWR_DisableSEVOnPend(void);
<> 149:156823d33999 476
<> 149:156823d33999 477
<> 149:156823d33999 478
<> 149:156823d33999 479 void HAL_PWR_PVD_IRQHandler(void);
<> 149:156823d33999 480 void HAL_PWR_PVDCallback(void);
<> 149:156823d33999 481 /**
<> 149:156823d33999 482 * @}
<> 149:156823d33999 483 */
<> 149:156823d33999 484
<> 149:156823d33999 485 /**
<> 149:156823d33999 486 * @}
<> 149:156823d33999 487 */
<> 149:156823d33999 488
<> 149:156823d33999 489 /**
<> 149:156823d33999 490 * @}
<> 149:156823d33999 491 */
<> 149:156823d33999 492
<> 149:156823d33999 493 /**
<> 149:156823d33999 494 * @}
<> 149:156823d33999 495 */
<> 149:156823d33999 496
<> 149:156823d33999 497 #ifdef __cplusplus
<> 149:156823d33999 498 }
<> 149:156823d33999 499 #endif
<> 149:156823d33999 500
<> 149:156823d33999 501
<> 149:156823d33999 502 #endif /* __STM32L1xx_HAL_PWR_H */
<> 149:156823d33999 503
<> 149:156823d33999 504 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/