pravin sarode / Mymbed-dev

MBED-DEV only fro Nucleo STM32F303K8T6

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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dac.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_dac.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DAC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F3xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F3xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f3xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DAC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup DAC_Exported_Types DAC Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 69 HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
<> 144:ef7eb2e8f9f7 70 HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
<> 144:ef7eb2e8f9f7 71 HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
<> 144:ef7eb2e8f9f7 72 HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 }HAL_DAC_StateTypeDef;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief DAC Configuration regular Channel structure definition
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef struct
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref DACEx_trigger_selection */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
<> 144:ef7eb2e8f9f7 85 This parameter can be a value of @ref DAC_output_buffer
<> 144:ef7eb2e8f9f7 86 For a given DAC channel, is this paramater applies then DAC_OutputSwitch
<> 144:ef7eb2e8f9f7 87 does not apply */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref DAC_OutputSwitch
<> 144:ef7eb2e8f9f7 91 For a given DAC channel, is this paramater applies then DAC_OutputBuffer
<> 144:ef7eb2e8f9f7 92 does not apply */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 }DAC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /**
<> 144:ef7eb2e8f9f7 97 * @brief DAC handle Structure definition
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 typedef struct __DAC_HandleTypeDef
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 DAC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 HAL_LockTypeDef Lock; /*!< DAC locking object */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 __IO uint32_t ErrorCode; /*!< DAC Error code */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 }DAC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 114 /**
<> 144:ef7eb2e8f9f7 115 * @}
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup DAC_Exported_Constants DAC Exported Constants
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @defgroup DAC_Error_Code DAC Error Code
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
<> 144:ef7eb2e8f9f7 127 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 128 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 129 #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @}
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 #define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
<> 144:ef7eb2e8f9f7 138 #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 139 #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 140 #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 141 #define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 142 #define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 143 #define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 144 #define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 145 #define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 146 #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 147 #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 148 #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
<> 144:ef7eb2e8f9f7 149 #define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
<> 144:ef7eb2e8f9f7 150 #define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
<> 144:ef7eb2e8f9f7 151 #define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
<> 144:ef7eb2e8f9f7 152 #define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
<> 144:ef7eb2e8f9f7 153 #define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
<> 144:ef7eb2e8f9f7 154 #define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
<> 144:ef7eb2e8f9f7 155 #define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
<> 144:ef7eb2e8f9f7 156 #define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
<> 144:ef7eb2e8f9f7 157 #define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
<> 144:ef7eb2e8f9f7 158 #define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
<> 144:ef7eb2e8f9f7 159 #define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
<> 144:ef7eb2e8f9f7 160 #define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /**
<> 144:ef7eb2e8f9f7 163 * @}
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** @defgroup DAC_output_buffer DAC output buffer
<> 144:ef7eb2e8f9f7 167 * @{
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 170 #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 177 /** @defgroup DAC_output_switch DAC output switch
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 #define DAC_OUTPUTSWITCH_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 181 #define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 188 /** @defgroup DAC_data_alignement DAC data alignement
<> 144:ef7eb2e8f9f7 189 * @{
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 #define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 192 #define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 193 #define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup DAC_flags_definition DAC flags definition
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 203 #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /** @defgroup DAC_interrupts_definition DAC interrupts definition
<> 144:ef7eb2e8f9f7 209 * @{
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 #define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
<> 144:ef7eb2e8f9f7 212 #define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @}
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /** @defgroup DAC_Exported_Macros DAC Exported Macros
<> 144:ef7eb2e8f9f7 225 * @{
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** @brief Reset DAC handle state
<> 144:ef7eb2e8f9f7 229 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 230 * @retval None
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /** @brief Enable the DAC channel
<> 144:ef7eb2e8f9f7 235 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 236 * @param __DAC_Channel__: specifies the DAC channel
<> 144:ef7eb2e8f9f7 237 * @retval None
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
<> 144:ef7eb2e8f9f7 240 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /** @brief Disable the DAC channel
<> 144:ef7eb2e8f9f7 243 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 244 * @param __DAC_Channel__: specifies the DAC channel.
<> 144:ef7eb2e8f9f7 245 * @retval None
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
<> 144:ef7eb2e8f9f7 248 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /** @brief Set DHR12R1 alignment
<> 144:ef7eb2e8f9f7 251 * @param __ALIGNMENT__: specifies the DAC alignment
<> 144:ef7eb2e8f9f7 252 * @retval None
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /** @brief Set DHR12R2 alignment
<> 144:ef7eb2e8f9f7 257 * @param __ALIGNMENT__: specifies the DAC alignment
<> 144:ef7eb2e8f9f7 258 * @retval None
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /** @brief Set DHR12RD alignment
<> 144:ef7eb2e8f9f7 263 * @param __ALIGNMENT__: specifies the DAC alignment
<> 144:ef7eb2e8f9f7 264 * @retval None
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** @brief Enable the DAC interrupt
<> 144:ef7eb2e8f9f7 269 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 270 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 271 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 272 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 273 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 274 * @retval None
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /** @brief Disable the DAC interrupt
<> 144:ef7eb2e8f9f7 279 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 280 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 281 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 282 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 283 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 284 * @retval None
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @brief Check whether the specified DAC interrupt source is enabled or not
<> 144:ef7eb2e8f9f7 289 * @param __HANDLE__: DAC handle
<> 144:ef7eb2e8f9f7 290 * @param __INTERRUPT__: DAC interrupt source to check
<> 144:ef7eb2e8f9f7 291 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 292 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 293 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 294 * @retval State of interruption (SET or RESET)
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /** @brief Get the selected DAC's flag status
<> 144:ef7eb2e8f9f7 299 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 300 * @param __FLAG__: specifies the DAC flag to get.
<> 144:ef7eb2e8f9f7 301 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 302 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 144:ef7eb2e8f9f7 303 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
<> 144:ef7eb2e8f9f7 304 * @retval None
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @brief Clear the DAC's flag
<> 144:ef7eb2e8f9f7 309 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 310 * @param __FLAG__: specifies the DAC flag to clear.
<> 144:ef7eb2e8f9f7 311 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 312 * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
<> 144:ef7eb2e8f9f7 313 * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
<> 144:ef7eb2e8f9f7 314 * @retval None
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @}
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /** @addtogroup DAC_Private_Macros
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
<> 144:ef7eb2e8f9f7 329 ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
<> 144:ef7eb2e8f9f7 330 ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
<> 144:ef7eb2e8f9f7 331 ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
<> 144:ef7eb2e8f9f7 332 ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
<> 144:ef7eb2e8f9f7 333 ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
<> 144:ef7eb2e8f9f7 334 ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
<> 144:ef7eb2e8f9f7 335 ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
<> 144:ef7eb2e8f9f7 336 ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
<> 144:ef7eb2e8f9f7 337 ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
<> 144:ef7eb2e8f9f7 338 ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
<> 144:ef7eb2e8f9f7 339 ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
<> 144:ef7eb2e8f9f7 340 ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
<> 144:ef7eb2e8f9f7 341 ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
<> 144:ef7eb2e8f9f7 342 ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
<> 144:ef7eb2e8f9f7 343 ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
<> 144:ef7eb2e8f9f7 344 ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
<> 144:ef7eb2e8f9f7 345 ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
<> 144:ef7eb2e8f9f7 346 ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
<> 144:ef7eb2e8f9f7 347 ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
<> 144:ef7eb2e8f9f7 348 ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
<> 144:ef7eb2e8f9f7 349 ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
<> 144:ef7eb2e8f9f7 350 ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
<> 144:ef7eb2e8f9f7 351 ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
<> 144:ef7eb2e8f9f7 354 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
<> 144:ef7eb2e8f9f7 357 #define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
<> 144:ef7eb2e8f9f7 358 ((STATE) == DAC_OUTPUTSWITCH_ENABLE))
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
<> 144:ef7eb2e8f9f7 361 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
<> 144:ef7eb2e8f9f7 362 ((ALIGN) == DAC_ALIGN_12B_L) || \
<> 144:ef7eb2e8f9f7 363 ((ALIGN) == DAC_ALIGN_8B_R))
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @}
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Include DAC HAL Extended module */
<> 144:ef7eb2e8f9f7 375 #include "stm32f3xx_hal_dac_ex.h"
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /** @addtogroup DAC_Exported_Functions
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /** @addtogroup DAC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 384 * @{
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 389 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 390 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /**
<> 144:ef7eb2e8f9f7 393 * @}
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** @addtogroup DAC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 397 * @{
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 400 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 401 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 402 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
<> 144:ef7eb2e8f9f7 403 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 404 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 405 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 408 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 409 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 410 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 411 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /**
<> 144:ef7eb2e8f9f7 414 * @}
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /** @addtogroup DAC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 418 * @{
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 421 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @}
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /** @addtogroup DAC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 428 * @{
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 431 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 432 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /**
<> 144:ef7eb2e8f9f7 435 * @}
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @}
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /**
<> 144:ef7eb2e8f9f7 443 * @}
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @}
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452 #endif
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 #endif /*__STM32F3xx_HAL_DAC_H */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/