pravin sarode / Mymbed-dev

MBED-DEV only fro Nucleo STM32F303K8T6

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.c@151:acf04f8e7d03, 2016-11-19 (annotated)

Committer:
pravinautosys
Date:
Sat Nov 19 10:38:54 2016 +0000
Revision:
151:acf04f8e7d03
Parent:
149:156823d33999 
MyMBED-DEVWithSTM32F303K8T6;

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UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_tim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Base Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Base Start
<> 144:ef7eb2e8f9f7 12 * + Time Base Start Interruption
<> 144:ef7eb2e8f9f7 13 * + Time Base Start DMA
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Initialization
<> 144:ef7eb2e8f9f7 15 * + Time Output Compare/PWM Channel Configuration
<> 144:ef7eb2e8f9f7 16 * + Time Output Compare/PWM Start
<> 144:ef7eb2e8f9f7 17 * + Time Output Compare/PWM Start Interruption
<> 144:ef7eb2e8f9f7 18 * + Time Output Compare/PWM Start DMA
<> 144:ef7eb2e8f9f7 19 * + Time Input Capture Initialization
<> 144:ef7eb2e8f9f7 20 * + Time Input Capture Channel Configuration
<> 144:ef7eb2e8f9f7 21 * + Time Input Capture Start
<> 144:ef7eb2e8f9f7 22 * + Time Input Capture Start Interruption
<> 144:ef7eb2e8f9f7 23 * + Time Input Capture Start DMA
<> 144:ef7eb2e8f9f7 24 * + Time One Pulse Initialization
<> 144:ef7eb2e8f9f7 25 * + Time One Pulse Channel Configuration
<> 144:ef7eb2e8f9f7 26 * + Time One Pulse Start
<> 144:ef7eb2e8f9f7 27 * + Time Encoder Interface Initialization
<> 144:ef7eb2e8f9f7 28 * + Time Encoder Interface Start
<> 144:ef7eb2e8f9f7 29 * + Time Encoder Interface Start Interruption
<> 144:ef7eb2e8f9f7 30 * + Time Encoder Interface Start DMA
<> 144:ef7eb2e8f9f7 31 * + Commutation Event configuration with Interruption and DMA
<> 144:ef7eb2e8f9f7 32 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 33 * + Time External Clock configuration
<> 144:ef7eb2e8f9f7 34 @verbatim
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 ##### TIMER Generic features #####
<> 144:ef7eb2e8f9f7 37 ==============================================================================
<> 144:ef7eb2e8f9f7 38 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 39 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<> 144:ef7eb2e8f9f7 41 counter clock frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 42 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 43 (++) Input Capture
<> 144:ef7eb2e8f9f7 44 (++) Output Compare
<> 144:ef7eb2e8f9f7 45 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 46 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 49 ==============================================================================
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 52 depending from feature used :
<> 144:ef7eb2e8f9f7 53 (++) Time Base : HAL_TIM_Base_MspInit()
<> 144:ef7eb2e8f9f7 54 (++) Input Capture : HAL_TIM_IC_MspInit()
<> 144:ef7eb2e8f9f7 55 (++) Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
<> 144:ef7eb2e8f9f7 62 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 63 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 64 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 68 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 70 any start function.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 73 Initialization function of this driver:
<> 144:ef7eb2e8f9f7 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<> 144:ef7eb2e8f9f7 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<> 144:ef7eb2e8f9f7 76 Output Compare signal.
<> 144:ef7eb2e8f9f7 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<> 144:ef7eb2e8f9f7 78 PWM signal.
<> 144:ef7eb2e8f9f7 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<> 144:ef7eb2e8f9f7 80 external signal.
<> 144:ef7eb2e8f9f7 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<> 144:ef7eb2e8f9f7 82 in One Pulse Mode.
<> 144:ef7eb2e8f9f7 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<> 144:ef7eb2e8f9f7 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<> 144:ef7eb2e8f9f7 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<> 144:ef7eb2e8f9f7 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<> 144:ef7eb2e8f9f7 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<> 144:ef7eb2e8f9f7 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<> 144:ef7eb2e8f9f7 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) The DMA Burst is managed with the two following functions:
<> 144:ef7eb2e8f9f7 94 HAL_TIM_DMABurst_WriteStart()
<> 144:ef7eb2e8f9f7 95 HAL_TIM_DMABurst_ReadStart()
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup TIM TIM
<> 144:ef7eb2e8f9f7 136 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @defgroup TIM_Private_Functions TIM Private Functions
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 152 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 153 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 154 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 155 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 156 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 157 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 158 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 159 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
<> 144:ef7eb2e8f9f7 160 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 163 TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @}
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup TIM_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<> 144:ef7eb2e8f9f7 176 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 177 *
<> 144:ef7eb2e8f9f7 178 @verbatim
<> 144:ef7eb2e8f9f7 179 ==============================================================================
<> 144:ef7eb2e8f9f7 180 ##### Time Base functions #####
<> 144:ef7eb2e8f9f7 181 ==============================================================================
<> 144:ef7eb2e8f9f7 182 [..]
<> 144:ef7eb2e8f9f7 183 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 184 (+) Initialize and configure the TIM base.
<> 144:ef7eb2e8f9f7 185 (+) De-initialize the TIM base.
<> 144:ef7eb2e8f9f7 186 (+) Start the Time Base.
<> 144:ef7eb2e8f9f7 187 (+) Stop the Time Base.
<> 144:ef7eb2e8f9f7 188 (+) Start the Time Base and enable interrupt.
<> 144:ef7eb2e8f9f7 189 (+) Stop the Time Base and disable interrupt.
<> 144:ef7eb2e8f9f7 190 (+) Start the Time Base and enable DMA transfer.
<> 144:ef7eb2e8f9f7 191 (+) Stop the Time Base and disable DMA transfer.
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 @endverbatim
<> 144:ef7eb2e8f9f7 194 * @{
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @brief Initializes the TIM Time base Unit according to the specified
<> 144:ef7eb2e8f9f7 198 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 199 * @param htim: TIM Base handle
<> 144:ef7eb2e8f9f7 200 * @retval HAL status
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 205 if(htim == NULL)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Check the parameters */
<> 144:ef7eb2e8f9f7 211 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 212 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 213 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 218 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 221 HAL_TIM_Base_MspInit(htim);
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 225 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Set the Time Base configuration */
<> 144:ef7eb2e8f9f7 228 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 231 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 return HAL_OK;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @brief DeInitializes the TIM Base peripheral
<> 144:ef7eb2e8f9f7 238 * @param htim: TIM Base handle
<> 144:ef7eb2e8f9f7 239 * @retval HAL status
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 /* Check the parameters */
<> 144:ef7eb2e8f9f7 244 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 249 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 252 HAL_TIM_Base_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Change TIM state */
<> 144:ef7eb2e8f9f7 255 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Release Lock */
<> 144:ef7eb2e8f9f7 258 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 return HAL_OK;
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief Initializes the TIM Base MSP.
<> 144:ef7eb2e8f9f7 265 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 271 UNUSED(htim);
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 274 the HAL_TIM_Base_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief DeInitializes TIM Base MSP.
<> 144:ef7eb2e8f9f7 280 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 281 * @retval None
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 286 UNUSED(htim);
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 289 the HAL_TIM_Base_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Starts the TIM Base generation.
<> 144:ef7eb2e8f9f7 296 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 297 * @retval HAL status
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 /* Check the parameters */
<> 144:ef7eb2e8f9f7 302 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 305 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 308 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 311 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Return function status */
<> 144:ef7eb2e8f9f7 314 return HAL_OK;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Stops the TIM Base generation.
<> 144:ef7eb2e8f9f7 319 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 320 * @retval HAL status
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Check the parameters */
<> 144:ef7eb2e8f9f7 325 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 328 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 331 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 334 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Return function status */
<> 144:ef7eb2e8f9f7 337 return HAL_OK;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /**
<> 144:ef7eb2e8f9f7 341 * @brief Starts the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 342 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 343 * @retval HAL status
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 /* Check the parameters */
<> 144:ef7eb2e8f9f7 348 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Enable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 351 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 354 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Return function status */
<> 144:ef7eb2e8f9f7 357 return HAL_OK;
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @brief Stops the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 362 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 363 * @retval HAL status
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 /* Check the parameters */
<> 144:ef7eb2e8f9f7 368 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 369 /* Disable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 370 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 373 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Return function status */
<> 144:ef7eb2e8f9f7 376 return HAL_OK;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief Starts the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 381 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 382 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 383 * @param Length: The length of data to be transferred from memory to peripheral.
<> 144:ef7eb2e8f9f7 384 * @retval HAL status
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Check the parameters */
<> 144:ef7eb2e8f9f7 389 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 407 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 410 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 413 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Enable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 416 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 419 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Return function status */
<> 144:ef7eb2e8f9f7 422 return HAL_OK;
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /**
<> 144:ef7eb2e8f9f7 426 * @brief Stops the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 427 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 428 * @retval HAL status
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 /* Check the parameters */
<> 144:ef7eb2e8f9f7 433 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 436 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 439 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Change the htim state */
<> 144:ef7eb2e8f9f7 442 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Return function status */
<> 144:ef7eb2e8f9f7 445 return HAL_OK;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /**
<> 144:ef7eb2e8f9f7 449 * @}
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<> 144:ef7eb2e8f9f7 453 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 454 *
<> 144:ef7eb2e8f9f7 455 @verbatim
<> 144:ef7eb2e8f9f7 456 ==============================================================================
<> 144:ef7eb2e8f9f7 457 ##### Time Output Compare functions #####
<> 144:ef7eb2e8f9f7 458 ==============================================================================
<> 144:ef7eb2e8f9f7 459 [..]
<> 144:ef7eb2e8f9f7 460 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 461 (+) Initialize and configure the TIM Output Compare.
<> 144:ef7eb2e8f9f7 462 (+) De-initialize the TIM Output Compare.
<> 144:ef7eb2e8f9f7 463 (+) Start the Time Output Compare.
<> 144:ef7eb2e8f9f7 464 (+) Stop the Time Output Compare.
<> 144:ef7eb2e8f9f7 465 (+) Start the Time Output Compare and enable interrupt.
<> 144:ef7eb2e8f9f7 466 (+) Stop the Time Output Compare and disable interrupt.
<> 144:ef7eb2e8f9f7 467 (+) Start the Time Output Compare and enable DMA transfer.
<> 144:ef7eb2e8f9f7 468 (+) Stop the Time Output Compare and disable DMA transfer.
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 @endverbatim
<> 144:ef7eb2e8f9f7 471 * @{
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 /**
<> 144:ef7eb2e8f9f7 474 * @brief Initializes the TIM Output Compare according to the specified
<> 144:ef7eb2e8f9f7 475 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 476 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 477 * @retval HAL status
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 482 if(htim == NULL)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Check the parameters */
<> 144:ef7eb2e8f9f7 488 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 489 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 490 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 495 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 498 HAL_TIM_OC_MspInit(htim);
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 502 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Init the base time for the Output Compare */
<> 144:ef7eb2e8f9f7 505 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 508 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 return HAL_OK;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 515 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 516 * @retval HAL status
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 /* Check the parameters */
<> 144:ef7eb2e8f9f7 521 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 526 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 529 HAL_TIM_OC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Change TIM state */
<> 144:ef7eb2e8f9f7 532 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Release Lock */
<> 144:ef7eb2e8f9f7 535 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 return HAL_OK;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /**
<> 144:ef7eb2e8f9f7 541 * @brief Initializes the TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 542 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 543 * @retval None
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 548 UNUSED(htim);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 551 the HAL_TIM_OC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /**
<> 144:ef7eb2e8f9f7 556 * @brief DeInitializes TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 557 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 558 * @retval None
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 563 UNUSED(htim);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 566 the HAL_TIM_OC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @brief Starts the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 572 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 573 * @param Channel: TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 574 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 575 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 576 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 577 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 578 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 579 * @retval HAL status
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 /* Check the parameters */
<> 144:ef7eb2e8f9f7 584 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 587 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Enable the main output */
<> 144:ef7eb2e8f9f7 592 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 596 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Return function status */
<> 144:ef7eb2e8f9f7 599 return HAL_OK;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @brief Stops the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 604 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 605 * @param Channel: TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 606 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 607 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 608 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 609 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 610 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 611 * @retval HAL status
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 /* Check the parameters */
<> 144:ef7eb2e8f9f7 616 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 619 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 624 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 628 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Return function status */
<> 144:ef7eb2e8f9f7 631 return HAL_OK;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /**
<> 144:ef7eb2e8f9f7 635 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 636 * @param htim: TIM OC handle
<> 144:ef7eb2e8f9f7 637 * @param Channel: TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 638 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 643 * @retval HAL status
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 /* Check the parameters */
<> 144:ef7eb2e8f9f7 648 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 switch (Channel)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657 break;
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 break;
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671 break;
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678 break;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 default:
<> 144:ef7eb2e8f9f7 681 break;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 685 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 /* Enable the main output */
<> 144:ef7eb2e8f9f7 690 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 694 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Return function status */
<> 144:ef7eb2e8f9f7 697 return HAL_OK;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 702 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 703 * @param Channel: TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 704 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 709 * @retval HAL status
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Check the parameters */
<> 144:ef7eb2e8f9f7 714 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 switch (Channel)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 721 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723 break;
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 break;
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737 break;
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 742 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 743 }
<> 144:ef7eb2e8f9f7 744 break;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 default:
<> 144:ef7eb2e8f9f7 747 break;
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 751 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 754 {
<> 144:ef7eb2e8f9f7 755 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 756 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 760 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Return function status */
<> 144:ef7eb2e8f9f7 763 return HAL_OK;
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @brief Starts the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 768 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 769 * @param Channel: TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 770 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 773 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 774 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 775 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 776 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 777 * @retval HAL status
<> 144:ef7eb2e8f9f7 778 */
<> 144:ef7eb2e8f9f7 779 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* Check the parameters */
<> 144:ef7eb2e8f9f7 782 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 787 }
<> 144:ef7eb2e8f9f7 788 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794 else
<> 144:ef7eb2e8f9f7 795 {
<> 144:ef7eb2e8f9f7 796 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799 switch (Channel)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 804 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 807 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 810 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 813 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815 break;
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 820 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 823 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 826 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 829 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 830 }
<> 144:ef7eb2e8f9f7 831 break;
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 836 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 839 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 842 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847 break;
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 852 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 855 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 858 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 861 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 break;
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 default:
<> 144:ef7eb2e8f9f7 866 break;
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 870 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 /* Enable the main output */
<> 144:ef7eb2e8f9f7 875 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 879 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Return function status */
<> 144:ef7eb2e8f9f7 882 return HAL_OK;
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /**
<> 144:ef7eb2e8f9f7 886 * @brief Stops the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 887 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 888 * @param Channel: TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 889 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 890 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 891 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 892 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 893 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 894 * @retval HAL status
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 /* Check the parameters */
<> 144:ef7eb2e8f9f7 899 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 switch (Channel)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908 break;
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 913 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 break;
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 918 {
<> 144:ef7eb2e8f9f7 919 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922 break;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929 break;
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 default:
<> 144:ef7eb2e8f9f7 932 break;
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 936 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 939 {
<> 144:ef7eb2e8f9f7 940 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 941 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 942 }
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 945 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Change the htim state */
<> 144:ef7eb2e8f9f7 948 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Return function status */
<> 144:ef7eb2e8f9f7 951 return HAL_OK;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @}
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<> 144:ef7eb2e8f9f7 959 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 960 *
<> 144:ef7eb2e8f9f7 961 @verbatim
<> 144:ef7eb2e8f9f7 962 ==============================================================================
<> 144:ef7eb2e8f9f7 963 ##### Time PWM functions #####
<> 144:ef7eb2e8f9f7 964 ==============================================================================
<> 144:ef7eb2e8f9f7 965 [..]
<> 144:ef7eb2e8f9f7 966 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 967 (+) Initialize and configure the TIM OPWM.
<> 144:ef7eb2e8f9f7 968 (+) De-initialize the TIM PWM.
<> 144:ef7eb2e8f9f7 969 (+) Start the Time PWM.
<> 144:ef7eb2e8f9f7 970 (+) Stop the Time PWM.
<> 144:ef7eb2e8f9f7 971 (+) Start the Time PWM and enable interrupt.
<> 144:ef7eb2e8f9f7 972 (+) Stop the Time PWM and disable interrupt.
<> 144:ef7eb2e8f9f7 973 (+) Start the Time PWM and enable DMA transfer.
<> 144:ef7eb2e8f9f7 974 (+) Stop the Time PWM and disable DMA transfer.
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 @endverbatim
<> 144:ef7eb2e8f9f7 977 * @{
<> 144:ef7eb2e8f9f7 978 */
<> 144:ef7eb2e8f9f7 979 /**
<> 144:ef7eb2e8f9f7 980 * @brief Initializes the TIM PWM Time Base according to the specified
<> 144:ef7eb2e8f9f7 981 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 982 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 983 * @retval HAL status
<> 144:ef7eb2e8f9f7 984 */
<> 144:ef7eb2e8f9f7 985 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 988 if(htim == NULL)
<> 144:ef7eb2e8f9f7 989 {
<> 144:ef7eb2e8f9f7 990 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /* Check the parameters */
<> 144:ef7eb2e8f9f7 994 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 995 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 996 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1001 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1004 HAL_TIM_PWM_MspInit(htim);
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1008 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Init the base time for the PWM */
<> 144:ef7eb2e8f9f7 1011 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1014 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 return HAL_OK;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /**
<> 144:ef7eb2e8f9f7 1020 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1021 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1022 * @retval HAL status
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1025 {
<> 144:ef7eb2e8f9f7 1026 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1027 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1032 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1035 HAL_TIM_PWM_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1038 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /* Release Lock */
<> 144:ef7eb2e8f9f7 1041 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 return HAL_OK;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /**
<> 144:ef7eb2e8f9f7 1047 * @brief Initializes the TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1048 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1049 * @retval None
<> 144:ef7eb2e8f9f7 1050 */
<> 144:ef7eb2e8f9f7 1051 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1052 {
<> 144:ef7eb2e8f9f7 1053 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1054 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1057 the HAL_TIM_PWM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1058 */
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /**
<> 144:ef7eb2e8f9f7 1062 * @brief DeInitializes TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1063 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1064 * @retval None
<> 144:ef7eb2e8f9f7 1065 */
<> 144:ef7eb2e8f9f7 1066 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1069 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1072 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1073 */
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @brief Starts the PWM signal generation.
<> 144:ef7eb2e8f9f7 1078 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1079 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1080 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1081 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1082 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1083 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1084 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1085 * @retval HAL status
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1090 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1093 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1096 {
<> 144:ef7eb2e8f9f7 1097 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1098 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1102 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /* Return function status */
<> 144:ef7eb2e8f9f7 1105 return HAL_OK;
<> 144:ef7eb2e8f9f7 1106 }
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /**
<> 144:ef7eb2e8f9f7 1109 * @brief Stops the PWM signal generation.
<> 144:ef7eb2e8f9f7 1110 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1111 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1112 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1115 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1116 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1117 * @retval HAL status
<> 144:ef7eb2e8f9f7 1118 */
<> 144:ef7eb2e8f9f7 1119 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1120 {
<> 144:ef7eb2e8f9f7 1121 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1122 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1125 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1130 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1134 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1137 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Return function status */
<> 144:ef7eb2e8f9f7 1140 return HAL_OK;
<> 144:ef7eb2e8f9f7 1141 }
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 /**
<> 144:ef7eb2e8f9f7 1144 * @brief Starts the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1145 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1146 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1147 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1148 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1149 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1150 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1151 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1152 * @retval HAL status
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1157 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 switch (Channel)
<> 144:ef7eb2e8f9f7 1160 {
<> 144:ef7eb2e8f9f7 1161 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1164 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1165 }
<> 144:ef7eb2e8f9f7 1166 break;
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1169 {
<> 144:ef7eb2e8f9f7 1170 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1171 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173 break;
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1176 {
<> 144:ef7eb2e8f9f7 1177 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1178 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1179 }
<> 144:ef7eb2e8f9f7 1180 break;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1183 {
<> 144:ef7eb2e8f9f7 1184 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1185 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 break;
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 default:
<> 144:ef7eb2e8f9f7 1190 break;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1194 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1197 {
<> 144:ef7eb2e8f9f7 1198 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1199 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1200 }
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1203 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Return function status */
<> 144:ef7eb2e8f9f7 1206 return HAL_OK;
<> 144:ef7eb2e8f9f7 1207 }
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @brief Stops the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1211 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1212 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1213 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1214 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1215 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1216 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1217 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1218 * @retval HAL status
<> 144:ef7eb2e8f9f7 1219 */
<> 144:ef7eb2e8f9f7 1220 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1221 {
<> 144:ef7eb2e8f9f7 1222 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1223 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 switch (Channel)
<> 144:ef7eb2e8f9f7 1226 {
<> 144:ef7eb2e8f9f7 1227 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1228 {
<> 144:ef7eb2e8f9f7 1229 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1230 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1231 }
<> 144:ef7eb2e8f9f7 1232 break;
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1235 {
<> 144:ef7eb2e8f9f7 1236 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1237 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1238 }
<> 144:ef7eb2e8f9f7 1239 break;
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1244 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1245 }
<> 144:ef7eb2e8f9f7 1246 break;
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1251 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253 break;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 default:
<> 144:ef7eb2e8f9f7 1256 break;
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1260 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1263 {
<> 144:ef7eb2e8f9f7 1264 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1265 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1269 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /* Return function status */
<> 144:ef7eb2e8f9f7 1272 return HAL_OK;
<> 144:ef7eb2e8f9f7 1273 }
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /**
<> 144:ef7eb2e8f9f7 1276 * @brief Starts the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1277 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1278 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1279 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1280 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1281 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1282 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1283 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1284 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1285 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1286 * @retval HAL status
<> 144:ef7eb2e8f9f7 1287 */
<> 144:ef7eb2e8f9f7 1288 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1289 {
<> 144:ef7eb2e8f9f7 1290 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1291 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1294 {
<> 144:ef7eb2e8f9f7 1295 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1298 {
<> 144:ef7eb2e8f9f7 1299 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1300 {
<> 144:ef7eb2e8f9f7 1301 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1302 }
<> 144:ef7eb2e8f9f7 1303 else
<> 144:ef7eb2e8f9f7 1304 {
<> 144:ef7eb2e8f9f7 1305 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1306 }
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308 switch (Channel)
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1313 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1316 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1319 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1322 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1323 }
<> 144:ef7eb2e8f9f7 1324 break;
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1327 {
<> 144:ef7eb2e8f9f7 1328 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1329 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1332 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1335 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1338 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1339 }
<> 144:ef7eb2e8f9f7 1340 break;
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1343 {
<> 144:ef7eb2e8f9f7 1344 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1345 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1348 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1351 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Enable the TIM Output Capture/Compare 3 request */
<> 144:ef7eb2e8f9f7 1354 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1355 }
<> 144:ef7eb2e8f9f7 1356 break;
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1359 {
<> 144:ef7eb2e8f9f7 1360 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1361 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1364 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1365
<> 144:ef7eb2e8f9f7 1366 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1367 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1370 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1371 }
<> 144:ef7eb2e8f9f7 1372 break;
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 default:
<> 144:ef7eb2e8f9f7 1375 break;
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1379 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1382 {
<> 144:ef7eb2e8f9f7 1383 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1384 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1388 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Return function status */
<> 144:ef7eb2e8f9f7 1391 return HAL_OK;
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /**
<> 144:ef7eb2e8f9f7 1395 * @brief Stops the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1396 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1397 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1398 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1401 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1402 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1403 * @retval HAL status
<> 144:ef7eb2e8f9f7 1404 */
<> 144:ef7eb2e8f9f7 1405 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1406 {
<> 144:ef7eb2e8f9f7 1407 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1408 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 switch (Channel)
<> 144:ef7eb2e8f9f7 1411 {
<> 144:ef7eb2e8f9f7 1412 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1413 {
<> 144:ef7eb2e8f9f7 1414 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1415 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1416 }
<> 144:ef7eb2e8f9f7 1417 break;
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1420 {
<> 144:ef7eb2e8f9f7 1421 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1422 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1423 }
<> 144:ef7eb2e8f9f7 1424 break;
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1427 {
<> 144:ef7eb2e8f9f7 1428 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1429 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431 break;
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1434 {
<> 144:ef7eb2e8f9f7 1435 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1436 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1437 }
<> 144:ef7eb2e8f9f7 1438 break;
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 default:
<> 144:ef7eb2e8f9f7 1441 break;
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1445 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1448 {
<> 144:ef7eb2e8f9f7 1449 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1450 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1451 }
<> 144:ef7eb2e8f9f7 1452
<> 144:ef7eb2e8f9f7 1453 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1454 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1457 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /* Return function status */
<> 144:ef7eb2e8f9f7 1460 return HAL_OK;
<> 144:ef7eb2e8f9f7 1461 }
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 /**
<> 144:ef7eb2e8f9f7 1464 * @}
<> 144:ef7eb2e8f9f7 1465 */
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<> 144:ef7eb2e8f9f7 1468 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1469 *
<> 144:ef7eb2e8f9f7 1470 @verbatim
<> 144:ef7eb2e8f9f7 1471 ==============================================================================
<> 144:ef7eb2e8f9f7 1472 ##### Time Input Capture functions #####
<> 144:ef7eb2e8f9f7 1473 ==============================================================================
<> 144:ef7eb2e8f9f7 1474 [..]
<> 144:ef7eb2e8f9f7 1475 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1476 (+) Initialize and configure the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1477 (+) De-initialize the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1478 (+) Start the Time Input Capture.
<> 144:ef7eb2e8f9f7 1479 (+) Stop the Time Input Capture.
<> 144:ef7eb2e8f9f7 1480 (+) Start the Time Input Capture and enable interrupt.
<> 144:ef7eb2e8f9f7 1481 (+) Stop the Time Input Capture and disable interrupt.
<> 144:ef7eb2e8f9f7 1482 (+) Start the Time Input Capture and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1483 (+) Stop the Time Input Capture and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 @endverbatim
<> 144:ef7eb2e8f9f7 1486 * @{
<> 144:ef7eb2e8f9f7 1487 */
<> 144:ef7eb2e8f9f7 1488 /**
<> 144:ef7eb2e8f9f7 1489 * @brief Initializes the TIM Input Capture Time base according to the specified
<> 144:ef7eb2e8f9f7 1490 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1491 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1492 * @retval HAL status
<> 144:ef7eb2e8f9f7 1493 */
<> 144:ef7eb2e8f9f7 1494 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1495 {
<> 144:ef7eb2e8f9f7 1496 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1497 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1498 {
<> 144:ef7eb2e8f9f7 1499 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1500 }
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1503 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1504 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1505 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1508 {
<> 144:ef7eb2e8f9f7 1509 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1510 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1513 HAL_TIM_IC_MspInit(htim);
<> 144:ef7eb2e8f9f7 1514 }
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1517 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 /* Init the base time for the input capture */
<> 144:ef7eb2e8f9f7 1520 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1523 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 return HAL_OK;
<> 144:ef7eb2e8f9f7 1526 }
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 /**
<> 144:ef7eb2e8f9f7 1529 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1530 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1531 * @retval HAL status
<> 144:ef7eb2e8f9f7 1532 */
<> 144:ef7eb2e8f9f7 1533 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1534 {
<> 144:ef7eb2e8f9f7 1535 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1536 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1541 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1544 HAL_TIM_IC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1545
<> 144:ef7eb2e8f9f7 1546 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1547 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 /* Release Lock */
<> 144:ef7eb2e8f9f7 1550 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 return HAL_OK;
<> 144:ef7eb2e8f9f7 1553 }
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 /**
<> 144:ef7eb2e8f9f7 1556 * @brief Initializes the TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1557 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1558 * @retval None
<> 144:ef7eb2e8f9f7 1559 */
<> 144:ef7eb2e8f9f7 1560 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1561 {
<> 144:ef7eb2e8f9f7 1562 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1563 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1566 the HAL_TIM_IC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1567 */
<> 144:ef7eb2e8f9f7 1568 }
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /**
<> 144:ef7eb2e8f9f7 1571 * @brief DeInitializes TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1572 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1573 * @retval None
<> 144:ef7eb2e8f9f7 1574 */
<> 144:ef7eb2e8f9f7 1575 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1576 {
<> 144:ef7eb2e8f9f7 1577 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1578 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1581 the HAL_TIM_IC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1582 */
<> 144:ef7eb2e8f9f7 1583 }
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /**
<> 144:ef7eb2e8f9f7 1586 * @brief Starts the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1587 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1588 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1589 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1590 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1591 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1592 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1593 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1594 * @retval HAL status
<> 144:ef7eb2e8f9f7 1595 */
<> 144:ef7eb2e8f9f7 1596 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1597 {
<> 144:ef7eb2e8f9f7 1598 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1599 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1602 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1605 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /* Return function status */
<> 144:ef7eb2e8f9f7 1608 return HAL_OK;
<> 144:ef7eb2e8f9f7 1609 }
<> 144:ef7eb2e8f9f7 1610
<> 144:ef7eb2e8f9f7 1611 /**
<> 144:ef7eb2e8f9f7 1612 * @brief Stops the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1613 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1614 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1615 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1620 * @retval HAL status
<> 144:ef7eb2e8f9f7 1621 */
<> 144:ef7eb2e8f9f7 1622 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1623 {
<> 144:ef7eb2e8f9f7 1624 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1625 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1631 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /* Return function status */
<> 144:ef7eb2e8f9f7 1634 return HAL_OK;
<> 144:ef7eb2e8f9f7 1635 }
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /**
<> 144:ef7eb2e8f9f7 1638 * @brief Starts the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1639 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1640 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1641 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1642 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1643 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1644 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1645 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1646 * @retval HAL status
<> 144:ef7eb2e8f9f7 1647 */
<> 144:ef7eb2e8f9f7 1648 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1649 {
<> 144:ef7eb2e8f9f7 1650 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1651 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 switch (Channel)
<> 144:ef7eb2e8f9f7 1654 {
<> 144:ef7eb2e8f9f7 1655 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1656 {
<> 144:ef7eb2e8f9f7 1657 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1658 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1659 }
<> 144:ef7eb2e8f9f7 1660 break;
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1663 {
<> 144:ef7eb2e8f9f7 1664 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1666 }
<> 144:ef7eb2e8f9f7 1667 break;
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1670 {
<> 144:ef7eb2e8f9f7 1671 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1672 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1673 }
<> 144:ef7eb2e8f9f7 1674 break;
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1677 {
<> 144:ef7eb2e8f9f7 1678 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1679 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1680 }
<> 144:ef7eb2e8f9f7 1681 break;
<> 144:ef7eb2e8f9f7 1682
<> 144:ef7eb2e8f9f7 1683 default:
<> 144:ef7eb2e8f9f7 1684 break;
<> 144:ef7eb2e8f9f7 1685 }
<> 144:ef7eb2e8f9f7 1686 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1687 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1690 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1691
<> 144:ef7eb2e8f9f7 1692 /* Return function status */
<> 144:ef7eb2e8f9f7 1693 return HAL_OK;
<> 144:ef7eb2e8f9f7 1694 }
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /**
<> 144:ef7eb2e8f9f7 1697 * @brief Stops the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1698 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1699 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1700 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1701 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1702 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1703 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1704 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1705 * @retval HAL status
<> 144:ef7eb2e8f9f7 1706 */
<> 144:ef7eb2e8f9f7 1707 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1708 {
<> 144:ef7eb2e8f9f7 1709 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1710 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 switch (Channel)
<> 144:ef7eb2e8f9f7 1713 {
<> 144:ef7eb2e8f9f7 1714 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1715 {
<> 144:ef7eb2e8f9f7 1716 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1717 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1718 }
<> 144:ef7eb2e8f9f7 1719 break;
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1722 {
<> 144:ef7eb2e8f9f7 1723 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1724 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1725 }
<> 144:ef7eb2e8f9f7 1726 break;
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1729 {
<> 144:ef7eb2e8f9f7 1730 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1731 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1732 }
<> 144:ef7eb2e8f9f7 1733 break;
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1736 {
<> 144:ef7eb2e8f9f7 1737 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1738 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1739 }
<> 144:ef7eb2e8f9f7 1740 break;
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 default:
<> 144:ef7eb2e8f9f7 1743 break;
<> 144:ef7eb2e8f9f7 1744 }
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1747 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1748
<> 144:ef7eb2e8f9f7 1749 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1750 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1751
<> 144:ef7eb2e8f9f7 1752 /* Return function status */
<> 144:ef7eb2e8f9f7 1753 return HAL_OK;
<> 144:ef7eb2e8f9f7 1754 }
<> 144:ef7eb2e8f9f7 1755
<> 144:ef7eb2e8f9f7 1756 /**
<> 144:ef7eb2e8f9f7 1757 * @brief Starts the TIM Input Capture measurement in DMA mode.
<> 144:ef7eb2e8f9f7 1758 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1759 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 1760 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1761 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1762 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1763 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1764 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1765 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 1766 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 1767 * @retval HAL status
<> 144:ef7eb2e8f9f7 1768 */
<> 144:ef7eb2e8f9f7 1769 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1770 {
<> 144:ef7eb2e8f9f7 1771 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1772 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1773 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1776 {
<> 144:ef7eb2e8f9f7 1777 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1778 }
<> 144:ef7eb2e8f9f7 1779 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1780 {
<> 144:ef7eb2e8f9f7 1781 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1782 {
<> 144:ef7eb2e8f9f7 1783 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1784 }
<> 144:ef7eb2e8f9f7 1785 else
<> 144:ef7eb2e8f9f7 1786 {
<> 144:ef7eb2e8f9f7 1787 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1788 }
<> 144:ef7eb2e8f9f7 1789 }
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 switch (Channel)
<> 144:ef7eb2e8f9f7 1792 {
<> 144:ef7eb2e8f9f7 1793 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1794 {
<> 144:ef7eb2e8f9f7 1795 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1796 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1797
<> 144:ef7eb2e8f9f7 1798 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1799 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1802 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1805 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1806 }
<> 144:ef7eb2e8f9f7 1807 break;
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1810 {
<> 144:ef7eb2e8f9f7 1811 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1812 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1813
<> 144:ef7eb2e8f9f7 1814 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1815 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1816
<> 144:ef7eb2e8f9f7 1817 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1818 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1819
<> 144:ef7eb2e8f9f7 1820 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1821 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1822 }
<> 144:ef7eb2e8f9f7 1823 break;
<> 144:ef7eb2e8f9f7 1824
<> 144:ef7eb2e8f9f7 1825 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1826 {
<> 144:ef7eb2e8f9f7 1827 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1828 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1829
<> 144:ef7eb2e8f9f7 1830 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1831 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1832
<> 144:ef7eb2e8f9f7 1833 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1834 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1837 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839 break;
<> 144:ef7eb2e8f9f7 1840
<> 144:ef7eb2e8f9f7 1841 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1842 {
<> 144:ef7eb2e8f9f7 1843 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1844 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1845
<> 144:ef7eb2e8f9f7 1846 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1847 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1848
<> 144:ef7eb2e8f9f7 1849 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1850 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1853 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1854 }
<> 144:ef7eb2e8f9f7 1855 break;
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 default:
<> 144:ef7eb2e8f9f7 1858 break;
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1862 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1865 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1866
<> 144:ef7eb2e8f9f7 1867 /* Return function status */
<> 144:ef7eb2e8f9f7 1868 return HAL_OK;
<> 144:ef7eb2e8f9f7 1869 }
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 /**
<> 144:ef7eb2e8f9f7 1872 * @brief Stops the TIM Input Capture measurement in DMA mode.
<> 144:ef7eb2e8f9f7 1873 * @param htim: TIM Input Capture handle
<> 144:ef7eb2e8f9f7 1874 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 1875 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1878 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1879 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1880 * @retval HAL status
<> 144:ef7eb2e8f9f7 1881 */
<> 144:ef7eb2e8f9f7 1882 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1883 {
<> 144:ef7eb2e8f9f7 1884 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1885 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1886 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1887
<> 144:ef7eb2e8f9f7 1888 switch (Channel)
<> 144:ef7eb2e8f9f7 1889 {
<> 144:ef7eb2e8f9f7 1890 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1891 {
<> 144:ef7eb2e8f9f7 1892 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1893 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1894 }
<> 144:ef7eb2e8f9f7 1895 break;
<> 144:ef7eb2e8f9f7 1896
<> 144:ef7eb2e8f9f7 1897 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1898 {
<> 144:ef7eb2e8f9f7 1899 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1900 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1901 }
<> 144:ef7eb2e8f9f7 1902 break;
<> 144:ef7eb2e8f9f7 1903
<> 144:ef7eb2e8f9f7 1904 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1905 {
<> 144:ef7eb2e8f9f7 1906 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1907 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1908 }
<> 144:ef7eb2e8f9f7 1909 break;
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1912 {
<> 144:ef7eb2e8f9f7 1913 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1915 }
<> 144:ef7eb2e8f9f7 1916 break;
<> 144:ef7eb2e8f9f7 1917
<> 144:ef7eb2e8f9f7 1918 default:
<> 144:ef7eb2e8f9f7 1919 break;
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921
<> 144:ef7eb2e8f9f7 1922 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1923 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1926 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1927
<> 144:ef7eb2e8f9f7 1928 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1929 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1930
<> 144:ef7eb2e8f9f7 1931 /* Return function status */
<> 144:ef7eb2e8f9f7 1932 return HAL_OK;
<> 144:ef7eb2e8f9f7 1933 }
<> 144:ef7eb2e8f9f7 1934 /**
<> 144:ef7eb2e8f9f7 1935 * @}
<> 144:ef7eb2e8f9f7 1936 */
<> 144:ef7eb2e8f9f7 1937
<> 144:ef7eb2e8f9f7 1938 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<> 144:ef7eb2e8f9f7 1939 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1940 *
<> 144:ef7eb2e8f9f7 1941 @verbatim
<> 144:ef7eb2e8f9f7 1942 ==============================================================================
<> 144:ef7eb2e8f9f7 1943 ##### Time One Pulse functions #####
<> 144:ef7eb2e8f9f7 1944 ==============================================================================
<> 144:ef7eb2e8f9f7 1945 [..]
<> 144:ef7eb2e8f9f7 1946 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1947 (+) Initialize and configure the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1948 (+) De-initialize the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1949 (+) Start the Time One Pulse.
<> 144:ef7eb2e8f9f7 1950 (+) Stop the Time One Pulse.
<> 144:ef7eb2e8f9f7 1951 (+) Start the Time One Pulse and enable interrupt.
<> 144:ef7eb2e8f9f7 1952 (+) Stop the Time One Pulse and disable interrupt.
<> 144:ef7eb2e8f9f7 1953 (+) Start the Time One Pulse and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1954 (+) Stop the Time One Pulse and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1955
<> 144:ef7eb2e8f9f7 1956 @endverbatim
<> 144:ef7eb2e8f9f7 1957 * @{
<> 144:ef7eb2e8f9f7 1958 */
<> 144:ef7eb2e8f9f7 1959 /**
<> 144:ef7eb2e8f9f7 1960 * @brief Initializes the TIM One Pulse Time Base according to the specified
<> 144:ef7eb2e8f9f7 1961 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1962 * @param htim: TIM OnePulse handle
<> 144:ef7eb2e8f9f7 1963 * @param OnePulseMode: Select the One pulse mode.
<> 144:ef7eb2e8f9f7 1964 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1965 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<> 144:ef7eb2e8f9f7 1966 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
<> 144:ef7eb2e8f9f7 1967 * @retval HAL status
<> 144:ef7eb2e8f9f7 1968 */
<> 144:ef7eb2e8f9f7 1969 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<> 144:ef7eb2e8f9f7 1970 {
<> 144:ef7eb2e8f9f7 1971 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1972 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1973 {
<> 144:ef7eb2e8f9f7 1974 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1975 }
<> 144:ef7eb2e8f9f7 1976
<> 144:ef7eb2e8f9f7 1977 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1978 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1979 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1980 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1981 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<> 144:ef7eb2e8f9f7 1982
<> 144:ef7eb2e8f9f7 1983 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1984 {
<> 144:ef7eb2e8f9f7 1985 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1986 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1987
<> 144:ef7eb2e8f9f7 1988 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1989 HAL_TIM_OnePulse_MspInit(htim);
<> 144:ef7eb2e8f9f7 1990 }
<> 144:ef7eb2e8f9f7 1991
<> 144:ef7eb2e8f9f7 1992 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1993 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1994
<> 144:ef7eb2e8f9f7 1995 /* Configure the Time base in the One Pulse Mode */
<> 144:ef7eb2e8f9f7 1996 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1997
<> 144:ef7eb2e8f9f7 1998 /* Reset the OPM Bit */
<> 144:ef7eb2e8f9f7 1999 htim->Instance->CR1 &= ~TIM_CR1_OPM;
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /* Configure the OPM Mode */
<> 144:ef7eb2e8f9f7 2002 htim->Instance->CR1 |= OnePulseMode;
<> 144:ef7eb2e8f9f7 2003
<> 144:ef7eb2e8f9f7 2004 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2005 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2006
<> 144:ef7eb2e8f9f7 2007 return HAL_OK;
<> 144:ef7eb2e8f9f7 2008 }
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /**
<> 144:ef7eb2e8f9f7 2011 * @brief DeInitializes the TIM One Pulse
<> 144:ef7eb2e8f9f7 2012 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2013 * @retval HAL status
<> 144:ef7eb2e8f9f7 2014 */
<> 144:ef7eb2e8f9f7 2015 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2016 {
<> 144:ef7eb2e8f9f7 2017 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2018 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2019
<> 144:ef7eb2e8f9f7 2020 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2021
<> 144:ef7eb2e8f9f7 2022 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2023 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2024
<> 144:ef7eb2e8f9f7 2025 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2026 HAL_TIM_OnePulse_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2027
<> 144:ef7eb2e8f9f7 2028 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2029 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2030
<> 144:ef7eb2e8f9f7 2031 /* Release Lock */
<> 144:ef7eb2e8f9f7 2032 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2033
<> 144:ef7eb2e8f9f7 2034 return HAL_OK;
<> 144:ef7eb2e8f9f7 2035 }
<> 144:ef7eb2e8f9f7 2036
<> 144:ef7eb2e8f9f7 2037 /**
<> 144:ef7eb2e8f9f7 2038 * @brief Initializes the TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2039 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 2040 * @retval None
<> 144:ef7eb2e8f9f7 2041 */
<> 144:ef7eb2e8f9f7 2042 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2043 {
<> 144:ef7eb2e8f9f7 2044 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2045 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2046
<> 144:ef7eb2e8f9f7 2047 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2048 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2049 */
<> 144:ef7eb2e8f9f7 2050 }
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /**
<> 144:ef7eb2e8f9f7 2053 * @brief DeInitializes TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2054 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 2055 * @retval None
<> 144:ef7eb2e8f9f7 2056 */
<> 144:ef7eb2e8f9f7 2057 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2058 {
<> 144:ef7eb2e8f9f7 2059 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2060 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2061
<> 144:ef7eb2e8f9f7 2062 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2063 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2064 */
<> 144:ef7eb2e8f9f7 2065 }
<> 144:ef7eb2e8f9f7 2066
<> 144:ef7eb2e8f9f7 2067 /**
<> 144:ef7eb2e8f9f7 2068 * @brief Starts the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2069 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2070 * @param OutputChannel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2071 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2072 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2073 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2074 * @retval HAL status
<> 144:ef7eb2e8f9f7 2075 */
<> 144:ef7eb2e8f9f7 2076 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2077 {
<> 144:ef7eb2e8f9f7 2078 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2079 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2080 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2081 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2082 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2083
<> 144:ef7eb2e8f9f7 2084 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2085 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2088 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2089
<> 144:ef7eb2e8f9f7 2090 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2091 {
<> 144:ef7eb2e8f9f7 2092 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2093 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2094 }
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 /* Return function status */
<> 144:ef7eb2e8f9f7 2097 return HAL_OK;
<> 144:ef7eb2e8f9f7 2098 }
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /**
<> 144:ef7eb2e8f9f7 2101 * @brief Stops the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2102 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2103 * @param OutputChannel: TIM Channels to be disable
<> 144:ef7eb2e8f9f7 2104 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2105 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2106 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2107 * @retval HAL status
<> 144:ef7eb2e8f9f7 2108 */
<> 144:ef7eb2e8f9f7 2109 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2110 {
<> 144:ef7eb2e8f9f7 2111 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2112 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2113 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2114 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2115 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2116
<> 144:ef7eb2e8f9f7 2117 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2118 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2119
<> 144:ef7eb2e8f9f7 2120 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2121 {
<> 144:ef7eb2e8f9f7 2122 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 2123 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2124 }
<> 144:ef7eb2e8f9f7 2125
<> 144:ef7eb2e8f9f7 2126 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2127 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2128
<> 144:ef7eb2e8f9f7 2129 /* Return function status */
<> 144:ef7eb2e8f9f7 2130 return HAL_OK;
<> 144:ef7eb2e8f9f7 2131 }
<> 144:ef7eb2e8f9f7 2132
<> 144:ef7eb2e8f9f7 2133 /**
<> 144:ef7eb2e8f9f7 2134 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2135 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2136 * @param OutputChannel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2137 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2138 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2139 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2140 * @retval HAL status
<> 144:ef7eb2e8f9f7 2141 */
<> 144:ef7eb2e8f9f7 2142 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2143 {
<> 144:ef7eb2e8f9f7 2144 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2145 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2146 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2147 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2148 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2149
<> 144:ef7eb2e8f9f7 2150 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2151 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2152
<> 144:ef7eb2e8f9f7 2153 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2154 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2157 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2158
<> 144:ef7eb2e8f9f7 2159 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2160 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2163 {
<> 144:ef7eb2e8f9f7 2164 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2165 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2166 }
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 /* Return function status */
<> 144:ef7eb2e8f9f7 2169 return HAL_OK;
<> 144:ef7eb2e8f9f7 2170 }
<> 144:ef7eb2e8f9f7 2171
<> 144:ef7eb2e8f9f7 2172 /**
<> 144:ef7eb2e8f9f7 2173 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2174 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 2175 * @param OutputChannel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2176 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2177 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2178 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2179 * @retval HAL status
<> 144:ef7eb2e8f9f7 2180 */
<> 144:ef7eb2e8f9f7 2181 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2182 {
<> 144:ef7eb2e8f9f7 2183 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2184 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2187 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2188
<> 144:ef7eb2e8f9f7 2189 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2190 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2191 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2192 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2193 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2194 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2195 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2196
<> 144:ef7eb2e8f9f7 2197 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2198 {
<> 144:ef7eb2e8f9f7 2199 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 2200 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2201 }
<> 144:ef7eb2e8f9f7 2202
<> 144:ef7eb2e8f9f7 2203 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2204 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2205
<> 144:ef7eb2e8f9f7 2206 /* Return function status */
<> 144:ef7eb2e8f9f7 2207 return HAL_OK;
<> 144:ef7eb2e8f9f7 2208 }
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210 /**
<> 144:ef7eb2e8f9f7 2211 * @}
<> 144:ef7eb2e8f9f7 2212 */
<> 144:ef7eb2e8f9f7 2213
<> 144:ef7eb2e8f9f7 2214 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<> 144:ef7eb2e8f9f7 2215 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 2216 *
<> 144:ef7eb2e8f9f7 2217 @verbatim
<> 144:ef7eb2e8f9f7 2218 ==============================================================================
<> 144:ef7eb2e8f9f7 2219 ##### Time Encoder functions #####
<> 144:ef7eb2e8f9f7 2220 ==============================================================================
<> 144:ef7eb2e8f9f7 2221 [..]
<> 144:ef7eb2e8f9f7 2222 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2223 (+) Initialize and configure the TIM Encoder.
<> 144:ef7eb2e8f9f7 2224 (+) De-initialize the TIM Encoder.
<> 144:ef7eb2e8f9f7 2225 (+) Start the Time Encoder.
<> 144:ef7eb2e8f9f7 2226 (+) Stop the Time Encoder.
<> 144:ef7eb2e8f9f7 2227 (+) Start the Time Encoder and enable interrupt.
<> 144:ef7eb2e8f9f7 2228 (+) Stop the Time Encoder and disable interrupt.
<> 144:ef7eb2e8f9f7 2229 (+) Start the Time Encoder and enable DMA transfer.
<> 144:ef7eb2e8f9f7 2230 (+) Stop the Time Encoder and disable DMA transfer.
<> 144:ef7eb2e8f9f7 2231
<> 144:ef7eb2e8f9f7 2232 @endverbatim
<> 144:ef7eb2e8f9f7 2233 * @{
<> 144:ef7eb2e8f9f7 2234 */
<> 144:ef7eb2e8f9f7 2235 /**
<> 144:ef7eb2e8f9f7 2236 * @brief Initializes the TIM Encoder Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 2237 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2238 * @param sConfig: TIM Encoder Interface configuration structure
<> 144:ef7eb2e8f9f7 2239 * @retval HAL status
<> 144:ef7eb2e8f9f7 2240 */
<> 144:ef7eb2e8f9f7 2241 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 2242 {
<> 144:ef7eb2e8f9f7 2243 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 2244 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 2245 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2248 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2249 {
<> 144:ef7eb2e8f9f7 2250 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2251 }
<> 144:ef7eb2e8f9f7 2252
<> 144:ef7eb2e8f9f7 2253 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2254 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2255 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<> 144:ef7eb2e8f9f7 2256 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<> 144:ef7eb2e8f9f7 2257 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<> 144:ef7eb2e8f9f7 2258 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 2259 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<> 144:ef7eb2e8f9f7 2260 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 2261 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<> 144:ef7eb2e8f9f7 2262 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 2263 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<> 144:ef7eb2e8f9f7 2264
<> 144:ef7eb2e8f9f7 2265 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2266 {
<> 144:ef7eb2e8f9f7 2267 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2268 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2269
<> 144:ef7eb2e8f9f7 2270 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2271 HAL_TIM_Encoder_MspInit(htim);
<> 144:ef7eb2e8f9f7 2272 }
<> 144:ef7eb2e8f9f7 2273
<> 144:ef7eb2e8f9f7 2274 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2275 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2276
<> 144:ef7eb2e8f9f7 2277 /* Reset the SMS bits */
<> 144:ef7eb2e8f9f7 2278 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 2279
<> 144:ef7eb2e8f9f7 2280 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 2281 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2282
<> 144:ef7eb2e8f9f7 2283 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2284 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2285
<> 144:ef7eb2e8f9f7 2286 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2287 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 2288
<> 144:ef7eb2e8f9f7 2289 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2290 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /* Set the encoder Mode */
<> 144:ef7eb2e8f9f7 2293 tmpsmcr |= sConfig->EncoderMode;
<> 144:ef7eb2e8f9f7 2294
<> 144:ef7eb2e8f9f7 2295 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
<> 144:ef7eb2e8f9f7 2296 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
<> 144:ef7eb2e8f9f7 2297 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
<> 144:ef7eb2e8f9f7 2298
<> 144:ef7eb2e8f9f7 2299 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<> 144:ef7eb2e8f9f7 2300 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
<> 144:ef7eb2e8f9f7 2301 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 2302 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
<> 144:ef7eb2e8f9f7 2303 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
<> 144:ef7eb2e8f9f7 2304
<> 144:ef7eb2e8f9f7 2305 /* Set the TI1 and the TI2 Polarities */
<> 144:ef7eb2e8f9f7 2306 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
<> 144:ef7eb2e8f9f7 2307 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 2308 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
<> 144:ef7eb2e8f9f7 2309
<> 144:ef7eb2e8f9f7 2310 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 2311 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2312
<> 144:ef7eb2e8f9f7 2313 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 2314 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 2315
<> 144:ef7eb2e8f9f7 2316 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2317 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2318
<> 144:ef7eb2e8f9f7 2319 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2320 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2321
<> 144:ef7eb2e8f9f7 2322 return HAL_OK;
<> 144:ef7eb2e8f9f7 2323 }
<> 144:ef7eb2e8f9f7 2324
<> 144:ef7eb2e8f9f7 2325
<> 144:ef7eb2e8f9f7 2326 /**
<> 144:ef7eb2e8f9f7 2327 * @brief DeInitializes the TIM Encoder interface
<> 144:ef7eb2e8f9f7 2328 * @param htim: TIM Encoder handle
<> 144:ef7eb2e8f9f7 2329 * @retval HAL status
<> 144:ef7eb2e8f9f7 2330 */
<> 144:ef7eb2e8f9f7 2331 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2332 {
<> 144:ef7eb2e8f9f7 2333 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2334 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2335
<> 144:ef7eb2e8f9f7 2336 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2339 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2340
<> 144:ef7eb2e8f9f7 2341 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2342 HAL_TIM_Encoder_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2343
<> 144:ef7eb2e8f9f7 2344 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2345 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 /* Release Lock */
<> 144:ef7eb2e8f9f7 2348 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 return HAL_OK;
<> 144:ef7eb2e8f9f7 2351 }
<> 144:ef7eb2e8f9f7 2352
<> 144:ef7eb2e8f9f7 2353 /**
<> 144:ef7eb2e8f9f7 2354 * @brief Initializes the TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2355 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 2356 * @retval None
<> 144:ef7eb2e8f9f7 2357 */
<> 144:ef7eb2e8f9f7 2358 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2359 {
<> 144:ef7eb2e8f9f7 2360 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2361 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2362
<> 144:ef7eb2e8f9f7 2363 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2364 the HAL_TIM_Encoder_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2365 */
<> 144:ef7eb2e8f9f7 2366 }
<> 144:ef7eb2e8f9f7 2367
<> 144:ef7eb2e8f9f7 2368 /**
<> 144:ef7eb2e8f9f7 2369 * @brief DeInitializes TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2370 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 2371 * @retval None
<> 144:ef7eb2e8f9f7 2372 */
<> 144:ef7eb2e8f9f7 2373 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2374 {
<> 144:ef7eb2e8f9f7 2375 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2376 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2377
<> 144:ef7eb2e8f9f7 2378 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2379 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2380 */
<> 144:ef7eb2e8f9f7 2381 }
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /**
<> 144:ef7eb2e8f9f7 2384 * @brief Starts the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2385 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2386 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2387 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2388 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2389 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2390 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2391 * @retval HAL status
<> 144:ef7eb2e8f9f7 2392 */
<> 144:ef7eb2e8f9f7 2393 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2394 {
<> 144:ef7eb2e8f9f7 2395 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2396 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2397
<> 144:ef7eb2e8f9f7 2398 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2399 switch (Channel)
<> 144:ef7eb2e8f9f7 2400 {
<> 144:ef7eb2e8f9f7 2401 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2402 {
<> 144:ef7eb2e8f9f7 2403 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2404 break;
<> 144:ef7eb2e8f9f7 2405 }
<> 144:ef7eb2e8f9f7 2406 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2407 {
<> 144:ef7eb2e8f9f7 2408 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2409 break;
<> 144:ef7eb2e8f9f7 2410 }
<> 144:ef7eb2e8f9f7 2411 default :
<> 144:ef7eb2e8f9f7 2412 {
<> 144:ef7eb2e8f9f7 2413 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2415 break;
<> 144:ef7eb2e8f9f7 2416 }
<> 144:ef7eb2e8f9f7 2417 }
<> 144:ef7eb2e8f9f7 2418 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2419 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2420
<> 144:ef7eb2e8f9f7 2421 /* Return function status */
<> 144:ef7eb2e8f9f7 2422 return HAL_OK;
<> 144:ef7eb2e8f9f7 2423 }
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425 /**
<> 144:ef7eb2e8f9f7 2426 * @brief Stops the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2427 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2428 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 2429 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2430 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2431 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2432 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2433 * @retval HAL status
<> 144:ef7eb2e8f9f7 2434 */
<> 144:ef7eb2e8f9f7 2435 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2436 {
<> 144:ef7eb2e8f9f7 2437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2438 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2439
<> 144:ef7eb2e8f9f7 2440 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2441 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2442 switch (Channel)
<> 144:ef7eb2e8f9f7 2443 {
<> 144:ef7eb2e8f9f7 2444 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2445 {
<> 144:ef7eb2e8f9f7 2446 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2447 break;
<> 144:ef7eb2e8f9f7 2448 }
<> 144:ef7eb2e8f9f7 2449 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2450 {
<> 144:ef7eb2e8f9f7 2451 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2452 break;
<> 144:ef7eb2e8f9f7 2453 }
<> 144:ef7eb2e8f9f7 2454 default :
<> 144:ef7eb2e8f9f7 2455 {
<> 144:ef7eb2e8f9f7 2456 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2457 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2458 break;
<> 144:ef7eb2e8f9f7 2459 }
<> 144:ef7eb2e8f9f7 2460 }
<> 144:ef7eb2e8f9f7 2461
<> 144:ef7eb2e8f9f7 2462 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2463 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2464
<> 144:ef7eb2e8f9f7 2465 /* Return function status */
<> 144:ef7eb2e8f9f7 2466 return HAL_OK;
<> 144:ef7eb2e8f9f7 2467 }
<> 144:ef7eb2e8f9f7 2468
<> 144:ef7eb2e8f9f7 2469 /**
<> 144:ef7eb2e8f9f7 2470 * @brief Starts the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2471 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2472 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2473 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2474 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2475 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2476 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2477 * @retval HAL status
<> 144:ef7eb2e8f9f7 2478 */
<> 144:ef7eb2e8f9f7 2479 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2480 {
<> 144:ef7eb2e8f9f7 2481 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2482 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2483
<> 144:ef7eb2e8f9f7 2484 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2485 /* Enable the capture compare Interrupts 1 and/or 2 */
<> 144:ef7eb2e8f9f7 2486 switch (Channel)
<> 144:ef7eb2e8f9f7 2487 {
<> 144:ef7eb2e8f9f7 2488 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2489 {
<> 144:ef7eb2e8f9f7 2490 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2491 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2492 break;
<> 144:ef7eb2e8f9f7 2493 }
<> 144:ef7eb2e8f9f7 2494 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2495 {
<> 144:ef7eb2e8f9f7 2496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2497 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2498 break;
<> 144:ef7eb2e8f9f7 2499 }
<> 144:ef7eb2e8f9f7 2500 default :
<> 144:ef7eb2e8f9f7 2501 {
<> 144:ef7eb2e8f9f7 2502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2504 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2505 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2506 break;
<> 144:ef7eb2e8f9f7 2507 }
<> 144:ef7eb2e8f9f7 2508 }
<> 144:ef7eb2e8f9f7 2509
<> 144:ef7eb2e8f9f7 2510 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2511 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2512
<> 144:ef7eb2e8f9f7 2513 /* Return function status */
<> 144:ef7eb2e8f9f7 2514 return HAL_OK;
<> 144:ef7eb2e8f9f7 2515 }
<> 144:ef7eb2e8f9f7 2516
<> 144:ef7eb2e8f9f7 2517 /**
<> 144:ef7eb2e8f9f7 2518 * @brief Stops the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2519 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2520 * @param Channel: TIM Channels to be disabled
<> 144:ef7eb2e8f9f7 2521 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2522 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2523 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2524 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2525 * @retval HAL status
<> 144:ef7eb2e8f9f7 2526 */
<> 144:ef7eb2e8f9f7 2527 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2528 {
<> 144:ef7eb2e8f9f7 2529 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2530 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2531
<> 144:ef7eb2e8f9f7 2532 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2533 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2534 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2535 {
<> 144:ef7eb2e8f9f7 2536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2537
<> 144:ef7eb2e8f9f7 2538 /* Disable the capture compare Interrupts 1 */
<> 144:ef7eb2e8f9f7 2539 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2540 }
<> 144:ef7eb2e8f9f7 2541 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2542 {
<> 144:ef7eb2e8f9f7 2543 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2544
<> 144:ef7eb2e8f9f7 2545 /* Disable the capture compare Interrupts 2 */
<> 144:ef7eb2e8f9f7 2546 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2547 }
<> 144:ef7eb2e8f9f7 2548 else
<> 144:ef7eb2e8f9f7 2549 {
<> 144:ef7eb2e8f9f7 2550 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2551 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2552
<> 144:ef7eb2e8f9f7 2553 /* Disable the capture compare Interrupts 1 and 2 */
<> 144:ef7eb2e8f9f7 2554 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2555 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2556 }
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2559 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2560
<> 144:ef7eb2e8f9f7 2561 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2562 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2563
<> 144:ef7eb2e8f9f7 2564 /* Return function status */
<> 144:ef7eb2e8f9f7 2565 return HAL_OK;
<> 144:ef7eb2e8f9f7 2566 }
<> 144:ef7eb2e8f9f7 2567
<> 144:ef7eb2e8f9f7 2568 /**
<> 144:ef7eb2e8f9f7 2569 * @brief Starts the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2570 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2571 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2572 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2573 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2574 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2575 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2576 * @param pData1: The destination Buffer address for IC1.
<> 144:ef7eb2e8f9f7 2577 * @param pData2: The destination Buffer address for IC2.
<> 144:ef7eb2e8f9f7 2578 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 2579 * @retval HAL status
<> 144:ef7eb2e8f9f7 2580 */
<> 144:ef7eb2e8f9f7 2581 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
<> 144:ef7eb2e8f9f7 2582 {
<> 144:ef7eb2e8f9f7 2583 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2584 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2585
<> 144:ef7eb2e8f9f7 2586 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 2587 {
<> 144:ef7eb2e8f9f7 2588 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2589 }
<> 144:ef7eb2e8f9f7 2590 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 2591 {
<> 144:ef7eb2e8f9f7 2592 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
<> 144:ef7eb2e8f9f7 2593 {
<> 144:ef7eb2e8f9f7 2594 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2595 }
<> 144:ef7eb2e8f9f7 2596 else
<> 144:ef7eb2e8f9f7 2597 {
<> 144:ef7eb2e8f9f7 2598 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2599 }
<> 144:ef7eb2e8f9f7 2600 }
<> 144:ef7eb2e8f9f7 2601
<> 144:ef7eb2e8f9f7 2602 switch (Channel)
<> 144:ef7eb2e8f9f7 2603 {
<> 144:ef7eb2e8f9f7 2604 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2605 {
<> 144:ef7eb2e8f9f7 2606 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2607 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2608
<> 144:ef7eb2e8f9f7 2609 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2610 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2611
<> 144:ef7eb2e8f9f7 2612 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2613 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<> 144:ef7eb2e8f9f7 2614
<> 144:ef7eb2e8f9f7 2615 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2616 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2617
<> 144:ef7eb2e8f9f7 2618 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2619 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2620
<> 144:ef7eb2e8f9f7 2621 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2622 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2623 }
<> 144:ef7eb2e8f9f7 2624 break;
<> 144:ef7eb2e8f9f7 2625
<> 144:ef7eb2e8f9f7 2626 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2627 {
<> 144:ef7eb2e8f9f7 2628 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2629 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2630
<> 144:ef7eb2e8f9f7 2631 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2632 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 2633 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2634 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2635
<> 144:ef7eb2e8f9f7 2636 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2637 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2638
<> 144:ef7eb2e8f9f7 2639 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2640 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2641
<> 144:ef7eb2e8f9f7 2642 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2643 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2644 }
<> 144:ef7eb2e8f9f7 2645 break;
<> 144:ef7eb2e8f9f7 2646
<> 144:ef7eb2e8f9f7 2647 case TIM_CHANNEL_ALL:
<> 144:ef7eb2e8f9f7 2648 {
<> 144:ef7eb2e8f9f7 2649 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2650 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2651
<> 144:ef7eb2e8f9f7 2652 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2653 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2654
<> 144:ef7eb2e8f9f7 2655 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2656 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<> 144:ef7eb2e8f9f7 2657
<> 144:ef7eb2e8f9f7 2658 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2659 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2660
<> 144:ef7eb2e8f9f7 2661 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2662 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2663
<> 144:ef7eb2e8f9f7 2664 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2665 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2666
<> 144:ef7eb2e8f9f7 2667 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2668 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2669
<> 144:ef7eb2e8f9f7 2670 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2671 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2672 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2673
<> 144:ef7eb2e8f9f7 2674 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2675 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2676 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2677 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2678 }
<> 144:ef7eb2e8f9f7 2679 break;
<> 144:ef7eb2e8f9f7 2680
<> 144:ef7eb2e8f9f7 2681 default:
<> 144:ef7eb2e8f9f7 2682 break;
<> 144:ef7eb2e8f9f7 2683 }
<> 144:ef7eb2e8f9f7 2684 /* Return function status */
<> 144:ef7eb2e8f9f7 2685 return HAL_OK;
<> 144:ef7eb2e8f9f7 2686 }
<> 144:ef7eb2e8f9f7 2687
<> 144:ef7eb2e8f9f7 2688 /**
<> 144:ef7eb2e8f9f7 2689 * @brief Stops the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2690 * @param htim: TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 2691 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2692 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2693 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2694 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2695 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2696 * @retval HAL status
<> 144:ef7eb2e8f9f7 2697 */
<> 144:ef7eb2e8f9f7 2698 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2699 {
<> 144:ef7eb2e8f9f7 2700 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2701 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2702
<> 144:ef7eb2e8f9f7 2703 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2704 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2705 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2706 {
<> 144:ef7eb2e8f9f7 2707 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2708
<> 144:ef7eb2e8f9f7 2709 /* Disable the capture compare DMA Request 1 */
<> 144:ef7eb2e8f9f7 2710 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2711 }
<> 144:ef7eb2e8f9f7 2712 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2713 {
<> 144:ef7eb2e8f9f7 2714 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2715
<> 144:ef7eb2e8f9f7 2716 /* Disable the capture compare DMA Request 2 */
<> 144:ef7eb2e8f9f7 2717 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2718 }
<> 144:ef7eb2e8f9f7 2719 else
<> 144:ef7eb2e8f9f7 2720 {
<> 144:ef7eb2e8f9f7 2721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2722 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2723
<> 144:ef7eb2e8f9f7 2724 /* Disable the capture compare DMA Request 1 and 2 */
<> 144:ef7eb2e8f9f7 2725 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2726 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2727 }
<> 144:ef7eb2e8f9f7 2728
<> 144:ef7eb2e8f9f7 2729 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2730 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2731
<> 144:ef7eb2e8f9f7 2732 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2733 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2734
<> 144:ef7eb2e8f9f7 2735 /* Return function status */
<> 144:ef7eb2e8f9f7 2736 return HAL_OK;
<> 144:ef7eb2e8f9f7 2737 }
<> 144:ef7eb2e8f9f7 2738
<> 144:ef7eb2e8f9f7 2739 /**
<> 144:ef7eb2e8f9f7 2740 * @}
<> 144:ef7eb2e8f9f7 2741 */
<> 144:ef7eb2e8f9f7 2742 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<> 144:ef7eb2e8f9f7 2743 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 2744 *
<> 144:ef7eb2e8f9f7 2745 @verbatim
<> 144:ef7eb2e8f9f7 2746 ==============================================================================
<> 144:ef7eb2e8f9f7 2747 ##### IRQ handler management #####
<> 144:ef7eb2e8f9f7 2748 ==============================================================================
<> 144:ef7eb2e8f9f7 2749 [..]
<> 144:ef7eb2e8f9f7 2750 This section provides Timer IRQ handler function.
<> 144:ef7eb2e8f9f7 2751
<> 144:ef7eb2e8f9f7 2752 @endverbatim
<> 144:ef7eb2e8f9f7 2753 * @{
<> 144:ef7eb2e8f9f7 2754 */
<> 144:ef7eb2e8f9f7 2755 /**
<> 144:ef7eb2e8f9f7 2756 * @brief This function handles TIM interrupts requests.
<> 144:ef7eb2e8f9f7 2757 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 2758 * @retval None
<> 144:ef7eb2e8f9f7 2759 */
<> 144:ef7eb2e8f9f7 2760 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2761 {
<> 144:ef7eb2e8f9f7 2762 /* Capture compare 1 event */
<> 144:ef7eb2e8f9f7 2763 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<> 144:ef7eb2e8f9f7 2764 {
<> 144:ef7eb2e8f9f7 2765 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<> 144:ef7eb2e8f9f7 2766 {
<> 144:ef7eb2e8f9f7 2767 {
<> 144:ef7eb2e8f9f7 2768 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2769 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 2770
<> 144:ef7eb2e8f9f7 2771 /* Input capture event */
<> 144:ef7eb2e8f9f7 2772 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
<> 144:ef7eb2e8f9f7 2773 {
<> 144:ef7eb2e8f9f7 2774 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2775 }
<> 144:ef7eb2e8f9f7 2776 /* Output compare event */
<> 144:ef7eb2e8f9f7 2777 else
<> 144:ef7eb2e8f9f7 2778 {
<> 144:ef7eb2e8f9f7 2779 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2780 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2781 }
<> 144:ef7eb2e8f9f7 2782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2783 }
<> 144:ef7eb2e8f9f7 2784 }
<> 144:ef7eb2e8f9f7 2785 }
<> 144:ef7eb2e8f9f7 2786 /* Capture compare 2 event */
<> 144:ef7eb2e8f9f7 2787 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<> 144:ef7eb2e8f9f7 2788 {
<> 144:ef7eb2e8f9f7 2789 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<> 144:ef7eb2e8f9f7 2790 {
<> 144:ef7eb2e8f9f7 2791 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2792 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 2793 /* Input capture event */
<> 144:ef7eb2e8f9f7 2794 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
<> 144:ef7eb2e8f9f7 2795 {
<> 144:ef7eb2e8f9f7 2796 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2797 }
<> 144:ef7eb2e8f9f7 2798 /* Output compare event */
<> 144:ef7eb2e8f9f7 2799 else
<> 144:ef7eb2e8f9f7 2800 {
<> 144:ef7eb2e8f9f7 2801 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2802 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2803 }
<> 144:ef7eb2e8f9f7 2804 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2805 }
<> 144:ef7eb2e8f9f7 2806 }
<> 144:ef7eb2e8f9f7 2807 /* Capture compare 3 event */
<> 144:ef7eb2e8f9f7 2808 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<> 144:ef7eb2e8f9f7 2809 {
<> 144:ef7eb2e8f9f7 2810 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<> 144:ef7eb2e8f9f7 2811 {
<> 144:ef7eb2e8f9f7 2812 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 2813 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 2814 /* Input capture event */
<> 144:ef7eb2e8f9f7 2815 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
<> 144:ef7eb2e8f9f7 2816 {
<> 144:ef7eb2e8f9f7 2817 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2818 }
<> 144:ef7eb2e8f9f7 2819 /* Output compare event */
<> 144:ef7eb2e8f9f7 2820 else
<> 144:ef7eb2e8f9f7 2821 {
<> 144:ef7eb2e8f9f7 2822 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2823 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2824 }
<> 144:ef7eb2e8f9f7 2825 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2826 }
<> 144:ef7eb2e8f9f7 2827 }
<> 144:ef7eb2e8f9f7 2828 /* Capture compare 4 event */
<> 144:ef7eb2e8f9f7 2829 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<> 144:ef7eb2e8f9f7 2830 {
<> 144:ef7eb2e8f9f7 2831 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<> 144:ef7eb2e8f9f7 2832 {
<> 144:ef7eb2e8f9f7 2833 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 2834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 2835 /* Input capture event */
<> 144:ef7eb2e8f9f7 2836 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
<> 144:ef7eb2e8f9f7 2837 {
<> 144:ef7eb2e8f9f7 2838 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2839 }
<> 144:ef7eb2e8f9f7 2840 /* Output compare event */
<> 144:ef7eb2e8f9f7 2841 else
<> 144:ef7eb2e8f9f7 2842 {
<> 144:ef7eb2e8f9f7 2843 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2844 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2845 }
<> 144:ef7eb2e8f9f7 2846 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2847 }
<> 144:ef7eb2e8f9f7 2848 }
<> 144:ef7eb2e8f9f7 2849 /* TIM Update event */
<> 144:ef7eb2e8f9f7 2850 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<> 144:ef7eb2e8f9f7 2851 {
<> 144:ef7eb2e8f9f7 2852 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<> 144:ef7eb2e8f9f7 2853 {
<> 144:ef7eb2e8f9f7 2854 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 2855 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2856 }
<> 144:ef7eb2e8f9f7 2857 }
<> 144:ef7eb2e8f9f7 2858 /* TIM Break input event */
<> 144:ef7eb2e8f9f7 2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<> 144:ef7eb2e8f9f7 2860 {
<> 144:ef7eb2e8f9f7 2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<> 144:ef7eb2e8f9f7 2862 {
<> 144:ef7eb2e8f9f7 2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 2864 HAL_TIMEx_BreakCallback(htim);
<> 144:ef7eb2e8f9f7 2865 }
<> 144:ef7eb2e8f9f7 2866 }
<> 144:ef7eb2e8f9f7 2867 /* TIM Trigger detection event */
<> 144:ef7eb2e8f9f7 2868 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<> 144:ef7eb2e8f9f7 2869 {
<> 144:ef7eb2e8f9f7 2870 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<> 144:ef7eb2e8f9f7 2871 {
<> 144:ef7eb2e8f9f7 2872 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 2873 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 2874 }
<> 144:ef7eb2e8f9f7 2875 }
<> 144:ef7eb2e8f9f7 2876 /* TIM commutation event */
<> 144:ef7eb2e8f9f7 2877 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<> 144:ef7eb2e8f9f7 2878 {
<> 144:ef7eb2e8f9f7 2879 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<> 144:ef7eb2e8f9f7 2880 {
<> 144:ef7eb2e8f9f7 2881 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<> 144:ef7eb2e8f9f7 2882 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2883 }
<> 144:ef7eb2e8f9f7 2884 }
<> 144:ef7eb2e8f9f7 2885 }
<> 144:ef7eb2e8f9f7 2886
<> 144:ef7eb2e8f9f7 2887 /**
<> 144:ef7eb2e8f9f7 2888 * @}
<> 144:ef7eb2e8f9f7 2889 */
<> 144:ef7eb2e8f9f7 2890
<> 144:ef7eb2e8f9f7 2891 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 2892 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 2893 *
<> 144:ef7eb2e8f9f7 2894 @verbatim
<> 144:ef7eb2e8f9f7 2895 ==============================================================================
<> 144:ef7eb2e8f9f7 2896 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 2897 ==============================================================================
<> 144:ef7eb2e8f9f7 2898 [..]
<> 144:ef7eb2e8f9f7 2899 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2900 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 2901 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 2902 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 2903 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 2904 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 2905
<> 144:ef7eb2e8f9f7 2906 @endverbatim
<> 144:ef7eb2e8f9f7 2907 * @{
<> 144:ef7eb2e8f9f7 2908 */
<> 144:ef7eb2e8f9f7 2909
<> 144:ef7eb2e8f9f7 2910 /**
<> 144:ef7eb2e8f9f7 2911 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2912 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2913 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 2914 * @param sConfig: TIM Output Compare configuration structure
<> 144:ef7eb2e8f9f7 2915 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2916 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2917 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2918 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2919 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2920 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2921 * @retval HAL status
<> 144:ef7eb2e8f9f7 2922 */
<> 144:ef7eb2e8f9f7 2923 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2924 {
<> 144:ef7eb2e8f9f7 2925 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2926 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2927 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2928 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2929
<> 144:ef7eb2e8f9f7 2930 /* Check input state */
<> 144:ef7eb2e8f9f7 2931 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2932
<> 144:ef7eb2e8f9f7 2933 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2934
<> 144:ef7eb2e8f9f7 2935 switch (Channel)
<> 144:ef7eb2e8f9f7 2936 {
<> 144:ef7eb2e8f9f7 2937 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2938 {
<> 144:ef7eb2e8f9f7 2939 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2940 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2941 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2942 }
<> 144:ef7eb2e8f9f7 2943 break;
<> 144:ef7eb2e8f9f7 2944
<> 144:ef7eb2e8f9f7 2945 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2946 {
<> 144:ef7eb2e8f9f7 2947 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2948 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 2949 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2950 }
<> 144:ef7eb2e8f9f7 2951 break;
<> 144:ef7eb2e8f9f7 2952
<> 144:ef7eb2e8f9f7 2953 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2954 {
<> 144:ef7eb2e8f9f7 2955 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2956 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 2957 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2958 }
<> 144:ef7eb2e8f9f7 2959 break;
<> 144:ef7eb2e8f9f7 2960
<> 144:ef7eb2e8f9f7 2961 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 2962 {
<> 144:ef7eb2e8f9f7 2963 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2964 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 2965 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2966 }
<> 144:ef7eb2e8f9f7 2967 break;
<> 144:ef7eb2e8f9f7 2968
<> 144:ef7eb2e8f9f7 2969 default:
<> 144:ef7eb2e8f9f7 2970 break;
<> 144:ef7eb2e8f9f7 2971 }
<> 144:ef7eb2e8f9f7 2972 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2973
<> 144:ef7eb2e8f9f7 2974 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2975
<> 144:ef7eb2e8f9f7 2976 return HAL_OK;
<> 144:ef7eb2e8f9f7 2977 }
<> 144:ef7eb2e8f9f7 2978
<> 144:ef7eb2e8f9f7 2979 /**
<> 144:ef7eb2e8f9f7 2980 * @brief Initializes the TIM Input Capture Channels according to the specified
<> 144:ef7eb2e8f9f7 2981 * parameters in the TIM_IC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2982 * @param htim: TIM IC handle
<> 144:ef7eb2e8f9f7 2983 * @param sConfig: TIM Input Capture configuration structure
<> 144:ef7eb2e8f9f7 2984 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 2985 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2986 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2987 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2988 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2989 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2990 * @retval HAL status
<> 144:ef7eb2e8f9f7 2991 */
<> 144:ef7eb2e8f9f7 2992 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2993 {
<> 144:ef7eb2e8f9f7 2994 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2995 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2996 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<> 144:ef7eb2e8f9f7 2997 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<> 144:ef7eb2e8f9f7 2998 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<> 144:ef7eb2e8f9f7 2999 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<> 144:ef7eb2e8f9f7 3000
<> 144:ef7eb2e8f9f7 3001 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3002
<> 144:ef7eb2e8f9f7 3003 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3004
<> 144:ef7eb2e8f9f7 3005 if (Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 3006 {
<> 144:ef7eb2e8f9f7 3007 /* TI1 Configuration */
<> 144:ef7eb2e8f9f7 3008 TIM_TI1_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3009 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3010 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3011 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3012
<> 144:ef7eb2e8f9f7 3013 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3014 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3015
<> 144:ef7eb2e8f9f7 3016 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 3017 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3018 }
<> 144:ef7eb2e8f9f7 3019 else if (Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 3020 {
<> 144:ef7eb2e8f9f7 3021 /* TI2 Configuration */
<> 144:ef7eb2e8f9f7 3022 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3023
<> 144:ef7eb2e8f9f7 3024 TIM_TI2_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3025 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3026 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3027 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3028
<> 144:ef7eb2e8f9f7 3029 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3030 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3031
<> 144:ef7eb2e8f9f7 3032 /* Set the IC2PSC value */
<> 144:ef7eb2e8f9f7 3033 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
<> 144:ef7eb2e8f9f7 3034 }
<> 144:ef7eb2e8f9f7 3035 else if (Channel == TIM_CHANNEL_3)
<> 144:ef7eb2e8f9f7 3036 {
<> 144:ef7eb2e8f9f7 3037 /* TI3 Configuration */
<> 144:ef7eb2e8f9f7 3038 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3039
<> 144:ef7eb2e8f9f7 3040 TIM_TI3_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3041 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3042 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3043 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3044
<> 144:ef7eb2e8f9f7 3045 /* Reset the IC3PSC Bits */
<> 144:ef7eb2e8f9f7 3046 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<> 144:ef7eb2e8f9f7 3047
<> 144:ef7eb2e8f9f7 3048 /* Set the IC3PSC value */
<> 144:ef7eb2e8f9f7 3049 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3050 }
<> 144:ef7eb2e8f9f7 3051 else
<> 144:ef7eb2e8f9f7 3052 {
<> 144:ef7eb2e8f9f7 3053 /* TI4 Configuration */
<> 144:ef7eb2e8f9f7 3054 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3055
<> 144:ef7eb2e8f9f7 3056 TIM_TI4_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3057 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3058 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3059 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3060
<> 144:ef7eb2e8f9f7 3061 /* Reset the IC4PSC Bits */
<> 144:ef7eb2e8f9f7 3062 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<> 144:ef7eb2e8f9f7 3063
<> 144:ef7eb2e8f9f7 3064 /* Set the IC4PSC value */
<> 144:ef7eb2e8f9f7 3065 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
<> 144:ef7eb2e8f9f7 3066 }
<> 144:ef7eb2e8f9f7 3067
<> 144:ef7eb2e8f9f7 3068 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3069
<> 144:ef7eb2e8f9f7 3070 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3071
<> 144:ef7eb2e8f9f7 3072 return HAL_OK;
<> 144:ef7eb2e8f9f7 3073 }
<> 144:ef7eb2e8f9f7 3074
<> 144:ef7eb2e8f9f7 3075 /**
<> 144:ef7eb2e8f9f7 3076 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 3077 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 3078 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3079 * @param sConfig: TIM PWM configuration structure
<> 144:ef7eb2e8f9f7 3080 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3081 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3084 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3085 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3086 * @retval HAL status
<> 144:ef7eb2e8f9f7 3087 */
<> 144:ef7eb2e8f9f7 3088 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3089 {
<> 144:ef7eb2e8f9f7 3090 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3091
<> 144:ef7eb2e8f9f7 3092 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3093 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3094 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 3095 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 3096 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 3097
<> 144:ef7eb2e8f9f7 3098 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3099
<> 144:ef7eb2e8f9f7 3100 switch (Channel)
<> 144:ef7eb2e8f9f7 3101 {
<> 144:ef7eb2e8f9f7 3102 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3103 {
<> 144:ef7eb2e8f9f7 3104 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3105 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 3106 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3107
<> 144:ef7eb2e8f9f7 3108 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 3109 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 3110
<> 144:ef7eb2e8f9f7 3111 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3112 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 3113 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3114 }
<> 144:ef7eb2e8f9f7 3115 break;
<> 144:ef7eb2e8f9f7 3116
<> 144:ef7eb2e8f9f7 3117 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3118 {
<> 144:ef7eb2e8f9f7 3119 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3120 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 3121 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3122
<> 144:ef7eb2e8f9f7 3123 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 3124 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 3125
<> 144:ef7eb2e8f9f7 3126 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3127 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 144:ef7eb2e8f9f7 3128 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 3129 }
<> 144:ef7eb2e8f9f7 3130 break;
<> 144:ef7eb2e8f9f7 3131
<> 144:ef7eb2e8f9f7 3132 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3133 {
<> 144:ef7eb2e8f9f7 3134 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3135 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 3136 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3137
<> 144:ef7eb2e8f9f7 3138 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 3139 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 3140
<> 144:ef7eb2e8f9f7 3141 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3142 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 3143 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3144 }
<> 144:ef7eb2e8f9f7 3145 break;
<> 144:ef7eb2e8f9f7 3146
<> 144:ef7eb2e8f9f7 3147 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3148 {
<> 144:ef7eb2e8f9f7 3149 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3150 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 3151 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3152
<> 144:ef7eb2e8f9f7 3153 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 3154 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 3155
<> 144:ef7eb2e8f9f7 3156 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3157 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 144:ef7eb2e8f9f7 3158 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 3159 }
<> 144:ef7eb2e8f9f7 3160 break;
<> 144:ef7eb2e8f9f7 3161
<> 144:ef7eb2e8f9f7 3162 default:
<> 144:ef7eb2e8f9f7 3163 break;
<> 144:ef7eb2e8f9f7 3164 }
<> 144:ef7eb2e8f9f7 3165
<> 144:ef7eb2e8f9f7 3166 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3167
<> 144:ef7eb2e8f9f7 3168 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3169
<> 144:ef7eb2e8f9f7 3170 return HAL_OK;
<> 144:ef7eb2e8f9f7 3171 }
<> 144:ef7eb2e8f9f7 3172
<> 144:ef7eb2e8f9f7 3173 /**
<> 144:ef7eb2e8f9f7 3174 * @brief Initializes the TIM One Pulse Channels according to the specified
<> 144:ef7eb2e8f9f7 3175 * parameters in the TIM_OnePulse_InitTypeDef.
<> 144:ef7eb2e8f9f7 3176 * @param htim: TIM One Pulse handle
<> 144:ef7eb2e8f9f7 3177 * @param sConfig: TIM One Pulse configuration structure
<> 144:ef7eb2e8f9f7 3178 * @param OutputChannel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3179 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3180 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3181 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3182 * @param InputChannel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 3183 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3184 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3185 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3186 * @retval HAL status
<> 144:ef7eb2e8f9f7 3187 */
<> 144:ef7eb2e8f9f7 3188 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<> 144:ef7eb2e8f9f7 3189 {
<> 144:ef7eb2e8f9f7 3190 TIM_OC_InitTypeDef temp1;
<> 144:ef7eb2e8f9f7 3191
<> 144:ef7eb2e8f9f7 3192 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3193 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<> 144:ef7eb2e8f9f7 3194 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<> 144:ef7eb2e8f9f7 3195
<> 144:ef7eb2e8f9f7 3196 if(OutputChannel != InputChannel)
<> 144:ef7eb2e8f9f7 3197 {
<> 144:ef7eb2e8f9f7 3198 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3199
<> 144:ef7eb2e8f9f7 3200 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3201
<> 144:ef7eb2e8f9f7 3202 /* Extract the Ouput compare configuration from sConfig structure */
<> 144:ef7eb2e8f9f7 3203 temp1.OCMode = sConfig->OCMode;
<> 144:ef7eb2e8f9f7 3204 temp1.Pulse = sConfig->Pulse;
<> 144:ef7eb2e8f9f7 3205 temp1.OCPolarity = sConfig->OCPolarity;
<> 144:ef7eb2e8f9f7 3206 temp1.OCNPolarity = sConfig->OCNPolarity;
<> 144:ef7eb2e8f9f7 3207 temp1.OCIdleState = sConfig->OCIdleState;
<> 144:ef7eb2e8f9f7 3208 temp1.OCNIdleState = sConfig->OCNIdleState;
<> 144:ef7eb2e8f9f7 3209
<> 144:ef7eb2e8f9f7 3210 switch (OutputChannel)
<> 144:ef7eb2e8f9f7 3211 {
<> 144:ef7eb2e8f9f7 3212 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3213 {
<> 144:ef7eb2e8f9f7 3214 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3215
<> 144:ef7eb2e8f9f7 3216 TIM_OC1_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3217 }
<> 144:ef7eb2e8f9f7 3218 break;
<> 144:ef7eb2e8f9f7 3219 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3220 {
<> 144:ef7eb2e8f9f7 3221 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3222
<> 144:ef7eb2e8f9f7 3223 TIM_OC2_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3224 }
<> 144:ef7eb2e8f9f7 3225 break;
<> 144:ef7eb2e8f9f7 3226 default:
<> 144:ef7eb2e8f9f7 3227 break;
<> 144:ef7eb2e8f9f7 3228 }
<> 144:ef7eb2e8f9f7 3229 switch (InputChannel)
<> 144:ef7eb2e8f9f7 3230 {
<> 144:ef7eb2e8f9f7 3231 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3232 {
<> 144:ef7eb2e8f9f7 3233 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3234
<> 144:ef7eb2e8f9f7 3235 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3236 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3237
<> 144:ef7eb2e8f9f7 3238 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3239 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3240
<> 144:ef7eb2e8f9f7 3241 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3242 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3243 htim->Instance->SMCR |= TIM_TS_TI1FP1;
<> 144:ef7eb2e8f9f7 3244
<> 144:ef7eb2e8f9f7 3245 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3246 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3247 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3248 }
<> 144:ef7eb2e8f9f7 3249 break;
<> 144:ef7eb2e8f9f7 3250 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3251 {
<> 144:ef7eb2e8f9f7 3252 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3253
<> 144:ef7eb2e8f9f7 3254 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3255 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3256
<> 144:ef7eb2e8f9f7 3257 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3258 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3259
<> 144:ef7eb2e8f9f7 3260 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3261 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3262 htim->Instance->SMCR |= TIM_TS_TI2FP2;
<> 144:ef7eb2e8f9f7 3263
<> 144:ef7eb2e8f9f7 3264 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3265 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3266 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3267 }
<> 144:ef7eb2e8f9f7 3268 break;
<> 144:ef7eb2e8f9f7 3269
<> 144:ef7eb2e8f9f7 3270 default:
<> 144:ef7eb2e8f9f7 3271 break;
<> 144:ef7eb2e8f9f7 3272 }
<> 144:ef7eb2e8f9f7 3273
<> 144:ef7eb2e8f9f7 3274 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3275
<> 144:ef7eb2e8f9f7 3276 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3277
<> 144:ef7eb2e8f9f7 3278 return HAL_OK;
<> 144:ef7eb2e8f9f7 3279 }
<> 144:ef7eb2e8f9f7 3280 else
<> 144:ef7eb2e8f9f7 3281 {
<> 144:ef7eb2e8f9f7 3282 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3283 }
<> 144:ef7eb2e8f9f7 3284 }
<> 144:ef7eb2e8f9f7 3285
<> 144:ef7eb2e8f9f7 3286 /**
<> 144:ef7eb2e8f9f7 3287 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<> 144:ef7eb2e8f9f7 3288 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3289 * @param BurstBaseAddress: TIM Base address from where the DMA will start the Data write
<> 144:ef7eb2e8f9f7 3290 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3291 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3292 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3293 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3294 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3295 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3296 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3297 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3298 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3299 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3300 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3301 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3302 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3303 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3304 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3305 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3306 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3307 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3308 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3309 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3310 * @param BurstRequestSrc: TIM DMA Request sources
<> 144:ef7eb2e8f9f7 3311 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3312 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3313 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3314 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3315 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3316 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3317 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3318 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3319 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3320 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3321 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3322 * @retval HAL status
<> 144:ef7eb2e8f9f7 3323 */
<> 144:ef7eb2e8f9f7 3324 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3325 uint32_t* BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3326 {
<> 144:ef7eb2e8f9f7 3327 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3328 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3329 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3330 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3331 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3332
<> 144:ef7eb2e8f9f7 3333 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3334 {
<> 144:ef7eb2e8f9f7 3335 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3336 }
<> 144:ef7eb2e8f9f7 3337 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3338 {
<> 144:ef7eb2e8f9f7 3339 if((BurstBuffer == 0 ) && (BurstLength > 0))
<> 144:ef7eb2e8f9f7 3340 {
<> 144:ef7eb2e8f9f7 3341 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3342 }
<> 144:ef7eb2e8f9f7 3343 else
<> 144:ef7eb2e8f9f7 3344 {
<> 144:ef7eb2e8f9f7 3345 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3346 }
<> 144:ef7eb2e8f9f7 3347 }
<> 144:ef7eb2e8f9f7 3348 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3349 {
<> 144:ef7eb2e8f9f7 3350 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3351 {
<> 144:ef7eb2e8f9f7 3352 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3353 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3354
<> 144:ef7eb2e8f9f7 3355 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3356 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3357
<> 144:ef7eb2e8f9f7 3358 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3359 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3360 }
<> 144:ef7eb2e8f9f7 3361 break;
<> 144:ef7eb2e8f9f7 3362 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3363 {
<> 144:ef7eb2e8f9f7 3364 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3365 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3366
<> 144:ef7eb2e8f9f7 3367 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3368 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3369
<> 144:ef7eb2e8f9f7 3370 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3371 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3372 }
<> 144:ef7eb2e8f9f7 3373 break;
<> 144:ef7eb2e8f9f7 3374 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3375 {
<> 144:ef7eb2e8f9f7 3376 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3377 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3378
<> 144:ef7eb2e8f9f7 3379 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3380 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3381
<> 144:ef7eb2e8f9f7 3382 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3383 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3384 }
<> 144:ef7eb2e8f9f7 3385 break;
<> 144:ef7eb2e8f9f7 3386 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3387 {
<> 144:ef7eb2e8f9f7 3388 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3389 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3390
<> 144:ef7eb2e8f9f7 3391 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3392 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3393
<> 144:ef7eb2e8f9f7 3394 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3395 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3396 }
<> 144:ef7eb2e8f9f7 3397 break;
<> 144:ef7eb2e8f9f7 3398 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3399 {
<> 144:ef7eb2e8f9f7 3400 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3401 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3402
<> 144:ef7eb2e8f9f7 3403 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3404 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3405
<> 144:ef7eb2e8f9f7 3406 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3407 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3408 }
<> 144:ef7eb2e8f9f7 3409 break;
<> 144:ef7eb2e8f9f7 3410 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3411 {
<> 144:ef7eb2e8f9f7 3412 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3413 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3414
<> 144:ef7eb2e8f9f7 3415 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3416 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3417
<> 144:ef7eb2e8f9f7 3418 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3419 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3420 }
<> 144:ef7eb2e8f9f7 3421 break;
<> 144:ef7eb2e8f9f7 3422 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3423 {
<> 144:ef7eb2e8f9f7 3424 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3425 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3426
<> 144:ef7eb2e8f9f7 3427 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3428 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3429
<> 144:ef7eb2e8f9f7 3430 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3431 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3432 }
<> 144:ef7eb2e8f9f7 3433 break;
<> 144:ef7eb2e8f9f7 3434 default:
<> 144:ef7eb2e8f9f7 3435 break;
<> 144:ef7eb2e8f9f7 3436 }
<> 144:ef7eb2e8f9f7 3437 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3438 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3439
<> 144:ef7eb2e8f9f7 3440 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3441 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3442
<> 144:ef7eb2e8f9f7 3443 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3444
<> 144:ef7eb2e8f9f7 3445 /* Return function status */
<> 144:ef7eb2e8f9f7 3446 return HAL_OK;
<> 144:ef7eb2e8f9f7 3447 }
<> 144:ef7eb2e8f9f7 3448
<> 144:ef7eb2e8f9f7 3449 /**
<> 144:ef7eb2e8f9f7 3450 * @brief Stops the TIM DMA Burst mode
<> 144:ef7eb2e8f9f7 3451 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3452 * @param BurstRequestSrc: TIM DMA Request sources to disable
<> 144:ef7eb2e8f9f7 3453 * @retval HAL status
<> 144:ef7eb2e8f9f7 3454 */
<> 144:ef7eb2e8f9f7 3455 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3456 {
<> 144:ef7eb2e8f9f7 3457 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3458 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3459
<> 144:ef7eb2e8f9f7 3460 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3461 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3462 {
<> 144:ef7eb2e8f9f7 3463 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3464 {
<> 144:ef7eb2e8f9f7 3465 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3466 }
<> 144:ef7eb2e8f9f7 3467 break;
<> 144:ef7eb2e8f9f7 3468 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3469 {
<> 144:ef7eb2e8f9f7 3470 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3471 }
<> 144:ef7eb2e8f9f7 3472 break;
<> 144:ef7eb2e8f9f7 3473 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3474 {
<> 144:ef7eb2e8f9f7 3475 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3476 }
<> 144:ef7eb2e8f9f7 3477 break;
<> 144:ef7eb2e8f9f7 3478 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3479 {
<> 144:ef7eb2e8f9f7 3480 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3481 }
<> 144:ef7eb2e8f9f7 3482 break;
<> 144:ef7eb2e8f9f7 3483 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3484 {
<> 144:ef7eb2e8f9f7 3485 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3486 }
<> 144:ef7eb2e8f9f7 3487 break;
<> 144:ef7eb2e8f9f7 3488 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3489 {
<> 144:ef7eb2e8f9f7 3490 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3491 }
<> 144:ef7eb2e8f9f7 3492 break;
<> 144:ef7eb2e8f9f7 3493 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3494 {
<> 144:ef7eb2e8f9f7 3495 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3496 }
<> 144:ef7eb2e8f9f7 3497 break;
<> 144:ef7eb2e8f9f7 3498 default:
<> 144:ef7eb2e8f9f7 3499 break;
<> 144:ef7eb2e8f9f7 3500 }
<> 144:ef7eb2e8f9f7 3501
<> 144:ef7eb2e8f9f7 3502 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3503 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3504
<> 144:ef7eb2e8f9f7 3505 /* Return function status */
<> 144:ef7eb2e8f9f7 3506 return HAL_OK;
<> 144:ef7eb2e8f9f7 3507 }
<> 144:ef7eb2e8f9f7 3508
<> 144:ef7eb2e8f9f7 3509 /**
<> 144:ef7eb2e8f9f7 3510 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<> 144:ef7eb2e8f9f7 3511 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3512 * @param BurstBaseAddress: TIM Base address from where the DMA will starts the Data read
<> 144:ef7eb2e8f9f7 3513 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3514 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3515 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3516 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3517 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3518 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3519 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3520 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3521 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3522 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3523 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3524 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3525 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3526 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3527 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3528 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3529 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3530 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3531 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3532 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3533 * @param BurstRequestSrc: TIM DMA Request sources
<> 144:ef7eb2e8f9f7 3534 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3535 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3536 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3537 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3538 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3539 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3540 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3541 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3542 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3543 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3544 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3545 * @retval HAL status
<> 144:ef7eb2e8f9f7 3546 */
<> 144:ef7eb2e8f9f7 3547 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3548 uint32_t *BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3549 {
<> 144:ef7eb2e8f9f7 3550 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3551 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3552 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3553 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3554 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3555
<> 144:ef7eb2e8f9f7 3556 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3557 {
<> 144:ef7eb2e8f9f7 3558 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3559 }
<> 144:ef7eb2e8f9f7 3560 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3561 {
<> 144:ef7eb2e8f9f7 3562 if((BurstBuffer == 0 ) && (BurstLength > 0))
<> 144:ef7eb2e8f9f7 3563 {
<> 144:ef7eb2e8f9f7 3564 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3565 }
<> 144:ef7eb2e8f9f7 3566 else
<> 144:ef7eb2e8f9f7 3567 {
<> 144:ef7eb2e8f9f7 3568 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3569 }
<> 144:ef7eb2e8f9f7 3570 }
<> 144:ef7eb2e8f9f7 3571 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3572 {
<> 144:ef7eb2e8f9f7 3573 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3574 {
<> 144:ef7eb2e8f9f7 3575 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3576 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3577
<> 144:ef7eb2e8f9f7 3578 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3579 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3580
<> 144:ef7eb2e8f9f7 3581 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3582 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3583 }
<> 144:ef7eb2e8f9f7 3584 break;
<> 144:ef7eb2e8f9f7 3585 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3586 {
<> 144:ef7eb2e8f9f7 3587 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3588 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3589
<> 144:ef7eb2e8f9f7 3590 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3591 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3592
<> 144:ef7eb2e8f9f7 3593 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3594 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3595 }
<> 144:ef7eb2e8f9f7 3596 break;
<> 144:ef7eb2e8f9f7 3597 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3598 {
<> 144:ef7eb2e8f9f7 3599 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3600 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3601
<> 144:ef7eb2e8f9f7 3602 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3603 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3604
<> 144:ef7eb2e8f9f7 3605 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3606 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3607 }
<> 144:ef7eb2e8f9f7 3608 break;
<> 144:ef7eb2e8f9f7 3609 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3610 {
<> 144:ef7eb2e8f9f7 3611 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3612 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3613
<> 144:ef7eb2e8f9f7 3614 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3615 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3616
<> 144:ef7eb2e8f9f7 3617 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3618 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3619 }
<> 144:ef7eb2e8f9f7 3620 break;
<> 144:ef7eb2e8f9f7 3621 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3622 {
<> 144:ef7eb2e8f9f7 3623 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3624 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3625
<> 144:ef7eb2e8f9f7 3626 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3627 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3628
<> 144:ef7eb2e8f9f7 3629 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3630 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3631 }
<> 144:ef7eb2e8f9f7 3632 break;
<> 144:ef7eb2e8f9f7 3633 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3634 {
<> 144:ef7eb2e8f9f7 3635 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3636 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3637
<> 144:ef7eb2e8f9f7 3638 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3639 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3640
<> 144:ef7eb2e8f9f7 3641 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3642 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3643 }
<> 144:ef7eb2e8f9f7 3644 break;
<> 144:ef7eb2e8f9f7 3645 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3646 {
<> 144:ef7eb2e8f9f7 3647 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3648 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3649
<> 144:ef7eb2e8f9f7 3650 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3651 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3652
<> 144:ef7eb2e8f9f7 3653 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 3654 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3655 }
<> 144:ef7eb2e8f9f7 3656 break;
<> 144:ef7eb2e8f9f7 3657 default:
<> 144:ef7eb2e8f9f7 3658 break;
<> 144:ef7eb2e8f9f7 3659 }
<> 144:ef7eb2e8f9f7 3660
<> 144:ef7eb2e8f9f7 3661 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3662 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3663
<> 144:ef7eb2e8f9f7 3664 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3665 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3666
<> 144:ef7eb2e8f9f7 3667 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3668
<> 144:ef7eb2e8f9f7 3669 /* Return function status */
<> 144:ef7eb2e8f9f7 3670 return HAL_OK;
<> 144:ef7eb2e8f9f7 3671 }
<> 144:ef7eb2e8f9f7 3672
<> 144:ef7eb2e8f9f7 3673 /**
<> 144:ef7eb2e8f9f7 3674 * @brief Stop the DMA burst reading
<> 144:ef7eb2e8f9f7 3675 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3676 * @param BurstRequestSrc: TIM DMA Request sources to disable.
<> 144:ef7eb2e8f9f7 3677 * @retval HAL status
<> 144:ef7eb2e8f9f7 3678 */
<> 144:ef7eb2e8f9f7 3679 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3680 {
<> 144:ef7eb2e8f9f7 3681 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3682 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3683
<> 144:ef7eb2e8f9f7 3684 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3685 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3686 {
<> 144:ef7eb2e8f9f7 3687 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3688 {
<> 144:ef7eb2e8f9f7 3689 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3690 }
<> 144:ef7eb2e8f9f7 3691 break;
<> 144:ef7eb2e8f9f7 3692 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3693 {
<> 144:ef7eb2e8f9f7 3694 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3695 }
<> 144:ef7eb2e8f9f7 3696 break;
<> 144:ef7eb2e8f9f7 3697 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3698 {
<> 144:ef7eb2e8f9f7 3699 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3700 }
<> 144:ef7eb2e8f9f7 3701 break;
<> 144:ef7eb2e8f9f7 3702 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3703 {
<> 144:ef7eb2e8f9f7 3704 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3705 }
<> 144:ef7eb2e8f9f7 3706 break;
<> 144:ef7eb2e8f9f7 3707 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3708 {
<> 144:ef7eb2e8f9f7 3709 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3710 }
<> 144:ef7eb2e8f9f7 3711 break;
<> 144:ef7eb2e8f9f7 3712 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3713 {
<> 144:ef7eb2e8f9f7 3714 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3715 }
<> 144:ef7eb2e8f9f7 3716 break;
<> 144:ef7eb2e8f9f7 3717 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3718 {
<> 144:ef7eb2e8f9f7 3719 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3720 }
<> 144:ef7eb2e8f9f7 3721 break;
<> 144:ef7eb2e8f9f7 3722 default:
<> 144:ef7eb2e8f9f7 3723 break;
<> 144:ef7eb2e8f9f7 3724 }
<> 144:ef7eb2e8f9f7 3725
<> 144:ef7eb2e8f9f7 3726 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3727 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3728
<> 144:ef7eb2e8f9f7 3729 /* Return function status */
<> 144:ef7eb2e8f9f7 3730 return HAL_OK;
<> 144:ef7eb2e8f9f7 3731 }
<> 144:ef7eb2e8f9f7 3732
<> 144:ef7eb2e8f9f7 3733 /**
<> 144:ef7eb2e8f9f7 3734 * @brief Generate a software event
<> 144:ef7eb2e8f9f7 3735 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3736 * @param EventSource: specifies the event source.
<> 144:ef7eb2e8f9f7 3737 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3738 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<> 144:ef7eb2e8f9f7 3739 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<> 144:ef7eb2e8f9f7 3740 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<> 144:ef7eb2e8f9f7 3741 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<> 144:ef7eb2e8f9f7 3742 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<> 144:ef7eb2e8f9f7 3743 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
<> 144:ef7eb2e8f9f7 3744 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<> 144:ef7eb2e8f9f7 3745 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<> 144:ef7eb2e8f9f7 3746 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
<> 144:ef7eb2e8f9f7 3747 * @retval HAL status
<> 144:ef7eb2e8f9f7 3748 * @note TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx
<> 144:ef7eb2e8f9f7 3749 * devices
<> 144:ef7eb2e8f9f7 3750 */
<> 144:ef7eb2e8f9f7 3751
<> 144:ef7eb2e8f9f7 3752 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<> 144:ef7eb2e8f9f7 3753 {
<> 144:ef7eb2e8f9f7 3754 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3755 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3756 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<> 144:ef7eb2e8f9f7 3757
<> 144:ef7eb2e8f9f7 3758 /* Process Locked */
<> 144:ef7eb2e8f9f7 3759 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3760
<> 144:ef7eb2e8f9f7 3761 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3762 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3763
<> 144:ef7eb2e8f9f7 3764 /* Set the event sources */
<> 144:ef7eb2e8f9f7 3765 htim->Instance->EGR = EventSource;
<> 144:ef7eb2e8f9f7 3766
<> 144:ef7eb2e8f9f7 3767 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3768 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3769
<> 144:ef7eb2e8f9f7 3770 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3771
<> 144:ef7eb2e8f9f7 3772 /* Return function status */
<> 144:ef7eb2e8f9f7 3773 return HAL_OK;
<> 144:ef7eb2e8f9f7 3774 }
<> 144:ef7eb2e8f9f7 3775
<> 144:ef7eb2e8f9f7 3776 /**
<> 144:ef7eb2e8f9f7 3777 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 3778 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3779 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3780 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3781 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 3782 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3783 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 3784 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 3785 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 3786 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 3787 * @retval HAL status
<> 144:ef7eb2e8f9f7 3788 */
<> 144:ef7eb2e8f9f7 3789 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3790 {
<> 144:ef7eb2e8f9f7 3791 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3792 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3793 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3794 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 3795
<> 144:ef7eb2e8f9f7 3796 /* Process Locked */
<> 144:ef7eb2e8f9f7 3797 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3798
<> 144:ef7eb2e8f9f7 3799 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3800
<> 144:ef7eb2e8f9f7 3801 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
<> 144:ef7eb2e8f9f7 3802 {
<> 144:ef7eb2e8f9f7 3803 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3804 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 3805 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 3806 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 3807
<> 144:ef7eb2e8f9f7 3808 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3809 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 3810 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 3811 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 3812 }
<> 144:ef7eb2e8f9f7 3813
<> 144:ef7eb2e8f9f7 3814 switch (Channel)
<> 144:ef7eb2e8f9f7 3815 {
<> 144:ef7eb2e8f9f7 3816 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3817 {
<> 144:ef7eb2e8f9f7 3818 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3819 {
<> 144:ef7eb2e8f9f7 3820 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3821 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3822 }
<> 144:ef7eb2e8f9f7 3823 else
<> 144:ef7eb2e8f9f7 3824 {
<> 144:ef7eb2e8f9f7 3825 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3826 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3827 }
<> 144:ef7eb2e8f9f7 3828 }
<> 144:ef7eb2e8f9f7 3829 break;
<> 144:ef7eb2e8f9f7 3830 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3831 {
<> 144:ef7eb2e8f9f7 3832 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3833 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3834 {
<> 144:ef7eb2e8f9f7 3835 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3836 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3837 }
<> 144:ef7eb2e8f9f7 3838 else
<> 144:ef7eb2e8f9f7 3839 {
<> 144:ef7eb2e8f9f7 3840 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3841 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3842 }
<> 144:ef7eb2e8f9f7 3843 }
<> 144:ef7eb2e8f9f7 3844 break;
<> 144:ef7eb2e8f9f7 3845 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3846 {
<> 144:ef7eb2e8f9f7 3847 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3848 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3849 {
<> 144:ef7eb2e8f9f7 3850 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3851 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3852 }
<> 144:ef7eb2e8f9f7 3853 else
<> 144:ef7eb2e8f9f7 3854 {
<> 144:ef7eb2e8f9f7 3855 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3856 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3857 }
<> 144:ef7eb2e8f9f7 3858 }
<> 144:ef7eb2e8f9f7 3859 break;
<> 144:ef7eb2e8f9f7 3860 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3861 {
<> 144:ef7eb2e8f9f7 3862 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3863 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3864 {
<> 144:ef7eb2e8f9f7 3865 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3866 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3867 }
<> 144:ef7eb2e8f9f7 3868 else
<> 144:ef7eb2e8f9f7 3869 {
<> 144:ef7eb2e8f9f7 3870 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3871 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3872 }
<> 144:ef7eb2e8f9f7 3873 }
<> 144:ef7eb2e8f9f7 3874 break;
<> 144:ef7eb2e8f9f7 3875 default:
<> 144:ef7eb2e8f9f7 3876 break;
<> 144:ef7eb2e8f9f7 3877 }
<> 144:ef7eb2e8f9f7 3878
<> 144:ef7eb2e8f9f7 3879 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3880
<> 144:ef7eb2e8f9f7 3881 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3882
<> 144:ef7eb2e8f9f7 3883 return HAL_OK;
<> 144:ef7eb2e8f9f7 3884 }
<> 144:ef7eb2e8f9f7 3885
<> 144:ef7eb2e8f9f7 3886 /**
<> 144:ef7eb2e8f9f7 3887 * @brief Configures the clock source to be used
<> 144:ef7eb2e8f9f7 3888 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 3889 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3890 * contains the clock source information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3891 * @retval HAL status
<> 144:ef7eb2e8f9f7 3892 */
<> 144:ef7eb2e8f9f7 3893 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
<> 144:ef7eb2e8f9f7 3894 {
<> 144:ef7eb2e8f9f7 3895 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 3896
<> 144:ef7eb2e8f9f7 3897 /* Process Locked */
<> 144:ef7eb2e8f9f7 3898 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3899
<> 144:ef7eb2e8f9f7 3900 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3901
<> 144:ef7eb2e8f9f7 3902 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3903 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<> 144:ef7eb2e8f9f7 3904
<> 144:ef7eb2e8f9f7 3905 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<> 144:ef7eb2e8f9f7 3906 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3907 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3908 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3909 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3910
<> 144:ef7eb2e8f9f7 3911 switch (sClockSourceConfig->ClockSource)
<> 144:ef7eb2e8f9f7 3912 {
<> 144:ef7eb2e8f9f7 3913 case TIM_CLOCKSOURCE_INTERNAL:
<> 144:ef7eb2e8f9f7 3914 {
<> 144:ef7eb2e8f9f7 3915 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3916 /* Disable slave mode to clock the prescaler directly with the internal clock */
<> 144:ef7eb2e8f9f7 3917 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3918 }
<> 144:ef7eb2e8f9f7 3919 break;
<> 144:ef7eb2e8f9f7 3920
<> 144:ef7eb2e8f9f7 3921 case TIM_CLOCKSOURCE_ETRMODE1:
<> 144:ef7eb2e8f9f7 3922 {
<> 144:ef7eb2e8f9f7 3923 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
<> 144:ef7eb2e8f9f7 3924 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3925
<> 144:ef7eb2e8f9f7 3926 /* Check ETR input conditioning related parameters */
<> 144:ef7eb2e8f9f7 3927 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3928 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3929 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3930
<> 144:ef7eb2e8f9f7 3931 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3932 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3933 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3934 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3935 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3936 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 3937 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3938 /* Reset the SMS and TS Bits */
<> 144:ef7eb2e8f9f7 3939 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3940 /* Select the External clock mode1 and the ETRF trigger */
<> 144:ef7eb2e8f9f7 3941 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
<> 144:ef7eb2e8f9f7 3942 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 3943 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3944 }
<> 144:ef7eb2e8f9f7 3945 break;
<> 144:ef7eb2e8f9f7 3946
<> 144:ef7eb2e8f9f7 3947 case TIM_CLOCKSOURCE_ETRMODE2:
<> 144:ef7eb2e8f9f7 3948 {
<> 144:ef7eb2e8f9f7 3949 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
<> 144:ef7eb2e8f9f7 3950 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3951
<> 144:ef7eb2e8f9f7 3952 /* Check ETR input conditioning related parameters */
<> 144:ef7eb2e8f9f7 3953 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3954 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3955 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3956
<> 144:ef7eb2e8f9f7 3957 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3958 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3959 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3960 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3961 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3962 /* Enable the External clock mode2 */
<> 144:ef7eb2e8f9f7 3963 htim->Instance->SMCR |= TIM_SMCR_ECE;
<> 144:ef7eb2e8f9f7 3964 }
<> 144:ef7eb2e8f9f7 3965 break;
<> 144:ef7eb2e8f9f7 3966
<> 144:ef7eb2e8f9f7 3967 case TIM_CLOCKSOURCE_TI1:
<> 144:ef7eb2e8f9f7 3968 {
<> 144:ef7eb2e8f9f7 3969 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 3970 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3971
<> 144:ef7eb2e8f9f7 3972 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 3973 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3974 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3975
<> 144:ef7eb2e8f9f7 3976 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 3977 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3978 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3979 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<> 144:ef7eb2e8f9f7 3980 }
<> 144:ef7eb2e8f9f7 3981 break;
<> 144:ef7eb2e8f9f7 3982 case TIM_CLOCKSOURCE_TI2:
<> 144:ef7eb2e8f9f7 3983 {
<> 144:ef7eb2e8f9f7 3984 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
<> 144:ef7eb2e8f9f7 3985 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3986
<> 144:ef7eb2e8f9f7 3987 /* Check TI2 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 3988 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3989 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3990
<> 144:ef7eb2e8f9f7 3991 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 3992 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3993 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3994 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<> 144:ef7eb2e8f9f7 3995 }
<> 144:ef7eb2e8f9f7 3996 break;
<> 144:ef7eb2e8f9f7 3997 case TIM_CLOCKSOURCE_TI1ED:
<> 144:ef7eb2e8f9f7 3998 {
<> 144:ef7eb2e8f9f7 3999 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4000 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4001
<> 144:ef7eb2e8f9f7 4002 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4003 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4004 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4005
<> 144:ef7eb2e8f9f7 4006 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4007 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4008 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4009 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<> 144:ef7eb2e8f9f7 4010 }
<> 144:ef7eb2e8f9f7 4011 break;
<> 144:ef7eb2e8f9f7 4012 case TIM_CLOCKSOURCE_ITR0:
<> 144:ef7eb2e8f9f7 4013 {
<> 144:ef7eb2e8f9f7 4014 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4015 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4016
<> 144:ef7eb2e8f9f7 4017 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<> 144:ef7eb2e8f9f7 4018 }
<> 144:ef7eb2e8f9f7 4019 break;
<> 144:ef7eb2e8f9f7 4020 case TIM_CLOCKSOURCE_ITR1:
<> 144:ef7eb2e8f9f7 4021 {
<> 144:ef7eb2e8f9f7 4022 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4023 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4024
<> 144:ef7eb2e8f9f7 4025 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<> 144:ef7eb2e8f9f7 4026 }
<> 144:ef7eb2e8f9f7 4027 break;
<> 144:ef7eb2e8f9f7 4028 case TIM_CLOCKSOURCE_ITR2:
<> 144:ef7eb2e8f9f7 4029 {
<> 144:ef7eb2e8f9f7 4030 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4031 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4032
<> 144:ef7eb2e8f9f7 4033 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<> 144:ef7eb2e8f9f7 4034 }
<> 144:ef7eb2e8f9f7 4035 break;
<> 144:ef7eb2e8f9f7 4036 case TIM_CLOCKSOURCE_ITR3:
<> 144:ef7eb2e8f9f7 4037 {
<> 144:ef7eb2e8f9f7 4038 /* Check whether or not the timer instance supports external clock mode 1 */
<> 144:ef7eb2e8f9f7 4039 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4040
<> 144:ef7eb2e8f9f7 4041 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<> 144:ef7eb2e8f9f7 4042 }
<> 144:ef7eb2e8f9f7 4043 break;
<> 144:ef7eb2e8f9f7 4044
<> 144:ef7eb2e8f9f7 4045 default:
<> 144:ef7eb2e8f9f7 4046 break;
<> 144:ef7eb2e8f9f7 4047 }
<> 144:ef7eb2e8f9f7 4048 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4049
<> 144:ef7eb2e8f9f7 4050 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4051
<> 144:ef7eb2e8f9f7 4052 return HAL_OK;
<> 144:ef7eb2e8f9f7 4053 }
<> 144:ef7eb2e8f9f7 4054
<> 144:ef7eb2e8f9f7 4055 /**
<> 144:ef7eb2e8f9f7 4056 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
<> 144:ef7eb2e8f9f7 4057 * or a XOR combination between CH1_input, CH2_input & CH3_input
<> 144:ef7eb2e8f9f7 4058 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4059 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<> 144:ef7eb2e8f9f7 4060 * output of a XOR gate.
<> 144:ef7eb2e8f9f7 4061 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4062 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<> 144:ef7eb2e8f9f7 4063 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<> 144:ef7eb2e8f9f7 4064 * pins are connected to the TI1 input (XOR combination)
<> 144:ef7eb2e8f9f7 4065 * @retval HAL status
<> 144:ef7eb2e8f9f7 4066 */
<> 144:ef7eb2e8f9f7 4067 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<> 144:ef7eb2e8f9f7 4068 {
<> 144:ef7eb2e8f9f7 4069 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4070
<> 144:ef7eb2e8f9f7 4071 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4072 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4073 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<> 144:ef7eb2e8f9f7 4074
<> 144:ef7eb2e8f9f7 4075 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4076 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 4077
<> 144:ef7eb2e8f9f7 4078 /* Reset the TI1 selection */
<> 144:ef7eb2e8f9f7 4079 tmpcr2 &= ~TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 4080
<> 144:ef7eb2e8f9f7 4081 /* Set the the TI1 selection */
<> 144:ef7eb2e8f9f7 4082 tmpcr2 |= TI1_Selection;
<> 144:ef7eb2e8f9f7 4083
<> 144:ef7eb2e8f9f7 4084 /* Write to TIMxCR2 */
<> 144:ef7eb2e8f9f7 4085 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4086
<> 144:ef7eb2e8f9f7 4087 return HAL_OK;
<> 144:ef7eb2e8f9f7 4088 }
<> 144:ef7eb2e8f9f7 4089
<> 144:ef7eb2e8f9f7 4090 /**
<> 144:ef7eb2e8f9f7 4091 * @brief Configures the TIM in Slave mode
<> 144:ef7eb2e8f9f7 4092 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4093 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4094 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4095 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4096 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4097 * @retval HAL status
<> 144:ef7eb2e8f9f7 4098 */
<> 144:ef7eb2e8f9f7 4099 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4100 {
<> 144:ef7eb2e8f9f7 4101 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4102 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4103 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4104 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4105
<> 144:ef7eb2e8f9f7 4106 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4107
<> 144:ef7eb2e8f9f7 4108 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4109
<> 144:ef7eb2e8f9f7 4110 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4111
<> 144:ef7eb2e8f9f7 4112 /* Disable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4113 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4114
<> 144:ef7eb2e8f9f7 4115 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4116 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4117
<> 144:ef7eb2e8f9f7 4118 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4119
<> 144:ef7eb2e8f9f7 4120 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4121
<> 144:ef7eb2e8f9f7 4122 return HAL_OK;
<> 144:ef7eb2e8f9f7 4123 }
<> 144:ef7eb2e8f9f7 4124
<> 144:ef7eb2e8f9f7 4125 /**
<> 144:ef7eb2e8f9f7 4126 * @brief Configures the TIM in Slave mode in interrupt mode
<> 144:ef7eb2e8f9f7 4127 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4128 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4129 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4130 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4131 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4132 * @retval HAL status
<> 144:ef7eb2e8f9f7 4133 */
<> 144:ef7eb2e8f9f7 4134 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4135 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4136 {
<> 144:ef7eb2e8f9f7 4137 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4138 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4139 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4140 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4141
<> 144:ef7eb2e8f9f7 4142 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4143
<> 144:ef7eb2e8f9f7 4144 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4145
<> 144:ef7eb2e8f9f7 4146 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4147
<> 144:ef7eb2e8f9f7 4148 /* Enable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4149 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4150
<> 144:ef7eb2e8f9f7 4151 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4152 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4153
<> 144:ef7eb2e8f9f7 4154 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4155
<> 144:ef7eb2e8f9f7 4156 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4157
<> 144:ef7eb2e8f9f7 4158 return HAL_OK;
<> 144:ef7eb2e8f9f7 4159 }
<> 144:ef7eb2e8f9f7 4160
<> 144:ef7eb2e8f9f7 4161 /**
<> 144:ef7eb2e8f9f7 4162 * @brief Read the captured value from Capture Compare unit
<> 144:ef7eb2e8f9f7 4163 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4164 * @param Channel: TIM Channels to be enabled
<> 144:ef7eb2e8f9f7 4165 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4166 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 4167 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 4168 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 4169 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 4170 * @retval Captured value
<> 144:ef7eb2e8f9f7 4171 */
<> 144:ef7eb2e8f9f7 4172 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 4173 {
<> 144:ef7eb2e8f9f7 4174 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 4175
<> 144:ef7eb2e8f9f7 4176 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4177
<> 144:ef7eb2e8f9f7 4178 switch (Channel)
<> 144:ef7eb2e8f9f7 4179 {
<> 144:ef7eb2e8f9f7 4180 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 4181 {
<> 144:ef7eb2e8f9f7 4182 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4183 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4184
<> 144:ef7eb2e8f9f7 4185 /* Return the capture 1 value */
<> 144:ef7eb2e8f9f7 4186 tmpreg = htim->Instance->CCR1;
<> 144:ef7eb2e8f9f7 4187
<> 144:ef7eb2e8f9f7 4188 break;
<> 144:ef7eb2e8f9f7 4189 }
<> 144:ef7eb2e8f9f7 4190 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 4191 {
<> 144:ef7eb2e8f9f7 4192 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4193 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4194
<> 144:ef7eb2e8f9f7 4195 /* Return the capture 2 value */
<> 144:ef7eb2e8f9f7 4196 tmpreg = htim->Instance->CCR2;
<> 144:ef7eb2e8f9f7 4197
<> 144:ef7eb2e8f9f7 4198 break;
<> 144:ef7eb2e8f9f7 4199 }
<> 144:ef7eb2e8f9f7 4200
<> 144:ef7eb2e8f9f7 4201 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 4202 {
<> 144:ef7eb2e8f9f7 4203 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4204 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4205
<> 144:ef7eb2e8f9f7 4206 /* Return the capture 3 value */
<> 144:ef7eb2e8f9f7 4207 tmpreg = htim->Instance->CCR3;
<> 144:ef7eb2e8f9f7 4208
<> 144:ef7eb2e8f9f7 4209 break;
<> 144:ef7eb2e8f9f7 4210 }
<> 144:ef7eb2e8f9f7 4211
<> 144:ef7eb2e8f9f7 4212 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 4213 {
<> 144:ef7eb2e8f9f7 4214 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4215 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4216
<> 144:ef7eb2e8f9f7 4217 /* Return the capture 4 value */
<> 144:ef7eb2e8f9f7 4218 tmpreg = htim->Instance->CCR4;
<> 144:ef7eb2e8f9f7 4219
<> 144:ef7eb2e8f9f7 4220 break;
<> 144:ef7eb2e8f9f7 4221 }
<> 144:ef7eb2e8f9f7 4222
<> 144:ef7eb2e8f9f7 4223 default:
<> 144:ef7eb2e8f9f7 4224 break;
<> 144:ef7eb2e8f9f7 4225 }
<> 144:ef7eb2e8f9f7 4226
<> 144:ef7eb2e8f9f7 4227 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4228 return tmpreg;
<> 144:ef7eb2e8f9f7 4229 }
<> 144:ef7eb2e8f9f7 4230
<> 144:ef7eb2e8f9f7 4231 /**
<> 144:ef7eb2e8f9f7 4232 * @}
<> 144:ef7eb2e8f9f7 4233 */
<> 144:ef7eb2e8f9f7 4234
<> 144:ef7eb2e8f9f7 4235 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4236 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4237 *
<> 144:ef7eb2e8f9f7 4238 @verbatim
<> 144:ef7eb2e8f9f7 4239 ==============================================================================
<> 144:ef7eb2e8f9f7 4240 ##### TIM Callbacks functions #####
<> 144:ef7eb2e8f9f7 4241 ==============================================================================
<> 144:ef7eb2e8f9f7 4242 [..]
<> 144:ef7eb2e8f9f7 4243 This section provides TIM callback functions:
<> 144:ef7eb2e8f9f7 4244 (+) Timer Period elapsed callback
<> 144:ef7eb2e8f9f7 4245 (+) Timer Output Compare callback
<> 144:ef7eb2e8f9f7 4246 (+) Timer Input capture callback
<> 144:ef7eb2e8f9f7 4247 (+) Timer Trigger callback
<> 144:ef7eb2e8f9f7 4248 (+) Timer Error callback
<> 144:ef7eb2e8f9f7 4249
<> 144:ef7eb2e8f9f7 4250 @endverbatim
<> 144:ef7eb2e8f9f7 4251 * @{
<> 144:ef7eb2e8f9f7 4252 */
<> 144:ef7eb2e8f9f7 4253
<> 144:ef7eb2e8f9f7 4254 /**
<> 144:ef7eb2e8f9f7 4255 * @brief Period elapsed callback in non blocking mode
<> 144:ef7eb2e8f9f7 4256 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 4257 * @retval None
<> 144:ef7eb2e8f9f7 4258 */
<> 144:ef7eb2e8f9f7 4259 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4260 {
<> 144:ef7eb2e8f9f7 4261 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4262 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4263
<> 144:ef7eb2e8f9f7 4264 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4265 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4266 */
<> 144:ef7eb2e8f9f7 4267
<> 144:ef7eb2e8f9f7 4268 }
<> 144:ef7eb2e8f9f7 4269 /**
<> 144:ef7eb2e8f9f7 4270 * @brief Output Compare callback in non blocking mode
<> 144:ef7eb2e8f9f7 4271 * @param htim: TIM OC handle
<> 144:ef7eb2e8f9f7 4272 * @retval None
<> 144:ef7eb2e8f9f7 4273 */
<> 144:ef7eb2e8f9f7 4274 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4275 {
<> 144:ef7eb2e8f9f7 4276 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4277 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4278
<> 144:ef7eb2e8f9f7 4279 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4280 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4281 */
<> 144:ef7eb2e8f9f7 4282 }
<> 144:ef7eb2e8f9f7 4283 /**
<> 144:ef7eb2e8f9f7 4284 * @brief Input Capture callback in non blocking mode
<> 144:ef7eb2e8f9f7 4285 * @param htim: TIM IC handle
<> 144:ef7eb2e8f9f7 4286 * @retval None
<> 144:ef7eb2e8f9f7 4287 */
<> 144:ef7eb2e8f9f7 4288 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4289 {
<> 144:ef7eb2e8f9f7 4290 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4291 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4292
<> 144:ef7eb2e8f9f7 4293 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4294 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4295 */
<> 144:ef7eb2e8f9f7 4296 }
<> 144:ef7eb2e8f9f7 4297
<> 144:ef7eb2e8f9f7 4298 /**
<> 144:ef7eb2e8f9f7 4299 * @brief PWM Pulse finished callback in non blocking mode
<> 144:ef7eb2e8f9f7 4300 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 4301 * @retval None
<> 144:ef7eb2e8f9f7 4302 */
<> 144:ef7eb2e8f9f7 4303 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4304 {
<> 144:ef7eb2e8f9f7 4305 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4306 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4307
<> 144:ef7eb2e8f9f7 4308 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4309 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4310 */
<> 144:ef7eb2e8f9f7 4311 }
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 /**
<> 144:ef7eb2e8f9f7 4314 * @brief Hall Trigger detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 4315 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 4316 * @retval None
<> 144:ef7eb2e8f9f7 4317 */
<> 144:ef7eb2e8f9f7 4318 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4319 {
<> 144:ef7eb2e8f9f7 4320 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4321 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4322
<> 144:ef7eb2e8f9f7 4323 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4324 the HAL_TIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4325 */
<> 144:ef7eb2e8f9f7 4326 }
<> 144:ef7eb2e8f9f7 4327
<> 144:ef7eb2e8f9f7 4328 /**
<> 144:ef7eb2e8f9f7 4329 * @brief Timer error callback in non blocking mode
<> 144:ef7eb2e8f9f7 4330 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 4331 * @retval None
<> 144:ef7eb2e8f9f7 4332 */
<> 144:ef7eb2e8f9f7 4333 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4334 {
<> 144:ef7eb2e8f9f7 4335 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4336 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4337
<> 144:ef7eb2e8f9f7 4338 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4339 the HAL_TIM_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4340 */
<> 144:ef7eb2e8f9f7 4341 }
<> 144:ef7eb2e8f9f7 4342
<> 144:ef7eb2e8f9f7 4343 /**
<> 144:ef7eb2e8f9f7 4344 * @}
<> 144:ef7eb2e8f9f7 4345 */
<> 144:ef7eb2e8f9f7 4346
<> 144:ef7eb2e8f9f7 4347 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<> 144:ef7eb2e8f9f7 4348 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 4349 *
<> 144:ef7eb2e8f9f7 4350 @verbatim
<> 144:ef7eb2e8f9f7 4351 ==============================================================================
<> 144:ef7eb2e8f9f7 4352 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 4353 ==============================================================================
<> 144:ef7eb2e8f9f7 4354 [..]
<> 144:ef7eb2e8f9f7 4355 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 4356 and the data flow.
<> 144:ef7eb2e8f9f7 4357
<> 144:ef7eb2e8f9f7 4358 @endverbatim
<> 144:ef7eb2e8f9f7 4359 * @{
<> 144:ef7eb2e8f9f7 4360 */
<> 144:ef7eb2e8f9f7 4361
<> 144:ef7eb2e8f9f7 4362 /**
<> 144:ef7eb2e8f9f7 4363 * @brief Return the TIM Base state
<> 144:ef7eb2e8f9f7 4364 * @param htim: TIM Base handle
<> 144:ef7eb2e8f9f7 4365 * @retval HAL state
<> 144:ef7eb2e8f9f7 4366 */
<> 144:ef7eb2e8f9f7 4367 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4368 {
<> 144:ef7eb2e8f9f7 4369 return htim->State;
<> 144:ef7eb2e8f9f7 4370 }
<> 144:ef7eb2e8f9f7 4371
<> 144:ef7eb2e8f9f7 4372 /**
<> 144:ef7eb2e8f9f7 4373 * @brief Return the TIM OC state
<> 144:ef7eb2e8f9f7 4374 * @param htim: TIM Ouput Compare handle
<> 144:ef7eb2e8f9f7 4375 * @retval HAL state
<> 144:ef7eb2e8f9f7 4376 */
<> 144:ef7eb2e8f9f7 4377 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4378 {
<> 144:ef7eb2e8f9f7 4379 return htim->State;
<> 144:ef7eb2e8f9f7 4380 }
<> 144:ef7eb2e8f9f7 4381
<> 144:ef7eb2e8f9f7 4382 /**
<> 144:ef7eb2e8f9f7 4383 * @brief Return the TIM PWM state
<> 144:ef7eb2e8f9f7 4384 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 4385 * @retval HAL state
<> 144:ef7eb2e8f9f7 4386 */
<> 144:ef7eb2e8f9f7 4387 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4388 {
<> 144:ef7eb2e8f9f7 4389 return htim->State;
<> 144:ef7eb2e8f9f7 4390 }
<> 144:ef7eb2e8f9f7 4391
<> 144:ef7eb2e8f9f7 4392 /**
<> 144:ef7eb2e8f9f7 4393 * @brief Return the TIM Input Capture state
<> 144:ef7eb2e8f9f7 4394 * @param htim: TIM IC handle
<> 144:ef7eb2e8f9f7 4395 * @retval HAL state
<> 144:ef7eb2e8f9f7 4396 */
<> 144:ef7eb2e8f9f7 4397 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4398 {
<> 144:ef7eb2e8f9f7 4399 return htim->State;
<> 144:ef7eb2e8f9f7 4400 }
<> 144:ef7eb2e8f9f7 4401
<> 144:ef7eb2e8f9f7 4402 /**
<> 144:ef7eb2e8f9f7 4403 * @brief Return the TIM One Pulse Mode state
<> 144:ef7eb2e8f9f7 4404 * @param htim: TIM OPM handle
<> 144:ef7eb2e8f9f7 4405 * @retval HAL state
<> 144:ef7eb2e8f9f7 4406 */
<> 144:ef7eb2e8f9f7 4407 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4408 {
<> 144:ef7eb2e8f9f7 4409 return htim->State;
<> 144:ef7eb2e8f9f7 4410 }
<> 144:ef7eb2e8f9f7 4411
<> 144:ef7eb2e8f9f7 4412 /**
<> 144:ef7eb2e8f9f7 4413 * @brief Return the TIM Encoder Mode state
<> 144:ef7eb2e8f9f7 4414 * @param htim: TIM Encoder handle
<> 144:ef7eb2e8f9f7 4415 * @retval HAL state
<> 144:ef7eb2e8f9f7 4416 */
<> 144:ef7eb2e8f9f7 4417 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4418 {
<> 144:ef7eb2e8f9f7 4419 return htim->State;
<> 144:ef7eb2e8f9f7 4420 }
<> 144:ef7eb2e8f9f7 4421
<> 144:ef7eb2e8f9f7 4422 /**
<> 144:ef7eb2e8f9f7 4423 * @}
<> 144:ef7eb2e8f9f7 4424 */
<> 144:ef7eb2e8f9f7 4425
<> 144:ef7eb2e8f9f7 4426 /**
<> 144:ef7eb2e8f9f7 4427 * @}
<> 144:ef7eb2e8f9f7 4428 */
<> 144:ef7eb2e8f9f7 4429
<> 144:ef7eb2e8f9f7 4430 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
<> 144:ef7eb2e8f9f7 4431 * @{
<> 144:ef7eb2e8f9f7 4432 */
<> 144:ef7eb2e8f9f7 4433
<> 144:ef7eb2e8f9f7 4434 /**
<> 144:ef7eb2e8f9f7 4435 * @brief TIM DMA error callback
<> 144:ef7eb2e8f9f7 4436 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4437 * @retval None
<> 144:ef7eb2e8f9f7 4438 */
<> 144:ef7eb2e8f9f7 4439 void TIM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4440 {
<> 144:ef7eb2e8f9f7 4441 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4442
<> 144:ef7eb2e8f9f7 4443 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4444
<> 144:ef7eb2e8f9f7 4445 HAL_TIM_ErrorCallback(htim);
<> 144:ef7eb2e8f9f7 4446 }
<> 144:ef7eb2e8f9f7 4447
<> 144:ef7eb2e8f9f7 4448 /**
<> 144:ef7eb2e8f9f7 4449 * @brief TIM DMA Delay Pulse complete callback.
<> 144:ef7eb2e8f9f7 4450 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4451 * @retval None
<> 144:ef7eb2e8f9f7 4452 */
<> 144:ef7eb2e8f9f7 4453 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4454 {
<> 144:ef7eb2e8f9f7 4455 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4456
<> 144:ef7eb2e8f9f7 4457 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4458
<> 144:ef7eb2e8f9f7 4459 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4460 {
<> 144:ef7eb2e8f9f7 4461 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4462 }
<> 144:ef7eb2e8f9f7 4463 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4464 {
<> 144:ef7eb2e8f9f7 4465 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4466 }
<> 144:ef7eb2e8f9f7 4467 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4468 {
<> 144:ef7eb2e8f9f7 4469 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4470 }
<> 144:ef7eb2e8f9f7 4471 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4472 {
<> 144:ef7eb2e8f9f7 4473 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4474 }
<> 144:ef7eb2e8f9f7 4475
<> 144:ef7eb2e8f9f7 4476 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 4477
<> 144:ef7eb2e8f9f7 4478 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4479 }
<> 144:ef7eb2e8f9f7 4480 /**
<> 144:ef7eb2e8f9f7 4481 * @brief TIM DMA Capture complete callback.
<> 144:ef7eb2e8f9f7 4482 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4483 * @retval None
<> 144:ef7eb2e8f9f7 4484 */
<> 144:ef7eb2e8f9f7 4485 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4486 {
<> 144:ef7eb2e8f9f7 4487 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4488
<> 144:ef7eb2e8f9f7 4489 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4490
<> 144:ef7eb2e8f9f7 4491 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4492 {
<> 144:ef7eb2e8f9f7 4493 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4494 }
<> 144:ef7eb2e8f9f7 4495 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4496 {
<> 144:ef7eb2e8f9f7 4497 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4498 }
<> 144:ef7eb2e8f9f7 4499 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4500 {
<> 144:ef7eb2e8f9f7 4501 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4502 }
<> 144:ef7eb2e8f9f7 4503 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4504 {
<> 144:ef7eb2e8f9f7 4505 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4506 }
<> 144:ef7eb2e8f9f7 4507
<> 144:ef7eb2e8f9f7 4508 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4511 }
<> 144:ef7eb2e8f9f7 4512
<> 144:ef7eb2e8f9f7 4513 /**
<> 144:ef7eb2e8f9f7 4514 * @brief TIM DMA Period Elapse complete callback.
<> 144:ef7eb2e8f9f7 4515 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4516 * @retval None
<> 144:ef7eb2e8f9f7 4517 */
<> 144:ef7eb2e8f9f7 4518 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4519 {
<> 144:ef7eb2e8f9f7 4520 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4521
<> 144:ef7eb2e8f9f7 4522 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4523
<> 144:ef7eb2e8f9f7 4524 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 4525 }
<> 144:ef7eb2e8f9f7 4526
<> 144:ef7eb2e8f9f7 4527 /**
<> 144:ef7eb2e8f9f7 4528 * @brief TIM DMA Trigger callback.
<> 144:ef7eb2e8f9f7 4529 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 4530 * @retval None
<> 144:ef7eb2e8f9f7 4531 */
<> 144:ef7eb2e8f9f7 4532 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4533 {
<> 144:ef7eb2e8f9f7 4534 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4535
<> 144:ef7eb2e8f9f7 4536 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4537
<> 144:ef7eb2e8f9f7 4538 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 4539 }
<> 144:ef7eb2e8f9f7 4540
<> 144:ef7eb2e8f9f7 4541 /**
<> 144:ef7eb2e8f9f7 4542 * @brief Time Base configuration
<> 144:ef7eb2e8f9f7 4543 * @param TIMx: TIM periheral
<> 144:ef7eb2e8f9f7 4544 * @param Structure: TIM Base configuration structure
<> 144:ef7eb2e8f9f7 4545 * @retval None
<> 144:ef7eb2e8f9f7 4546 */
<> 144:ef7eb2e8f9f7 4547 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
<> 144:ef7eb2e8f9f7 4548 {
<> 144:ef7eb2e8f9f7 4549 uint32_t tmpcr1 = 0;
<> 144:ef7eb2e8f9f7 4550 tmpcr1 = TIMx->CR1;
<> 144:ef7eb2e8f9f7 4551
<> 144:ef7eb2e8f9f7 4552 /* Set TIM Time Base Unit parameters ---------------------------------------*/
<> 144:ef7eb2e8f9f7 4553 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4554 {
<> 144:ef7eb2e8f9f7 4555 /* Select the Counter Mode */
<> 144:ef7eb2e8f9f7 4556 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
<> 144:ef7eb2e8f9f7 4557 tmpcr1 |= Structure->CounterMode;
<> 144:ef7eb2e8f9f7 4558 }
<> 144:ef7eb2e8f9f7 4559
<> 144:ef7eb2e8f9f7 4560 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4561 {
<> 144:ef7eb2e8f9f7 4562 /* Set the clock division */
<> 144:ef7eb2e8f9f7 4563 tmpcr1 &= ~TIM_CR1_CKD;
<> 144:ef7eb2e8f9f7 4564 tmpcr1 |= (uint32_t)Structure->ClockDivision;
<> 144:ef7eb2e8f9f7 4565 }
<> 144:ef7eb2e8f9f7 4566
<> 144:ef7eb2e8f9f7 4567 TIMx->CR1 = tmpcr1;
<> 144:ef7eb2e8f9f7 4568
<> 144:ef7eb2e8f9f7 4569 /* Set the Autoreload value */
<> 144:ef7eb2e8f9f7 4570 TIMx->ARR = (uint32_t)Structure->Period ;
<> 144:ef7eb2e8f9f7 4571
<> 144:ef7eb2e8f9f7 4572 /* Set the Prescaler value */
<> 144:ef7eb2e8f9f7 4573 TIMx->PSC = (uint32_t)Structure->Prescaler;
<> 144:ef7eb2e8f9f7 4574
<> 144:ef7eb2e8f9f7 4575 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4576 {
<> 144:ef7eb2e8f9f7 4577 /* Set the Repetition Counter value */
<> 144:ef7eb2e8f9f7 4578 TIMx->RCR = Structure->RepetitionCounter;
<> 144:ef7eb2e8f9f7 4579 }
<> 144:ef7eb2e8f9f7 4580
<> 144:ef7eb2e8f9f7 4581 /* Generate an update event to reload the Prescaler
<> 144:ef7eb2e8f9f7 4582 and the repetition counter(only for TIM1 and TIM8) value immediatly */
<> 144:ef7eb2e8f9f7 4583 TIMx->EGR = TIM_EGR_UG;
<> 144:ef7eb2e8f9f7 4584 }
<> 144:ef7eb2e8f9f7 4585
<> 144:ef7eb2e8f9f7 4586 /**
<> 144:ef7eb2e8f9f7 4587 * @brief Time Ouput Compare 1 configuration
<> 144:ef7eb2e8f9f7 4588 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4589 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4590 * @retval None
<> 144:ef7eb2e8f9f7 4591 */
<> 144:ef7eb2e8f9f7 4592 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4593 {
<> 144:ef7eb2e8f9f7 4594 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4595 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4596 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4597
<> 144:ef7eb2e8f9f7 4598 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4599 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4600
<> 144:ef7eb2e8f9f7 4601 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4602 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4603 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4604 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4605
<> 144:ef7eb2e8f9f7 4606 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4607 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4608
<> 144:ef7eb2e8f9f7 4609 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 4610 tmpccmrx &= ~TIM_CCMR1_OC1M;
<> 144:ef7eb2e8f9f7 4611 tmpccmrx &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4612 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4613 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4614
<> 144:ef7eb2e8f9f7 4615 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4616 tmpccer &= ~TIM_CCER_CC1P;
<> 144:ef7eb2e8f9f7 4617 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4618 tmpccer |= OC_Config->OCPolarity;
<> 144:ef7eb2e8f9f7 4619
<> 144:ef7eb2e8f9f7 4620 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
<> 144:ef7eb2e8f9f7 4621 {
<> 144:ef7eb2e8f9f7 4622 /* Check parameters */
<> 144:ef7eb2e8f9f7 4623 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4624
<> 144:ef7eb2e8f9f7 4625 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4626 tmpccer &= ~TIM_CCER_CC1NP;
<> 144:ef7eb2e8f9f7 4627 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4628 tmpccer |= OC_Config->OCNPolarity;
<> 144:ef7eb2e8f9f7 4629 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4630 tmpccer &= ~TIM_CCER_CC1NE;
<> 144:ef7eb2e8f9f7 4631 }
<> 144:ef7eb2e8f9f7 4632
<> 144:ef7eb2e8f9f7 4633 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4634 {
<> 144:ef7eb2e8f9f7 4635 /* Check parameters */
<> 144:ef7eb2e8f9f7 4636 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4637 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4638
<> 144:ef7eb2e8f9f7 4639 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4640 tmpcr2 &= ~TIM_CR2_OIS1;
<> 144:ef7eb2e8f9f7 4641 tmpcr2 &= ~TIM_CR2_OIS1N;
<> 144:ef7eb2e8f9f7 4642 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4643 tmpcr2 |= OC_Config->OCIdleState;
<> 144:ef7eb2e8f9f7 4644 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4645 tmpcr2 |= OC_Config->OCNIdleState;
<> 144:ef7eb2e8f9f7 4646 }
<> 144:ef7eb2e8f9f7 4647 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4648 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4649
<> 144:ef7eb2e8f9f7 4650 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4651 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4652
<> 144:ef7eb2e8f9f7 4653 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4654 TIMx->CCR1 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4655
<> 144:ef7eb2e8f9f7 4656 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4657 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4658 }
<> 144:ef7eb2e8f9f7 4659
<> 144:ef7eb2e8f9f7 4660 /**
<> 144:ef7eb2e8f9f7 4661 * @brief Time Ouput Compare 2 configuration
<> 144:ef7eb2e8f9f7 4662 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4663 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4664 * @retval None
<> 144:ef7eb2e8f9f7 4665 */
<> 144:ef7eb2e8f9f7 4666 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4667 {
<> 144:ef7eb2e8f9f7 4668 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4669 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4670 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4671
<> 144:ef7eb2e8f9f7 4672 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4673 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4674
<> 144:ef7eb2e8f9f7 4675 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4676 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4677 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4678 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4679
<> 144:ef7eb2e8f9f7 4680 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4681 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4682
<> 144:ef7eb2e8f9f7 4683 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4684 tmpccmrx &= ~TIM_CCMR1_OC2M;
<> 144:ef7eb2e8f9f7 4685 tmpccmrx &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 4686
<> 144:ef7eb2e8f9f7 4687 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4688 tmpccmrx |= (OC_Config->OCMode << 8);
<> 144:ef7eb2e8f9f7 4689
<> 144:ef7eb2e8f9f7 4690 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4691 tmpccer &= ~TIM_CCER_CC2P;
<> 144:ef7eb2e8f9f7 4692 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4693 tmpccer |= (OC_Config->OCPolarity << 4);
<> 144:ef7eb2e8f9f7 4694
<> 144:ef7eb2e8f9f7 4695 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 4696 {
<> 144:ef7eb2e8f9f7 4697 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4698
<> 144:ef7eb2e8f9f7 4699 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4700 tmpccer &= ~TIM_CCER_CC2NP;
<> 144:ef7eb2e8f9f7 4701 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4702 tmpccer |= (OC_Config->OCNPolarity << 4);
<> 144:ef7eb2e8f9f7 4703 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4704 tmpccer &= ~TIM_CCER_CC2NE;
<> 144:ef7eb2e8f9f7 4705
<> 144:ef7eb2e8f9f7 4706 }
<> 144:ef7eb2e8f9f7 4707
<> 144:ef7eb2e8f9f7 4708 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4709 {
<> 144:ef7eb2e8f9f7 4710 /* Check parameters */
<> 144:ef7eb2e8f9f7 4711 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4712 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4713
<> 144:ef7eb2e8f9f7 4714 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4715 tmpcr2 &= ~TIM_CR2_OIS2;
<> 144:ef7eb2e8f9f7 4716 tmpcr2 &= ~TIM_CR2_OIS2N;
<> 144:ef7eb2e8f9f7 4717 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4718 tmpcr2 |= (OC_Config->OCIdleState << 2);
<> 144:ef7eb2e8f9f7 4719 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4720 tmpcr2 |= (OC_Config->OCNIdleState << 2);
<> 144:ef7eb2e8f9f7 4721 }
<> 144:ef7eb2e8f9f7 4722
<> 144:ef7eb2e8f9f7 4723 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4724 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4725
<> 144:ef7eb2e8f9f7 4726 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4727 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4728
<> 144:ef7eb2e8f9f7 4729 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4730 TIMx->CCR2 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4731
<> 144:ef7eb2e8f9f7 4732 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4733 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4734 }
<> 144:ef7eb2e8f9f7 4735
<> 144:ef7eb2e8f9f7 4736 /**
<> 144:ef7eb2e8f9f7 4737 * @brief Time Ouput Compare 3 configuration
<> 144:ef7eb2e8f9f7 4738 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4739 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4740 * @retval None
<> 144:ef7eb2e8f9f7 4741 */
<> 144:ef7eb2e8f9f7 4742 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4743 {
<> 144:ef7eb2e8f9f7 4744 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4745 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4746 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4747
<> 144:ef7eb2e8f9f7 4748 /* Disable the Channel 3: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4749 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4750
<> 144:ef7eb2e8f9f7 4751 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4752 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4753 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4754 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4755
<> 144:ef7eb2e8f9f7 4756 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4757 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4758
<> 144:ef7eb2e8f9f7 4759 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4760 tmpccmrx &= ~TIM_CCMR2_OC3M;
<> 144:ef7eb2e8f9f7 4761 tmpccmrx &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4762 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4763 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4764
<> 144:ef7eb2e8f9f7 4765 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4766 tmpccer &= ~TIM_CCER_CC3P;
<> 144:ef7eb2e8f9f7 4767 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4768 tmpccer |= (OC_Config->OCPolarity << 8);
<> 144:ef7eb2e8f9f7 4769
<> 144:ef7eb2e8f9f7 4770 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 4771 {
<> 144:ef7eb2e8f9f7 4772 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4773
<> 144:ef7eb2e8f9f7 4774 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4775 tmpccer &= ~TIM_CCER_CC3NP;
<> 144:ef7eb2e8f9f7 4776 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4777 tmpccer |= (OC_Config->OCNPolarity << 8);
<> 144:ef7eb2e8f9f7 4778 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4779 tmpccer &= ~TIM_CCER_CC3NE;
<> 144:ef7eb2e8f9f7 4780 }
<> 144:ef7eb2e8f9f7 4781
<> 144:ef7eb2e8f9f7 4782 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4783 {
<> 144:ef7eb2e8f9f7 4784 /* Check parameters */
<> 144:ef7eb2e8f9f7 4785 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
<> 144:ef7eb2e8f9f7 4786 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4787
<> 144:ef7eb2e8f9f7 4788 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4789 tmpcr2 &= ~TIM_CR2_OIS3;
<> 144:ef7eb2e8f9f7 4790 tmpcr2 &= ~TIM_CR2_OIS3N;
<> 144:ef7eb2e8f9f7 4791 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4792 tmpcr2 |= (OC_Config->OCIdleState << 4);
<> 144:ef7eb2e8f9f7 4793 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4794 tmpcr2 |= (OC_Config->OCNIdleState << 4);
<> 144:ef7eb2e8f9f7 4795 }
<> 144:ef7eb2e8f9f7 4796
<> 144:ef7eb2e8f9f7 4797 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4798 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4799
<> 144:ef7eb2e8f9f7 4800 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4801 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4802
<> 144:ef7eb2e8f9f7 4803 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4804 TIMx->CCR3 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4805
<> 144:ef7eb2e8f9f7 4806 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4807 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4808 }
<> 144:ef7eb2e8f9f7 4809
<> 144:ef7eb2e8f9f7 4810 /**
<> 144:ef7eb2e8f9f7 4811 * @brief Time Ouput Compare 4 configuration
<> 144:ef7eb2e8f9f7 4812 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4813 * @param OC_Config: The ouput configuration structure
<> 144:ef7eb2e8f9f7 4814 * @retval None
<> 144:ef7eb2e8f9f7 4815 */
<> 144:ef7eb2e8f9f7 4816 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4817 {
<> 144:ef7eb2e8f9f7 4818 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4819 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4820 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4821
<> 144:ef7eb2e8f9f7 4822 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4823 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4824
<> 144:ef7eb2e8f9f7 4825 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4826 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4827 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4828 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4829
<> 144:ef7eb2e8f9f7 4830 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4831 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4832
<> 144:ef7eb2e8f9f7 4833 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4834 tmpccmrx &= ~TIM_CCMR2_OC4M;
<> 144:ef7eb2e8f9f7 4835 tmpccmrx &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 4836
<> 144:ef7eb2e8f9f7 4837 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4838 tmpccmrx |= (OC_Config->OCMode << 8);
<> 144:ef7eb2e8f9f7 4839
<> 144:ef7eb2e8f9f7 4840 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4841 tmpccer &= ~TIM_CCER_CC4P;
<> 144:ef7eb2e8f9f7 4842 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4843 tmpccer |= (OC_Config->OCPolarity << 12);
<> 144:ef7eb2e8f9f7 4844
<> 144:ef7eb2e8f9f7 4845 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 4846 {
<> 144:ef7eb2e8f9f7 4847 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4848
<> 144:ef7eb2e8f9f7 4849 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 4850 tmpcr2 &= ~TIM_CR2_OIS4;
<> 144:ef7eb2e8f9f7 4851 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4852 tmpcr2 |= (OC_Config->OCIdleState << 6);
<> 144:ef7eb2e8f9f7 4853 }
<> 144:ef7eb2e8f9f7 4854
<> 144:ef7eb2e8f9f7 4855 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4856 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4857
<> 144:ef7eb2e8f9f7 4858 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4859 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4860
<> 144:ef7eb2e8f9f7 4861 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4862 TIMx->CCR4 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4863
<> 144:ef7eb2e8f9f7 4864 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4865 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4866 }
<> 144:ef7eb2e8f9f7 4867
<> 144:ef7eb2e8f9f7 4868 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4869 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4870 {
<> 144:ef7eb2e8f9f7 4871 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 4872 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 4873 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4874
<> 144:ef7eb2e8f9f7 4875 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4876 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4877
<> 144:ef7eb2e8f9f7 4878 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 4879 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 4880 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 4881 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 4882
<> 144:ef7eb2e8f9f7 4883 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 4884 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 4885 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 4886 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 4887
<> 144:ef7eb2e8f9f7 4888 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4889 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4890
<> 144:ef7eb2e8f9f7 4891 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 4892 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 4893 {
<> 144:ef7eb2e8f9f7 4894 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 4895 {
<> 144:ef7eb2e8f9f7 4896 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4897 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4898 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 4899 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4900 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4901 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 4902 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4903 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 4904 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4905 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4906 }
<> 144:ef7eb2e8f9f7 4907 break;
<> 144:ef7eb2e8f9f7 4908
<> 144:ef7eb2e8f9f7 4909 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 4910 {
<> 144:ef7eb2e8f9f7 4911 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4912 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4913 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4914
<> 144:ef7eb2e8f9f7 4915 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4916 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 4917 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4918 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 4919
<> 144:ef7eb2e8f9f7 4920 /* Set the filter */
<> 144:ef7eb2e8f9f7 4921 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 4922 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
<> 144:ef7eb2e8f9f7 4923
<> 144:ef7eb2e8f9f7 4924 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4925 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 4926 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4927
<> 144:ef7eb2e8f9f7 4928 }
<> 144:ef7eb2e8f9f7 4929 break;
<> 144:ef7eb2e8f9f7 4930
<> 144:ef7eb2e8f9f7 4931 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 4932 {
<> 144:ef7eb2e8f9f7 4933 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4934 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4935 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4936 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4937
<> 144:ef7eb2e8f9f7 4938 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 4939 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4940 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4941 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4942 }
<> 144:ef7eb2e8f9f7 4943 break;
<> 144:ef7eb2e8f9f7 4944
<> 144:ef7eb2e8f9f7 4945 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 4946 {
<> 144:ef7eb2e8f9f7 4947 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4948 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4949 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4950 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4951
<> 144:ef7eb2e8f9f7 4952 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 4953 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4954 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4955 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4956 }
<> 144:ef7eb2e8f9f7 4957 break;
<> 144:ef7eb2e8f9f7 4958
<> 144:ef7eb2e8f9f7 4959 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 4960 {
<> 144:ef7eb2e8f9f7 4961 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4962 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4963 }
<> 144:ef7eb2e8f9f7 4964 break;
<> 144:ef7eb2e8f9f7 4965
<> 144:ef7eb2e8f9f7 4966 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 4967 {
<> 144:ef7eb2e8f9f7 4968 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4969 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4970 }
<> 144:ef7eb2e8f9f7 4971 break;
<> 144:ef7eb2e8f9f7 4972
<> 144:ef7eb2e8f9f7 4973 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 4974 {
<> 144:ef7eb2e8f9f7 4975 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4976 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4977 }
<> 144:ef7eb2e8f9f7 4978 break;
<> 144:ef7eb2e8f9f7 4979
<> 144:ef7eb2e8f9f7 4980 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 4981 {
<> 144:ef7eb2e8f9f7 4982 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4983 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4984 }
<> 144:ef7eb2e8f9f7 4985 break;
<> 144:ef7eb2e8f9f7 4986
<> 144:ef7eb2e8f9f7 4987 default:
<> 144:ef7eb2e8f9f7 4988 break;
<> 144:ef7eb2e8f9f7 4989 }
<> 144:ef7eb2e8f9f7 4990 }
<> 144:ef7eb2e8f9f7 4991
<> 144:ef7eb2e8f9f7 4992 /**
<> 144:ef7eb2e8f9f7 4993 * @brief Configure the TI1 as Input.
<> 144:ef7eb2e8f9f7 4994 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 4995 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 4996 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4997 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 4998 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 4999 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5000 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5001 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5002 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5003 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5004 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5005 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5006 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5007 * @retval None
<> 144:ef7eb2e8f9f7 5008 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<> 144:ef7eb2e8f9f7 5009 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5010 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5011 */
<> 144:ef7eb2e8f9f7 5012 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5013 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5014 {
<> 144:ef7eb2e8f9f7 5015 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5016 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5017
<> 144:ef7eb2e8f9f7 5018 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5019 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5020 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5021 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5022
<> 144:ef7eb2e8f9f7 5023 /* Select the Input */
<> 144:ef7eb2e8f9f7 5024 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 5025 {
<> 144:ef7eb2e8f9f7 5026 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 5027 tmpccmr1 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5028 }
<> 144:ef7eb2e8f9f7 5029 else
<> 144:ef7eb2e8f9f7 5030 {
<> 144:ef7eb2e8f9f7 5031 tmpccmr1 |= TIM_CCMR1_CC1S_0;
<> 144:ef7eb2e8f9f7 5032 }
<> 144:ef7eb2e8f9f7 5033
<> 144:ef7eb2e8f9f7 5034 /* Set the filter */
<> 144:ef7eb2e8f9f7 5035 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5036 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
<> 144:ef7eb2e8f9f7 5037
<> 144:ef7eb2e8f9f7 5038 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5039 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5040 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
<> 144:ef7eb2e8f9f7 5041
<> 144:ef7eb2e8f9f7 5042 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5043 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5044 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5045 }
<> 144:ef7eb2e8f9f7 5046
<> 144:ef7eb2e8f9f7 5047 /**
<> 144:ef7eb2e8f9f7 5048 * @brief Configure the Polarity and Filter for TI1.
<> 144:ef7eb2e8f9f7 5049 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5050 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5051 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5052 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5053 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5054 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5055 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5056 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5057 * @retval None
<> 144:ef7eb2e8f9f7 5058 */
<> 144:ef7eb2e8f9f7 5059 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5060 {
<> 144:ef7eb2e8f9f7 5061 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5062 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5063
<> 144:ef7eb2e8f9f7 5064 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5065 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5066 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5067 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5068
<> 144:ef7eb2e8f9f7 5069 /* Set the filter */
<> 144:ef7eb2e8f9f7 5070 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5071 tmpccmr1 |= (TIM_ICFilter << 4);
<> 144:ef7eb2e8f9f7 5072
<> 144:ef7eb2e8f9f7 5073 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5074 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5075 tmpccer |= TIM_ICPolarity;
<> 144:ef7eb2e8f9f7 5076
<> 144:ef7eb2e8f9f7 5077 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5078 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5079 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5080 }
<> 144:ef7eb2e8f9f7 5081
<> 144:ef7eb2e8f9f7 5082 /**
<> 144:ef7eb2e8f9f7 5083 * @brief Configure the TI2 as Input.
<> 144:ef7eb2e8f9f7 5084 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5085 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5086 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5087 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5088 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5089 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5090 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5091 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5092 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5093 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5094 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5095 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5096 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5097 * @retval None
<> 144:ef7eb2e8f9f7 5098 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<> 144:ef7eb2e8f9f7 5099 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5100 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5101 */
<> 144:ef7eb2e8f9f7 5102 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5103 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5104 {
<> 144:ef7eb2e8f9f7 5105 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5106 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5107
<> 144:ef7eb2e8f9f7 5108 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5109 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5110 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5111 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5112
<> 144:ef7eb2e8f9f7 5113 /* Select the Input */
<> 144:ef7eb2e8f9f7 5114 tmpccmr1 &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 5115 tmpccmr1 |= (TIM_ICSelection << 8);
<> 144:ef7eb2e8f9f7 5116
<> 144:ef7eb2e8f9f7 5117 /* Set the filter */
<> 144:ef7eb2e8f9f7 5118 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 144:ef7eb2e8f9f7 5119 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 5120
<> 144:ef7eb2e8f9f7 5121 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5122 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 5123 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
<> 144:ef7eb2e8f9f7 5124
<> 144:ef7eb2e8f9f7 5125 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5126 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5127 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5128 }
<> 144:ef7eb2e8f9f7 5129
<> 144:ef7eb2e8f9f7 5130 /**
<> 144:ef7eb2e8f9f7 5131 * @brief Configure the Polarity and Filter for TI2.
<> 144:ef7eb2e8f9f7 5132 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5133 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5134 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5135 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5136 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5137 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5138 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5139 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5140 * @retval None
<> 144:ef7eb2e8f9f7 5141 */
<> 144:ef7eb2e8f9f7 5142 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5143 {
<> 144:ef7eb2e8f9f7 5144 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5145 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5146
<> 144:ef7eb2e8f9f7 5147 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5148 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5149 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5150 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5151
<> 144:ef7eb2e8f9f7 5152 /* Set the filter */
<> 144:ef7eb2e8f9f7 5153 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 144:ef7eb2e8f9f7 5154 tmpccmr1 |= (TIM_ICFilter << 12);
<> 144:ef7eb2e8f9f7 5155
<> 144:ef7eb2e8f9f7 5156 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5157 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 5158 tmpccer |= (TIM_ICPolarity << 4);
<> 144:ef7eb2e8f9f7 5159
<> 144:ef7eb2e8f9f7 5160 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5161 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5162 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5163 }
<> 144:ef7eb2e8f9f7 5164
<> 144:ef7eb2e8f9f7 5165 /**
<> 144:ef7eb2e8f9f7 5166 * @brief Configure the TI3 as Input.
<> 144:ef7eb2e8f9f7 5167 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5168 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5169 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5170 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5171 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5172 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5173 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5174 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5175 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5176 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5177 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5178 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5179 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5180 * @retval None
<> 144:ef7eb2e8f9f7 5181 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<> 144:ef7eb2e8f9f7 5182 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5183 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5184 */
<> 144:ef7eb2e8f9f7 5185 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5186 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5187 {
<> 144:ef7eb2e8f9f7 5188 uint32_t tmpccmr2 = 0;
<> 144:ef7eb2e8f9f7 5189 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5190
<> 144:ef7eb2e8f9f7 5191 /* Disable the Channel 3: Reset the CC3E Bit */
<> 144:ef7eb2e8f9f7 5192 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 5193 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5194 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5195
<> 144:ef7eb2e8f9f7 5196 /* Select the Input */
<> 144:ef7eb2e8f9f7 5197 tmpccmr2 &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 5198 tmpccmr2 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5199
<> 144:ef7eb2e8f9f7 5200 /* Set the filter */
<> 144:ef7eb2e8f9f7 5201 tmpccmr2 &= ~TIM_CCMR2_IC3F;
<> 144:ef7eb2e8f9f7 5202 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
<> 144:ef7eb2e8f9f7 5203
<> 144:ef7eb2e8f9f7 5204 /* Select the Polarity and set the CC3E Bit */
<> 144:ef7eb2e8f9f7 5205 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
<> 144:ef7eb2e8f9f7 5206 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
<> 144:ef7eb2e8f9f7 5207
<> 144:ef7eb2e8f9f7 5208 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5209 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5210 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5211 }
<> 144:ef7eb2e8f9f7 5212
<> 144:ef7eb2e8f9f7 5213 /**
<> 144:ef7eb2e8f9f7 5214 * @brief Configure the TI4 as Input.
<> 144:ef7eb2e8f9f7 5215 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5216 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5217 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5218 * @arg TIM_ICPOLARITY_RISING
<> 144:ef7eb2e8f9f7 5219 * @arg TIM_ICPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 5220 * @arg TIM_ICPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 5221 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5222 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5223 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5224 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5225 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5226 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5227 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5228 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<> 144:ef7eb2e8f9f7 5229 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5230 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5231 * @retval None
<> 144:ef7eb2e8f9f7 5232 */
<> 144:ef7eb2e8f9f7 5233 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5234 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5235 {
<> 144:ef7eb2e8f9f7 5236 uint32_t tmpccmr2 = 0;
<> 144:ef7eb2e8f9f7 5237 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5238
<> 144:ef7eb2e8f9f7 5239 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 5240 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 5241 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5242 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5243
<> 144:ef7eb2e8f9f7 5244 /* Select the Input */
<> 144:ef7eb2e8f9f7 5245 tmpccmr2 &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 5246 tmpccmr2 |= (TIM_ICSelection << 8);
<> 144:ef7eb2e8f9f7 5247
<> 144:ef7eb2e8f9f7 5248 /* Set the filter */
<> 144:ef7eb2e8f9f7 5249 tmpccmr2 &= ~TIM_CCMR2_IC4F;
<> 144:ef7eb2e8f9f7 5250 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
<> 144:ef7eb2e8f9f7 5251
<> 144:ef7eb2e8f9f7 5252 /* Select the Polarity and set the CC4E Bit */
<> 144:ef7eb2e8f9f7 5253 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
<> 144:ef7eb2e8f9f7 5254 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
<> 144:ef7eb2e8f9f7 5255
<> 144:ef7eb2e8f9f7 5256 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5257 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5258 TIMx->CCER = tmpccer ;
<> 144:ef7eb2e8f9f7 5259 }
<> 144:ef7eb2e8f9f7 5260
<> 144:ef7eb2e8f9f7 5261 /**
<> 144:ef7eb2e8f9f7 5262 * @brief Selects the Input Trigger source
<> 144:ef7eb2e8f9f7 5263 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5264 * @param InputTriggerSource: The Input Trigger source.
<> 144:ef7eb2e8f9f7 5265 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5266 * @arg TIM_TS_ITR0: Internal Trigger 0
<> 144:ef7eb2e8f9f7 5267 * @arg TIM_TS_ITR1: Internal Trigger 1
<> 144:ef7eb2e8f9f7 5268 * @arg TIM_TS_ITR2: Internal Trigger 2
<> 144:ef7eb2e8f9f7 5269 * @arg TIM_TS_ITR3: Internal Trigger 3
<> 144:ef7eb2e8f9f7 5270 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<> 144:ef7eb2e8f9f7 5271 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<> 144:ef7eb2e8f9f7 5272 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<> 144:ef7eb2e8f9f7 5273 * @arg TIM_TS_ETRF: External Trigger input
<> 144:ef7eb2e8f9f7 5274 * @retval None
<> 144:ef7eb2e8f9f7 5275 */
<> 144:ef7eb2e8f9f7 5276 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
<> 144:ef7eb2e8f9f7 5277 {
<> 144:ef7eb2e8f9f7 5278 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 5279
<> 144:ef7eb2e8f9f7 5280 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5281 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5282 /* Reset the TS Bits */
<> 144:ef7eb2e8f9f7 5283 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5284 /* Set the Input Trigger source and the slave mode*/
<> 144:ef7eb2e8f9f7 5285 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
<> 144:ef7eb2e8f9f7 5286 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5287 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5288 }
<> 144:ef7eb2e8f9f7 5289 /**
<> 144:ef7eb2e8f9f7 5290 * @brief Configures the TIMx External Trigger (ETR).
<> 144:ef7eb2e8f9f7 5291 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5292 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<> 144:ef7eb2e8f9f7 5293 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5294 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
<> 144:ef7eb2e8f9f7 5295 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
<> 144:ef7eb2e8f9f7 5296 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
<> 144:ef7eb2e8f9f7 5297 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
<> 144:ef7eb2e8f9f7 5298 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<> 144:ef7eb2e8f9f7 5299 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5300 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
<> 144:ef7eb2e8f9f7 5301 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
<> 144:ef7eb2e8f9f7 5302 * @param ExtTRGFilter: External Trigger Filter.
<> 144:ef7eb2e8f9f7 5303 * This parameter must be a value between 0x00 and 0x0F
<> 144:ef7eb2e8f9f7 5304 * @retval None
<> 144:ef7eb2e8f9f7 5305 */
<> 144:ef7eb2e8f9f7 5306 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 5307 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<> 144:ef7eb2e8f9f7 5308 {
<> 144:ef7eb2e8f9f7 5309 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 5310
<> 144:ef7eb2e8f9f7 5311 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5312
<> 144:ef7eb2e8f9f7 5313 /* Reset the ETR Bits */
<> 144:ef7eb2e8f9f7 5314 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 5315
<> 144:ef7eb2e8f9f7 5316 /* Set the Prescaler, the Filter value and the Polarity */
<> 144:ef7eb2e8f9f7 5317 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
<> 144:ef7eb2e8f9f7 5318
<> 144:ef7eb2e8f9f7 5319 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5320 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5321 }
<> 144:ef7eb2e8f9f7 5322
<> 144:ef7eb2e8f9f7 5323 /**
<> 144:ef7eb2e8f9f7 5324 * @brief Enables or disables the TIM Capture Compare Channel x.
<> 144:ef7eb2e8f9f7 5325 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5326 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 5327 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5328 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 5329 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 5330 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 5331 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 5332 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
<> 144:ef7eb2e8f9f7 5333 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<> 144:ef7eb2e8f9f7 5334 * @retval None
<> 144:ef7eb2e8f9f7 5335 */
<> 144:ef7eb2e8f9f7 5336 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<> 144:ef7eb2e8f9f7 5337 {
<> 144:ef7eb2e8f9f7 5338 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 5339
<> 144:ef7eb2e8f9f7 5340 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5341 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 5342 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 5343
<> 144:ef7eb2e8f9f7 5344 tmp = TIM_CCER_CC1E << Channel;
<> 144:ef7eb2e8f9f7 5345
<> 144:ef7eb2e8f9f7 5346 /* Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5347 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 5348
<> 144:ef7eb2e8f9f7 5349 /* Set or reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5350 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
<> 144:ef7eb2e8f9f7 5351 }
<> 144:ef7eb2e8f9f7 5352
<> 144:ef7eb2e8f9f7 5353
<> 144:ef7eb2e8f9f7 5354 /**
<> 144:ef7eb2e8f9f7 5355 * @}
<> 144:ef7eb2e8f9f7 5356 */
<> 144:ef7eb2e8f9f7 5357
<> 144:ef7eb2e8f9f7 5358 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 5359 /**
<> 144:ef7eb2e8f9f7 5360 * @}
<> 144:ef7eb2e8f9f7 5361 */
<> 144:ef7eb2e8f9f7 5362
<> 144:ef7eb2e8f9f7 5363 /**
<> 144:ef7eb2e8f9f7 5364 * @}
<> 144:ef7eb2e8f9f7 5365 */
<> 144:ef7eb2e8f9f7 5366 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/