pravin sarode / Mymbed-dev

MBED-DEV only fro Nucleo STM32F303K8T6

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sram.h@151:acf04f8e7d03, 2016-11-19 (annotated)

Committer:
pravinautosys
Date:
Sat Nov 19 10:38:54 2016 +0000
Revision:
151:acf04f8e7d03
Parent:
149:156823d33999 
MyMBED-DEVWithSTM32F303K8T6;

Who changed what in which revision?

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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_sram.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SRAM HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F3xx_HAL_SRAM_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F3xx_HAL_SRAM_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
<> 144:ef7eb2e8f9f7 48 #include "stm32f3xx_ll_fmc.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup SRAM
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported typedef ----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /** @defgroup SRAM_Exported_Types SRAM Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL SRAM State structures definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 69 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
<> 144:ef7eb2e8f9f7 70 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
<> 144:ef7eb2e8f9f7 71 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
<> 144:ef7eb2e8f9f7 72 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 }HAL_SRAM_StateTypeDef;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief SRAM handle Structure definition
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef struct
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 HAL_LockTypeDef Lock; /*!< SRAM locking object */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 }SRAM_HandleTypeDef;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @brief Reset SRAM handle state
<> 144:ef7eb2e8f9f7 107 * @param __HANDLE__: SRAM handle
<> 144:ef7eb2e8f9f7 108 * @retval None
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /**
<> 144:ef7eb2e8f9f7 113 * @}
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
<> 144:ef7eb2e8f9f7 118 * @{
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 126 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
<> 144:ef7eb2e8f9f7 127 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
<> 144:ef7eb2e8f9f7 128 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
<> 144:ef7eb2e8f9f7 129 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 132 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 143 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 144 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 145 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 146 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 147 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 148 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 149 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 150 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @}
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* SRAM Control functions ****************************************************/
<> 144:ef7eb2e8f9f7 161 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
<> 144:ef7eb2e8f9f7 162 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @}
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 169 * @{
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* SRAM Peripheral State functions ********************************************/
<> 144:ef7eb2e8f9f7 173 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @}
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195 #endif
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #endif /* __STM32F3xx_HAL_SRAM_H */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/