MBED-DEV only fro Nucleo STM32F303K8T6
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi.c@151:acf04f8e7d03, 2016-11-19 (annotated)
- Committer:
- pravinautosys
- Date:
- Sat Nov 19 10:38:54 2016 +0000
- Revision:
- 151:acf04f8e7d03
- Parent:
- 149:156823d33999
MyMBED-DEVWithSTM32F303K8T6;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f3xx_hal_spi.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.3.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 01-July-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief SPI HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the Serial Peripheral Interface (SPI) peripheral: |
<> | 144:ef7eb2e8f9f7 | 10 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 12 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 13 | * + Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 16 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 18 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 19 | [..] |
<> | 144:ef7eb2e8f9f7 | 20 | The SPI HAL driver can be used as follows: |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | (#) Declare a SPI_HandleTypeDef handle structure, for example: |
<> | 144:ef7eb2e8f9f7 | 23 | SPI_HandleTypeDef hspi; |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: |
<> | 144:ef7eb2e8f9f7 | 26 | (##) Enable the SPIx interface clock |
<> | 144:ef7eb2e8f9f7 | 27 | (##) SPI pins configuration |
<> | 144:ef7eb2e8f9f7 | 28 | (+++) Enable the clock for the SPI GPIOs |
<> | 144:ef7eb2e8f9f7 | 29 | (+++) Configure these SPI pins as alternate function push-pull |
<> | 144:ef7eb2e8f9f7 | 30 | (##) NVIC configuration if you need to use interrupt process |
<> | 144:ef7eb2e8f9f7 | 31 | (+++) Configure the SPIx interrupt priority |
<> | 144:ef7eb2e8f9f7 | 32 | (+++) Enable the NVIC SPI IRQ handle |
<> | 144:ef7eb2e8f9f7 | 33 | (##) DMA Configuration if you need to use DMA process |
<> | 144:ef7eb2e8f9f7 | 34 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
<> | 144:ef7eb2e8f9f7 | 35 | (+++) Enable the DMAx clock |
<> | 144:ef7eb2e8f9f7 | 36 | (+++) Configure the DMA handle parameters |
<> | 144:ef7eb2e8f9f7 | 37 | (+++) Configure the DMA Tx or Rx channel |
<> | 144:ef7eb2e8f9f7 | 38 | (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle |
<> | 144:ef7eb2e8f9f7 | 39 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS |
<> | 144:ef7eb2e8f9f7 | 42 | management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: |
<> | 144:ef7eb2e8f9f7 | 45 | (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
<> | 144:ef7eb2e8f9f7 | 46 | by calling the customized HAL_SPI_MspInit() API. |
<> | 144:ef7eb2e8f9f7 | 47 | [..] |
<> | 144:ef7eb2e8f9f7 | 48 | Circular mode restriction: |
<> | 144:ef7eb2e8f9f7 | 49 | (#) The DMA circular mode cannot be used when the SPI is configured in these modes: |
<> | 144:ef7eb2e8f9f7 | 50 | (##) Master 2Lines RxOnly |
<> | 144:ef7eb2e8f9f7 | 51 | (##) Master 1Line Rx |
<> | 144:ef7eb2e8f9f7 | 52 | (#) The CRC feature is not managed when the DMA circular mode is enabled |
<> | 144:ef7eb2e8f9f7 | 53 | (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs |
<> | 144:ef7eb2e8f9f7 | 54 | the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | @note |
<> | 144:ef7eb2e8f9f7 | 57 | (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() |
<> | 144:ef7eb2e8f9f7 | 58 | (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 59 | (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 62 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 63 | * @attention |
<> | 144:ef7eb2e8f9f7 | 64 | * |
<> | 144:ef7eb2e8f9f7 | 65 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 66 | * |
<> | 144:ef7eb2e8f9f7 | 67 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 68 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 69 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 70 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 71 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 72 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 73 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 74 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 75 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 76 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 77 | * |
<> | 144:ef7eb2e8f9f7 | 78 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 79 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 80 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 81 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 82 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 83 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 84 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 85 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 86 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 87 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 88 | * |
<> | 144:ef7eb2e8f9f7 | 89 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 90 | */ |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | /* |
<> | 144:ef7eb2e8f9f7 | 93 | Additional Table: |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | Using the HAL it is not possible to reach all supported SPI frequency with the differents |
<> | 144:ef7eb2e8f9f7 | 96 | the following table resume the max SPI frequency reached with data size 8bits/16bits, |
<> | 144:ef7eb2e8f9f7 | 97 | according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : |
<> | 144:ef7eb2e8f9f7 | 98 | +-----------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 99 | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | |
<> | 144:ef7eb2e8f9f7 | 100 | | Process | Tranfert mode |--------------------|--------------------|--------------------| |
<> | 144:ef7eb2e8f9f7 | 101 | | | | Master | Slave | Master | Slave | Master | Slave | |
<> | 144:ef7eb2e8f9f7 | 102 | |=========================================================================================| |
<> | 144:ef7eb2e8f9f7 | 103 | | T | Polling | Fcpu/4 | Fcpu/8 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 104 | | X |----------------|----------|---------|----------|---------|----------|---------| |
<> | 144:ef7eb2e8f9f7 | 105 | | / | Interrupt | Fcpu/4 | Fcpu/16 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 106 | | R |----------------|----------|---------|----------|---------|----------|---------| |
<> | 144:ef7eb2e8f9f7 | 107 | | X | DMA | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA | |
<> | 144:ef7eb2e8f9f7 | 108 | |=========|================|==========|=========|==========|=========|==========|=========| |
<> | 144:ef7eb2e8f9f7 | 109 | | | Polling | Fcpu/4 | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | |
<> | 144:ef7eb2e8f9f7 | 110 | | |----------------|----------|---------|----------|---------|----------|---------| |
<> | 144:ef7eb2e8f9f7 | 111 | | R | Interrupt | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | Fcpu/4 | |
<> | 144:ef7eb2e8f9f7 | 112 | | X |----------------|----------|---------|----------|---------|----------|---------| |
<> | 144:ef7eb2e8f9f7 | 113 | | | DMA | Fcpu/4 | Fcpu/2 | Fcpu/2 | Fcpu/16 | Fcpu/2 | Fcpu/16 | |
<> | 144:ef7eb2e8f9f7 | 114 | |=========|================|==========|=========|==========|=========|==========|=========| |
<> | 144:ef7eb2e8f9f7 | 115 | | | Polling | Fcpu/8 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/8 | |
<> | 144:ef7eb2e8f9f7 | 116 | | |----------------|----------|---------|----------|---------|----------|---------| |
<> | 144:ef7eb2e8f9f7 | 117 | | T | Interrupt | Fcpu/2 | Fcpu/4 | NA | NA | Fcpu/16 | Fcpu/8 | |
<> | 144:ef7eb2e8f9f7 | 118 | | X |----------------|----------|---------|----------|---------|----------|---------| |
<> | 144:ef7eb2e8f9f7 | 119 | | | DMA | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/16 | |
<> | 144:ef7eb2e8f9f7 | 120 | +-----------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 121 | @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16 |
<> | 144:ef7eb2e8f9f7 | 122 | SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | */ |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 127 | #include "stm32f3xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 128 | |
<> | 144:ef7eb2e8f9f7 | 129 | /** @addtogroup STM32F3xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 130 | * @{ |
<> | 144:ef7eb2e8f9f7 | 131 | */ |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | /** @defgroup SPI SPI |
<> | 144:ef7eb2e8f9f7 | 134 | * @brief SPI HAL module driver |
<> | 144:ef7eb2e8f9f7 | 135 | * @{ |
<> | 144:ef7eb2e8f9f7 | 136 | */ |
<> | 144:ef7eb2e8f9f7 | 137 | #ifdef HAL_SPI_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 140 | /* Private defines -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 141 | /** @defgroup SPI_Private_Constants SPI Private Constants |
<> | 144:ef7eb2e8f9f7 | 142 | * @{ |
<> | 144:ef7eb2e8f9f7 | 143 | */ |
<> | 144:ef7eb2e8f9f7 | 144 | #define SPI_DEFAULT_TIMEOUT 50 |
<> | 144:ef7eb2e8f9f7 | 145 | /** |
<> | 144:ef7eb2e8f9f7 | 146 | * @} |
<> | 144:ef7eb2e8f9f7 | 147 | */ |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | /* Private macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 150 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 151 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 152 | /** @defgroup SPI_Private_Functions SPI Private Functions |
<> | 144:ef7eb2e8f9f7 | 153 | * @{ |
<> | 144:ef7eb2e8f9f7 | 154 | */ |
<> | 144:ef7eb2e8f9f7 | 155 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 156 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 157 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 158 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 159 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 160 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 161 | static void SPI_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 162 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 163 | static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 164 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 165 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 166 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 167 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 168 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 169 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 170 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 171 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 172 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 173 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 174 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 175 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 176 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 177 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 178 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); |
<> | 144:ef7eb2e8f9f7 | 179 | static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 180 | static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 181 | /** |
<> | 144:ef7eb2e8f9f7 | 182 | * @} |
<> | 144:ef7eb2e8f9f7 | 183 | */ |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | /** @defgroup SPI_Exported_Functions SPI Exported Functions |
<> | 144:ef7eb2e8f9f7 | 188 | * @{ |
<> | 144:ef7eb2e8f9f7 | 189 | */ |
<> | 144:ef7eb2e8f9f7 | 190 | |
<> | 144:ef7eb2e8f9f7 | 191 | /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 192 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 193 | * |
<> | 144:ef7eb2e8f9f7 | 194 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 195 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 196 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 197 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 198 | [..] This subsection provides a set of functions allowing to initialize and |
<> | 144:ef7eb2e8f9f7 | 199 | de-initialize the SPIx peripheral: |
<> | 144:ef7eb2e8f9f7 | 200 | |
<> | 144:ef7eb2e8f9f7 | 201 | (+) User must implement HAL_SPI_MspInit() function in which he configures |
<> | 144:ef7eb2e8f9f7 | 202 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
<> | 144:ef7eb2e8f9f7 | 203 | |
<> | 144:ef7eb2e8f9f7 | 204 | (+) Call the function HAL_SPI_Init() to configure the selected device with |
<> | 144:ef7eb2e8f9f7 | 205 | the selected configuration: |
<> | 144:ef7eb2e8f9f7 | 206 | (++) Mode |
<> | 144:ef7eb2e8f9f7 | 207 | (++) Direction |
<> | 144:ef7eb2e8f9f7 | 208 | (++) Data Size |
<> | 144:ef7eb2e8f9f7 | 209 | (++) Clock Polarity and Phase |
<> | 144:ef7eb2e8f9f7 | 210 | (++) NSS Management |
<> | 144:ef7eb2e8f9f7 | 211 | (++) BaudRate Prescaler |
<> | 144:ef7eb2e8f9f7 | 212 | (++) FirstBit |
<> | 144:ef7eb2e8f9f7 | 213 | (++) TIMode |
<> | 144:ef7eb2e8f9f7 | 214 | (++) CRC Calculation |
<> | 144:ef7eb2e8f9f7 | 215 | (++) CRC Polynomial if CRC enabled |
<> | 144:ef7eb2e8f9f7 | 216 | (++) CRC Length, used only with Data8 and Data16 |
<> | 144:ef7eb2e8f9f7 | 217 | (++) FIFO reception threshold |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | (+) Call the function HAL_SPI_DeInit() to restore the default configuration |
<> | 144:ef7eb2e8f9f7 | 220 | of the selected SPIx peripheral. |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 223 | * @{ |
<> | 144:ef7eb2e8f9f7 | 224 | */ |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | /** |
<> | 144:ef7eb2e8f9f7 | 227 | * @brief Initialize the SPI according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 228 | * in the SPI_InitTypeDef and initialize the associated handle. |
<> | 144:ef7eb2e8f9f7 | 229 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 230 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 231 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 232 | */ |
<> | 144:ef7eb2e8f9f7 | 233 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 234 | { |
<> | 144:ef7eb2e8f9f7 | 235 | uint32_t frxth; |
<> | 144:ef7eb2e8f9f7 | 236 | |
<> | 144:ef7eb2e8f9f7 | 237 | /* Check the SPI handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 238 | if(hspi == NULL) |
<> | 144:ef7eb2e8f9f7 | 239 | { |
<> | 144:ef7eb2e8f9f7 | 240 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 241 | } |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 244 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
<> | 144:ef7eb2e8f9f7 | 245 | assert_param(IS_SPI_MODE(hspi->Init.Mode)); |
<> | 144:ef7eb2e8f9f7 | 246 | assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 247 | assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); |
<> | 144:ef7eb2e8f9f7 | 248 | assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); |
<> | 144:ef7eb2e8f9f7 | 249 | assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); |
<> | 144:ef7eb2e8f9f7 | 250 | assert_param(IS_SPI_NSS(hspi->Init.NSS)); |
<> | 144:ef7eb2e8f9f7 | 251 | assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); |
<> | 144:ef7eb2e8f9f7 | 252 | assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); |
<> | 144:ef7eb2e8f9f7 | 253 | assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); |
<> | 144:ef7eb2e8f9f7 | 254 | assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); |
<> | 144:ef7eb2e8f9f7 | 255 | assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); |
<> | 144:ef7eb2e8f9f7 | 256 | assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); |
<> | 144:ef7eb2e8f9f7 | 257 | assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | if(hspi->State == HAL_SPI_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 260 | { |
<> | 144:ef7eb2e8f9f7 | 261 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 262 | hspi->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | /* Init the low level hardware : GPIO, CLOCK, NVIC... */ |
<> | 144:ef7eb2e8f9f7 | 265 | HAL_SPI_MspInit(hspi); |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | hspi->State = HAL_SPI_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 269 | |
<> | 144:ef7eb2e8f9f7 | 270 | /* Disable the selected SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 271 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | /* Align by default the rs fifo threshold on the data size */ |
<> | 144:ef7eb2e8f9f7 | 274 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 275 | { |
<> | 144:ef7eb2e8f9f7 | 276 | frxth = SPI_RXFIFO_THRESHOLD_HF; |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | else |
<> | 144:ef7eb2e8f9f7 | 279 | { |
<> | 144:ef7eb2e8f9f7 | 280 | frxth = SPI_RXFIFO_THRESHOLD_QF; |
<> | 144:ef7eb2e8f9f7 | 281 | } |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | /* CRC calculation is valid only for 16Bit and 8 Bit */ |
<> | 144:ef7eb2e8f9f7 | 284 | if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) |
<> | 144:ef7eb2e8f9f7 | 285 | { |
<> | 144:ef7eb2e8f9f7 | 286 | /* CRC must be disabled */ |
<> | 144:ef7eb2e8f9f7 | 287 | hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
<> | 144:ef7eb2e8f9f7 | 288 | } |
<> | 144:ef7eb2e8f9f7 | 289 | |
<> | 144:ef7eb2e8f9f7 | 290 | /* Align the CRC Length on the data size */ |
<> | 144:ef7eb2e8f9f7 | 291 | if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) |
<> | 144:ef7eb2e8f9f7 | 292 | { |
<> | 144:ef7eb2e8f9f7 | 293 | /* CRC Length aligned on the data size : value set by default */ |
<> | 144:ef7eb2e8f9f7 | 294 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 295 | { |
<> | 144:ef7eb2e8f9f7 | 296 | hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | else |
<> | 144:ef7eb2e8f9f7 | 299 | { |
<> | 144:ef7eb2e8f9f7 | 300 | hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; |
<> | 144:ef7eb2e8f9f7 | 301 | } |
<> | 144:ef7eb2e8f9f7 | 302 | } |
<> | 144:ef7eb2e8f9f7 | 303 | |
<> | 144:ef7eb2e8f9f7 | 304 | /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 305 | /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, |
<> | 144:ef7eb2e8f9f7 | 306 | Communication speed, First bit, CRC calculation state, CRC Length */ |
<> | 144:ef7eb2e8f9f7 | 307 | hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | |
<> | 144:ef7eb2e8f9f7 | 308 | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | |
<> | 144:ef7eb2e8f9f7 | 309 | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) |
<> | 144:ef7eb2e8f9f7 | 312 | { |
<> | 144:ef7eb2e8f9f7 | 313 | hspi->Instance->CR1|= SPI_CR1_CRCL; |
<> | 144:ef7eb2e8f9f7 | 314 | } |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | /* Configure : NSS management */ |
<> | 144:ef7eb2e8f9f7 | 317 | /* Configure : Rx Fifo Threshold */ |
<> | 144:ef7eb2e8f9f7 | 318 | hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | |
<> | 144:ef7eb2e8f9f7 | 319 | hspi->Init.DataSize ) | frxth; |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ |
<> | 144:ef7eb2e8f9f7 | 322 | /* Configure : CRC Polynomial */ |
<> | 144:ef7eb2e8f9f7 | 323 | hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; |
<> | 144:ef7eb2e8f9f7 | 324 | |
<> | 144:ef7eb2e8f9f7 | 325 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 326 | hspi->State= HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 327 | |
<> | 144:ef7eb2e8f9f7 | 328 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 329 | } |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | /** |
<> | 144:ef7eb2e8f9f7 | 332 | * @brief DeInitialize the SPI peripheral. |
<> | 144:ef7eb2e8f9f7 | 333 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 334 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 335 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 336 | */ |
<> | 144:ef7eb2e8f9f7 | 337 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 338 | { |
<> | 144:ef7eb2e8f9f7 | 339 | /* Check the SPI handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 340 | if(hspi == NULL) |
<> | 144:ef7eb2e8f9f7 | 341 | { |
<> | 144:ef7eb2e8f9f7 | 342 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 343 | } |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 346 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
<> | 144:ef7eb2e8f9f7 | 347 | hspi->State = HAL_SPI_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /* Disable the SPI Peripheral Clock */ |
<> | 144:ef7eb2e8f9f7 | 350 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 351 | |
<> | 144:ef7eb2e8f9f7 | 352 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
<> | 144:ef7eb2e8f9f7 | 353 | HAL_SPI_MspDeInit(hspi); |
<> | 144:ef7eb2e8f9f7 | 354 | |
<> | 144:ef7eb2e8f9f7 | 355 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 356 | hspi->State = HAL_SPI_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 357 | |
<> | 144:ef7eb2e8f9f7 | 358 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 359 | |
<> | 144:ef7eb2e8f9f7 | 360 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 361 | } |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | /** |
<> | 144:ef7eb2e8f9f7 | 364 | * @brief Initialize the SPI MSP. |
<> | 144:ef7eb2e8f9f7 | 365 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 366 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 367 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 368 | */ |
<> | 144:ef7eb2e8f9f7 | 369 | __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 370 | { |
<> | 144:ef7eb2e8f9f7 | 371 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 372 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 373 | |
<> | 144:ef7eb2e8f9f7 | 374 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 375 | the HAL_SPI_MspInit should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 376 | */ |
<> | 144:ef7eb2e8f9f7 | 377 | } |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | /** |
<> | 144:ef7eb2e8f9f7 | 380 | * @brief DeInitialize the SPI MSP. |
<> | 144:ef7eb2e8f9f7 | 381 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 382 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 383 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 384 | */ |
<> | 144:ef7eb2e8f9f7 | 385 | __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 386 | { |
<> | 144:ef7eb2e8f9f7 | 387 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 388 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 391 | the HAL_SPI_MspDeInit should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 392 | */ |
<> | 144:ef7eb2e8f9f7 | 393 | } |
<> | 144:ef7eb2e8f9f7 | 394 | |
<> | 144:ef7eb2e8f9f7 | 395 | /** |
<> | 144:ef7eb2e8f9f7 | 396 | * @} |
<> | 144:ef7eb2e8f9f7 | 397 | */ |
<> | 144:ef7eb2e8f9f7 | 398 | |
<> | 144:ef7eb2e8f9f7 | 399 | /** @defgroup SPI_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 400 | * @brief Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 401 | * |
<> | 144:ef7eb2e8f9f7 | 402 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 403 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 404 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 405 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 406 | [..] |
<> | 144:ef7eb2e8f9f7 | 407 | This subsection provides a set of functions allowing to manage the SPI |
<> | 144:ef7eb2e8f9f7 | 408 | data transfers. |
<> | 144:ef7eb2e8f9f7 | 409 | |
<> | 144:ef7eb2e8f9f7 | 410 | [..] The SPI supports master and slave mode : |
<> | 144:ef7eb2e8f9f7 | 411 | |
<> | 144:ef7eb2e8f9f7 | 412 | (#) There are two modes of transfer: |
<> | 144:ef7eb2e8f9f7 | 413 | (++) Blocking mode: The communication is performed in polling mode. |
<> | 144:ef7eb2e8f9f7 | 414 | The HAL status of all data processing is returned by the same function |
<> | 144:ef7eb2e8f9f7 | 415 | after finishing transfer. |
<> | 144:ef7eb2e8f9f7 | 416 | (++) No-Blocking mode: The communication is performed using Interrupts |
<> | 144:ef7eb2e8f9f7 | 417 | or DMA, These APIs return the HAL status. |
<> | 144:ef7eb2e8f9f7 | 418 | The end of the data processing will be indicated through the |
<> | 144:ef7eb2e8f9f7 | 419 | dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when |
<> | 144:ef7eb2e8f9f7 | 420 | using DMA mode. |
<> | 144:ef7eb2e8f9f7 | 421 | The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks |
<> | 144:ef7eb2e8f9f7 | 422 | will be executed respectively at the end of the transmit or Receive process |
<> | 144:ef7eb2e8f9f7 | 423 | The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected |
<> | 144:ef7eb2e8f9f7 | 424 | |
<> | 144:ef7eb2e8f9f7 | 425 | (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) |
<> | 144:ef7eb2e8f9f7 | 426 | exist for 1Line (simplex) and 2Lines (full duplex) modes. |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 429 | * @{ |
<> | 144:ef7eb2e8f9f7 | 430 | */ |
<> | 144:ef7eb2e8f9f7 | 431 | |
<> | 144:ef7eb2e8f9f7 | 432 | /** |
<> | 144:ef7eb2e8f9f7 | 433 | * @brief Transmit an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 434 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 435 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 436 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 437 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 438 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 439 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 440 | */ |
<> | 144:ef7eb2e8f9f7 | 441 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 442 | { |
<> | 144:ef7eb2e8f9f7 | 443 | uint32_t tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 444 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 445 | |
<> | 144:ef7eb2e8f9f7 | 446 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 447 | |
<> | 144:ef7eb2e8f9f7 | 448 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 449 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 450 | |
<> | 144:ef7eb2e8f9f7 | 451 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 452 | { |
<> | 144:ef7eb2e8f9f7 | 453 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 454 | goto error; |
<> | 144:ef7eb2e8f9f7 | 455 | } |
<> | 144:ef7eb2e8f9f7 | 456 | |
<> | 144:ef7eb2e8f9f7 | 457 | if((pData == NULL ) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 458 | { |
<> | 144:ef7eb2e8f9f7 | 459 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 460 | goto error; |
<> | 144:ef7eb2e8f9f7 | 461 | } |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | /* Set the transaction information */ |
<> | 144:ef7eb2e8f9f7 | 464 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 465 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 466 | hspi->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 467 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 468 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 469 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 470 | hspi->RxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 471 | hspi->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 472 | |
<> | 144:ef7eb2e8f9f7 | 473 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 474 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 475 | { |
<> | 144:ef7eb2e8f9f7 | 476 | SPI_1LINE_TX(hspi); |
<> | 144:ef7eb2e8f9f7 | 477 | } |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 480 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 481 | { |
<> | 144:ef7eb2e8f9f7 | 482 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 483 | } |
<> | 144:ef7eb2e8f9f7 | 484 | |
<> | 144:ef7eb2e8f9f7 | 485 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 486 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 487 | { |
<> | 144:ef7eb2e8f9f7 | 488 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 489 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 490 | } |
<> | 144:ef7eb2e8f9f7 | 491 | |
<> | 144:ef7eb2e8f9f7 | 492 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 493 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 494 | { |
<> | 144:ef7eb2e8f9f7 | 495 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 496 | while (hspi->TxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 497 | { |
<> | 144:ef7eb2e8f9f7 | 498 | /* Wait until TXE flag is set to send data */ |
<> | 144:ef7eb2e8f9f7 | 499 | if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) |
<> | 144:ef7eb2e8f9f7 | 500 | { |
<> | 144:ef7eb2e8f9f7 | 501 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 502 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 503 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 504 | } |
<> | 144:ef7eb2e8f9f7 | 505 | else |
<> | 144:ef7eb2e8f9f7 | 506 | { |
<> | 144:ef7eb2e8f9f7 | 507 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 508 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 509 | { |
<> | 144:ef7eb2e8f9f7 | 510 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 511 | goto error; |
<> | 144:ef7eb2e8f9f7 | 512 | } |
<> | 144:ef7eb2e8f9f7 | 513 | } |
<> | 144:ef7eb2e8f9f7 | 514 | } |
<> | 144:ef7eb2e8f9f7 | 515 | } |
<> | 144:ef7eb2e8f9f7 | 516 | /* Transmit data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 517 | else |
<> | 144:ef7eb2e8f9f7 | 518 | { |
<> | 144:ef7eb2e8f9f7 | 519 | while (hspi->TxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 520 | { |
<> | 144:ef7eb2e8f9f7 | 521 | /* Wait until TXE flag is set to send data */ |
<> | 144:ef7eb2e8f9f7 | 522 | if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) |
<> | 144:ef7eb2e8f9f7 | 523 | { |
<> | 144:ef7eb2e8f9f7 | 524 | if(hspi->TxXferCount > 1) |
<> | 144:ef7eb2e8f9f7 | 525 | { |
<> | 144:ef7eb2e8f9f7 | 526 | /* write on the data register in packing mode */ |
<> | 144:ef7eb2e8f9f7 | 527 | hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 528 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 529 | hspi->TxXferCount -= 2; |
<> | 144:ef7eb2e8f9f7 | 530 | } |
<> | 144:ef7eb2e8f9f7 | 531 | else |
<> | 144:ef7eb2e8f9f7 | 532 | { |
<> | 144:ef7eb2e8f9f7 | 533 | *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 534 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 535 | } |
<> | 144:ef7eb2e8f9f7 | 536 | } |
<> | 144:ef7eb2e8f9f7 | 537 | else |
<> | 144:ef7eb2e8f9f7 | 538 | { |
<> | 144:ef7eb2e8f9f7 | 539 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 540 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 541 | { |
<> | 144:ef7eb2e8f9f7 | 542 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 543 | goto error; |
<> | 144:ef7eb2e8f9f7 | 544 | } |
<> | 144:ef7eb2e8f9f7 | 545 | } |
<> | 144:ef7eb2e8f9f7 | 546 | } |
<> | 144:ef7eb2e8f9f7 | 547 | } |
<> | 144:ef7eb2e8f9f7 | 548 | |
<> | 144:ef7eb2e8f9f7 | 549 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 550 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 551 | { |
<> | 144:ef7eb2e8f9f7 | 552 | hspi->Instance->CR1|= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 553 | } |
<> | 144:ef7eb2e8f9f7 | 554 | |
<> | 144:ef7eb2e8f9f7 | 555 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 556 | if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 557 | { |
<> | 144:ef7eb2e8f9f7 | 558 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 559 | } |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 562 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 563 | { |
<> | 144:ef7eb2e8f9f7 | 564 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 565 | } |
<> | 144:ef7eb2e8f9f7 | 566 | |
<> | 144:ef7eb2e8f9f7 | 567 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 568 | { |
<> | 144:ef7eb2e8f9f7 | 569 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | error: |
<> | 144:ef7eb2e8f9f7 | 573 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 574 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 575 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 576 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 577 | } |
<> | 144:ef7eb2e8f9f7 | 578 | |
<> | 144:ef7eb2e8f9f7 | 579 | /** |
<> | 144:ef7eb2e8f9f7 | 580 | * @brief Receive an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 581 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 582 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 583 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 584 | * @param Size: amount of data to be received |
<> | 144:ef7eb2e8f9f7 | 585 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 586 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 587 | */ |
<> | 144:ef7eb2e8f9f7 | 588 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 589 | { |
<> | 144:ef7eb2e8f9f7 | 590 | __IO uint16_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 591 | uint32_t tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 592 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
<> | 144:ef7eb2e8f9f7 | 595 | { |
<> | 144:ef7eb2e8f9f7 | 596 | /* the receive process is not supported in 2Lines direction master mode */ |
<> | 144:ef7eb2e8f9f7 | 597 | /* in this case we call the TransmitReceive process */ |
<> | 144:ef7eb2e8f9f7 | 598 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 599 | return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); |
<> | 144:ef7eb2e8f9f7 | 600 | } |
<> | 144:ef7eb2e8f9f7 | 601 | |
<> | 144:ef7eb2e8f9f7 | 602 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 603 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 604 | |
<> | 144:ef7eb2e8f9f7 | 605 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 606 | { |
<> | 144:ef7eb2e8f9f7 | 607 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 608 | goto error; |
<> | 144:ef7eb2e8f9f7 | 609 | } |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | if((pData == NULL ) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 612 | { |
<> | 144:ef7eb2e8f9f7 | 613 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 614 | goto error; |
<> | 144:ef7eb2e8f9f7 | 615 | } |
<> | 144:ef7eb2e8f9f7 | 616 | |
<> | 144:ef7eb2e8f9f7 | 617 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 618 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 619 | hspi->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 620 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 621 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 622 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 623 | hspi->TxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 624 | hspi->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 625 | |
<> | 144:ef7eb2e8f9f7 | 626 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 627 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 628 | { |
<> | 144:ef7eb2e8f9f7 | 629 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 630 | /* this is done to handle the CRCNEXT before the latest data */ |
<> | 144:ef7eb2e8f9f7 | 631 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 632 | } |
<> | 144:ef7eb2e8f9f7 | 633 | |
<> | 144:ef7eb2e8f9f7 | 634 | /* Set the Rx Fido threshold */ |
<> | 144:ef7eb2e8f9f7 | 635 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 636 | { |
<> | 144:ef7eb2e8f9f7 | 637 | /* set fiforxthresold according the reception data length: 16bit */ |
<> | 144:ef7eb2e8f9f7 | 638 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 639 | } |
<> | 144:ef7eb2e8f9f7 | 640 | else |
<> | 144:ef7eb2e8f9f7 | 641 | { |
<> | 144:ef7eb2e8f9f7 | 642 | /* set fiforxthresold according the reception data length: 8bit */ |
<> | 144:ef7eb2e8f9f7 | 643 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 644 | } |
<> | 144:ef7eb2e8f9f7 | 645 | |
<> | 144:ef7eb2e8f9f7 | 646 | /* Configure communication direction 1Line and enabled SPI if needed */ |
<> | 144:ef7eb2e8f9f7 | 647 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 648 | { |
<> | 144:ef7eb2e8f9f7 | 649 | SPI_1LINE_RX(hspi); |
<> | 144:ef7eb2e8f9f7 | 650 | } |
<> | 144:ef7eb2e8f9f7 | 651 | |
<> | 144:ef7eb2e8f9f7 | 652 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 653 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 654 | { |
<> | 144:ef7eb2e8f9f7 | 655 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 656 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 657 | } |
<> | 144:ef7eb2e8f9f7 | 658 | |
<> | 144:ef7eb2e8f9f7 | 659 | if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 660 | { |
<> | 144:ef7eb2e8f9f7 | 661 | /* Transfer loop */ |
<> | 144:ef7eb2e8f9f7 | 662 | while(hspi->RxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 663 | { |
<> | 144:ef7eb2e8f9f7 | 664 | /* Check the RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 665 | if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) |
<> | 144:ef7eb2e8f9f7 | 666 | { |
<> | 144:ef7eb2e8f9f7 | 667 | /* read the received data */ |
<> | 144:ef7eb2e8f9f7 | 668 | (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 669 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 670 | } |
<> | 144:ef7eb2e8f9f7 | 671 | else |
<> | 144:ef7eb2e8f9f7 | 672 | { |
<> | 144:ef7eb2e8f9f7 | 673 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 674 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 675 | { |
<> | 144:ef7eb2e8f9f7 | 676 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 677 | goto error; |
<> | 144:ef7eb2e8f9f7 | 678 | } |
<> | 144:ef7eb2e8f9f7 | 679 | } |
<> | 144:ef7eb2e8f9f7 | 680 | } |
<> | 144:ef7eb2e8f9f7 | 681 | } |
<> | 144:ef7eb2e8f9f7 | 682 | else |
<> | 144:ef7eb2e8f9f7 | 683 | { |
<> | 144:ef7eb2e8f9f7 | 684 | /* Transfer loop */ |
<> | 144:ef7eb2e8f9f7 | 685 | while(hspi->RxXferCount > 0) |
<> | 144:ef7eb2e8f9f7 | 686 | { |
<> | 144:ef7eb2e8f9f7 | 687 | /* Check the RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 688 | if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) |
<> | 144:ef7eb2e8f9f7 | 689 | { |
<> | 144:ef7eb2e8f9f7 | 690 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 691 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 692 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 693 | } |
<> | 144:ef7eb2e8f9f7 | 694 | else |
<> | 144:ef7eb2e8f9f7 | 695 | { |
<> | 144:ef7eb2e8f9f7 | 696 | /* Timeout management */ |
<> | 144:ef7eb2e8f9f7 | 697 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
<> | 144:ef7eb2e8f9f7 | 698 | { |
<> | 144:ef7eb2e8f9f7 | 699 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 700 | goto error; |
<> | 144:ef7eb2e8f9f7 | 701 | } |
<> | 144:ef7eb2e8f9f7 | 702 | } |
<> | 144:ef7eb2e8f9f7 | 703 | } |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /* Handle the CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 707 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 708 | { |
<> | 144:ef7eb2e8f9f7 | 709 | /* freeze the CRC before the latest data */ |
<> | 144:ef7eb2e8f9f7 | 710 | hspi->Instance->CR1|= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 711 | |
<> | 144:ef7eb2e8f9f7 | 712 | /* Read the latest data */ |
<> | 144:ef7eb2e8f9f7 | 713 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 714 | { |
<> | 144:ef7eb2e8f9f7 | 715 | /* the latest data has not been received */ |
<> | 144:ef7eb2e8f9f7 | 716 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 717 | goto error; |
<> | 144:ef7eb2e8f9f7 | 718 | } |
<> | 144:ef7eb2e8f9f7 | 719 | |
<> | 144:ef7eb2e8f9f7 | 720 | /* Receive last data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 721 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 722 | { |
<> | 144:ef7eb2e8f9f7 | 723 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 724 | } |
<> | 144:ef7eb2e8f9f7 | 725 | /* Receive last data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 726 | else |
<> | 144:ef7eb2e8f9f7 | 727 | { |
<> | 144:ef7eb2e8f9f7 | 728 | *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 729 | } |
<> | 144:ef7eb2e8f9f7 | 730 | |
<> | 144:ef7eb2e8f9f7 | 731 | /* Wait until TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 732 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 733 | { |
<> | 144:ef7eb2e8f9f7 | 734 | /* Flag Error*/ |
<> | 144:ef7eb2e8f9f7 | 735 | hspi->ErrorCode = HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 736 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 737 | goto error; |
<> | 144:ef7eb2e8f9f7 | 738 | } |
<> | 144:ef7eb2e8f9f7 | 739 | |
<> | 144:ef7eb2e8f9f7 | 740 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
<> | 144:ef7eb2e8f9f7 | 741 | { |
<> | 144:ef7eb2e8f9f7 | 742 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 743 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 744 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 745 | } |
<> | 144:ef7eb2e8f9f7 | 746 | else |
<> | 144:ef7eb2e8f9f7 | 747 | { |
<> | 144:ef7eb2e8f9f7 | 748 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 749 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 750 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 751 | |
<> | 144:ef7eb2e8f9f7 | 752 | if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) |
<> | 144:ef7eb2e8f9f7 | 753 | { |
<> | 144:ef7eb2e8f9f7 | 754 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 755 | { |
<> | 144:ef7eb2e8f9f7 | 756 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 757 | hspi->ErrorCode = HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 758 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 759 | goto error; |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 762 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 763 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | } |
<> | 144:ef7eb2e8f9f7 | 766 | } |
<> | 144:ef7eb2e8f9f7 | 767 | |
<> | 144:ef7eb2e8f9f7 | 768 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 769 | if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 770 | { |
<> | 144:ef7eb2e8f9f7 | 771 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 772 | } |
<> | 144:ef7eb2e8f9f7 | 773 | |
<> | 144:ef7eb2e8f9f7 | 774 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 775 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 776 | { |
<> | 144:ef7eb2e8f9f7 | 777 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 778 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 779 | } |
<> | 144:ef7eb2e8f9f7 | 780 | |
<> | 144:ef7eb2e8f9f7 | 781 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 782 | { |
<> | 144:ef7eb2e8f9f7 | 783 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 784 | } |
<> | 144:ef7eb2e8f9f7 | 785 | |
<> | 144:ef7eb2e8f9f7 | 786 | error : |
<> | 144:ef7eb2e8f9f7 | 787 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 788 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 789 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 790 | } |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | /** |
<> | 144:ef7eb2e8f9f7 | 793 | * @brief Transmit and Receive an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 794 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 795 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 796 | * @param pTxData: pointer to transmission data buffer |
<> | 144:ef7eb2e8f9f7 | 797 | * @param pRxData: pointer to reception data buffer |
<> | 144:ef7eb2e8f9f7 | 798 | * @param Size: amount of data to be sent and received |
<> | 144:ef7eb2e8f9f7 | 799 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 800 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 801 | */ |
<> | 144:ef7eb2e8f9f7 | 802 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 803 | { |
<> | 144:ef7eb2e8f9f7 | 804 | __IO uint16_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 805 | uint32_t tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 806 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 807 | |
<> | 144:ef7eb2e8f9f7 | 808 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 809 | |
<> | 144:ef7eb2e8f9f7 | 810 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 811 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 812 | |
<> | 144:ef7eb2e8f9f7 | 813 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 814 | { |
<> | 144:ef7eb2e8f9f7 | 815 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 816 | goto error; |
<> | 144:ef7eb2e8f9f7 | 817 | } |
<> | 144:ef7eb2e8f9f7 | 818 | |
<> | 144:ef7eb2e8f9f7 | 819 | if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 820 | { |
<> | 144:ef7eb2e8f9f7 | 821 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 822 | goto error; |
<> | 144:ef7eb2e8f9f7 | 823 | } |
<> | 144:ef7eb2e8f9f7 | 824 | |
<> | 144:ef7eb2e8f9f7 | 825 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
<> | 144:ef7eb2e8f9f7 | 826 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 827 | hspi->pRxBuffPtr = pRxData; |
<> | 144:ef7eb2e8f9f7 | 828 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 829 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 830 | hspi->pTxBuffPtr = pTxData; |
<> | 144:ef7eb2e8f9f7 | 831 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 832 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 833 | |
<> | 144:ef7eb2e8f9f7 | 834 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 835 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 836 | { |
<> | 144:ef7eb2e8f9f7 | 837 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 838 | } |
<> | 144:ef7eb2e8f9f7 | 839 | |
<> | 144:ef7eb2e8f9f7 | 840 | /* Set the Rx Fido threshold */ |
<> | 144:ef7eb2e8f9f7 | 841 | if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) |
<> | 144:ef7eb2e8f9f7 | 842 | { |
<> | 144:ef7eb2e8f9f7 | 843 | /* set fiforxthreshold according the reception data length: 16bit */ |
<> | 144:ef7eb2e8f9f7 | 844 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 845 | } |
<> | 144:ef7eb2e8f9f7 | 846 | else |
<> | 144:ef7eb2e8f9f7 | 847 | { |
<> | 144:ef7eb2e8f9f7 | 848 | /* set fiforxthreshold according the reception data length: 8bit */ |
<> | 144:ef7eb2e8f9f7 | 849 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 850 | } |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 853 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 854 | { |
<> | 144:ef7eb2e8f9f7 | 855 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 856 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 857 | } |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | /* Transmit and Receive data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 860 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 861 | { |
<> | 144:ef7eb2e8f9f7 | 862 | while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) |
<> | 144:ef7eb2e8f9f7 | 863 | { |
<> | 144:ef7eb2e8f9f7 | 864 | /* Check TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 865 | if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) |
<> | 144:ef7eb2e8f9f7 | 866 | { |
<> | 144:ef7eb2e8f9f7 | 867 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 868 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 869 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 870 | |
<> | 144:ef7eb2e8f9f7 | 871 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 872 | if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 873 | { |
<> | 144:ef7eb2e8f9f7 | 874 | /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ |
<> | 144:ef7eb2e8f9f7 | 875 | if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) |
<> | 144:ef7eb2e8f9f7 | 876 | { |
<> | 144:ef7eb2e8f9f7 | 877 | SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); |
<> | 144:ef7eb2e8f9f7 | 878 | } |
<> | 144:ef7eb2e8f9f7 | 879 | hspi->Instance->CR1|= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 880 | } |
<> | 144:ef7eb2e8f9f7 | 881 | } |
<> | 144:ef7eb2e8f9f7 | 882 | |
<> | 144:ef7eb2e8f9f7 | 883 | /* Check RXNE flag */ |
<> | 144:ef7eb2e8f9f7 | 884 | if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) |
<> | 144:ef7eb2e8f9f7 | 885 | { |
<> | 144:ef7eb2e8f9f7 | 886 | *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 887 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 888 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 889 | } |
<> | 144:ef7eb2e8f9f7 | 890 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 891 | { |
<> | 144:ef7eb2e8f9f7 | 892 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 893 | goto error; |
<> | 144:ef7eb2e8f9f7 | 894 | } |
<> | 144:ef7eb2e8f9f7 | 895 | } |
<> | 144:ef7eb2e8f9f7 | 896 | } |
<> | 144:ef7eb2e8f9f7 | 897 | /* Transmit and Receive data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 898 | else |
<> | 144:ef7eb2e8f9f7 | 899 | { |
<> | 144:ef7eb2e8f9f7 | 900 | while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) |
<> | 144:ef7eb2e8f9f7 | 901 | { |
<> | 144:ef7eb2e8f9f7 | 902 | /* check TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 903 | if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) |
<> | 144:ef7eb2e8f9f7 | 904 | { |
<> | 144:ef7eb2e8f9f7 | 905 | if(hspi->TxXferCount > 1) |
<> | 144:ef7eb2e8f9f7 | 906 | { |
<> | 144:ef7eb2e8f9f7 | 907 | hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 908 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 909 | hspi->TxXferCount -= 2; |
<> | 144:ef7eb2e8f9f7 | 910 | } |
<> | 144:ef7eb2e8f9f7 | 911 | else |
<> | 144:ef7eb2e8f9f7 | 912 | { |
<> | 144:ef7eb2e8f9f7 | 913 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 914 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 915 | } |
<> | 144:ef7eb2e8f9f7 | 916 | |
<> | 144:ef7eb2e8f9f7 | 917 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 918 | if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 919 | { |
<> | 144:ef7eb2e8f9f7 | 920 | /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ |
<> | 144:ef7eb2e8f9f7 | 921 | if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP)) |
<> | 144:ef7eb2e8f9f7 | 922 | { |
<> | 144:ef7eb2e8f9f7 | 923 | SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); |
<> | 144:ef7eb2e8f9f7 | 924 | } |
<> | 144:ef7eb2e8f9f7 | 925 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 926 | } |
<> | 144:ef7eb2e8f9f7 | 927 | } |
<> | 144:ef7eb2e8f9f7 | 928 | |
<> | 144:ef7eb2e8f9f7 | 929 | /* Wait until RXNE flag is reset */ |
<> | 144:ef7eb2e8f9f7 | 930 | if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) |
<> | 144:ef7eb2e8f9f7 | 931 | { |
<> | 144:ef7eb2e8f9f7 | 932 | if(hspi->RxXferCount > 1) |
<> | 144:ef7eb2e8f9f7 | 933 | { |
<> | 144:ef7eb2e8f9f7 | 934 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 935 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 936 | hspi->RxXferCount -= 2; |
<> | 144:ef7eb2e8f9f7 | 937 | if(hspi->RxXferCount <= 1) |
<> | 144:ef7eb2e8f9f7 | 938 | { |
<> | 144:ef7eb2e8f9f7 | 939 | /* set fiforxthresold before to switch on 8 bit data size */ |
<> | 144:ef7eb2e8f9f7 | 940 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 941 | } |
<> | 144:ef7eb2e8f9f7 | 942 | } |
<> | 144:ef7eb2e8f9f7 | 943 | else |
<> | 144:ef7eb2e8f9f7 | 944 | { |
<> | 144:ef7eb2e8f9f7 | 945 | (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 946 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 947 | } |
<> | 144:ef7eb2e8f9f7 | 948 | } |
<> | 144:ef7eb2e8f9f7 | 949 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 950 | { |
<> | 144:ef7eb2e8f9f7 | 951 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 952 | goto error; |
<> | 144:ef7eb2e8f9f7 | 953 | } |
<> | 144:ef7eb2e8f9f7 | 954 | } |
<> | 144:ef7eb2e8f9f7 | 955 | } |
<> | 144:ef7eb2e8f9f7 | 956 | |
<> | 144:ef7eb2e8f9f7 | 957 | /* Read CRC from DR to close CRC calculation process */ |
<> | 144:ef7eb2e8f9f7 | 958 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 959 | { |
<> | 144:ef7eb2e8f9f7 | 960 | /* Wait until TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 961 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 962 | { |
<> | 144:ef7eb2e8f9f7 | 963 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 964 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 965 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 966 | goto error; |
<> | 144:ef7eb2e8f9f7 | 967 | } |
<> | 144:ef7eb2e8f9f7 | 968 | |
<> | 144:ef7eb2e8f9f7 | 969 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
<> | 144:ef7eb2e8f9f7 | 970 | { |
<> | 144:ef7eb2e8f9f7 | 971 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 972 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 973 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 974 | } |
<> | 144:ef7eb2e8f9f7 | 975 | else |
<> | 144:ef7eb2e8f9f7 | 976 | { |
<> | 144:ef7eb2e8f9f7 | 977 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 978 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 979 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 980 | |
<> | 144:ef7eb2e8f9f7 | 981 | if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) |
<> | 144:ef7eb2e8f9f7 | 982 | { |
<> | 144:ef7eb2e8f9f7 | 983 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 984 | { |
<> | 144:ef7eb2e8f9f7 | 985 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 986 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 987 | errorcode = HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 988 | goto error; |
<> | 144:ef7eb2e8f9f7 | 989 | } |
<> | 144:ef7eb2e8f9f7 | 990 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 991 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 992 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 993 | } |
<> | 144:ef7eb2e8f9f7 | 994 | } |
<> | 144:ef7eb2e8f9f7 | 995 | } |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 998 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 999 | { |
<> | 144:ef7eb2e8f9f7 | 1000 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 1001 | /* Clear CRC Flag */ |
<> | 144:ef7eb2e8f9f7 | 1002 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1003 | |
<> | 144:ef7eb2e8f9f7 | 1004 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1005 | } |
<> | 144:ef7eb2e8f9f7 | 1006 | |
<> | 144:ef7eb2e8f9f7 | 1007 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 1008 | if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1009 | { |
<> | 144:ef7eb2e8f9f7 | 1010 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 1011 | } |
<> | 144:ef7eb2e8f9f7 | 1012 | |
<> | 144:ef7eb2e8f9f7 | 1013 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 1014 | { |
<> | 144:ef7eb2e8f9f7 | 1015 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1016 | } |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | error : |
<> | 144:ef7eb2e8f9f7 | 1019 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1020 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1021 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1022 | } |
<> | 144:ef7eb2e8f9f7 | 1023 | |
<> | 144:ef7eb2e8f9f7 | 1024 | /** |
<> | 144:ef7eb2e8f9f7 | 1025 | * @brief Transmit an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 1026 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1027 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1028 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1029 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1030 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1031 | */ |
<> | 144:ef7eb2e8f9f7 | 1032 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1033 | { |
<> | 144:ef7eb2e8f9f7 | 1034 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1035 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1036 | |
<> | 144:ef7eb2e8f9f7 | 1037 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1038 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1039 | |
<> | 144:ef7eb2e8f9f7 | 1040 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 1041 | { |
<> | 144:ef7eb2e8f9f7 | 1042 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1043 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1044 | } |
<> | 144:ef7eb2e8f9f7 | 1045 | |
<> | 144:ef7eb2e8f9f7 | 1046 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1047 | { |
<> | 144:ef7eb2e8f9f7 | 1048 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1049 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1050 | } |
<> | 144:ef7eb2e8f9f7 | 1051 | |
<> | 144:ef7eb2e8f9f7 | 1052 | /* prepare the transfer */ |
<> | 144:ef7eb2e8f9f7 | 1053 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 1054 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1055 | hspi->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1056 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1057 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1058 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1059 | hspi->RxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 1060 | hspi->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1061 | hspi->RxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1062 | |
<> | 144:ef7eb2e8f9f7 | 1063 | /* Set the function for IT treatment */ |
<> | 144:ef7eb2e8f9f7 | 1064 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
<> | 144:ef7eb2e8f9f7 | 1065 | { |
<> | 144:ef7eb2e8f9f7 | 1066 | hspi->TxISR = SPI_TxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1067 | } |
<> | 144:ef7eb2e8f9f7 | 1068 | else |
<> | 144:ef7eb2e8f9f7 | 1069 | { |
<> | 144:ef7eb2e8f9f7 | 1070 | hspi->TxISR = SPI_TxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1071 | } |
<> | 144:ef7eb2e8f9f7 | 1072 | |
<> | 144:ef7eb2e8f9f7 | 1073 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1074 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1075 | { |
<> | 144:ef7eb2e8f9f7 | 1076 | SPI_1LINE_TX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1077 | } |
<> | 144:ef7eb2e8f9f7 | 1078 | |
<> | 144:ef7eb2e8f9f7 | 1079 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1080 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1081 | { |
<> | 144:ef7eb2e8f9f7 | 1082 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1083 | } |
<> | 144:ef7eb2e8f9f7 | 1084 | |
<> | 144:ef7eb2e8f9f7 | 1085 | /* Enable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1086 | __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); |
<> | 144:ef7eb2e8f9f7 | 1087 | |
<> | 144:ef7eb2e8f9f7 | 1088 | |
<> | 144:ef7eb2e8f9f7 | 1089 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1090 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1091 | { |
<> | 144:ef7eb2e8f9f7 | 1092 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1093 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1094 | } |
<> | 144:ef7eb2e8f9f7 | 1095 | |
<> | 144:ef7eb2e8f9f7 | 1096 | error : |
<> | 144:ef7eb2e8f9f7 | 1097 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1098 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1099 | } |
<> | 144:ef7eb2e8f9f7 | 1100 | |
<> | 144:ef7eb2e8f9f7 | 1101 | /** |
<> | 144:ef7eb2e8f9f7 | 1102 | * @brief Receive an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 1103 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1104 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1105 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1106 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1107 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1108 | */ |
<> | 144:ef7eb2e8f9f7 | 1109 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1110 | { |
<> | 144:ef7eb2e8f9f7 | 1111 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1112 | |
<> | 144:ef7eb2e8f9f7 | 1113 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1114 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1115 | |
<> | 144:ef7eb2e8f9f7 | 1116 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1117 | { |
<> | 144:ef7eb2e8f9f7 | 1118 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1119 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1120 | } |
<> | 144:ef7eb2e8f9f7 | 1121 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 1122 | { |
<> | 144:ef7eb2e8f9f7 | 1123 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1124 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1125 | } |
<> | 144:ef7eb2e8f9f7 | 1126 | |
<> | 144:ef7eb2e8f9f7 | 1127 | /* Configure communication */ |
<> | 144:ef7eb2e8f9f7 | 1128 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1129 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1130 | hspi->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1131 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1132 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1133 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1134 | hspi->TxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 1135 | hspi->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1136 | |
<> | 144:ef7eb2e8f9f7 | 1137 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
<> | 144:ef7eb2e8f9f7 | 1138 | { |
<> | 144:ef7eb2e8f9f7 | 1139 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1140 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1141 | /* the receive process is not supported in 2Lines direction master mode */ |
<> | 144:ef7eb2e8f9f7 | 1142 | /* in this we call the TransmitReceive process */ |
<> | 144:ef7eb2e8f9f7 | 1143 | return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); |
<> | 144:ef7eb2e8f9f7 | 1144 | } |
<> | 144:ef7eb2e8f9f7 | 1145 | |
<> | 144:ef7eb2e8f9f7 | 1146 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1147 | { |
<> | 144:ef7eb2e8f9f7 | 1148 | hspi->CRCSize = 1; |
<> | 144:ef7eb2e8f9f7 | 1149 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) |
<> | 144:ef7eb2e8f9f7 | 1150 | { |
<> | 144:ef7eb2e8f9f7 | 1151 | hspi->CRCSize = 2; |
<> | 144:ef7eb2e8f9f7 | 1152 | } |
<> | 144:ef7eb2e8f9f7 | 1153 | } |
<> | 144:ef7eb2e8f9f7 | 1154 | else |
<> | 144:ef7eb2e8f9f7 | 1155 | { |
<> | 144:ef7eb2e8f9f7 | 1156 | hspi->CRCSize = 0; |
<> | 144:ef7eb2e8f9f7 | 1157 | } |
<> | 144:ef7eb2e8f9f7 | 1158 | |
<> | 144:ef7eb2e8f9f7 | 1159 | hspi->TxISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1160 | /* check the data size to adapt Rx threshold and the set the function for IT treatment */ |
<> | 144:ef7eb2e8f9f7 | 1161 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
<> | 144:ef7eb2e8f9f7 | 1162 | { |
<> | 144:ef7eb2e8f9f7 | 1163 | /* set fiforxthresold according the reception data length: 16 bit */ |
<> | 144:ef7eb2e8f9f7 | 1164 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1165 | hspi->RxISR = SPI_RxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1166 | } |
<> | 144:ef7eb2e8f9f7 | 1167 | else |
<> | 144:ef7eb2e8f9f7 | 1168 | { |
<> | 144:ef7eb2e8f9f7 | 1169 | /* set fiforxthresold according the reception data length: 8 bit */ |
<> | 144:ef7eb2e8f9f7 | 1170 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1171 | hspi->RxISR = SPI_RxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1172 | } |
<> | 144:ef7eb2e8f9f7 | 1173 | |
<> | 144:ef7eb2e8f9f7 | 1174 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1175 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1176 | { |
<> | 144:ef7eb2e8f9f7 | 1177 | SPI_1LINE_RX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1178 | } |
<> | 144:ef7eb2e8f9f7 | 1179 | |
<> | 144:ef7eb2e8f9f7 | 1180 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1181 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1182 | { |
<> | 144:ef7eb2e8f9f7 | 1183 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1184 | } |
<> | 144:ef7eb2e8f9f7 | 1185 | |
<> | 144:ef7eb2e8f9f7 | 1186 | /* Enable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1187 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1188 | |
<> | 144:ef7eb2e8f9f7 | 1189 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1190 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1191 | { |
<> | 144:ef7eb2e8f9f7 | 1192 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1193 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1194 | } |
<> | 144:ef7eb2e8f9f7 | 1195 | |
<> | 144:ef7eb2e8f9f7 | 1196 | error : |
<> | 144:ef7eb2e8f9f7 | 1197 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1198 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1199 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1200 | } |
<> | 144:ef7eb2e8f9f7 | 1201 | |
<> | 144:ef7eb2e8f9f7 | 1202 | /** |
<> | 144:ef7eb2e8f9f7 | 1203 | * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 1204 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1205 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1206 | * @param pTxData: pointer to transmission data buffer |
<> | 144:ef7eb2e8f9f7 | 1207 | * @param pRxData: pointer to reception data buffer |
<> | 144:ef7eb2e8f9f7 | 1208 | * @param Size: amount of data to be sent and received |
<> | 144:ef7eb2e8f9f7 | 1209 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1210 | */ |
<> | 144:ef7eb2e8f9f7 | 1211 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1212 | { |
<> | 144:ef7eb2e8f9f7 | 1213 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1214 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1215 | |
<> | 144:ef7eb2e8f9f7 | 1216 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1217 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1218 | |
<> | 144:ef7eb2e8f9f7 | 1219 | if(!((hspi->State == HAL_SPI_STATE_READY) || \ |
<> | 144:ef7eb2e8f9f7 | 1220 | ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) |
<> | 144:ef7eb2e8f9f7 | 1221 | { |
<> | 144:ef7eb2e8f9f7 | 1222 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1223 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1224 | } |
<> | 144:ef7eb2e8f9f7 | 1225 | |
<> | 144:ef7eb2e8f9f7 | 1226 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 1227 | { |
<> | 144:ef7eb2e8f9f7 | 1228 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1229 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1230 | } |
<> | 144:ef7eb2e8f9f7 | 1231 | |
<> | 144:ef7eb2e8f9f7 | 1232 | hspi->CRCSize = 0; |
<> | 144:ef7eb2e8f9f7 | 1233 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1234 | { |
<> | 144:ef7eb2e8f9f7 | 1235 | hspi->CRCSize = 1; |
<> | 144:ef7eb2e8f9f7 | 1236 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) |
<> | 144:ef7eb2e8f9f7 | 1237 | { |
<> | 144:ef7eb2e8f9f7 | 1238 | hspi->CRCSize = 2; |
<> | 144:ef7eb2e8f9f7 | 1239 | } |
<> | 144:ef7eb2e8f9f7 | 1240 | } |
<> | 144:ef7eb2e8f9f7 | 1241 | |
<> | 144:ef7eb2e8f9f7 | 1242 | if(hspi->State != HAL_SPI_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 1243 | { |
<> | 144:ef7eb2e8f9f7 | 1244 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
<> | 144:ef7eb2e8f9f7 | 1245 | } |
<> | 144:ef7eb2e8f9f7 | 1246 | |
<> | 144:ef7eb2e8f9f7 | 1247 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1248 | hspi->pTxBuffPtr = pTxData; |
<> | 144:ef7eb2e8f9f7 | 1249 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1250 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1251 | hspi->pRxBuffPtr = pRxData; |
<> | 144:ef7eb2e8f9f7 | 1252 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1253 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1254 | |
<> | 144:ef7eb2e8f9f7 | 1255 | /* Set the function for IT treatment */ |
<> | 144:ef7eb2e8f9f7 | 1256 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
<> | 144:ef7eb2e8f9f7 | 1257 | { |
<> | 144:ef7eb2e8f9f7 | 1258 | hspi->RxISR = SPI_2linesRxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1259 | hspi->TxISR = SPI_2linesTxISR_16BIT; |
<> | 144:ef7eb2e8f9f7 | 1260 | } |
<> | 144:ef7eb2e8f9f7 | 1261 | else |
<> | 144:ef7eb2e8f9f7 | 1262 | { |
<> | 144:ef7eb2e8f9f7 | 1263 | hspi->RxISR = SPI_2linesRxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1264 | hspi->TxISR = SPI_2linesTxISR_8BIT; |
<> | 144:ef7eb2e8f9f7 | 1265 | } |
<> | 144:ef7eb2e8f9f7 | 1266 | |
<> | 144:ef7eb2e8f9f7 | 1267 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1268 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1269 | { |
<> | 144:ef7eb2e8f9f7 | 1270 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1271 | } |
<> | 144:ef7eb2e8f9f7 | 1272 | |
<> | 144:ef7eb2e8f9f7 | 1273 | /* check if packing mode is enabled and if there is more than 2 data to receive */ |
<> | 144:ef7eb2e8f9f7 | 1274 | if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) |
<> | 144:ef7eb2e8f9f7 | 1275 | { |
<> | 144:ef7eb2e8f9f7 | 1276 | /* set fiforxthresold according the reception data length: 16 bit */ |
<> | 144:ef7eb2e8f9f7 | 1277 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1278 | } |
<> | 144:ef7eb2e8f9f7 | 1279 | else |
<> | 144:ef7eb2e8f9f7 | 1280 | { |
<> | 144:ef7eb2e8f9f7 | 1281 | /* set fiforxthresold according the reception data length: 8 bit */ |
<> | 144:ef7eb2e8f9f7 | 1282 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1283 | } |
<> | 144:ef7eb2e8f9f7 | 1284 | |
<> | 144:ef7eb2e8f9f7 | 1285 | /* Enable TXE, RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1286 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 1287 | |
<> | 144:ef7eb2e8f9f7 | 1288 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1289 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1290 | { |
<> | 144:ef7eb2e8f9f7 | 1291 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1292 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1293 | } |
<> | 144:ef7eb2e8f9f7 | 1294 | |
<> | 144:ef7eb2e8f9f7 | 1295 | error : |
<> | 144:ef7eb2e8f9f7 | 1296 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1297 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1298 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1299 | } |
<> | 144:ef7eb2e8f9f7 | 1300 | |
<> | 144:ef7eb2e8f9f7 | 1301 | /** |
<> | 144:ef7eb2e8f9f7 | 1302 | * @brief Transmit an amount of data in non-blocking mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 1303 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1304 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1305 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1306 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1307 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1308 | */ |
<> | 144:ef7eb2e8f9f7 | 1309 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1310 | { |
<> | 144:ef7eb2e8f9f7 | 1311 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1312 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1313 | |
<> | 144:ef7eb2e8f9f7 | 1314 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1315 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1316 | |
<> | 144:ef7eb2e8f9f7 | 1317 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1318 | { |
<> | 144:ef7eb2e8f9f7 | 1319 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1320 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1321 | } |
<> | 144:ef7eb2e8f9f7 | 1322 | |
<> | 144:ef7eb2e8f9f7 | 1323 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 1324 | { |
<> | 144:ef7eb2e8f9f7 | 1325 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1326 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1327 | } |
<> | 144:ef7eb2e8f9f7 | 1328 | |
<> | 144:ef7eb2e8f9f7 | 1329 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 1330 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1331 | hspi->pTxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1332 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1333 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1334 | hspi->pRxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1335 | hspi->RxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 1336 | hspi->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1337 | |
<> | 144:ef7eb2e8f9f7 | 1338 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1339 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1340 | { |
<> | 144:ef7eb2e8f9f7 | 1341 | SPI_1LINE_TX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1342 | } |
<> | 144:ef7eb2e8f9f7 | 1343 | |
<> | 144:ef7eb2e8f9f7 | 1344 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1345 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1346 | { |
<> | 144:ef7eb2e8f9f7 | 1347 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1348 | } |
<> | 144:ef7eb2e8f9f7 | 1349 | |
<> | 144:ef7eb2e8f9f7 | 1350 | /* Set the SPI TxDMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1351 | hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 1352 | |
<> | 144:ef7eb2e8f9f7 | 1353 | /* Set the SPI TxDMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1354 | hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 1355 | |
<> | 144:ef7eb2e8f9f7 | 1356 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1357 | hspi->hdmatx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1358 | |
<> | 144:ef7eb2e8f9f7 | 1359 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
<> | 144:ef7eb2e8f9f7 | 1360 | /* packing mode is enabled only if the DMA setting is HALWORD */ |
<> | 144:ef7eb2e8f9f7 | 1361 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) |
<> | 144:ef7eb2e8f9f7 | 1362 | { |
<> | 144:ef7eb2e8f9f7 | 1363 | /* Check the even/odd of the data size + crc if enabled */ |
<> | 144:ef7eb2e8f9f7 | 1364 | if((hspi->TxXferCount & 0x1) == 0) |
<> | 144:ef7eb2e8f9f7 | 1365 | { |
<> | 144:ef7eb2e8f9f7 | 1366 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
<> | 144:ef7eb2e8f9f7 | 1367 | hspi->TxXferCount = (hspi->TxXferCount >> 1); |
<> | 144:ef7eb2e8f9f7 | 1368 | } |
<> | 144:ef7eb2e8f9f7 | 1369 | else |
<> | 144:ef7eb2e8f9f7 | 1370 | { |
<> | 144:ef7eb2e8f9f7 | 1371 | SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
<> | 144:ef7eb2e8f9f7 | 1372 | hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; |
<> | 144:ef7eb2e8f9f7 | 1373 | } |
<> | 144:ef7eb2e8f9f7 | 1374 | } |
<> | 144:ef7eb2e8f9f7 | 1375 | |
<> | 144:ef7eb2e8f9f7 | 1376 | /* Enable the Tx DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1377 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1378 | |
<> | 144:ef7eb2e8f9f7 | 1379 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1380 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1381 | { |
<> | 144:ef7eb2e8f9f7 | 1382 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1383 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1384 | } |
<> | 144:ef7eb2e8f9f7 | 1385 | |
<> | 144:ef7eb2e8f9f7 | 1386 | /* Enable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1387 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1388 | |
<> | 144:ef7eb2e8f9f7 | 1389 | error : |
<> | 144:ef7eb2e8f9f7 | 1390 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1391 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1392 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1393 | } |
<> | 144:ef7eb2e8f9f7 | 1394 | |
<> | 144:ef7eb2e8f9f7 | 1395 | /** |
<> | 144:ef7eb2e8f9f7 | 1396 | * @brief Receive an amount of data in non-blocking mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 1397 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1398 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1399 | * @param pData: pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1400 | * @note When the CRC feature is enabled the pData Length must be Size + 1. |
<> | 144:ef7eb2e8f9f7 | 1401 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1402 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1403 | */ |
<> | 144:ef7eb2e8f9f7 | 1404 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1405 | { |
<> | 144:ef7eb2e8f9f7 | 1406 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1407 | |
<> | 144:ef7eb2e8f9f7 | 1408 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1409 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1410 | |
<> | 144:ef7eb2e8f9f7 | 1411 | if(hspi->State != HAL_SPI_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1412 | { |
<> | 144:ef7eb2e8f9f7 | 1413 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1414 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1415 | } |
<> | 144:ef7eb2e8f9f7 | 1416 | |
<> | 144:ef7eb2e8f9f7 | 1417 | if((pData == NULL) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 1418 | { |
<> | 144:ef7eb2e8f9f7 | 1419 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1420 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1421 | } |
<> | 144:ef7eb2e8f9f7 | 1422 | |
<> | 144:ef7eb2e8f9f7 | 1423 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1424 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1425 | hspi->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1426 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1427 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1428 | hspi->pTxBuffPtr = (uint8_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 1429 | hspi->TxXferSize = 0; |
<> | 144:ef7eb2e8f9f7 | 1430 | hspi->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1431 | |
<> | 144:ef7eb2e8f9f7 | 1432 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
<> | 144:ef7eb2e8f9f7 | 1433 | { |
<> | 144:ef7eb2e8f9f7 | 1434 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1435 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1436 | /* the receive process is not supported in 2Lines direction master mode */ |
<> | 144:ef7eb2e8f9f7 | 1437 | /* in this case we call the TransmitReceive process */ |
<> | 144:ef7eb2e8f9f7 | 1438 | return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); |
<> | 144:ef7eb2e8f9f7 | 1439 | } |
<> | 144:ef7eb2e8f9f7 | 1440 | |
<> | 144:ef7eb2e8f9f7 | 1441 | /* Configure communication direction : 1Line */ |
<> | 144:ef7eb2e8f9f7 | 1442 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
<> | 144:ef7eb2e8f9f7 | 1443 | { |
<> | 144:ef7eb2e8f9f7 | 1444 | SPI_1LINE_RX(hspi); |
<> | 144:ef7eb2e8f9f7 | 1445 | } |
<> | 144:ef7eb2e8f9f7 | 1446 | |
<> | 144:ef7eb2e8f9f7 | 1447 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 1448 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1449 | { |
<> | 144:ef7eb2e8f9f7 | 1450 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1451 | } |
<> | 144:ef7eb2e8f9f7 | 1452 | |
<> | 144:ef7eb2e8f9f7 | 1453 | /* packing mode management is enabled by the DMA settings */ |
<> | 144:ef7eb2e8f9f7 | 1454 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) |
<> | 144:ef7eb2e8f9f7 | 1455 | { |
<> | 144:ef7eb2e8f9f7 | 1456 | /* Restriction the DMA data received is not allowed in this mode */ |
<> | 144:ef7eb2e8f9f7 | 1457 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1458 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1459 | } |
<> | 144:ef7eb2e8f9f7 | 1460 | |
<> | 144:ef7eb2e8f9f7 | 1461 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); |
<> | 144:ef7eb2e8f9f7 | 1462 | if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 1463 | { |
<> | 144:ef7eb2e8f9f7 | 1464 | /* set fiforxthresold according the reception data length: 16bit */ |
<> | 144:ef7eb2e8f9f7 | 1465 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1466 | } |
<> | 144:ef7eb2e8f9f7 | 1467 | else |
<> | 144:ef7eb2e8f9f7 | 1468 | { |
<> | 144:ef7eb2e8f9f7 | 1469 | /* set fiforxthresold according the reception data length: 8bit */ |
<> | 144:ef7eb2e8f9f7 | 1470 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1471 | } |
<> | 144:ef7eb2e8f9f7 | 1472 | |
<> | 144:ef7eb2e8f9f7 | 1473 | /* Set the SPI RxDMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1474 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1475 | |
<> | 144:ef7eb2e8f9f7 | 1476 | /* Set the SPI Rx DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1477 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1478 | |
<> | 144:ef7eb2e8f9f7 | 1479 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1480 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1481 | |
<> | 144:ef7eb2e8f9f7 | 1482 | /* Enable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1483 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1484 | |
<> | 144:ef7eb2e8f9f7 | 1485 | /* Enable the Rx DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1486 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1487 | |
<> | 144:ef7eb2e8f9f7 | 1488 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1489 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1490 | { |
<> | 144:ef7eb2e8f9f7 | 1491 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1492 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1493 | } |
<> | 144:ef7eb2e8f9f7 | 1494 | |
<> | 144:ef7eb2e8f9f7 | 1495 | error: |
<> | 144:ef7eb2e8f9f7 | 1496 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1497 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1498 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1499 | } |
<> | 144:ef7eb2e8f9f7 | 1500 | |
<> | 144:ef7eb2e8f9f7 | 1501 | /** |
<> | 144:ef7eb2e8f9f7 | 1502 | * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 1503 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1504 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1505 | * @param pTxData: pointer to transmission data buffer |
<> | 144:ef7eb2e8f9f7 | 1506 | * @param pRxData: pointer to reception data buffer |
<> | 144:ef7eb2e8f9f7 | 1507 | * @note When the CRC feature is enabled the pRxData Length must be Size + 1 |
<> | 144:ef7eb2e8f9f7 | 1508 | * @param Size: amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1509 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1510 | */ |
<> | 144:ef7eb2e8f9f7 | 1511 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1512 | { |
<> | 144:ef7eb2e8f9f7 | 1513 | HAL_StatusTypeDef errorcode = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1514 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
<> | 144:ef7eb2e8f9f7 | 1515 | |
<> | 144:ef7eb2e8f9f7 | 1516 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1517 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1518 | |
<> | 144:ef7eb2e8f9f7 | 1519 | if(!((hspi->State == HAL_SPI_STATE_READY) || |
<> | 144:ef7eb2e8f9f7 | 1520 | ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) |
<> | 144:ef7eb2e8f9f7 | 1521 | { |
<> | 144:ef7eb2e8f9f7 | 1522 | errorcode = HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1523 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1524 | } |
<> | 144:ef7eb2e8f9f7 | 1525 | |
<> | 144:ef7eb2e8f9f7 | 1526 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
<> | 144:ef7eb2e8f9f7 | 1527 | { |
<> | 144:ef7eb2e8f9f7 | 1528 | errorcode = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1529 | goto error; |
<> | 144:ef7eb2e8f9f7 | 1530 | } |
<> | 144:ef7eb2e8f9f7 | 1531 | |
<> | 144:ef7eb2e8f9f7 | 1532 | /* check if the transmit Receive function is not called by a receive master */ |
<> | 144:ef7eb2e8f9f7 | 1533 | if(hspi->State != HAL_SPI_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 1534 | { |
<> | 144:ef7eb2e8f9f7 | 1535 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
<> | 144:ef7eb2e8f9f7 | 1536 | } |
<> | 144:ef7eb2e8f9f7 | 1537 | |
<> | 144:ef7eb2e8f9f7 | 1538 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1539 | hspi->pTxBuffPtr = (uint8_t *)pTxData; |
<> | 144:ef7eb2e8f9f7 | 1540 | hspi->TxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1541 | hspi->TxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1542 | hspi->pRxBuffPtr = (uint8_t *)pRxData; |
<> | 144:ef7eb2e8f9f7 | 1543 | hspi->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 1544 | hspi->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1545 | |
<> | 144:ef7eb2e8f9f7 | 1546 | /* Reset CRC Calculation + increase the rxsize */ |
<> | 144:ef7eb2e8f9f7 | 1547 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1548 | { |
<> | 144:ef7eb2e8f9f7 | 1549 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 1550 | } |
<> | 144:ef7eb2e8f9f7 | 1551 | |
<> | 144:ef7eb2e8f9f7 | 1552 | /* Reset the threshold bit */ |
<> | 144:ef7eb2e8f9f7 | 1553 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); |
<> | 144:ef7eb2e8f9f7 | 1554 | |
<> | 144:ef7eb2e8f9f7 | 1555 | /* the packing mode management is enabled by the DMA settings according the spi data size */ |
<> | 144:ef7eb2e8f9f7 | 1556 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 1557 | { |
<> | 144:ef7eb2e8f9f7 | 1558 | /* set fiforxthreshold according the reception data length: 16bit */ |
<> | 144:ef7eb2e8f9f7 | 1559 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1560 | } |
<> | 144:ef7eb2e8f9f7 | 1561 | else |
<> | 144:ef7eb2e8f9f7 | 1562 | { |
<> | 144:ef7eb2e8f9f7 | 1563 | /* set fiforxthresold according the reception data length: 8bit */ |
<> | 144:ef7eb2e8f9f7 | 1564 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1565 | |
<> | 144:ef7eb2e8f9f7 | 1566 | if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) |
<> | 144:ef7eb2e8f9f7 | 1567 | { |
<> | 144:ef7eb2e8f9f7 | 1568 | if((hspi->TxXferSize & 0x1) == 0x0) |
<> | 144:ef7eb2e8f9f7 | 1569 | { |
<> | 144:ef7eb2e8f9f7 | 1570 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
<> | 144:ef7eb2e8f9f7 | 1571 | hspi->TxXferCount = hspi->TxXferCount >> 1; |
<> | 144:ef7eb2e8f9f7 | 1572 | } |
<> | 144:ef7eb2e8f9f7 | 1573 | else |
<> | 144:ef7eb2e8f9f7 | 1574 | { |
<> | 144:ef7eb2e8f9f7 | 1575 | SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
<> | 144:ef7eb2e8f9f7 | 1576 | hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; |
<> | 144:ef7eb2e8f9f7 | 1577 | } |
<> | 144:ef7eb2e8f9f7 | 1578 | } |
<> | 144:ef7eb2e8f9f7 | 1579 | |
<> | 144:ef7eb2e8f9f7 | 1580 | if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) |
<> | 144:ef7eb2e8f9f7 | 1581 | { |
<> | 144:ef7eb2e8f9f7 | 1582 | /* set fiforxthresold according the reception data length: 16bit */ |
<> | 144:ef7eb2e8f9f7 | 1583 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 1584 | |
<> | 144:ef7eb2e8f9f7 | 1585 | if((hspi->RxXferCount & 0x1) == 0x0 ) |
<> | 144:ef7eb2e8f9f7 | 1586 | { |
<> | 144:ef7eb2e8f9f7 | 1587 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); |
<> | 144:ef7eb2e8f9f7 | 1588 | hspi->RxXferCount = hspi->RxXferCount >> 1; |
<> | 144:ef7eb2e8f9f7 | 1589 | } |
<> | 144:ef7eb2e8f9f7 | 1590 | else |
<> | 144:ef7eb2e8f9f7 | 1591 | { |
<> | 144:ef7eb2e8f9f7 | 1592 | SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); |
<> | 144:ef7eb2e8f9f7 | 1593 | hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; |
<> | 144:ef7eb2e8f9f7 | 1594 | } |
<> | 144:ef7eb2e8f9f7 | 1595 | } |
<> | 144:ef7eb2e8f9f7 | 1596 | } |
<> | 144:ef7eb2e8f9f7 | 1597 | |
<> | 144:ef7eb2e8f9f7 | 1598 | /* Set the SPI Rx DMA transfer complete callback if the transfer request is a |
<> | 144:ef7eb2e8f9f7 | 1599 | reception request (RXNE) */ |
<> | 144:ef7eb2e8f9f7 | 1600 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 1601 | { |
<> | 144:ef7eb2e8f9f7 | 1602 | /* Set the SPI Rx DMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1603 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1604 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1605 | } |
<> | 144:ef7eb2e8f9f7 | 1606 | else |
<> | 144:ef7eb2e8f9f7 | 1607 | { |
<> | 144:ef7eb2e8f9f7 | 1608 | /* Set the SPI Rx DMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1609 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1610 | hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1611 | } |
<> | 144:ef7eb2e8f9f7 | 1612 | |
<> | 144:ef7eb2e8f9f7 | 1613 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1614 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1615 | |
<> | 144:ef7eb2e8f9f7 | 1616 | /* Enable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1617 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1618 | |
<> | 144:ef7eb2e8f9f7 | 1619 | /* Enable the Rx DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1620 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1621 | |
<> | 144:ef7eb2e8f9f7 | 1622 | /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing |
<> | 144:ef7eb2e8f9f7 | 1623 | is performed in DMA reception complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1624 | hspi->hdmatx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1625 | hspi->hdmatx->XferCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1626 | |
<> | 144:ef7eb2e8f9f7 | 1627 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1628 | hspi->hdmatx->XferErrorCallback = SPI_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1629 | |
<> | 144:ef7eb2e8f9f7 | 1630 | /* Enable the Tx DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1631 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
<> | 144:ef7eb2e8f9f7 | 1632 | |
<> | 144:ef7eb2e8f9f7 | 1633 | /* Check if the SPI is already enabled */ |
<> | 144:ef7eb2e8f9f7 | 1634 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
<> | 144:ef7eb2e8f9f7 | 1635 | { |
<> | 144:ef7eb2e8f9f7 | 1636 | /* Enable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1637 | __HAL_SPI_ENABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 1638 | } |
<> | 144:ef7eb2e8f9f7 | 1639 | |
<> | 144:ef7eb2e8f9f7 | 1640 | /* Enable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1641 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1642 | |
<> | 144:ef7eb2e8f9f7 | 1643 | error : |
<> | 144:ef7eb2e8f9f7 | 1644 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1645 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1646 | return errorcode; |
<> | 144:ef7eb2e8f9f7 | 1647 | } |
<> | 144:ef7eb2e8f9f7 | 1648 | |
<> | 144:ef7eb2e8f9f7 | 1649 | /** |
<> | 144:ef7eb2e8f9f7 | 1650 | * @brief Pause the DMA Transfer. |
<> | 144:ef7eb2e8f9f7 | 1651 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1652 | * the configuration information for the specified SPI module. |
<> | 144:ef7eb2e8f9f7 | 1653 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1654 | */ |
<> | 144:ef7eb2e8f9f7 | 1655 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1656 | { |
<> | 144:ef7eb2e8f9f7 | 1657 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1658 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1659 | |
<> | 144:ef7eb2e8f9f7 | 1660 | /* Disable the SPI DMA Tx & Rx requests */ |
<> | 144:ef7eb2e8f9f7 | 1661 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1662 | |
<> | 144:ef7eb2e8f9f7 | 1663 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1664 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1665 | |
<> | 144:ef7eb2e8f9f7 | 1666 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1667 | } |
<> | 144:ef7eb2e8f9f7 | 1668 | |
<> | 144:ef7eb2e8f9f7 | 1669 | /** |
<> | 144:ef7eb2e8f9f7 | 1670 | * @brief Resume the DMA Transfer. |
<> | 144:ef7eb2e8f9f7 | 1671 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1672 | * the configuration information for the specified SPI module. |
<> | 144:ef7eb2e8f9f7 | 1673 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1674 | */ |
<> | 144:ef7eb2e8f9f7 | 1675 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1676 | { |
<> | 144:ef7eb2e8f9f7 | 1677 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1678 | __HAL_LOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1679 | |
<> | 144:ef7eb2e8f9f7 | 1680 | /* Enable the SPI DMA Tx & Rx requests */ |
<> | 144:ef7eb2e8f9f7 | 1681 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1682 | |
<> | 144:ef7eb2e8f9f7 | 1683 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1684 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 1685 | |
<> | 144:ef7eb2e8f9f7 | 1686 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1687 | } |
<> | 144:ef7eb2e8f9f7 | 1688 | |
<> | 144:ef7eb2e8f9f7 | 1689 | /** |
<> | 144:ef7eb2e8f9f7 | 1690 | * @brief Stop the DMA Transfer. |
<> | 144:ef7eb2e8f9f7 | 1691 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1692 | * the configuration information for the specified SPI module. |
<> | 144:ef7eb2e8f9f7 | 1693 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1694 | */ |
<> | 144:ef7eb2e8f9f7 | 1695 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1696 | { |
<> | 144:ef7eb2e8f9f7 | 1697 | /* The Lock is not implemented on this API to allow the user application |
<> | 144:ef7eb2e8f9f7 | 1698 | to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): |
<> | 144:ef7eb2e8f9f7 | 1699 | when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated |
<> | 144:ef7eb2e8f9f7 | 1700 | and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 1701 | */ |
<> | 144:ef7eb2e8f9f7 | 1702 | |
<> | 144:ef7eb2e8f9f7 | 1703 | /* Abort the SPI DMA tx channel */ |
<> | 144:ef7eb2e8f9f7 | 1704 | if(hspi->hdmatx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1705 | { |
<> | 144:ef7eb2e8f9f7 | 1706 | HAL_DMA_Abort(hspi->hdmatx); |
<> | 144:ef7eb2e8f9f7 | 1707 | } |
<> | 144:ef7eb2e8f9f7 | 1708 | /* Abort the SPI DMA rx channel */ |
<> | 144:ef7eb2e8f9f7 | 1709 | if(hspi->hdmarx != NULL) |
<> | 144:ef7eb2e8f9f7 | 1710 | { |
<> | 144:ef7eb2e8f9f7 | 1711 | HAL_DMA_Abort(hspi->hdmarx); |
<> | 144:ef7eb2e8f9f7 | 1712 | } |
<> | 144:ef7eb2e8f9f7 | 1713 | |
<> | 144:ef7eb2e8f9f7 | 1714 | /* Disable the SPI DMA Tx & Rx requests */ |
<> | 144:ef7eb2e8f9f7 | 1715 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1716 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1717 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1718 | } |
<> | 144:ef7eb2e8f9f7 | 1719 | |
<> | 144:ef7eb2e8f9f7 | 1720 | /** |
<> | 144:ef7eb2e8f9f7 | 1721 | * @brief Handle SPI interrupt request. |
<> | 144:ef7eb2e8f9f7 | 1722 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1723 | * the configuration information for the specified SPI module. |
<> | 144:ef7eb2e8f9f7 | 1724 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1725 | */ |
<> | 144:ef7eb2e8f9f7 | 1726 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1727 | { |
<> | 144:ef7eb2e8f9f7 | 1728 | uint32_t itsource = hspi->Instance->CR2; |
<> | 144:ef7eb2e8f9f7 | 1729 | uint32_t itflag = hspi->Instance->SR; |
<> | 144:ef7eb2e8f9f7 | 1730 | |
<> | 144:ef7eb2e8f9f7 | 1731 | /* SPI in mode Receiver ----------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1732 | if(((itflag & SPI_FLAG_OVR) == RESET) && |
<> | 144:ef7eb2e8f9f7 | 1733 | ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1734 | { |
<> | 144:ef7eb2e8f9f7 | 1735 | hspi->RxISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 1736 | return; |
<> | 144:ef7eb2e8f9f7 | 1737 | } |
<> | 144:ef7eb2e8f9f7 | 1738 | |
<> | 144:ef7eb2e8f9f7 | 1739 | /* SPI in mode Transmitter ---------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1740 | if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 1741 | { |
<> | 144:ef7eb2e8f9f7 | 1742 | hspi->TxISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 1743 | return; |
<> | 144:ef7eb2e8f9f7 | 1744 | } |
<> | 144:ef7eb2e8f9f7 | 1745 | |
<> | 144:ef7eb2e8f9f7 | 1746 | /* SPI in Error Treatment ---------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1747 | if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1748 | { |
<> | 144:ef7eb2e8f9f7 | 1749 | /* SPI Overrun error interrupt occurred -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1750 | if((itflag & SPI_FLAG_OVR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1751 | { |
<> | 144:ef7eb2e8f9f7 | 1752 | if(hspi->State != HAL_SPI_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 1753 | { |
<> | 144:ef7eb2e8f9f7 | 1754 | hspi->ErrorCode |= HAL_SPI_ERROR_OVR; |
<> | 144:ef7eb2e8f9f7 | 1755 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1756 | } |
<> | 144:ef7eb2e8f9f7 | 1757 | else |
<> | 144:ef7eb2e8f9f7 | 1758 | { |
<> | 144:ef7eb2e8f9f7 | 1759 | return; |
<> | 144:ef7eb2e8f9f7 | 1760 | } |
<> | 144:ef7eb2e8f9f7 | 1761 | } |
<> | 144:ef7eb2e8f9f7 | 1762 | |
<> | 144:ef7eb2e8f9f7 | 1763 | /* SPI Mode Fault error interrupt occurred -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1764 | if((itflag & SPI_FLAG_MODF) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1765 | { |
<> | 144:ef7eb2e8f9f7 | 1766 | hspi->ErrorCode |= HAL_SPI_ERROR_MODF; |
<> | 144:ef7eb2e8f9f7 | 1767 | __HAL_SPI_CLEAR_MODFFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1768 | } |
<> | 144:ef7eb2e8f9f7 | 1769 | |
<> | 144:ef7eb2e8f9f7 | 1770 | /* SPI Frame error interrupt occurred ----------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1771 | if((itflag & SPI_FLAG_FRE) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1772 | { |
<> | 144:ef7eb2e8f9f7 | 1773 | hspi->ErrorCode |= HAL_SPI_ERROR_FRE; |
<> | 144:ef7eb2e8f9f7 | 1774 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1775 | } |
<> | 144:ef7eb2e8f9f7 | 1776 | |
<> | 144:ef7eb2e8f9f7 | 1777 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); |
<> | 144:ef7eb2e8f9f7 | 1778 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1779 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1780 | return; |
<> | 144:ef7eb2e8f9f7 | 1781 | } |
<> | 144:ef7eb2e8f9f7 | 1782 | } |
<> | 144:ef7eb2e8f9f7 | 1783 | |
<> | 144:ef7eb2e8f9f7 | 1784 | /** |
<> | 144:ef7eb2e8f9f7 | 1785 | * @brief Tx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1786 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1787 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1788 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1789 | */ |
<> | 144:ef7eb2e8f9f7 | 1790 | __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1791 | { |
<> | 144:ef7eb2e8f9f7 | 1792 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1793 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1794 | |
<> | 144:ef7eb2e8f9f7 | 1795 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1796 | the HAL_SPI_TxCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1797 | */ |
<> | 144:ef7eb2e8f9f7 | 1798 | } |
<> | 144:ef7eb2e8f9f7 | 1799 | |
<> | 144:ef7eb2e8f9f7 | 1800 | /** |
<> | 144:ef7eb2e8f9f7 | 1801 | * @brief Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1802 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1803 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1804 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1805 | */ |
<> | 144:ef7eb2e8f9f7 | 1806 | __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1807 | { |
<> | 144:ef7eb2e8f9f7 | 1808 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1809 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1810 | |
<> | 144:ef7eb2e8f9f7 | 1811 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1812 | the HAL_SPI_RxCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1813 | */ |
<> | 144:ef7eb2e8f9f7 | 1814 | } |
<> | 144:ef7eb2e8f9f7 | 1815 | |
<> | 144:ef7eb2e8f9f7 | 1816 | /** |
<> | 144:ef7eb2e8f9f7 | 1817 | * @brief Tx and Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1818 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1819 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1820 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1821 | */ |
<> | 144:ef7eb2e8f9f7 | 1822 | __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1823 | { |
<> | 144:ef7eb2e8f9f7 | 1824 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1825 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1826 | |
<> | 144:ef7eb2e8f9f7 | 1827 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1828 | the HAL_SPI_TxRxCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1829 | */ |
<> | 144:ef7eb2e8f9f7 | 1830 | } |
<> | 144:ef7eb2e8f9f7 | 1831 | |
<> | 144:ef7eb2e8f9f7 | 1832 | /** |
<> | 144:ef7eb2e8f9f7 | 1833 | * @brief Tx Half Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1834 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1835 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1836 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1837 | */ |
<> | 144:ef7eb2e8f9f7 | 1838 | __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1839 | { |
<> | 144:ef7eb2e8f9f7 | 1840 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1841 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1842 | |
<> | 144:ef7eb2e8f9f7 | 1843 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1844 | the HAL_SPI_TxHalfCpltCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1845 | */ |
<> | 144:ef7eb2e8f9f7 | 1846 | } |
<> | 144:ef7eb2e8f9f7 | 1847 | |
<> | 144:ef7eb2e8f9f7 | 1848 | /** |
<> | 144:ef7eb2e8f9f7 | 1849 | * @brief Rx Half Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 1850 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1851 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1852 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1853 | */ |
<> | 144:ef7eb2e8f9f7 | 1854 | __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1855 | { |
<> | 144:ef7eb2e8f9f7 | 1856 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1857 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1858 | |
<> | 144:ef7eb2e8f9f7 | 1859 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1860 | the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1861 | */ |
<> | 144:ef7eb2e8f9f7 | 1862 | } |
<> | 144:ef7eb2e8f9f7 | 1863 | |
<> | 144:ef7eb2e8f9f7 | 1864 | /** |
<> | 144:ef7eb2e8f9f7 | 1865 | * @brief Tx and Rx Half Transfer callback. |
<> | 144:ef7eb2e8f9f7 | 1866 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1867 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1868 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1869 | */ |
<> | 144:ef7eb2e8f9f7 | 1870 | __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1871 | { |
<> | 144:ef7eb2e8f9f7 | 1872 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1873 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1874 | |
<> | 144:ef7eb2e8f9f7 | 1875 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1876 | the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1877 | */ |
<> | 144:ef7eb2e8f9f7 | 1878 | } |
<> | 144:ef7eb2e8f9f7 | 1879 | |
<> | 144:ef7eb2e8f9f7 | 1880 | /** |
<> | 144:ef7eb2e8f9f7 | 1881 | * @brief SPI error callback. |
<> | 144:ef7eb2e8f9f7 | 1882 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1883 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1884 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1885 | */ |
<> | 144:ef7eb2e8f9f7 | 1886 | __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1887 | { |
<> | 144:ef7eb2e8f9f7 | 1888 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1889 | UNUSED(hspi); |
<> | 144:ef7eb2e8f9f7 | 1890 | |
<> | 144:ef7eb2e8f9f7 | 1891 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1892 | the HAL_SPI_ErrorCallback should be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1893 | */ |
<> | 144:ef7eb2e8f9f7 | 1894 | /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes |
<> | 144:ef7eb2e8f9f7 | 1895 | and user can use HAL_SPI_GetError() API to check the latest error occurred |
<> | 144:ef7eb2e8f9f7 | 1896 | */ |
<> | 144:ef7eb2e8f9f7 | 1897 | } |
<> | 144:ef7eb2e8f9f7 | 1898 | |
<> | 144:ef7eb2e8f9f7 | 1899 | /** |
<> | 144:ef7eb2e8f9f7 | 1900 | * @} |
<> | 144:ef7eb2e8f9f7 | 1901 | */ |
<> | 144:ef7eb2e8f9f7 | 1902 | |
<> | 144:ef7eb2e8f9f7 | 1903 | /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 1904 | * @brief SPI control functions |
<> | 144:ef7eb2e8f9f7 | 1905 | * |
<> | 144:ef7eb2e8f9f7 | 1906 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1907 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1908 | ##### Peripheral State and Errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1909 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1910 | [..] |
<> | 144:ef7eb2e8f9f7 | 1911 | This subsection provides a set of functions allowing to control the SPI. |
<> | 144:ef7eb2e8f9f7 | 1912 | (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral |
<> | 144:ef7eb2e8f9f7 | 1913 | (+) HAL_SPI_GetError() check in run-time Errors occurring during communication |
<> | 144:ef7eb2e8f9f7 | 1914 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1915 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1916 | */ |
<> | 144:ef7eb2e8f9f7 | 1917 | |
<> | 144:ef7eb2e8f9f7 | 1918 | /** |
<> | 144:ef7eb2e8f9f7 | 1919 | * @brief Return the SPI handle state. |
<> | 144:ef7eb2e8f9f7 | 1920 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1921 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1922 | * @retval SPI state |
<> | 144:ef7eb2e8f9f7 | 1923 | */ |
<> | 144:ef7eb2e8f9f7 | 1924 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1925 | { |
<> | 144:ef7eb2e8f9f7 | 1926 | /* Return SPI handle state */ |
<> | 144:ef7eb2e8f9f7 | 1927 | return hspi->State; |
<> | 144:ef7eb2e8f9f7 | 1928 | } |
<> | 144:ef7eb2e8f9f7 | 1929 | |
<> | 144:ef7eb2e8f9f7 | 1930 | /** |
<> | 144:ef7eb2e8f9f7 | 1931 | * @brief Return the SPI error code. |
<> | 144:ef7eb2e8f9f7 | 1932 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1933 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 1934 | * @retval SPI error code in bitmap format |
<> | 144:ef7eb2e8f9f7 | 1935 | */ |
<> | 144:ef7eb2e8f9f7 | 1936 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 1937 | { |
<> | 144:ef7eb2e8f9f7 | 1938 | return hspi->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1939 | } |
<> | 144:ef7eb2e8f9f7 | 1940 | |
<> | 144:ef7eb2e8f9f7 | 1941 | /** |
<> | 144:ef7eb2e8f9f7 | 1942 | * @} |
<> | 144:ef7eb2e8f9f7 | 1943 | */ |
<> | 144:ef7eb2e8f9f7 | 1944 | |
<> | 144:ef7eb2e8f9f7 | 1945 | |
<> | 144:ef7eb2e8f9f7 | 1946 | /** |
<> | 144:ef7eb2e8f9f7 | 1947 | * @} |
<> | 144:ef7eb2e8f9f7 | 1948 | */ |
<> | 144:ef7eb2e8f9f7 | 1949 | |
<> | 144:ef7eb2e8f9f7 | 1950 | /** @addtogroup SPI_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 1951 | * @brief Private functions |
<> | 144:ef7eb2e8f9f7 | 1952 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1953 | */ |
<> | 144:ef7eb2e8f9f7 | 1954 | |
<> | 144:ef7eb2e8f9f7 | 1955 | /** |
<> | 144:ef7eb2e8f9f7 | 1956 | * @brief DMA SPI transmit process complete callback. |
<> | 144:ef7eb2e8f9f7 | 1957 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1958 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1959 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1960 | */ |
<> | 144:ef7eb2e8f9f7 | 1961 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1962 | { |
<> | 144:ef7eb2e8f9f7 | 1963 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1964 | |
<> | 144:ef7eb2e8f9f7 | 1965 | if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) |
<> | 144:ef7eb2e8f9f7 | 1966 | { |
<> | 144:ef7eb2e8f9f7 | 1967 | /* Disable Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1968 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1969 | |
<> | 144:ef7eb2e8f9f7 | 1970 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 1971 | if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1972 | { |
<> | 144:ef7eb2e8f9f7 | 1973 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 1974 | } |
<> | 144:ef7eb2e8f9f7 | 1975 | |
<> | 144:ef7eb2e8f9f7 | 1976 | /* Clear overrun flag in 2 Lines communication mode because received data is not read */ |
<> | 144:ef7eb2e8f9f7 | 1977 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 1978 | { |
<> | 144:ef7eb2e8f9f7 | 1979 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 1980 | } |
<> | 144:ef7eb2e8f9f7 | 1981 | |
<> | 144:ef7eb2e8f9f7 | 1982 | hspi->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1983 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1984 | |
<> | 144:ef7eb2e8f9f7 | 1985 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 1986 | { |
<> | 144:ef7eb2e8f9f7 | 1987 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1988 | return; |
<> | 144:ef7eb2e8f9f7 | 1989 | } |
<> | 144:ef7eb2e8f9f7 | 1990 | } |
<> | 144:ef7eb2e8f9f7 | 1991 | HAL_SPI_TxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 1992 | } |
<> | 144:ef7eb2e8f9f7 | 1993 | |
<> | 144:ef7eb2e8f9f7 | 1994 | /** |
<> | 144:ef7eb2e8f9f7 | 1995 | * @brief DMA SPI receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 1996 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1997 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 1998 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1999 | */ |
<> | 144:ef7eb2e8f9f7 | 2000 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2001 | { |
<> | 144:ef7eb2e8f9f7 | 2002 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2003 | |
<> | 144:ef7eb2e8f9f7 | 2004 | if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) |
<> | 144:ef7eb2e8f9f7 | 2005 | { |
<> | 144:ef7eb2e8f9f7 | 2006 | __IO uint16_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 2007 | |
<> | 144:ef7eb2e8f9f7 | 2008 | /* CRC handling */ |
<> | 144:ef7eb2e8f9f7 | 2009 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2010 | { |
<> | 144:ef7eb2e8f9f7 | 2011 | /* Wait until TXE flag */ |
<> | 144:ef7eb2e8f9f7 | 2012 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2013 | { |
<> | 144:ef7eb2e8f9f7 | 2014 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 2015 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2016 | } |
<> | 144:ef7eb2e8f9f7 | 2017 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 2018 | { |
<> | 144:ef7eb2e8f9f7 | 2019 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2020 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2021 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2022 | } |
<> | 144:ef7eb2e8f9f7 | 2023 | else |
<> | 144:ef7eb2e8f9f7 | 2024 | { |
<> | 144:ef7eb2e8f9f7 | 2025 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2026 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2027 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2028 | |
<> | 144:ef7eb2e8f9f7 | 2029 | if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) |
<> | 144:ef7eb2e8f9f7 | 2030 | { |
<> | 144:ef7eb2e8f9f7 | 2031 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2032 | { |
<> | 144:ef7eb2e8f9f7 | 2033 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 2034 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2035 | } |
<> | 144:ef7eb2e8f9f7 | 2036 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2037 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2038 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2039 | } |
<> | 144:ef7eb2e8f9f7 | 2040 | } |
<> | 144:ef7eb2e8f9f7 | 2041 | } |
<> | 144:ef7eb2e8f9f7 | 2042 | |
<> | 144:ef7eb2e8f9f7 | 2043 | /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ |
<> | 144:ef7eb2e8f9f7 | 2044 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 2045 | |
<> | 144:ef7eb2e8f9f7 | 2046 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2047 | if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2048 | { |
<> | 144:ef7eb2e8f9f7 | 2049 | hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2050 | } |
<> | 144:ef7eb2e8f9f7 | 2051 | |
<> | 144:ef7eb2e8f9f7 | 2052 | hspi->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 2053 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2054 | |
<> | 144:ef7eb2e8f9f7 | 2055 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2056 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2057 | { |
<> | 144:ef7eb2e8f9f7 | 2058 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2059 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2060 | } |
<> | 144:ef7eb2e8f9f7 | 2061 | |
<> | 144:ef7eb2e8f9f7 | 2062 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2063 | { |
<> | 144:ef7eb2e8f9f7 | 2064 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2065 | return; |
<> | 144:ef7eb2e8f9f7 | 2066 | } |
<> | 144:ef7eb2e8f9f7 | 2067 | } |
<> | 144:ef7eb2e8f9f7 | 2068 | HAL_SPI_RxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2069 | } |
<> | 144:ef7eb2e8f9f7 | 2070 | |
<> | 144:ef7eb2e8f9f7 | 2071 | /** |
<> | 144:ef7eb2e8f9f7 | 2072 | * @brief DMA SPI transmit receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 2073 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2074 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2075 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2076 | */ |
<> | 144:ef7eb2e8f9f7 | 2077 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2078 | { |
<> | 144:ef7eb2e8f9f7 | 2079 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2080 | |
<> | 144:ef7eb2e8f9f7 | 2081 | if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) |
<> | 144:ef7eb2e8f9f7 | 2082 | { |
<> | 144:ef7eb2e8f9f7 | 2083 | __IO int16_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 2084 | /* CRC handling */ |
<> | 144:ef7eb2e8f9f7 | 2085 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2086 | { |
<> | 144:ef7eb2e8f9f7 | 2087 | if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) |
<> | 144:ef7eb2e8f9f7 | 2088 | { |
<> | 144:ef7eb2e8f9f7 | 2089 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2090 | { |
<> | 144:ef7eb2e8f9f7 | 2091 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 2092 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2093 | } |
<> | 144:ef7eb2e8f9f7 | 2094 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2095 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2096 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2097 | } |
<> | 144:ef7eb2e8f9f7 | 2098 | else |
<> | 144:ef7eb2e8f9f7 | 2099 | { |
<> | 144:ef7eb2e8f9f7 | 2100 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2101 | { |
<> | 144:ef7eb2e8f9f7 | 2102 | /* Error on the CRC reception */ |
<> | 144:ef7eb2e8f9f7 | 2103 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2104 | } |
<> | 144:ef7eb2e8f9f7 | 2105 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2106 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2107 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2108 | } |
<> | 144:ef7eb2e8f9f7 | 2109 | } |
<> | 144:ef7eb2e8f9f7 | 2110 | |
<> | 144:ef7eb2e8f9f7 | 2111 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2112 | if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2113 | { |
<> | 144:ef7eb2e8f9f7 | 2114 | hspi->ErrorCode = HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2115 | } |
<> | 144:ef7eb2e8f9f7 | 2116 | |
<> | 144:ef7eb2e8f9f7 | 2117 | /* Disable Rx/Tx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 2118 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 2119 | |
<> | 144:ef7eb2e8f9f7 | 2120 | hspi->TxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 2121 | hspi->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 2122 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2123 | |
<> | 144:ef7eb2e8f9f7 | 2124 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2125 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2126 | { |
<> | 144:ef7eb2e8f9f7 | 2127 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2128 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2129 | } |
<> | 144:ef7eb2e8f9f7 | 2130 | |
<> | 144:ef7eb2e8f9f7 | 2131 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2132 | { |
<> | 144:ef7eb2e8f9f7 | 2133 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2134 | return; |
<> | 144:ef7eb2e8f9f7 | 2135 | } |
<> | 144:ef7eb2e8f9f7 | 2136 | } |
<> | 144:ef7eb2e8f9f7 | 2137 | HAL_SPI_TxRxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2138 | } |
<> | 144:ef7eb2e8f9f7 | 2139 | |
<> | 144:ef7eb2e8f9f7 | 2140 | /** |
<> | 144:ef7eb2e8f9f7 | 2141 | * @brief DMA SPI half transmit process complete callback. |
<> | 144:ef7eb2e8f9f7 | 2142 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2143 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2144 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2145 | */ |
<> | 144:ef7eb2e8f9f7 | 2146 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2147 | { |
<> | 144:ef7eb2e8f9f7 | 2148 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2149 | |
<> | 144:ef7eb2e8f9f7 | 2150 | HAL_SPI_TxHalfCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2151 | } |
<> | 144:ef7eb2e8f9f7 | 2152 | |
<> | 144:ef7eb2e8f9f7 | 2153 | /** |
<> | 144:ef7eb2e8f9f7 | 2154 | * @brief DMA SPI half receive process complete callback |
<> | 144:ef7eb2e8f9f7 | 2155 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2156 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2157 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2158 | */ |
<> | 144:ef7eb2e8f9f7 | 2159 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2160 | { |
<> | 144:ef7eb2e8f9f7 | 2161 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2162 | |
<> | 144:ef7eb2e8f9f7 | 2163 | HAL_SPI_RxHalfCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2164 | } |
<> | 144:ef7eb2e8f9f7 | 2165 | |
<> | 144:ef7eb2e8f9f7 | 2166 | /** |
<> | 144:ef7eb2e8f9f7 | 2167 | * @brief DMA SPI half transmit receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 2168 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2169 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2170 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2171 | */ |
<> | 144:ef7eb2e8f9f7 | 2172 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2173 | { |
<> | 144:ef7eb2e8f9f7 | 2174 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2175 | |
<> | 144:ef7eb2e8f9f7 | 2176 | HAL_SPI_TxRxHalfCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2177 | } |
<> | 144:ef7eb2e8f9f7 | 2178 | |
<> | 144:ef7eb2e8f9f7 | 2179 | /** |
<> | 144:ef7eb2e8f9f7 | 2180 | * @brief DMA SPI communication error callback. |
<> | 144:ef7eb2e8f9f7 | 2181 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2182 | * the configuration information for the specified DMA module. |
<> | 144:ef7eb2e8f9f7 | 2183 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2184 | */ |
<> | 144:ef7eb2e8f9f7 | 2185 | static void SPI_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2186 | { |
<> | 144:ef7eb2e8f9f7 | 2187 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2188 | |
<> | 144:ef7eb2e8f9f7 | 2189 | /* Stop the disable DMA transfer on SPI side */ |
<> | 144:ef7eb2e8f9f7 | 2190 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 2191 | |
<> | 144:ef7eb2e8f9f7 | 2192 | hspi->ErrorCode|= HAL_SPI_ERROR_DMA; |
<> | 144:ef7eb2e8f9f7 | 2193 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2194 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2195 | } |
<> | 144:ef7eb2e8f9f7 | 2196 | |
<> | 144:ef7eb2e8f9f7 | 2197 | /** |
<> | 144:ef7eb2e8f9f7 | 2198 | * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2199 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2200 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2201 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2202 | */ |
<> | 144:ef7eb2e8f9f7 | 2203 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2204 | { |
<> | 144:ef7eb2e8f9f7 | 2205 | /* Receive data in packing mode */ |
<> | 144:ef7eb2e8f9f7 | 2206 | if(hspi->RxXferCount > 1) |
<> | 144:ef7eb2e8f9f7 | 2207 | { |
<> | 144:ef7eb2e8f9f7 | 2208 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2209 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2210 | hspi->RxXferCount -= 2; |
<> | 144:ef7eb2e8f9f7 | 2211 | if(hspi->RxXferCount == 1) |
<> | 144:ef7eb2e8f9f7 | 2212 | { |
<> | 144:ef7eb2e8f9f7 | 2213 | /* set fiforxthresold according the reception data length: 8bit */ |
<> | 144:ef7eb2e8f9f7 | 2214 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 2215 | } |
<> | 144:ef7eb2e8f9f7 | 2216 | } |
<> | 144:ef7eb2e8f9f7 | 2217 | /* Receive data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2218 | else |
<> | 144:ef7eb2e8f9f7 | 2219 | { |
<> | 144:ef7eb2e8f9f7 | 2220 | *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2221 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2222 | } |
<> | 144:ef7eb2e8f9f7 | 2223 | |
<> | 144:ef7eb2e8f9f7 | 2224 | /* check end of the reception */ |
<> | 144:ef7eb2e8f9f7 | 2225 | if(hspi->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2226 | { |
<> | 144:ef7eb2e8f9f7 | 2227 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2228 | { |
<> | 144:ef7eb2e8f9f7 | 2229 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
<> | 144:ef7eb2e8f9f7 | 2230 | hspi->RxISR = SPI_2linesRxISR_8BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2231 | return; |
<> | 144:ef7eb2e8f9f7 | 2232 | } |
<> | 144:ef7eb2e8f9f7 | 2233 | |
<> | 144:ef7eb2e8f9f7 | 2234 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2235 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 2236 | |
<> | 144:ef7eb2e8f9f7 | 2237 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2238 | { |
<> | 144:ef7eb2e8f9f7 | 2239 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2240 | } |
<> | 144:ef7eb2e8f9f7 | 2241 | } |
<> | 144:ef7eb2e8f9f7 | 2242 | } |
<> | 144:ef7eb2e8f9f7 | 2243 | |
<> | 144:ef7eb2e8f9f7 | 2244 | /** |
<> | 144:ef7eb2e8f9f7 | 2245 | * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2246 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2247 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2248 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2249 | */ |
<> | 144:ef7eb2e8f9f7 | 2250 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2251 | { |
<> | 144:ef7eb2e8f9f7 | 2252 | __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2253 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2254 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2255 | |
<> | 144:ef7eb2e8f9f7 | 2256 | hspi->CRCSize--; |
<> | 144:ef7eb2e8f9f7 | 2257 | |
<> | 144:ef7eb2e8f9f7 | 2258 | /* check end of the reception */ |
<> | 144:ef7eb2e8f9f7 | 2259 | if(hspi->CRCSize == 0) |
<> | 144:ef7eb2e8f9f7 | 2260 | { |
<> | 144:ef7eb2e8f9f7 | 2261 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2262 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 2263 | |
<> | 144:ef7eb2e8f9f7 | 2264 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2265 | { |
<> | 144:ef7eb2e8f9f7 | 2266 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2267 | } |
<> | 144:ef7eb2e8f9f7 | 2268 | } |
<> | 144:ef7eb2e8f9f7 | 2269 | } |
<> | 144:ef7eb2e8f9f7 | 2270 | |
<> | 144:ef7eb2e8f9f7 | 2271 | /** |
<> | 144:ef7eb2e8f9f7 | 2272 | * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2273 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2274 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2275 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2276 | */ |
<> | 144:ef7eb2e8f9f7 | 2277 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2278 | { |
<> | 144:ef7eb2e8f9f7 | 2279 | /* Transmit data in packing Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2280 | if(hspi->TxXferCount >= 2) |
<> | 144:ef7eb2e8f9f7 | 2281 | { |
<> | 144:ef7eb2e8f9f7 | 2282 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 2283 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2284 | hspi->TxXferCount -= 2; |
<> | 144:ef7eb2e8f9f7 | 2285 | } |
<> | 144:ef7eb2e8f9f7 | 2286 | /* Transmit data in 8 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2287 | else |
<> | 144:ef7eb2e8f9f7 | 2288 | { |
<> | 144:ef7eb2e8f9f7 | 2289 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 2290 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2291 | } |
<> | 144:ef7eb2e8f9f7 | 2292 | |
<> | 144:ef7eb2e8f9f7 | 2293 | /* check the end of the transmission */ |
<> | 144:ef7eb2e8f9f7 | 2294 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2295 | { |
<> | 144:ef7eb2e8f9f7 | 2296 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2297 | { |
<> | 144:ef7eb2e8f9f7 | 2298 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2299 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2300 | return; |
<> | 144:ef7eb2e8f9f7 | 2301 | } |
<> | 144:ef7eb2e8f9f7 | 2302 | /* Disable TXE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2303 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2304 | |
<> | 144:ef7eb2e8f9f7 | 2305 | if(hspi->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2306 | { |
<> | 144:ef7eb2e8f9f7 | 2307 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2308 | } |
<> | 144:ef7eb2e8f9f7 | 2309 | } |
<> | 144:ef7eb2e8f9f7 | 2310 | } |
<> | 144:ef7eb2e8f9f7 | 2311 | |
<> | 144:ef7eb2e8f9f7 | 2312 | /** |
<> | 144:ef7eb2e8f9f7 | 2313 | * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2314 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2315 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2316 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2317 | */ |
<> | 144:ef7eb2e8f9f7 | 2318 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2319 | { |
<> | 144:ef7eb2e8f9f7 | 2320 | /* Receive data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2321 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2322 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2323 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2324 | |
<> | 144:ef7eb2e8f9f7 | 2325 | if(hspi->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2326 | { |
<> | 144:ef7eb2e8f9f7 | 2327 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2328 | { |
<> | 144:ef7eb2e8f9f7 | 2329 | hspi->RxISR = SPI_2linesRxISR_16BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2330 | return; |
<> | 144:ef7eb2e8f9f7 | 2331 | } |
<> | 144:ef7eb2e8f9f7 | 2332 | |
<> | 144:ef7eb2e8f9f7 | 2333 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2334 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 2335 | |
<> | 144:ef7eb2e8f9f7 | 2336 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2337 | { |
<> | 144:ef7eb2e8f9f7 | 2338 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2339 | } |
<> | 144:ef7eb2e8f9f7 | 2340 | } |
<> | 144:ef7eb2e8f9f7 | 2341 | } |
<> | 144:ef7eb2e8f9f7 | 2342 | |
<> | 144:ef7eb2e8f9f7 | 2343 | /** |
<> | 144:ef7eb2e8f9f7 | 2344 | * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2345 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2346 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2347 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2348 | */ |
<> | 144:ef7eb2e8f9f7 | 2349 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2350 | { |
<> | 144:ef7eb2e8f9f7 | 2351 | /* Receive data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2352 | __IO uint16_t tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2353 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2354 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2355 | |
<> | 144:ef7eb2e8f9f7 | 2356 | /* Disable RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2357 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 2358 | |
<> | 144:ef7eb2e8f9f7 | 2359 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2360 | } |
<> | 144:ef7eb2e8f9f7 | 2361 | |
<> | 144:ef7eb2e8f9f7 | 2362 | /** |
<> | 144:ef7eb2e8f9f7 | 2363 | * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2364 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2365 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2366 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2367 | */ |
<> | 144:ef7eb2e8f9f7 | 2368 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2369 | { |
<> | 144:ef7eb2e8f9f7 | 2370 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2371 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 2372 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2373 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2374 | |
<> | 144:ef7eb2e8f9f7 | 2375 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2376 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2377 | { |
<> | 144:ef7eb2e8f9f7 | 2378 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2379 | { |
<> | 144:ef7eb2e8f9f7 | 2380 | SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); |
<> | 144:ef7eb2e8f9f7 | 2381 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2382 | return; |
<> | 144:ef7eb2e8f9f7 | 2383 | } |
<> | 144:ef7eb2e8f9f7 | 2384 | /* Disable TXE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2385 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
<> | 144:ef7eb2e8f9f7 | 2386 | |
<> | 144:ef7eb2e8f9f7 | 2387 | if(hspi->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2388 | { |
<> | 144:ef7eb2e8f9f7 | 2389 | SPI_CloseRxTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2390 | } |
<> | 144:ef7eb2e8f9f7 | 2391 | } |
<> | 144:ef7eb2e8f9f7 | 2392 | } |
<> | 144:ef7eb2e8f9f7 | 2393 | |
<> | 144:ef7eb2e8f9f7 | 2394 | /** |
<> | 144:ef7eb2e8f9f7 | 2395 | * @brief Manage the CRC 8-bit receive in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2396 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2397 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2398 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2399 | */ |
<> | 144:ef7eb2e8f9f7 | 2400 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2401 | { |
<> | 144:ef7eb2e8f9f7 | 2402 | __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2403 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2404 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2405 | |
<> | 144:ef7eb2e8f9f7 | 2406 | hspi->CRCSize--; |
<> | 144:ef7eb2e8f9f7 | 2407 | |
<> | 144:ef7eb2e8f9f7 | 2408 | if(hspi->CRCSize == 0) |
<> | 144:ef7eb2e8f9f7 | 2409 | { |
<> | 144:ef7eb2e8f9f7 | 2410 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2411 | } |
<> | 144:ef7eb2e8f9f7 | 2412 | } |
<> | 144:ef7eb2e8f9f7 | 2413 | |
<> | 144:ef7eb2e8f9f7 | 2414 | /** |
<> | 144:ef7eb2e8f9f7 | 2415 | * @brief Manage the receive 8-bit in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2416 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2417 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2418 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2419 | */ |
<> | 144:ef7eb2e8f9f7 | 2420 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2421 | { |
<> | 144:ef7eb2e8f9f7 | 2422 | *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2423 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2424 | |
<> | 144:ef7eb2e8f9f7 | 2425 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2426 | if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 2427 | { |
<> | 144:ef7eb2e8f9f7 | 2428 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 2429 | } |
<> | 144:ef7eb2e8f9f7 | 2430 | |
<> | 144:ef7eb2e8f9f7 | 2431 | if(hspi->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2432 | { |
<> | 144:ef7eb2e8f9f7 | 2433 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2434 | { |
<> | 144:ef7eb2e8f9f7 | 2435 | hspi->RxISR = SPI_RxISR_8BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2436 | return; |
<> | 144:ef7eb2e8f9f7 | 2437 | } |
<> | 144:ef7eb2e8f9f7 | 2438 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2439 | } |
<> | 144:ef7eb2e8f9f7 | 2440 | } |
<> | 144:ef7eb2e8f9f7 | 2441 | |
<> | 144:ef7eb2e8f9f7 | 2442 | /** |
<> | 144:ef7eb2e8f9f7 | 2443 | * @brief Manage the CRC 16-bit receive in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2444 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2445 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2446 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2447 | */ |
<> | 144:ef7eb2e8f9f7 | 2448 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2449 | { |
<> | 144:ef7eb2e8f9f7 | 2450 | __IO uint16_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 2451 | |
<> | 144:ef7eb2e8f9f7 | 2452 | tmpreg = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2453 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2454 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2455 | |
<> | 144:ef7eb2e8f9f7 | 2456 | /* Disable RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2457 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2458 | |
<> | 144:ef7eb2e8f9f7 | 2459 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2460 | } |
<> | 144:ef7eb2e8f9f7 | 2461 | |
<> | 144:ef7eb2e8f9f7 | 2462 | /** |
<> | 144:ef7eb2e8f9f7 | 2463 | * @brief Manage the 16-bit receive in Interrupt context. |
<> | 144:ef7eb2e8f9f7 | 2464 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2465 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2466 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2467 | */ |
<> | 144:ef7eb2e8f9f7 | 2468 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2469 | { |
<> | 144:ef7eb2e8f9f7 | 2470 | *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 2471 | hspi->pRxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2472 | hspi->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2473 | |
<> | 144:ef7eb2e8f9f7 | 2474 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2475 | if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 2476 | { |
<> | 144:ef7eb2e8f9f7 | 2477 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 2478 | } |
<> | 144:ef7eb2e8f9f7 | 2479 | |
<> | 144:ef7eb2e8f9f7 | 2480 | if(hspi->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2481 | { |
<> | 144:ef7eb2e8f9f7 | 2482 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2483 | { |
<> | 144:ef7eb2e8f9f7 | 2484 | hspi->RxISR = SPI_RxISR_16BITCRC; |
<> | 144:ef7eb2e8f9f7 | 2485 | return; |
<> | 144:ef7eb2e8f9f7 | 2486 | } |
<> | 144:ef7eb2e8f9f7 | 2487 | SPI_CloseRx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2488 | } |
<> | 144:ef7eb2e8f9f7 | 2489 | } |
<> | 144:ef7eb2e8f9f7 | 2490 | |
<> | 144:ef7eb2e8f9f7 | 2491 | /** |
<> | 144:ef7eb2e8f9f7 | 2492 | * @brief Handle the data 8-bit transmit in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2493 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2494 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2495 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2496 | */ |
<> | 144:ef7eb2e8f9f7 | 2497 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2498 | { |
<> | 144:ef7eb2e8f9f7 | 2499 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 2500 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2501 | |
<> | 144:ef7eb2e8f9f7 | 2502 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2503 | { |
<> | 144:ef7eb2e8f9f7 | 2504 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2505 | { |
<> | 144:ef7eb2e8f9f7 | 2506 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2507 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 2508 | } |
<> | 144:ef7eb2e8f9f7 | 2509 | SPI_CloseTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2510 | } |
<> | 144:ef7eb2e8f9f7 | 2511 | } |
<> | 144:ef7eb2e8f9f7 | 2512 | |
<> | 144:ef7eb2e8f9f7 | 2513 | /** |
<> | 144:ef7eb2e8f9f7 | 2514 | * @brief Handle the data 16-bit transmit in Interrupt mode. |
<> | 144:ef7eb2e8f9f7 | 2515 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2516 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2517 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2518 | */ |
<> | 144:ef7eb2e8f9f7 | 2519 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2520 | { |
<> | 144:ef7eb2e8f9f7 | 2521 | /* Transmit data in 16 Bit mode */ |
<> | 144:ef7eb2e8f9f7 | 2522 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
<> | 144:ef7eb2e8f9f7 | 2523 | hspi->pTxBuffPtr += sizeof(uint16_t); |
<> | 144:ef7eb2e8f9f7 | 2524 | hspi->TxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 2525 | |
<> | 144:ef7eb2e8f9f7 | 2526 | if(hspi->TxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 2527 | { |
<> | 144:ef7eb2e8f9f7 | 2528 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2529 | { |
<> | 144:ef7eb2e8f9f7 | 2530 | /* Enable CRC Transmission */ |
<> | 144:ef7eb2e8f9f7 | 2531 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
<> | 144:ef7eb2e8f9f7 | 2532 | } |
<> | 144:ef7eb2e8f9f7 | 2533 | SPI_CloseTx_ISR(hspi); |
<> | 144:ef7eb2e8f9f7 | 2534 | } |
<> | 144:ef7eb2e8f9f7 | 2535 | } |
<> | 144:ef7eb2e8f9f7 | 2536 | |
<> | 144:ef7eb2e8f9f7 | 2537 | /** |
<> | 144:ef7eb2e8f9f7 | 2538 | * @brief Handle SPI Communication Timeout. |
<> | 144:ef7eb2e8f9f7 | 2539 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2540 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2541 | * @param Flag : SPI flag to check |
<> | 144:ef7eb2e8f9f7 | 2542 | * @param State : flag state to check |
<> | 144:ef7eb2e8f9f7 | 2543 | * @param Timeout : Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2544 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2545 | */ |
<> | 144:ef7eb2e8f9f7 | 2546 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 2547 | { |
<> | 144:ef7eb2e8f9f7 | 2548 | uint32_t tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2549 | |
<> | 144:ef7eb2e8f9f7 | 2550 | while((hspi->Instance->SR & Flag) != State) |
<> | 144:ef7eb2e8f9f7 | 2551 | { |
<> | 144:ef7eb2e8f9f7 | 2552 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 2553 | { |
<> | 144:ef7eb2e8f9f7 | 2554 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 2555 | { |
<> | 144:ef7eb2e8f9f7 | 2556 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
<> | 144:ef7eb2e8f9f7 | 2557 | on both master and slave sides in order to resynchronize the master |
<> | 144:ef7eb2e8f9f7 | 2558 | and slave for their respective CRC calculation */ |
<> | 144:ef7eb2e8f9f7 | 2559 | |
<> | 144:ef7eb2e8f9f7 | 2560 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
<> | 144:ef7eb2e8f9f7 | 2561 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2562 | |
<> | 144:ef7eb2e8f9f7 | 2563 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 2564 | { |
<> | 144:ef7eb2e8f9f7 | 2565 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 2566 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 2567 | } |
<> | 144:ef7eb2e8f9f7 | 2568 | |
<> | 144:ef7eb2e8f9f7 | 2569 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 2570 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2571 | { |
<> | 144:ef7eb2e8f9f7 | 2572 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 2573 | } |
<> | 144:ef7eb2e8f9f7 | 2574 | |
<> | 144:ef7eb2e8f9f7 | 2575 | hspi->State= HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2576 | |
<> | 144:ef7eb2e8f9f7 | 2577 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2578 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 2579 | |
<> | 144:ef7eb2e8f9f7 | 2580 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2581 | } |
<> | 144:ef7eb2e8f9f7 | 2582 | } |
<> | 144:ef7eb2e8f9f7 | 2583 | } |
<> | 144:ef7eb2e8f9f7 | 2584 | |
<> | 144:ef7eb2e8f9f7 | 2585 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2586 | } |
<> | 144:ef7eb2e8f9f7 | 2587 | |
<> | 144:ef7eb2e8f9f7 | 2588 | /** |
<> | 144:ef7eb2e8f9f7 | 2589 | * @brief Handle SPI FIFO Communication Timeout. |
<> | 144:ef7eb2e8f9f7 | 2590 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2591 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2592 | * @param Fifo : Fifo to check |
<> | 144:ef7eb2e8f9f7 | 2593 | * @param State : Fifo state to check |
<> | 144:ef7eb2e8f9f7 | 2594 | * @param Timeout : Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2595 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2596 | */ |
<> | 144:ef7eb2e8f9f7 | 2597 | static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 2598 | { |
<> | 144:ef7eb2e8f9f7 | 2599 | __IO uint8_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 2600 | uint32_t tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2601 | |
<> | 144:ef7eb2e8f9f7 | 2602 | while((hspi->Instance->SR & Fifo) != State) |
<> | 144:ef7eb2e8f9f7 | 2603 | { |
<> | 144:ef7eb2e8f9f7 | 2604 | if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) |
<> | 144:ef7eb2e8f9f7 | 2605 | { |
<> | 144:ef7eb2e8f9f7 | 2606 | tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); |
<> | 144:ef7eb2e8f9f7 | 2607 | /* To avoid GCC warning */ |
<> | 144:ef7eb2e8f9f7 | 2608 | UNUSED(tmpreg); |
<> | 144:ef7eb2e8f9f7 | 2609 | } |
<> | 144:ef7eb2e8f9f7 | 2610 | |
<> | 144:ef7eb2e8f9f7 | 2611 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 2612 | { |
<> | 144:ef7eb2e8f9f7 | 2613 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) |
<> | 144:ef7eb2e8f9f7 | 2614 | { |
<> | 144:ef7eb2e8f9f7 | 2615 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
<> | 144:ef7eb2e8f9f7 | 2616 | on both master and slave sides in order to resynchronize the master |
<> | 144:ef7eb2e8f9f7 | 2617 | and slave for their respective CRC calculation */ |
<> | 144:ef7eb2e8f9f7 | 2618 | |
<> | 144:ef7eb2e8f9f7 | 2619 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
<> | 144:ef7eb2e8f9f7 | 2620 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2621 | |
<> | 144:ef7eb2e8f9f7 | 2622 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 2623 | { |
<> | 144:ef7eb2e8f9f7 | 2624 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 2625 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 2626 | } |
<> | 144:ef7eb2e8f9f7 | 2627 | |
<> | 144:ef7eb2e8f9f7 | 2628 | /* Reset CRC Calculation */ |
<> | 144:ef7eb2e8f9f7 | 2629 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 2630 | { |
<> | 144:ef7eb2e8f9f7 | 2631 | SPI_RESET_CRC(hspi); |
<> | 144:ef7eb2e8f9f7 | 2632 | } |
<> | 144:ef7eb2e8f9f7 | 2633 | |
<> | 144:ef7eb2e8f9f7 | 2634 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2635 | |
<> | 144:ef7eb2e8f9f7 | 2636 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2637 | __HAL_UNLOCK(hspi); |
<> | 144:ef7eb2e8f9f7 | 2638 | |
<> | 144:ef7eb2e8f9f7 | 2639 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2640 | } |
<> | 144:ef7eb2e8f9f7 | 2641 | } |
<> | 144:ef7eb2e8f9f7 | 2642 | } |
<> | 144:ef7eb2e8f9f7 | 2643 | |
<> | 144:ef7eb2e8f9f7 | 2644 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2645 | } |
<> | 144:ef7eb2e8f9f7 | 2646 | |
<> | 144:ef7eb2e8f9f7 | 2647 | /** |
<> | 144:ef7eb2e8f9f7 | 2648 | * @brief Handle the check of the RX transaction complete. |
<> | 144:ef7eb2e8f9f7 | 2649 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2650 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2651 | * @param Timeout : Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2652 | * @retval None. |
<> | 144:ef7eb2e8f9f7 | 2653 | */ |
<> | 144:ef7eb2e8f9f7 | 2654 | static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 2655 | { |
<> | 144:ef7eb2e8f9f7 | 2656 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 2657 | { |
<> | 144:ef7eb2e8f9f7 | 2658 | /* Disable SPI peripheral */ |
<> | 144:ef7eb2e8f9f7 | 2659 | __HAL_SPI_DISABLE(hspi); |
<> | 144:ef7eb2e8f9f7 | 2660 | } |
<> | 144:ef7eb2e8f9f7 | 2661 | |
<> | 144:ef7eb2e8f9f7 | 2662 | /* Control the BSY flag */ |
<> | 144:ef7eb2e8f9f7 | 2663 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2664 | { |
<> | 144:ef7eb2e8f9f7 | 2665 | hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2666 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2667 | } |
<> | 144:ef7eb2e8f9f7 | 2668 | |
<> | 144:ef7eb2e8f9f7 | 2669 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
<> | 144:ef7eb2e8f9f7 | 2670 | { |
<> | 144:ef7eb2e8f9f7 | 2671 | /* Empty the FRLVL fifo */ |
<> | 144:ef7eb2e8f9f7 | 2672 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2673 | { |
<> | 144:ef7eb2e8f9f7 | 2674 | hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2675 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2676 | } |
<> | 144:ef7eb2e8f9f7 | 2677 | } |
<> | 144:ef7eb2e8f9f7 | 2678 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2679 | } |
<> | 144:ef7eb2e8f9f7 | 2680 | |
<> | 144:ef7eb2e8f9f7 | 2681 | /** |
<> | 144:ef7eb2e8f9f7 | 2682 | * @brief Handle the check of the RXTX or TX transaction complete. |
<> | 144:ef7eb2e8f9f7 | 2683 | * @param hspi: SPI handle |
<> | 144:ef7eb2e8f9f7 | 2684 | * @param Timeout : Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2685 | */ |
<> | 144:ef7eb2e8f9f7 | 2686 | static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 2687 | { |
<> | 144:ef7eb2e8f9f7 | 2688 | /* Control if the TX fifo is empty */ |
<> | 144:ef7eb2e8f9f7 | 2689 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2690 | { |
<> | 144:ef7eb2e8f9f7 | 2691 | hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2692 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2693 | } |
<> | 144:ef7eb2e8f9f7 | 2694 | /* Control the BSY flag */ |
<> | 144:ef7eb2e8f9f7 | 2695 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2696 | { |
<> | 144:ef7eb2e8f9f7 | 2697 | hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2698 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2699 | } |
<> | 144:ef7eb2e8f9f7 | 2700 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2701 | } |
<> | 144:ef7eb2e8f9f7 | 2702 | |
<> | 144:ef7eb2e8f9f7 | 2703 | /** |
<> | 144:ef7eb2e8f9f7 | 2704 | * @brief Handle the end of the RXTX transaction. |
<> | 144:ef7eb2e8f9f7 | 2705 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2706 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2707 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2708 | */ |
<> | 144:ef7eb2e8f9f7 | 2709 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2710 | { |
<> | 144:ef7eb2e8f9f7 | 2711 | /* Disable ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2712 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); |
<> | 144:ef7eb2e8f9f7 | 2713 | |
<> | 144:ef7eb2e8f9f7 | 2714 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2715 | if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2716 | { |
<> | 144:ef7eb2e8f9f7 | 2717 | hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2718 | } |
<> | 144:ef7eb2e8f9f7 | 2719 | |
<> | 144:ef7eb2e8f9f7 | 2720 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2721 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2722 | { |
<> | 144:ef7eb2e8f9f7 | 2723 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2724 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2725 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2726 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2727 | } |
<> | 144:ef7eb2e8f9f7 | 2728 | else |
<> | 144:ef7eb2e8f9f7 | 2729 | { |
<> | 144:ef7eb2e8f9f7 | 2730 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2731 | { |
<> | 144:ef7eb2e8f9f7 | 2732 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 2733 | { |
<> | 144:ef7eb2e8f9f7 | 2734 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2735 | HAL_SPI_RxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2736 | } |
<> | 144:ef7eb2e8f9f7 | 2737 | else |
<> | 144:ef7eb2e8f9f7 | 2738 | { |
<> | 144:ef7eb2e8f9f7 | 2739 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2740 | HAL_SPI_TxRxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2741 | } |
<> | 144:ef7eb2e8f9f7 | 2742 | } |
<> | 144:ef7eb2e8f9f7 | 2743 | else |
<> | 144:ef7eb2e8f9f7 | 2744 | { |
<> | 144:ef7eb2e8f9f7 | 2745 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2746 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2747 | } |
<> | 144:ef7eb2e8f9f7 | 2748 | } |
<> | 144:ef7eb2e8f9f7 | 2749 | } |
<> | 144:ef7eb2e8f9f7 | 2750 | |
<> | 144:ef7eb2e8f9f7 | 2751 | /** |
<> | 144:ef7eb2e8f9f7 | 2752 | * @brief Handle the end of the RX transaction. |
<> | 144:ef7eb2e8f9f7 | 2753 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2754 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2755 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2756 | */ |
<> | 144:ef7eb2e8f9f7 | 2757 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2758 | { |
<> | 144:ef7eb2e8f9f7 | 2759 | /* Disable RXNE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2760 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2761 | |
<> | 144:ef7eb2e8f9f7 | 2762 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2763 | if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2764 | { |
<> | 144:ef7eb2e8f9f7 | 2765 | hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2766 | } |
<> | 144:ef7eb2e8f9f7 | 2767 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2768 | |
<> | 144:ef7eb2e8f9f7 | 2769 | /* Check if CRC error occurred */ |
<> | 144:ef7eb2e8f9f7 | 2770 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2771 | { |
<> | 144:ef7eb2e8f9f7 | 2772 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
<> | 144:ef7eb2e8f9f7 | 2773 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2774 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2775 | } |
<> | 144:ef7eb2e8f9f7 | 2776 | else |
<> | 144:ef7eb2e8f9f7 | 2777 | { |
<> | 144:ef7eb2e8f9f7 | 2778 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2779 | { |
<> | 144:ef7eb2e8f9f7 | 2780 | HAL_SPI_RxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2781 | } |
<> | 144:ef7eb2e8f9f7 | 2782 | else |
<> | 144:ef7eb2e8f9f7 | 2783 | { |
<> | 144:ef7eb2e8f9f7 | 2784 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2785 | } |
<> | 144:ef7eb2e8f9f7 | 2786 | } |
<> | 144:ef7eb2e8f9f7 | 2787 | } |
<> | 144:ef7eb2e8f9f7 | 2788 | |
<> | 144:ef7eb2e8f9f7 | 2789 | /** |
<> | 144:ef7eb2e8f9f7 | 2790 | * @brief Handle the end of the TX transaction. |
<> | 144:ef7eb2e8f9f7 | 2791 | * @param hspi: pointer to a SPI_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2792 | * the configuration information for SPI module. |
<> | 144:ef7eb2e8f9f7 | 2793 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2794 | */ |
<> | 144:ef7eb2e8f9f7 | 2795 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) |
<> | 144:ef7eb2e8f9f7 | 2796 | { |
<> | 144:ef7eb2e8f9f7 | 2797 | /* Disable TXE and ERR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2798 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); |
<> | 144:ef7eb2e8f9f7 | 2799 | |
<> | 144:ef7eb2e8f9f7 | 2800 | /* Check the end of the transaction */ |
<> | 144:ef7eb2e8f9f7 | 2801 | if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2802 | { |
<> | 144:ef7eb2e8f9f7 | 2803 | hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; |
<> | 144:ef7eb2e8f9f7 | 2804 | } |
<> | 144:ef7eb2e8f9f7 | 2805 | |
<> | 144:ef7eb2e8f9f7 | 2806 | /* Clear overrun flag in 2 Lines communication mode because received is not read */ |
<> | 144:ef7eb2e8f9f7 | 2807 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
<> | 144:ef7eb2e8f9f7 | 2808 | { |
<> | 144:ef7eb2e8f9f7 | 2809 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
<> | 144:ef7eb2e8f9f7 | 2810 | } |
<> | 144:ef7eb2e8f9f7 | 2811 | |
<> | 144:ef7eb2e8f9f7 | 2812 | hspi->State = HAL_SPI_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2813 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 2814 | { |
<> | 144:ef7eb2e8f9f7 | 2815 | HAL_SPI_ErrorCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2816 | } |
<> | 144:ef7eb2e8f9f7 | 2817 | else |
<> | 144:ef7eb2e8f9f7 | 2818 | { |
<> | 144:ef7eb2e8f9f7 | 2819 | HAL_SPI_TxCpltCallback(hspi); |
<> | 144:ef7eb2e8f9f7 | 2820 | } |
<> | 144:ef7eb2e8f9f7 | 2821 | } |
<> | 144:ef7eb2e8f9f7 | 2822 | |
<> | 144:ef7eb2e8f9f7 | 2823 | /** |
<> | 144:ef7eb2e8f9f7 | 2824 | * @} |
<> | 144:ef7eb2e8f9f7 | 2825 | */ |
<> | 144:ef7eb2e8f9f7 | 2826 | |
<> | 144:ef7eb2e8f9f7 | 2827 | #endif /* HAL_SPI_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 2828 | |
<> | 144:ef7eb2e8f9f7 | 2829 | /** |
<> | 144:ef7eb2e8f9f7 | 2830 | * @} |
<> | 144:ef7eb2e8f9f7 | 2831 | */ |
<> | 144:ef7eb2e8f9f7 | 2832 | |
<> | 144:ef7eb2e8f9f7 | 2833 | /** |
<> | 144:ef7eb2e8f9f7 | 2834 | * @} |
<> | 144:ef7eb2e8f9f7 | 2835 | */ |
<> | 144:ef7eb2e8f9f7 | 2836 | |
<> | 144:ef7eb2e8f9f7 | 2837 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |