MBED-DEV only fro Nucleo STM32F303K8T6
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.h@151:acf04f8e7d03, 2016-11-19 (annotated)
- Committer:
- pravinautosys
- Date:
- Sat Nov 19 10:38:54 2016 +0000
- Revision:
- 151:acf04f8e7d03
- Parent:
- 149:156823d33999
MyMBED-DEVWithSTM32F303K8T6;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f3xx_hal_rcc.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.3.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 01-July-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief Header file of RCC HAL module. |
<> | 144:ef7eb2e8f9f7 | 8 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 9 | * @attention |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 19 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 21 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 22 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 36 | */ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 39 | #ifndef __STM32F3xx_HAL_RCC_H |
<> | 144:ef7eb2e8f9f7 | 40 | #define __STM32F3xx_HAL_RCC_H |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 43 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 47 | #include "stm32f3xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 50 | * @{ |
<> | 144:ef7eb2e8f9f7 | 51 | */ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /** @addtogroup RCC |
<> | 144:ef7eb2e8f9f7 | 54 | * @{ |
<> | 144:ef7eb2e8f9f7 | 55 | */ |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | /** @addtogroup RCC_Private_Constants |
<> | 144:ef7eb2e8f9f7 | 58 | * @{ |
<> | 144:ef7eb2e8f9f7 | 59 | */ |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | /** @defgroup RCC_Timeout RCC Timeout |
<> | 144:ef7eb2e8f9f7 | 62 | * @{ |
<> | 144:ef7eb2e8f9f7 | 63 | */ |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | /* Disable Backup domain write protection state change timeout */ |
<> | 144:ef7eb2e8f9f7 | 66 | #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ |
<> | 144:ef7eb2e8f9f7 | 67 | /* LSE state change timeout */ |
<> | 144:ef7eb2e8f9f7 | 68 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
<> | 144:ef7eb2e8f9f7 | 69 | #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ |
<> | 144:ef7eb2e8f9f7 | 70 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
<> | 144:ef7eb2e8f9f7 | 71 | #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ |
<> | 144:ef7eb2e8f9f7 | 72 | #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ |
<> | 144:ef7eb2e8f9f7 | 73 | #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ |
<> | 144:ef7eb2e8f9f7 | 74 | /** |
<> | 144:ef7eb2e8f9f7 | 75 | * @} |
<> | 144:ef7eb2e8f9f7 | 76 | */ |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | /** @defgroup RCC_Register_Offset Register offsets |
<> | 144:ef7eb2e8f9f7 | 79 | * @{ |
<> | 144:ef7eb2e8f9f7 | 80 | */ |
<> | 144:ef7eb2e8f9f7 | 81 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
<> | 144:ef7eb2e8f9f7 | 82 | #define RCC_CR_OFFSET 0x00 |
<> | 144:ef7eb2e8f9f7 | 83 | #define RCC_CFGR_OFFSET 0x04 |
<> | 144:ef7eb2e8f9f7 | 84 | #define RCC_CIR_OFFSET 0x08 |
<> | 144:ef7eb2e8f9f7 | 85 | #define RCC_BDCR_OFFSET 0x20 |
<> | 144:ef7eb2e8f9f7 | 86 | #define RCC_CSR_OFFSET 0x24 |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | /** |
<> | 144:ef7eb2e8f9f7 | 89 | * @} |
<> | 144:ef7eb2e8f9f7 | 90 | */ |
<> | 144:ef7eb2e8f9f7 | 91 | |
<> | 144:ef7eb2e8f9f7 | 92 | /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion |
<> | 144:ef7eb2e8f9f7 | 93 | * @brief RCC registers bit address in the alias region |
<> | 144:ef7eb2e8f9f7 | 94 | * @{ |
<> | 144:ef7eb2e8f9f7 | 95 | */ |
<> | 144:ef7eb2e8f9f7 | 96 | #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 97 | #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 98 | #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 99 | #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 100 | #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | /* --- CR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 103 | /* Alias word address of HSION bit */ |
<> | 144:ef7eb2e8f9f7 | 104 | #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) |
<> | 144:ef7eb2e8f9f7 | 105 | #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 106 | /* Alias word address of HSEON bit */ |
<> | 144:ef7eb2e8f9f7 | 107 | #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) |
<> | 144:ef7eb2e8f9f7 | 108 | #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 109 | /* Alias word address of CSSON bit */ |
<> | 144:ef7eb2e8f9f7 | 110 | #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) |
<> | 144:ef7eb2e8f9f7 | 111 | #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 112 | /* Alias word address of PLLON bit */ |
<> | 144:ef7eb2e8f9f7 | 113 | #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) |
<> | 144:ef7eb2e8f9f7 | 114 | #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | /* --- CSR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 117 | /* Alias word address of LSION bit */ |
<> | 144:ef7eb2e8f9f7 | 118 | #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) |
<> | 144:ef7eb2e8f9f7 | 119 | #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | /* Alias word address of RMVF bit */ |
<> | 144:ef7eb2e8f9f7 | 122 | #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) |
<> | 144:ef7eb2e8f9f7 | 123 | #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | /* --- BDCR Registers ---*/ |
<> | 144:ef7eb2e8f9f7 | 126 | /* Alias word address of LSEON bit */ |
<> | 144:ef7eb2e8f9f7 | 127 | #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) |
<> | 144:ef7eb2e8f9f7 | 128 | #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | /* Alias word address of LSEON bit */ |
<> | 144:ef7eb2e8f9f7 | 131 | #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) |
<> | 144:ef7eb2e8f9f7 | 132 | #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | /* Alias word address of RTCEN bit */ |
<> | 144:ef7eb2e8f9f7 | 135 | #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) |
<> | 144:ef7eb2e8f9f7 | 136 | #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | /* Alias word address of BDRST bit */ |
<> | 144:ef7eb2e8f9f7 | 139 | #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) |
<> | 144:ef7eb2e8f9f7 | 140 | #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4))) |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | /** |
<> | 144:ef7eb2e8f9f7 | 143 | * @} |
<> | 144:ef7eb2e8f9f7 | 144 | */ |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | /* CR register byte 2 (Bits[23:16]) base address */ |
<> | 144:ef7eb2e8f9f7 | 147 | #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | /* CIR register byte 1 (Bits[15:8]) base address */ |
<> | 144:ef7eb2e8f9f7 | 150 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | /* CIR register byte 2 (Bits[23:16]) base address */ |
<> | 144:ef7eb2e8f9f7 | 153 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /* Defines used for Flags */ |
<> | 144:ef7eb2e8f9f7 | 156 | #define CR_REG_INDEX ((uint8_t)1) |
<> | 144:ef7eb2e8f9f7 | 157 | #define BDCR_REG_INDEX ((uint8_t)2) |
<> | 144:ef7eb2e8f9f7 | 158 | #define CSR_REG_INDEX ((uint8_t)3) |
<> | 144:ef7eb2e8f9f7 | 159 | #define CFGR_REG_INDEX ((uint8_t)4) |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | /** |
<> | 144:ef7eb2e8f9f7 | 164 | * @} |
<> | 144:ef7eb2e8f9f7 | 165 | */ |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | /** @addtogroup RCC_Private_Macros |
<> | 144:ef7eb2e8f9f7 | 168 | * @{ |
<> | 144:ef7eb2e8f9f7 | 169 | */ |
<> | 144:ef7eb2e8f9f7 | 170 | #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ |
<> | 144:ef7eb2e8f9f7 | 171 | ((__SOURCE__) == RCC_PLLSOURCE_HSE)) |
<> | 144:ef7eb2e8f9f7 | 172 | #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ |
<> | 144:ef7eb2e8f9f7 | 173 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
<> | 144:ef7eb2e8f9f7 | 174 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
<> | 144:ef7eb2e8f9f7 | 175 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
<> | 144:ef7eb2e8f9f7 | 176 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
<> | 144:ef7eb2e8f9f7 | 177 | #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ |
<> | 144:ef7eb2e8f9f7 | 178 | ((__HSE__) == RCC_HSE_BYPASS)) |
<> | 144:ef7eb2e8f9f7 | 179 | #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ |
<> | 144:ef7eb2e8f9f7 | 180 | ((__LSE__) == RCC_LSE_BYPASS)) |
<> | 144:ef7eb2e8f9f7 | 181 | #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) |
<> | 144:ef7eb2e8f9f7 | 182 | #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) |
<> | 144:ef7eb2e8f9f7 | 183 | #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) |
<> | 144:ef7eb2e8f9f7 | 184 | #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ |
<> | 144:ef7eb2e8f9f7 | 185 | ((__PLL__) == RCC_PLL_ON)) |
<> | 144:ef7eb2e8f9f7 | 186 | #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) |
<> | 144:ef7eb2e8f9f7 | 187 | #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ |
<> | 144:ef7eb2e8f9f7 | 188 | ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ |
<> | 144:ef7eb2e8f9f7 | 189 | ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ |
<> | 144:ef7eb2e8f9f7 | 190 | ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ |
<> | 144:ef7eb2e8f9f7 | 191 | ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ |
<> | 144:ef7eb2e8f9f7 | 192 | ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ |
<> | 144:ef7eb2e8f9f7 | 193 | ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ |
<> | 144:ef7eb2e8f9f7 | 194 | ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) |
<> | 144:ef7eb2e8f9f7 | 195 | #else |
<> | 144:ef7eb2e8f9f7 | 196 | #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ |
<> | 144:ef7eb2e8f9f7 | 197 | ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) |
<> | 144:ef7eb2e8f9f7 | 198 | #endif |
<> | 144:ef7eb2e8f9f7 | 199 | #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) |
<> | 144:ef7eb2e8f9f7 | 200 | #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \ |
<> | 144:ef7eb2e8f9f7 | 201 | ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \ |
<> | 144:ef7eb2e8f9f7 | 202 | ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \ |
<> | 144:ef7eb2e8f9f7 | 203 | ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \ |
<> | 144:ef7eb2e8f9f7 | 204 | ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \ |
<> | 144:ef7eb2e8f9f7 | 205 | ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \ |
<> | 144:ef7eb2e8f9f7 | 206 | ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \ |
<> | 144:ef7eb2e8f9f7 | 207 | ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16)) |
<> | 144:ef7eb2e8f9f7 | 208 | #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ |
<> | 144:ef7eb2e8f9f7 | 209 | |
<> | 144:ef7eb2e8f9f7 | 210 | #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ |
<> | 144:ef7eb2e8f9f7 | 211 | ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ |
<> | 144:ef7eb2e8f9f7 | 212 | ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ |
<> | 144:ef7eb2e8f9f7 | 213 | ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ |
<> | 144:ef7eb2e8f9f7 | 214 | ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ |
<> | 144:ef7eb2e8f9f7 | 215 | ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ |
<> | 144:ef7eb2e8f9f7 | 216 | ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ |
<> | 144:ef7eb2e8f9f7 | 217 | ((__MUL__) == RCC_PLL_MUL16)) |
<> | 144:ef7eb2e8f9f7 | 218 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
<> | 144:ef7eb2e8f9f7 | 219 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
<> | 144:ef7eb2e8f9f7 | 220 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ |
<> | 144:ef7eb2e8f9f7 | 221 | (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) |
<> | 144:ef7eb2e8f9f7 | 222 | #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ |
<> | 144:ef7eb2e8f9f7 | 223 | ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ |
<> | 144:ef7eb2e8f9f7 | 224 | ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) |
<> | 144:ef7eb2e8f9f7 | 225 | #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
<> | 144:ef7eb2e8f9f7 | 226 | ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
<> | 144:ef7eb2e8f9f7 | 227 | ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) |
<> | 144:ef7eb2e8f9f7 | 228 | #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ |
<> | 144:ef7eb2e8f9f7 | 229 | ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ |
<> | 144:ef7eb2e8f9f7 | 230 | ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ |
<> | 144:ef7eb2e8f9f7 | 231 | ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ |
<> | 144:ef7eb2e8f9f7 | 232 | ((__HCLK__) == RCC_SYSCLK_DIV512)) |
<> | 144:ef7eb2e8f9f7 | 233 | #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ |
<> | 144:ef7eb2e8f9f7 | 234 | ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ |
<> | 144:ef7eb2e8f9f7 | 235 | ((__PCLK__) == RCC_HCLK_DIV16)) |
<> | 144:ef7eb2e8f9f7 | 236 | #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) |
<> | 144:ef7eb2e8f9f7 | 237 | #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ |
<> | 144:ef7eb2e8f9f7 | 238 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ |
<> | 144:ef7eb2e8f9f7 | 239 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ |
<> | 144:ef7eb2e8f9f7 | 240 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) |
<> | 144:ef7eb2e8f9f7 | 241 | #if defined(RCC_CFGR3_USART2SW) |
<> | 144:ef7eb2e8f9f7 | 242 | #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ |
<> | 144:ef7eb2e8f9f7 | 243 | ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
<> | 144:ef7eb2e8f9f7 | 244 | ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ |
<> | 144:ef7eb2e8f9f7 | 245 | ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) |
<> | 144:ef7eb2e8f9f7 | 246 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 144:ef7eb2e8f9f7 | 247 | #if defined(RCC_CFGR3_USART3SW) |
<> | 144:ef7eb2e8f9f7 | 248 | #define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ |
<> | 144:ef7eb2e8f9f7 | 249 | ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
<> | 144:ef7eb2e8f9f7 | 250 | ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ |
<> | 144:ef7eb2e8f9f7 | 251 | ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) |
<> | 144:ef7eb2e8f9f7 | 252 | #endif /* RCC_CFGR3_USART3SW */ |
<> | 144:ef7eb2e8f9f7 | 253 | #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ |
<> | 144:ef7eb2e8f9f7 | 254 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | /** |
<> | 144:ef7eb2e8f9f7 | 257 | * @} |
<> | 144:ef7eb2e8f9f7 | 258 | */ |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | /** @defgroup RCC_Exported_Types RCC Exported Types |
<> | 144:ef7eb2e8f9f7 | 263 | * @{ |
<> | 144:ef7eb2e8f9f7 | 264 | */ |
<> | 144:ef7eb2e8f9f7 | 265 | |
<> | 144:ef7eb2e8f9f7 | 266 | /** |
<> | 144:ef7eb2e8f9f7 | 267 | * @brief RCC PLL configuration structure definition |
<> | 144:ef7eb2e8f9f7 | 268 | */ |
<> | 144:ef7eb2e8f9f7 | 269 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 270 | { |
<> | 144:ef7eb2e8f9f7 | 271 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
<> | 144:ef7eb2e8f9f7 | 272 | This parameter can be a value of @ref RCC_PLL_Config */ |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
<> | 144:ef7eb2e8f9f7 | 275 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
<> | 144:ef7eb2e8f9f7 | 278 | This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ |
<> | 144:ef7eb2e8f9f7 | 279 | |
<> | 144:ef7eb2e8f9f7 | 280 | #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) |
<> | 144:ef7eb2e8f9f7 | 281 | uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock |
<> | 144:ef7eb2e8f9f7 | 282 | This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | #endif |
<> | 144:ef7eb2e8f9f7 | 285 | } RCC_PLLInitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 286 | |
<> | 144:ef7eb2e8f9f7 | 287 | /** |
<> | 144:ef7eb2e8f9f7 | 288 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
<> | 144:ef7eb2e8f9f7 | 289 | */ |
<> | 144:ef7eb2e8f9f7 | 290 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 291 | { |
<> | 144:ef7eb2e8f9f7 | 292 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
<> | 144:ef7eb2e8f9f7 | 293 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | uint32_t HSEState; /*!< The new state of the HSE. |
<> | 144:ef7eb2e8f9f7 | 296 | This parameter can be a value of @ref RCC_HSE_Config */ |
<> | 144:ef7eb2e8f9f7 | 297 | |
<> | 144:ef7eb2e8f9f7 | 298 | #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) |
<> | 144:ef7eb2e8f9f7 | 299 | uint32_t HSEPredivValue; /*!< The HSE predivision factor value. |
<> | 144:ef7eb2e8f9f7 | 300 | This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */ |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ |
<> | 144:ef7eb2e8f9f7 | 303 | uint32_t LSEState; /*!< The new state of the LSE. |
<> | 144:ef7eb2e8f9f7 | 304 | This parameter can be a value of @ref RCC_LSE_Config */ |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | uint32_t HSIState; /*!< The new state of the HSI. |
<> | 144:ef7eb2e8f9f7 | 307 | This parameter can be a value of @ref RCC_HSI_Config */ |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
<> | 144:ef7eb2e8f9f7 | 310 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
<> | 144:ef7eb2e8f9f7 | 311 | |
<> | 144:ef7eb2e8f9f7 | 312 | uint32_t LSIState; /*!< The new state of the LSI. |
<> | 144:ef7eb2e8f9f7 | 313 | This parameter can be a value of @ref RCC_LSI_Config */ |
<> | 144:ef7eb2e8f9f7 | 314 | |
<> | 144:ef7eb2e8f9f7 | 315 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
<> | 144:ef7eb2e8f9f7 | 316 | |
<> | 144:ef7eb2e8f9f7 | 317 | } RCC_OscInitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 318 | |
<> | 144:ef7eb2e8f9f7 | 319 | /** |
<> | 144:ef7eb2e8f9f7 | 320 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
<> | 144:ef7eb2e8f9f7 | 321 | */ |
<> | 144:ef7eb2e8f9f7 | 322 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 323 | { |
<> | 144:ef7eb2e8f9f7 | 324 | uint32_t ClockType; /*!< The clock to be configured. |
<> | 144:ef7eb2e8f9f7 | 325 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
<> | 144:ef7eb2e8f9f7 | 328 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
<> | 144:ef7eb2e8f9f7 | 331 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
<> | 144:ef7eb2e8f9f7 | 332 | |
<> | 144:ef7eb2e8f9f7 | 333 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
<> | 144:ef7eb2e8f9f7 | 334 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
<> | 144:ef7eb2e8f9f7 | 337 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
<> | 144:ef7eb2e8f9f7 | 338 | } RCC_ClkInitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /** |
<> | 144:ef7eb2e8f9f7 | 341 | * @} |
<> | 144:ef7eb2e8f9f7 | 342 | */ |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 345 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
<> | 144:ef7eb2e8f9f7 | 346 | * @{ |
<> | 144:ef7eb2e8f9f7 | 347 | */ |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
<> | 144:ef7eb2e8f9f7 | 350 | * @{ |
<> | 144:ef7eb2e8f9f7 | 351 | */ |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) |
<> | 144:ef7eb2e8f9f7 | 354 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */ |
<> | 144:ef7eb2e8f9f7 | 355 | #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ |
<> | 144:ef7eb2e8f9f7 | 356 | #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) |
<> | 144:ef7eb2e8f9f7 | 357 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
<> | 144:ef7eb2e8f9f7 | 358 | #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ |
<> | 144:ef7eb2e8f9f7 | 359 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ |
<> | 144:ef7eb2e8f9f7 | 360 | |
<> | 144:ef7eb2e8f9f7 | 361 | /** |
<> | 144:ef7eb2e8f9f7 | 362 | * @} |
<> | 144:ef7eb2e8f9f7 | 363 | */ |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
<> | 144:ef7eb2e8f9f7 | 366 | * @{ |
<> | 144:ef7eb2e8f9f7 | 367 | */ |
<> | 144:ef7eb2e8f9f7 | 368 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 369 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) |
<> | 144:ef7eb2e8f9f7 | 370 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) |
<> | 144:ef7eb2e8f9f7 | 371 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) |
<> | 144:ef7eb2e8f9f7 | 372 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) |
<> | 144:ef7eb2e8f9f7 | 373 | /** |
<> | 144:ef7eb2e8f9f7 | 374 | * @} |
<> | 144:ef7eb2e8f9f7 | 375 | */ |
<> | 144:ef7eb2e8f9f7 | 376 | |
<> | 144:ef7eb2e8f9f7 | 377 | /** @defgroup RCC_HSE_Config HSE Config |
<> | 144:ef7eb2e8f9f7 | 378 | * @{ |
<> | 144:ef7eb2e8f9f7 | 379 | */ |
<> | 144:ef7eb2e8f9f7 | 380 | #define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ |
<> | 144:ef7eb2e8f9f7 | 381 | #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ |
<> | 144:ef7eb2e8f9f7 | 382 | #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ |
<> | 144:ef7eb2e8f9f7 | 383 | /** |
<> | 144:ef7eb2e8f9f7 | 384 | * @} |
<> | 144:ef7eb2e8f9f7 | 385 | */ |
<> | 144:ef7eb2e8f9f7 | 386 | |
<> | 144:ef7eb2e8f9f7 | 387 | /** @defgroup RCC_LSE_Config LSE Config |
<> | 144:ef7eb2e8f9f7 | 388 | * @{ |
<> | 144:ef7eb2e8f9f7 | 389 | */ |
<> | 144:ef7eb2e8f9f7 | 390 | #define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ |
<> | 144:ef7eb2e8f9f7 | 391 | #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ |
<> | 144:ef7eb2e8f9f7 | 392 | #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ |
<> | 144:ef7eb2e8f9f7 | 393 | |
<> | 144:ef7eb2e8f9f7 | 394 | /** |
<> | 144:ef7eb2e8f9f7 | 395 | * @} |
<> | 144:ef7eb2e8f9f7 | 396 | */ |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | /** @defgroup RCC_HSI_Config HSI Config |
<> | 144:ef7eb2e8f9f7 | 399 | * @{ |
<> | 144:ef7eb2e8f9f7 | 400 | */ |
<> | 144:ef7eb2e8f9f7 | 401 | #define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ |
<> | 144:ef7eb2e8f9f7 | 402 | #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ |
<> | 144:ef7eb2e8f9f7 | 405 | |
<> | 144:ef7eb2e8f9f7 | 406 | /** |
<> | 144:ef7eb2e8f9f7 | 407 | * @} |
<> | 144:ef7eb2e8f9f7 | 408 | */ |
<> | 144:ef7eb2e8f9f7 | 409 | |
<> | 144:ef7eb2e8f9f7 | 410 | /** @defgroup RCC_LSI_Config LSI Config |
<> | 144:ef7eb2e8f9f7 | 411 | * @{ |
<> | 144:ef7eb2e8f9f7 | 412 | */ |
<> | 144:ef7eb2e8f9f7 | 413 | #define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ |
<> | 144:ef7eb2e8f9f7 | 414 | #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ |
<> | 144:ef7eb2e8f9f7 | 415 | |
<> | 144:ef7eb2e8f9f7 | 416 | /** |
<> | 144:ef7eb2e8f9f7 | 417 | * @} |
<> | 144:ef7eb2e8f9f7 | 418 | */ |
<> | 144:ef7eb2e8f9f7 | 419 | |
<> | 144:ef7eb2e8f9f7 | 420 | /** @defgroup RCC_PLL_Config PLL Config |
<> | 144:ef7eb2e8f9f7 | 421 | * @{ |
<> | 144:ef7eb2e8f9f7 | 422 | */ |
<> | 144:ef7eb2e8f9f7 | 423 | #define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ |
<> | 144:ef7eb2e8f9f7 | 424 | #define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ |
<> | 144:ef7eb2e8f9f7 | 425 | #define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | /** |
<> | 144:ef7eb2e8f9f7 | 428 | * @} |
<> | 144:ef7eb2e8f9f7 | 429 | */ |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | /** @defgroup RCC_System_Clock_Type System Clock Type |
<> | 144:ef7eb2e8f9f7 | 432 | * @{ |
<> | 144:ef7eb2e8f9f7 | 433 | */ |
<> | 144:ef7eb2e8f9f7 | 434 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ |
<> | 144:ef7eb2e8f9f7 | 435 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ |
<> | 144:ef7eb2e8f9f7 | 436 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ |
<> | 144:ef7eb2e8f9f7 | 437 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ |
<> | 144:ef7eb2e8f9f7 | 438 | |
<> | 144:ef7eb2e8f9f7 | 439 | /** |
<> | 144:ef7eb2e8f9f7 | 440 | * @} |
<> | 144:ef7eb2e8f9f7 | 441 | */ |
<> | 144:ef7eb2e8f9f7 | 442 | |
<> | 144:ef7eb2e8f9f7 | 443 | /** @defgroup RCC_System_Clock_Source System Clock Source |
<> | 144:ef7eb2e8f9f7 | 444 | * @{ |
<> | 144:ef7eb2e8f9f7 | 445 | */ |
<> | 144:ef7eb2e8f9f7 | 446 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ |
<> | 144:ef7eb2e8f9f7 | 447 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ |
<> | 144:ef7eb2e8f9f7 | 448 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ |
<> | 144:ef7eb2e8f9f7 | 449 | |
<> | 144:ef7eb2e8f9f7 | 450 | /** |
<> | 144:ef7eb2e8f9f7 | 451 | * @} |
<> | 144:ef7eb2e8f9f7 | 452 | */ |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
<> | 144:ef7eb2e8f9f7 | 455 | * @{ |
<> | 144:ef7eb2e8f9f7 | 456 | */ |
<> | 144:ef7eb2e8f9f7 | 457 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
<> | 144:ef7eb2e8f9f7 | 458 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
<> | 144:ef7eb2e8f9f7 | 459 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
<> | 144:ef7eb2e8f9f7 | 460 | |
<> | 144:ef7eb2e8f9f7 | 461 | /** |
<> | 144:ef7eb2e8f9f7 | 462 | * @} |
<> | 144:ef7eb2e8f9f7 | 463 | */ |
<> | 144:ef7eb2e8f9f7 | 464 | |
<> | 144:ef7eb2e8f9f7 | 465 | /** @defgroup RCC_AHB_Clock_Source AHB Clock Source |
<> | 144:ef7eb2e8f9f7 | 466 | * @{ |
<> | 144:ef7eb2e8f9f7 | 467 | */ |
<> | 144:ef7eb2e8f9f7 | 468 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
<> | 144:ef7eb2e8f9f7 | 469 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
<> | 144:ef7eb2e8f9f7 | 470 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
<> | 144:ef7eb2e8f9f7 | 471 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
<> | 144:ef7eb2e8f9f7 | 472 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
<> | 144:ef7eb2e8f9f7 | 473 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
<> | 144:ef7eb2e8f9f7 | 474 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
<> | 144:ef7eb2e8f9f7 | 475 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
<> | 144:ef7eb2e8f9f7 | 476 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
<> | 144:ef7eb2e8f9f7 | 477 | |
<> | 144:ef7eb2e8f9f7 | 478 | /** |
<> | 144:ef7eb2e8f9f7 | 479 | * @} |
<> | 144:ef7eb2e8f9f7 | 480 | */ |
<> | 144:ef7eb2e8f9f7 | 481 | |
<> | 144:ef7eb2e8f9f7 | 482 | /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source |
<> | 144:ef7eb2e8f9f7 | 483 | * @{ |
<> | 144:ef7eb2e8f9f7 | 484 | */ |
<> | 144:ef7eb2e8f9f7 | 485 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
<> | 144:ef7eb2e8f9f7 | 486 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
<> | 144:ef7eb2e8f9f7 | 487 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
<> | 144:ef7eb2e8f9f7 | 488 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
<> | 144:ef7eb2e8f9f7 | 489 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | /** |
<> | 144:ef7eb2e8f9f7 | 492 | * @} |
<> | 144:ef7eb2e8f9f7 | 493 | */ |
<> | 144:ef7eb2e8f9f7 | 494 | |
<> | 144:ef7eb2e8f9f7 | 495 | /** @defgroup RCC_RTC_Clock_Source RTC Clock Source |
<> | 144:ef7eb2e8f9f7 | 496 | * @{ |
<> | 144:ef7eb2e8f9f7 | 497 | */ |
<> | 144:ef7eb2e8f9f7 | 498 | #define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */ |
<> | 144:ef7eb2e8f9f7 | 499 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ |
<> | 144:ef7eb2e8f9f7 | 500 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ |
<> | 144:ef7eb2e8f9f7 | 501 | #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
<> | 144:ef7eb2e8f9f7 | 502 | /** |
<> | 144:ef7eb2e8f9f7 | 503 | * @} |
<> | 144:ef7eb2e8f9f7 | 504 | */ |
<> | 144:ef7eb2e8f9f7 | 505 | |
<> | 144:ef7eb2e8f9f7 | 506 | /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor |
<> | 144:ef7eb2e8f9f7 | 507 | * @{ |
<> | 144:ef7eb2e8f9f7 | 508 | */ |
<> | 144:ef7eb2e8f9f7 | 509 | #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 |
<> | 144:ef7eb2e8f9f7 | 510 | #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 |
<> | 144:ef7eb2e8f9f7 | 511 | #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 |
<> | 144:ef7eb2e8f9f7 | 512 | #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 |
<> | 144:ef7eb2e8f9f7 | 513 | #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 |
<> | 144:ef7eb2e8f9f7 | 514 | #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 |
<> | 144:ef7eb2e8f9f7 | 515 | #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 |
<> | 144:ef7eb2e8f9f7 | 516 | #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 |
<> | 144:ef7eb2e8f9f7 | 517 | #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 |
<> | 144:ef7eb2e8f9f7 | 518 | #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 |
<> | 144:ef7eb2e8f9f7 | 519 | #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 |
<> | 144:ef7eb2e8f9f7 | 520 | #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 |
<> | 144:ef7eb2e8f9f7 | 521 | #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 |
<> | 144:ef7eb2e8f9f7 | 522 | #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 |
<> | 144:ef7eb2e8f9f7 | 523 | #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 |
<> | 144:ef7eb2e8f9f7 | 524 | |
<> | 144:ef7eb2e8f9f7 | 525 | /** |
<> | 144:ef7eb2e8f9f7 | 526 | * @} |
<> | 144:ef7eb2e8f9f7 | 527 | */ |
<> | 144:ef7eb2e8f9f7 | 528 | |
<> | 144:ef7eb2e8f9f7 | 529 | #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) |
<> | 144:ef7eb2e8f9f7 | 530 | /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor |
<> | 144:ef7eb2e8f9f7 | 531 | * @{ |
<> | 144:ef7eb2e8f9f7 | 532 | */ |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
<> | 144:ef7eb2e8f9f7 | 535 | #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
<> | 144:ef7eb2e8f9f7 | 536 | #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
<> | 144:ef7eb2e8f9f7 | 537 | #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
<> | 144:ef7eb2e8f9f7 | 538 | #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
<> | 144:ef7eb2e8f9f7 | 539 | #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
<> | 144:ef7eb2e8f9f7 | 540 | #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
<> | 144:ef7eb2e8f9f7 | 541 | #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
<> | 144:ef7eb2e8f9f7 | 542 | #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
<> | 144:ef7eb2e8f9f7 | 543 | #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
<> | 144:ef7eb2e8f9f7 | 544 | #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
<> | 144:ef7eb2e8f9f7 | 545 | #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
<> | 144:ef7eb2e8f9f7 | 546 | #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
<> | 144:ef7eb2e8f9f7 | 547 | #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
<> | 144:ef7eb2e8f9f7 | 548 | #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
<> | 144:ef7eb2e8f9f7 | 549 | #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /** |
<> | 144:ef7eb2e8f9f7 | 552 | * @} |
<> | 144:ef7eb2e8f9f7 | 553 | */ |
<> | 144:ef7eb2e8f9f7 | 554 | |
<> | 144:ef7eb2e8f9f7 | 555 | #endif |
<> | 144:ef7eb2e8f9f7 | 556 | #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) |
<> | 144:ef7eb2e8f9f7 | 557 | /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor |
<> | 144:ef7eb2e8f9f7 | 558 | * @{ |
<> | 144:ef7eb2e8f9f7 | 559 | */ |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
<> | 144:ef7eb2e8f9f7 | 562 | #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
<> | 144:ef7eb2e8f9f7 | 563 | #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
<> | 144:ef7eb2e8f9f7 | 564 | #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
<> | 144:ef7eb2e8f9f7 | 565 | #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
<> | 144:ef7eb2e8f9f7 | 566 | #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
<> | 144:ef7eb2e8f9f7 | 567 | #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
<> | 144:ef7eb2e8f9f7 | 568 | #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
<> | 144:ef7eb2e8f9f7 | 569 | #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
<> | 144:ef7eb2e8f9f7 | 570 | #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
<> | 144:ef7eb2e8f9f7 | 571 | #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
<> | 144:ef7eb2e8f9f7 | 572 | #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
<> | 144:ef7eb2e8f9f7 | 573 | #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
<> | 144:ef7eb2e8f9f7 | 574 | #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
<> | 144:ef7eb2e8f9f7 | 575 | #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
<> | 144:ef7eb2e8f9f7 | 576 | #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | /** |
<> | 144:ef7eb2e8f9f7 | 579 | * @} |
<> | 144:ef7eb2e8f9f7 | 580 | */ |
<> | 144:ef7eb2e8f9f7 | 581 | #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | #if defined(RCC_CFGR3_USART2SW) |
<> | 144:ef7eb2e8f9f7 | 584 | /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source |
<> | 144:ef7eb2e8f9f7 | 585 | * @{ |
<> | 144:ef7eb2e8f9f7 | 586 | */ |
<> | 144:ef7eb2e8f9f7 | 587 | #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK |
<> | 144:ef7eb2e8f9f7 | 588 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK |
<> | 144:ef7eb2e8f9f7 | 589 | #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE |
<> | 144:ef7eb2e8f9f7 | 590 | #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | /** |
<> | 144:ef7eb2e8f9f7 | 593 | * @} |
<> | 144:ef7eb2e8f9f7 | 594 | */ |
<> | 144:ef7eb2e8f9f7 | 595 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 144:ef7eb2e8f9f7 | 596 | |
<> | 144:ef7eb2e8f9f7 | 597 | #if defined(RCC_CFGR3_USART3SW) |
<> | 144:ef7eb2e8f9f7 | 598 | /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source |
<> | 144:ef7eb2e8f9f7 | 599 | * @{ |
<> | 144:ef7eb2e8f9f7 | 600 | */ |
<> | 144:ef7eb2e8f9f7 | 601 | #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK |
<> | 144:ef7eb2e8f9f7 | 602 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK |
<> | 144:ef7eb2e8f9f7 | 603 | #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE |
<> | 144:ef7eb2e8f9f7 | 604 | #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI |
<> | 144:ef7eb2e8f9f7 | 605 | |
<> | 144:ef7eb2e8f9f7 | 606 | /** |
<> | 144:ef7eb2e8f9f7 | 607 | * @} |
<> | 144:ef7eb2e8f9f7 | 608 | */ |
<> | 144:ef7eb2e8f9f7 | 609 | #endif /* RCC_CFGR3_USART3SW */ |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source |
<> | 144:ef7eb2e8f9f7 | 612 | * @{ |
<> | 144:ef7eb2e8f9f7 | 613 | */ |
<> | 144:ef7eb2e8f9f7 | 614 | #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI |
<> | 144:ef7eb2e8f9f7 | 615 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK |
<> | 144:ef7eb2e8f9f7 | 616 | |
<> | 144:ef7eb2e8f9f7 | 617 | /** |
<> | 144:ef7eb2e8f9f7 | 618 | * @} |
<> | 144:ef7eb2e8f9f7 | 619 | */ |
<> | 144:ef7eb2e8f9f7 | 620 | /** @defgroup RCC_MCO_Index MCO Index |
<> | 144:ef7eb2e8f9f7 | 621 | * @{ |
<> | 144:ef7eb2e8f9f7 | 622 | */ |
<> | 144:ef7eb2e8f9f7 | 623 | #define RCC_MCO1 ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 624 | #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ |
<> | 144:ef7eb2e8f9f7 | 625 | |
<> | 144:ef7eb2e8f9f7 | 626 | /** |
<> | 144:ef7eb2e8f9f7 | 627 | * @} |
<> | 144:ef7eb2e8f9f7 | 628 | */ |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | /** @defgroup RCC_Interrupt Interrupts |
<> | 144:ef7eb2e8f9f7 | 631 | * @{ |
<> | 144:ef7eb2e8f9f7 | 632 | */ |
<> | 144:ef7eb2e8f9f7 | 633 | #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 634 | #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 635 | #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 636 | #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 637 | #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 638 | #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ |
<> | 144:ef7eb2e8f9f7 | 639 | /** |
<> | 144:ef7eb2e8f9f7 | 640 | * @} |
<> | 144:ef7eb2e8f9f7 | 641 | */ |
<> | 144:ef7eb2e8f9f7 | 642 | |
<> | 144:ef7eb2e8f9f7 | 643 | /** @defgroup RCC_Flag Flags |
<> | 144:ef7eb2e8f9f7 | 644 | * Elements values convention: XXXYYYYYb |
<> | 144:ef7eb2e8f9f7 | 645 | * - YYYYY : Flag position in the register |
<> | 144:ef7eb2e8f9f7 | 646 | * - XXX : Register index |
<> | 144:ef7eb2e8f9f7 | 647 | * - 001: CR register |
<> | 144:ef7eb2e8f9f7 | 648 | * - 010: BDCR register |
<> | 144:ef7eb2e8f9f7 | 649 | * - 011: CSR register |
<> | 144:ef7eb2e8f9f7 | 650 | * - 100: CFGR register |
<> | 144:ef7eb2e8f9f7 | 651 | * @{ |
<> | 144:ef7eb2e8f9f7 | 652 | */ |
<> | 144:ef7eb2e8f9f7 | 653 | /* Flags in the CR register */ |
<> | 144:ef7eb2e8f9f7 | 654 | #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ |
<> | 144:ef7eb2e8f9f7 | 655 | #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ |
<> | 144:ef7eb2e8f9f7 | 656 | #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | /* Flags in the CSR register */ |
<> | 144:ef7eb2e8f9f7 | 659 | #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ |
<> | 144:ef7eb2e8f9f7 | 660 | #if defined(RCC_CSR_V18PWRRSTF) |
<> | 144:ef7eb2e8f9f7 | 661 | #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_V18PWRRSTF))) |
<> | 144:ef7eb2e8f9f7 | 662 | #endif |
<> | 144:ef7eb2e8f9f7 | 663 | #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ |
<> | 144:ef7eb2e8f9f7 | 664 | #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ |
<> | 144:ef7eb2e8f9f7 | 665 | #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ |
<> | 144:ef7eb2e8f9f7 | 666 | #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ |
<> | 144:ef7eb2e8f9f7 | 667 | #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ |
<> | 144:ef7eb2e8f9f7 | 668 | #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ |
<> | 144:ef7eb2e8f9f7 | 669 | #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ |
<> | 144:ef7eb2e8f9f7 | 670 | |
<> | 144:ef7eb2e8f9f7 | 671 | /* Flags in the BDCR register */ |
<> | 144:ef7eb2e8f9f7 | 672 | #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ |
<> | 144:ef7eb2e8f9f7 | 673 | |
<> | 144:ef7eb2e8f9f7 | 674 | /* Flags in the CFGR register */ |
<> | 144:ef7eb2e8f9f7 | 675 | #if defined(RCC_CFGR_MCOF) |
<> | 144:ef7eb2e8f9f7 | 676 | #define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */ |
<> | 144:ef7eb2e8f9f7 | 677 | #endif /* RCC_CFGR_MCOF */ |
<> | 144:ef7eb2e8f9f7 | 678 | |
<> | 144:ef7eb2e8f9f7 | 679 | /** |
<> | 144:ef7eb2e8f9f7 | 680 | * @} |
<> | 144:ef7eb2e8f9f7 | 681 | */ |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | /** |
<> | 144:ef7eb2e8f9f7 | 684 | * @} |
<> | 144:ef7eb2e8f9f7 | 685 | */ |
<> | 144:ef7eb2e8f9f7 | 686 | |
<> | 144:ef7eb2e8f9f7 | 687 | /* Exported macro ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 688 | |
<> | 144:ef7eb2e8f9f7 | 689 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
<> | 144:ef7eb2e8f9f7 | 690 | * @{ |
<> | 144:ef7eb2e8f9f7 | 691 | */ |
<> | 144:ef7eb2e8f9f7 | 692 | |
<> | 144:ef7eb2e8f9f7 | 693 | /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable |
<> | 144:ef7eb2e8f9f7 | 694 | * @brief Enable or disable the AHB peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 695 | * @note After reset, the peripheral clock (used for registers read/write access) |
<> | 144:ef7eb2e8f9f7 | 696 | * is disabled and the application software has to enable this clock before |
<> | 144:ef7eb2e8f9f7 | 697 | * using it. |
<> | 144:ef7eb2e8f9f7 | 698 | * @{ |
<> | 144:ef7eb2e8f9f7 | 699 | */ |
<> | 144:ef7eb2e8f9f7 | 700 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 701 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 702 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ |
<> | 144:ef7eb2e8f9f7 | 703 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 704 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ |
<> | 144:ef7eb2e8f9f7 | 705 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 706 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 707 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 708 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 709 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ |
<> | 144:ef7eb2e8f9f7 | 710 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 711 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ |
<> | 144:ef7eb2e8f9f7 | 712 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 713 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 714 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 715 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 716 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ |
<> | 144:ef7eb2e8f9f7 | 717 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 718 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ |
<> | 144:ef7eb2e8f9f7 | 719 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 720 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 721 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 722 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 723 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ |
<> | 144:ef7eb2e8f9f7 | 724 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 725 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ |
<> | 144:ef7eb2e8f9f7 | 726 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 727 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 728 | #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 729 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 730 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
<> | 144:ef7eb2e8f9f7 | 731 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 732 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ |
<> | 144:ef7eb2e8f9f7 | 733 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 734 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 735 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 736 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 737 | SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ |
<> | 144:ef7eb2e8f9f7 | 738 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 739 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ |
<> | 144:ef7eb2e8f9f7 | 740 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 741 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 742 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 743 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 744 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ |
<> | 144:ef7eb2e8f9f7 | 745 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 746 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ |
<> | 144:ef7eb2e8f9f7 | 747 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 748 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 749 | #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 750 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 751 | SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ |
<> | 144:ef7eb2e8f9f7 | 752 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 753 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ |
<> | 144:ef7eb2e8f9f7 | 754 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 755 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 756 | #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 757 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 758 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ |
<> | 144:ef7eb2e8f9f7 | 759 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 760 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ |
<> | 144:ef7eb2e8f9f7 | 761 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 762 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 763 | #define __HAL_RCC_TSC_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 764 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 765 | SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ |
<> | 144:ef7eb2e8f9f7 | 766 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 767 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ |
<> | 144:ef7eb2e8f9f7 | 768 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 769 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 770 | |
<> | 144:ef7eb2e8f9f7 | 771 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) |
<> | 144:ef7eb2e8f9f7 | 772 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) |
<> | 144:ef7eb2e8f9f7 | 773 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) |
<> | 144:ef7eb2e8f9f7 | 774 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
<> | 144:ef7eb2e8f9f7 | 775 | #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) |
<> | 144:ef7eb2e8f9f7 | 776 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
<> | 144:ef7eb2e8f9f7 | 777 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
<> | 144:ef7eb2e8f9f7 | 778 | #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
<> | 144:ef7eb2e8f9f7 | 779 | #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
<> | 144:ef7eb2e8f9f7 | 780 | #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
<> | 144:ef7eb2e8f9f7 | 781 | /** |
<> | 144:ef7eb2e8f9f7 | 782 | * @} |
<> | 144:ef7eb2e8f9f7 | 783 | */ |
<> | 144:ef7eb2e8f9f7 | 784 | |
<> | 144:ef7eb2e8f9f7 | 785 | /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable |
<> | 144:ef7eb2e8f9f7 | 786 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 787 | * @note After reset, the peripheral clock (used for registers read/write access) |
<> | 144:ef7eb2e8f9f7 | 788 | * is disabled and the application software has to enable this clock before |
<> | 144:ef7eb2e8f9f7 | 789 | * using it. |
<> | 144:ef7eb2e8f9f7 | 790 | * @{ |
<> | 144:ef7eb2e8f9f7 | 791 | */ |
<> | 144:ef7eb2e8f9f7 | 792 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 793 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 794 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
<> | 144:ef7eb2e8f9f7 | 795 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 796 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
<> | 144:ef7eb2e8f9f7 | 797 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 798 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 799 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 800 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 801 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
<> | 144:ef7eb2e8f9f7 | 802 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 803 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
<> | 144:ef7eb2e8f9f7 | 804 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 805 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 806 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 807 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 808 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
<> | 144:ef7eb2e8f9f7 | 809 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 810 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
<> | 144:ef7eb2e8f9f7 | 811 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 812 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 813 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 814 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 815 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
<> | 144:ef7eb2e8f9f7 | 816 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 817 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
<> | 144:ef7eb2e8f9f7 | 818 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 819 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 820 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 821 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 822 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
<> | 144:ef7eb2e8f9f7 | 823 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 824 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
<> | 144:ef7eb2e8f9f7 | 825 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 826 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 827 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 828 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 829 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
<> | 144:ef7eb2e8f9f7 | 830 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 831 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
<> | 144:ef7eb2e8f9f7 | 832 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 833 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 834 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 835 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 836 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
<> | 144:ef7eb2e8f9f7 | 837 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 838 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
<> | 144:ef7eb2e8f9f7 | 839 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 840 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 841 | #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 842 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 843 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ |
<> | 144:ef7eb2e8f9f7 | 844 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 845 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ |
<> | 144:ef7eb2e8f9f7 | 846 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 847 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
<> | 144:ef7eb2e8f9f7 | 850 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
<> | 144:ef7eb2e8f9f7 | 851 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
<> | 144:ef7eb2e8f9f7 | 852 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
<> | 144:ef7eb2e8f9f7 | 853 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
<> | 144:ef7eb2e8f9f7 | 854 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
<> | 144:ef7eb2e8f9f7 | 855 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
<> | 144:ef7eb2e8f9f7 | 856 | #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) |
<> | 144:ef7eb2e8f9f7 | 857 | /** |
<> | 144:ef7eb2e8f9f7 | 858 | * @} |
<> | 144:ef7eb2e8f9f7 | 859 | */ |
<> | 144:ef7eb2e8f9f7 | 860 | |
<> | 144:ef7eb2e8f9f7 | 861 | /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable |
<> | 144:ef7eb2e8f9f7 | 862 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 863 | * @note After reset, the peripheral clock (used for registers read/write access) |
<> | 144:ef7eb2e8f9f7 | 864 | * is disabled and the application software has to enable this clock before |
<> | 144:ef7eb2e8f9f7 | 865 | * using it. |
<> | 144:ef7eb2e8f9f7 | 866 | * @{ |
<> | 144:ef7eb2e8f9f7 | 867 | */ |
<> | 144:ef7eb2e8f9f7 | 868 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 869 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 870 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
<> | 144:ef7eb2e8f9f7 | 871 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 872 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
<> | 144:ef7eb2e8f9f7 | 873 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 874 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 875 | #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 876 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 877 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
<> | 144:ef7eb2e8f9f7 | 878 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 879 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
<> | 144:ef7eb2e8f9f7 | 880 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 881 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 882 | #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 883 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 884 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ |
<> | 144:ef7eb2e8f9f7 | 885 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 886 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ |
<> | 144:ef7eb2e8f9f7 | 887 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 888 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 889 | #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 890 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 891 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ |
<> | 144:ef7eb2e8f9f7 | 892 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 893 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ |
<> | 144:ef7eb2e8f9f7 | 894 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 895 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 896 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
<> | 144:ef7eb2e8f9f7 | 897 | __IO uint32_t tmpreg; \ |
<> | 144:ef7eb2e8f9f7 | 898 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
<> | 144:ef7eb2e8f9f7 | 899 | /* Delay after an RCC peripheral clock enabling */ \ |
<> | 144:ef7eb2e8f9f7 | 900 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
<> | 144:ef7eb2e8f9f7 | 901 | UNUSED(tmpreg); \ |
<> | 144:ef7eb2e8f9f7 | 902 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
<> | 144:ef7eb2e8f9f7 | 905 | #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
<> | 144:ef7eb2e8f9f7 | 906 | #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) |
<> | 144:ef7eb2e8f9f7 | 907 | #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) |
<> | 144:ef7eb2e8f9f7 | 908 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
<> | 144:ef7eb2e8f9f7 | 909 | /** |
<> | 144:ef7eb2e8f9f7 | 910 | * @} |
<> | 144:ef7eb2e8f9f7 | 911 | */ |
<> | 144:ef7eb2e8f9f7 | 912 | |
<> | 144:ef7eb2e8f9f7 | 913 | /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status |
<> | 144:ef7eb2e8f9f7 | 914 | * @brief Get the enable or disable status of the AHB peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 915 | * @note After reset, the peripheral clock (used for registers read/write access) |
<> | 144:ef7eb2e8f9f7 | 916 | * is disabled and the application software has to enable this clock before |
<> | 144:ef7eb2e8f9f7 | 917 | * using it. |
<> | 144:ef7eb2e8f9f7 | 918 | * @{ |
<> | 144:ef7eb2e8f9f7 | 919 | */ |
<> | 144:ef7eb2e8f9f7 | 920 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 921 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 922 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 923 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 924 | #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 925 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 926 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 927 | #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 928 | #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 929 | #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 930 | |
<> | 144:ef7eb2e8f9f7 | 931 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 932 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 933 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 934 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 935 | #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 936 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 937 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 938 | #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 939 | #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 940 | #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 941 | /** |
<> | 144:ef7eb2e8f9f7 | 942 | * @} |
<> | 144:ef7eb2e8f9f7 | 943 | */ |
<> | 144:ef7eb2e8f9f7 | 944 | |
<> | 144:ef7eb2e8f9f7 | 945 | /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
<> | 144:ef7eb2e8f9f7 | 946 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 947 | * @note After reset, the peripheral clock (used for registers read/write access) |
<> | 144:ef7eb2e8f9f7 | 948 | * is disabled and the application software has to enable this clock before |
<> | 144:ef7eb2e8f9f7 | 949 | * using it. |
<> | 144:ef7eb2e8f9f7 | 950 | * @{ |
<> | 144:ef7eb2e8f9f7 | 951 | */ |
<> | 144:ef7eb2e8f9f7 | 952 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 953 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 954 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 955 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 956 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 957 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 958 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 959 | #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 960 | |
<> | 144:ef7eb2e8f9f7 | 961 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 962 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 963 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 964 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 965 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 966 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 967 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 968 | #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 969 | /** |
<> | 144:ef7eb2e8f9f7 | 970 | * @} |
<> | 144:ef7eb2e8f9f7 | 971 | */ |
<> | 144:ef7eb2e8f9f7 | 972 | |
<> | 144:ef7eb2e8f9f7 | 973 | /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
<> | 144:ef7eb2e8f9f7 | 974 | * @brief EGet the enable or disable status of the APB2 peripheral clock. |
<> | 144:ef7eb2e8f9f7 | 975 | * @note After reset, the peripheral clock (used for registers read/write access) |
<> | 144:ef7eb2e8f9f7 | 976 | * is disabled and the application software has to enable this clock before |
<> | 144:ef7eb2e8f9f7 | 977 | * using it. |
<> | 144:ef7eb2e8f9f7 | 978 | * @{ |
<> | 144:ef7eb2e8f9f7 | 979 | */ |
<> | 144:ef7eb2e8f9f7 | 980 | #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 981 | #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 982 | #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 983 | #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 984 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
<> | 144:ef7eb2e8f9f7 | 985 | |
<> | 144:ef7eb2e8f9f7 | 986 | #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 987 | #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 988 | #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 989 | #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 990 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
<> | 144:ef7eb2e8f9f7 | 991 | /** |
<> | 144:ef7eb2e8f9f7 | 992 | * @} |
<> | 144:ef7eb2e8f9f7 | 993 | */ |
<> | 144:ef7eb2e8f9f7 | 994 | |
<> | 144:ef7eb2e8f9f7 | 995 | /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset |
<> | 144:ef7eb2e8f9f7 | 996 | * @brief Force or release AHB peripheral reset. |
<> | 144:ef7eb2e8f9f7 | 997 | * @{ |
<> | 144:ef7eb2e8f9f7 | 998 | */ |
<> | 144:ef7eb2e8f9f7 | 999 | #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) |
<> | 144:ef7eb2e8f9f7 | 1000 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) |
<> | 144:ef7eb2e8f9f7 | 1001 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) |
<> | 144:ef7eb2e8f9f7 | 1002 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) |
<> | 144:ef7eb2e8f9f7 | 1003 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
<> | 144:ef7eb2e8f9f7 | 1004 | #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) |
<> | 144:ef7eb2e8f9f7 | 1005 | #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
<> | 144:ef7eb2e8f9f7 | 1006 | |
<> | 144:ef7eb2e8f9f7 | 1007 | #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 1008 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) |
<> | 144:ef7eb2e8f9f7 | 1009 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) |
<> | 144:ef7eb2e8f9f7 | 1010 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) |
<> | 144:ef7eb2e8f9f7 | 1011 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
<> | 144:ef7eb2e8f9f7 | 1012 | #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) |
<> | 144:ef7eb2e8f9f7 | 1013 | #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
<> | 144:ef7eb2e8f9f7 | 1014 | /** |
<> | 144:ef7eb2e8f9f7 | 1015 | * @} |
<> | 144:ef7eb2e8f9f7 | 1016 | */ |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset |
<> | 144:ef7eb2e8f9f7 | 1019 | * @brief Force or release APB1 peripheral reset. |
<> | 144:ef7eb2e8f9f7 | 1020 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1021 | */ |
<> | 144:ef7eb2e8f9f7 | 1022 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) |
<> | 144:ef7eb2e8f9f7 | 1023 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
<> | 144:ef7eb2e8f9f7 | 1024 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
<> | 144:ef7eb2e8f9f7 | 1025 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
<> | 144:ef7eb2e8f9f7 | 1026 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
<> | 144:ef7eb2e8f9f7 | 1027 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
<> | 144:ef7eb2e8f9f7 | 1028 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
<> | 144:ef7eb2e8f9f7 | 1029 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
<> | 144:ef7eb2e8f9f7 | 1030 | #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) |
<> | 144:ef7eb2e8f9f7 | 1031 | |
<> | 144:ef7eb2e8f9f7 | 1032 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 1033 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
<> | 144:ef7eb2e8f9f7 | 1034 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
<> | 144:ef7eb2e8f9f7 | 1035 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
<> | 144:ef7eb2e8f9f7 | 1036 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
<> | 144:ef7eb2e8f9f7 | 1037 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
<> | 144:ef7eb2e8f9f7 | 1038 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
<> | 144:ef7eb2e8f9f7 | 1039 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
<> | 144:ef7eb2e8f9f7 | 1040 | #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) |
<> | 144:ef7eb2e8f9f7 | 1041 | /** |
<> | 144:ef7eb2e8f9f7 | 1042 | * @} |
<> | 144:ef7eb2e8f9f7 | 1043 | */ |
<> | 144:ef7eb2e8f9f7 | 1044 | |
<> | 144:ef7eb2e8f9f7 | 1045 | /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset |
<> | 144:ef7eb2e8f9f7 | 1046 | * @brief Force or release APB2 peripheral reset. |
<> | 144:ef7eb2e8f9f7 | 1047 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1048 | */ |
<> | 144:ef7eb2e8f9f7 | 1049 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
<> | 144:ef7eb2e8f9f7 | 1050 | #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
<> | 144:ef7eb2e8f9f7 | 1051 | #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
<> | 144:ef7eb2e8f9f7 | 1052 | #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) |
<> | 144:ef7eb2e8f9f7 | 1053 | #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) |
<> | 144:ef7eb2e8f9f7 | 1054 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
<> | 144:ef7eb2e8f9f7 | 1055 | |
<> | 144:ef7eb2e8f9f7 | 1056 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 1057 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
<> | 144:ef7eb2e8f9f7 | 1058 | #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
<> | 144:ef7eb2e8f9f7 | 1059 | #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) |
<> | 144:ef7eb2e8f9f7 | 1060 | #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) |
<> | 144:ef7eb2e8f9f7 | 1061 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
<> | 144:ef7eb2e8f9f7 | 1062 | /** |
<> | 144:ef7eb2e8f9f7 | 1063 | * @} |
<> | 144:ef7eb2e8f9f7 | 1064 | */ |
<> | 144:ef7eb2e8f9f7 | 1065 | |
<> | 144:ef7eb2e8f9f7 | 1066 | /** @defgroup RCC_HSI_Configuration HSI Configuration |
<> | 144:ef7eb2e8f9f7 | 1067 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1068 | */ |
<> | 144:ef7eb2e8f9f7 | 1069 | |
<> | 144:ef7eb2e8f9f7 | 1070 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
<> | 144:ef7eb2e8f9f7 | 1071 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
<> | 144:ef7eb2e8f9f7 | 1072 | * It is used (enabled by hardware) as system clock source after startup |
<> | 144:ef7eb2e8f9f7 | 1073 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
<> | 144:ef7eb2e8f9f7 | 1074 | * of the HSE used directly or indirectly as system clock (if the Clock |
<> | 144:ef7eb2e8f9f7 | 1075 | * Security System CSS is enabled). |
<> | 144:ef7eb2e8f9f7 | 1076 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
<> | 144:ef7eb2e8f9f7 | 1077 | * you have to select another source of the system clock then stop the HSI. |
<> | 144:ef7eb2e8f9f7 | 1078 | * @note After enabling the HSI, the application software should wait on HSIRDY |
<> | 144:ef7eb2e8f9f7 | 1079 | * flag to be set indicating that HSI clock is stable and can be used as |
<> | 144:ef7eb2e8f9f7 | 1080 | * system clock source. |
<> | 144:ef7eb2e8f9f7 | 1081 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
<> | 144:ef7eb2e8f9f7 | 1082 | * clock cycles. |
<> | 144:ef7eb2e8f9f7 | 1083 | */ |
<> | 144:ef7eb2e8f9f7 | 1084 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1085 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 1086 | |
<> | 144:ef7eb2e8f9f7 | 1087 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
<> | 144:ef7eb2e8f9f7 | 1088 | * @note The calibration is used to compensate for the variations in voltage |
<> | 144:ef7eb2e8f9f7 | 1089 | * and temperature that influence the frequency of the internal HSI RC. |
<> | 144:ef7eb2e8f9f7 | 1090 | * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. |
<> | 144:ef7eb2e8f9f7 | 1091 | * (default is RCC_HSICALIBRATION_DEFAULT). |
<> | 144:ef7eb2e8f9f7 | 1092 | * This parameter must be a number between 0 and 0x1F. |
<> | 144:ef7eb2e8f9f7 | 1093 | */ |
<> | 144:ef7eb2e8f9f7 | 1094 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ |
<> | 144:ef7eb2e8f9f7 | 1095 | (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) |
<> | 144:ef7eb2e8f9f7 | 1096 | |
<> | 144:ef7eb2e8f9f7 | 1097 | /** |
<> | 144:ef7eb2e8f9f7 | 1098 | * @} |
<> | 144:ef7eb2e8f9f7 | 1099 | */ |
<> | 144:ef7eb2e8f9f7 | 1100 | |
<> | 144:ef7eb2e8f9f7 | 1101 | /** @defgroup RCC_LSI_Configuration LSI Configuration |
<> | 144:ef7eb2e8f9f7 | 1102 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1103 | */ |
<> | 144:ef7eb2e8f9f7 | 1104 | |
<> | 144:ef7eb2e8f9f7 | 1105 | /** @brief Macro to enable the Internal Low Speed oscillator (LSI). |
<> | 144:ef7eb2e8f9f7 | 1106 | * @note After enabling the LSI, the application software should wait on |
<> | 144:ef7eb2e8f9f7 | 1107 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
<> | 144:ef7eb2e8f9f7 | 1108 | * be used to clock the IWDG and/or the RTC. |
<> | 144:ef7eb2e8f9f7 | 1109 | */ |
<> | 144:ef7eb2e8f9f7 | 1110 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1111 | |
<> | 144:ef7eb2e8f9f7 | 1112 | /** @brief Macro to disable the Internal Low Speed oscillator (LSI). |
<> | 144:ef7eb2e8f9f7 | 1113 | * @note LSI can not be disabled if the IWDG is running. |
<> | 144:ef7eb2e8f9f7 | 1114 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
<> | 144:ef7eb2e8f9f7 | 1115 | * clock cycles. |
<> | 144:ef7eb2e8f9f7 | 1116 | */ |
<> | 144:ef7eb2e8f9f7 | 1117 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 1118 | |
<> | 144:ef7eb2e8f9f7 | 1119 | /** |
<> | 144:ef7eb2e8f9f7 | 1120 | * @} |
<> | 144:ef7eb2e8f9f7 | 1121 | */ |
<> | 144:ef7eb2e8f9f7 | 1122 | |
<> | 144:ef7eb2e8f9f7 | 1123 | /** @defgroup RCC_HSE_Configuration HSE Configuration |
<> | 144:ef7eb2e8f9f7 | 1124 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1125 | */ |
<> | 144:ef7eb2e8f9f7 | 1126 | |
<> | 144:ef7eb2e8f9f7 | 1127 | /** |
<> | 144:ef7eb2e8f9f7 | 1128 | * @brief Macro to configure the External High Speed oscillator (HSE). |
<> | 144:ef7eb2e8f9f7 | 1129 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not |
<> | 144:ef7eb2e8f9f7 | 1130 | * supported by this macro. User should request a transition to HSE Off |
<> | 144:ef7eb2e8f9f7 | 1131 | * first and then HSE On or HSE Bypass. |
<> | 144:ef7eb2e8f9f7 | 1132 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
<> | 144:ef7eb2e8f9f7 | 1133 | * software should wait on HSERDY flag to be set indicating that HSE clock |
<> | 144:ef7eb2e8f9f7 | 1134 | * is stable and can be used to clock the PLL and/or system clock. |
<> | 144:ef7eb2e8f9f7 | 1135 | * @note HSE state can not be changed if it is used directly or through the |
<> | 144:ef7eb2e8f9f7 | 1136 | * PLL as system clock. In this case, you have to select another source |
<> | 144:ef7eb2e8f9f7 | 1137 | * of the system clock then change the HSE state (ex. disable it). |
<> | 144:ef7eb2e8f9f7 | 1138 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
<> | 144:ef7eb2e8f9f7 | 1139 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
<> | 144:ef7eb2e8f9f7 | 1140 | * was previously enabled you have to enable it again after calling this |
<> | 144:ef7eb2e8f9f7 | 1141 | * function. |
<> | 144:ef7eb2e8f9f7 | 1142 | * @param __STATE__ specifies the new state of the HSE. |
<> | 144:ef7eb2e8f9f7 | 1143 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1144 | * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after |
<> | 144:ef7eb2e8f9f7 | 1145 | * 6 HSE oscillator clock cycles. |
<> | 144:ef7eb2e8f9f7 | 1146 | * @arg @ref RCC_HSE_ON turn ON the HSE oscillator |
<> | 144:ef7eb2e8f9f7 | 1147 | * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock |
<> | 144:ef7eb2e8f9f7 | 1148 | */ |
<> | 144:ef7eb2e8f9f7 | 1149 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
<> | 144:ef7eb2e8f9f7 | 1150 | do{ \ |
<> | 144:ef7eb2e8f9f7 | 1151 | if ((__STATE__) == RCC_HSE_ON) \ |
<> | 144:ef7eb2e8f9f7 | 1152 | { \ |
<> | 144:ef7eb2e8f9f7 | 1153 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1154 | } \ |
<> | 144:ef7eb2e8f9f7 | 1155 | else if ((__STATE__) == RCC_HSE_OFF) \ |
<> | 144:ef7eb2e8f9f7 | 1156 | { \ |
<> | 144:ef7eb2e8f9f7 | 1157 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1158 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
<> | 144:ef7eb2e8f9f7 | 1159 | } \ |
<> | 144:ef7eb2e8f9f7 | 1160 | else if ((__STATE__) == RCC_HSE_BYPASS) \ |
<> | 144:ef7eb2e8f9f7 | 1161 | { \ |
<> | 144:ef7eb2e8f9f7 | 1162 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
<> | 144:ef7eb2e8f9f7 | 1163 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1164 | } \ |
<> | 144:ef7eb2e8f9f7 | 1165 | else \ |
<> | 144:ef7eb2e8f9f7 | 1166 | { \ |
<> | 144:ef7eb2e8f9f7 | 1167 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1168 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
<> | 144:ef7eb2e8f9f7 | 1169 | } \ |
<> | 144:ef7eb2e8f9f7 | 1170 | }while(0) |
<> | 144:ef7eb2e8f9f7 | 1171 | |
<> | 144:ef7eb2e8f9f7 | 1172 | /** |
<> | 144:ef7eb2e8f9f7 | 1173 | * @} |
<> | 144:ef7eb2e8f9f7 | 1174 | */ |
<> | 144:ef7eb2e8f9f7 | 1175 | |
<> | 144:ef7eb2e8f9f7 | 1176 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
<> | 144:ef7eb2e8f9f7 | 1177 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1178 | */ |
<> | 144:ef7eb2e8f9f7 | 1179 | |
<> | 144:ef7eb2e8f9f7 | 1180 | /** |
<> | 144:ef7eb2e8f9f7 | 1181 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
<> | 144:ef7eb2e8f9f7 | 1182 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
<> | 144:ef7eb2e8f9f7 | 1183 | * @note As the LSE is in the Backup domain and write access is denied to |
<> | 144:ef7eb2e8f9f7 | 1184 | * this domain after reset, you have to enable write access using |
<> | 144:ef7eb2e8f9f7 | 1185 | * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
<> | 144:ef7eb2e8f9f7 | 1186 | * (to be done once after reset). |
<> | 144:ef7eb2e8f9f7 | 1187 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
<> | 144:ef7eb2e8f9f7 | 1188 | * software should wait on LSERDY flag to be set indicating that LSE clock |
<> | 144:ef7eb2e8f9f7 | 1189 | * is stable and can be used to clock the RTC. |
<> | 144:ef7eb2e8f9f7 | 1190 | * @param __STATE__ specifies the new state of the LSE. |
<> | 144:ef7eb2e8f9f7 | 1191 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1192 | * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after |
<> | 144:ef7eb2e8f9f7 | 1193 | * 6 LSE oscillator clock cycles. |
<> | 144:ef7eb2e8f9f7 | 1194 | * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. |
<> | 144:ef7eb2e8f9f7 | 1195 | * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. |
<> | 144:ef7eb2e8f9f7 | 1196 | */ |
<> | 144:ef7eb2e8f9f7 | 1197 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
<> | 144:ef7eb2e8f9f7 | 1198 | do{ \ |
<> | 144:ef7eb2e8f9f7 | 1199 | if ((__STATE__) == RCC_LSE_ON) \ |
<> | 144:ef7eb2e8f9f7 | 1200 | { \ |
<> | 144:ef7eb2e8f9f7 | 1201 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1202 | } \ |
<> | 144:ef7eb2e8f9f7 | 1203 | else if ((__STATE__) == RCC_LSE_OFF) \ |
<> | 144:ef7eb2e8f9f7 | 1204 | { \ |
<> | 144:ef7eb2e8f9f7 | 1205 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1206 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
<> | 144:ef7eb2e8f9f7 | 1207 | } \ |
<> | 144:ef7eb2e8f9f7 | 1208 | else if ((__STATE__) == RCC_LSE_BYPASS) \ |
<> | 144:ef7eb2e8f9f7 | 1209 | { \ |
<> | 144:ef7eb2e8f9f7 | 1210 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
<> | 144:ef7eb2e8f9f7 | 1211 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1212 | } \ |
<> | 144:ef7eb2e8f9f7 | 1213 | else \ |
<> | 144:ef7eb2e8f9f7 | 1214 | { \ |
<> | 144:ef7eb2e8f9f7 | 1215 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
<> | 144:ef7eb2e8f9f7 | 1216 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
<> | 144:ef7eb2e8f9f7 | 1217 | } \ |
<> | 144:ef7eb2e8f9f7 | 1218 | }while(0) |
<> | 144:ef7eb2e8f9f7 | 1219 | |
<> | 144:ef7eb2e8f9f7 | 1220 | /** |
<> | 144:ef7eb2e8f9f7 | 1221 | * @} |
<> | 144:ef7eb2e8f9f7 | 1222 | */ |
<> | 144:ef7eb2e8f9f7 | 1223 | |
<> | 144:ef7eb2e8f9f7 | 1224 | /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config |
<> | 144:ef7eb2e8f9f7 | 1225 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1226 | */ |
<> | 144:ef7eb2e8f9f7 | 1227 | |
<> | 144:ef7eb2e8f9f7 | 1228 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
<> | 144:ef7eb2e8f9f7 | 1229 | * @param __USART1CLKSOURCE__ specifies the USART1 clock source. |
<> | 144:ef7eb2e8f9f7 | 1230 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1231 | @if STM32F302xC |
<> | 144:ef7eb2e8f9f7 | 1232 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1233 | @endif |
<> | 144:ef7eb2e8f9f7 | 1234 | @if STM32F303xC |
<> | 144:ef7eb2e8f9f7 | 1235 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1236 | @endif |
<> | 144:ef7eb2e8f9f7 | 1237 | @if STM32F358xx |
<> | 144:ef7eb2e8f9f7 | 1238 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1239 | @endif |
<> | 144:ef7eb2e8f9f7 | 1240 | @if STM32F302xE |
<> | 144:ef7eb2e8f9f7 | 1241 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1242 | @endif |
<> | 144:ef7eb2e8f9f7 | 1243 | @if STM32F303xE |
<> | 144:ef7eb2e8f9f7 | 1244 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1245 | @endif |
<> | 144:ef7eb2e8f9f7 | 1246 | @if STM32F398xx |
<> | 144:ef7eb2e8f9f7 | 1247 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1248 | @endif |
<> | 144:ef7eb2e8f9f7 | 1249 | @if STM32F373xC |
<> | 144:ef7eb2e8f9f7 | 1250 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1251 | @endif |
<> | 144:ef7eb2e8f9f7 | 1252 | @if STM32F378xx |
<> | 144:ef7eb2e8f9f7 | 1253 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1254 | @endif |
<> | 144:ef7eb2e8f9f7 | 1255 | @if STM32F301x8 |
<> | 144:ef7eb2e8f9f7 | 1256 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1257 | @endif |
<> | 144:ef7eb2e8f9f7 | 1258 | @if STM32F302x8 |
<> | 144:ef7eb2e8f9f7 | 1259 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1260 | @endif |
<> | 144:ef7eb2e8f9f7 | 1261 | @if STM32F318xx |
<> | 144:ef7eb2e8f9f7 | 1262 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1263 | @endif |
<> | 144:ef7eb2e8f9f7 | 1264 | @if STM32F303x8 |
<> | 144:ef7eb2e8f9f7 | 1265 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1266 | @endif |
<> | 144:ef7eb2e8f9f7 | 1267 | @if STM32F334x8 |
<> | 144:ef7eb2e8f9f7 | 1268 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1269 | @endif |
<> | 144:ef7eb2e8f9f7 | 1270 | @if STM32F328xx |
<> | 144:ef7eb2e8f9f7 | 1271 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1272 | @endif |
<> | 144:ef7eb2e8f9f7 | 1273 | * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1274 | * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1275 | * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1276 | */ |
<> | 144:ef7eb2e8f9f7 | 1277 | #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 1278 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1279 | |
<> | 144:ef7eb2e8f9f7 | 1280 | /** @brief Macro to get the USART1 clock source. |
<> | 144:ef7eb2e8f9f7 | 1281 | * @retval The clock source can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1282 | @if STM32F302xC |
<> | 144:ef7eb2e8f9f7 | 1283 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1284 | @endif |
<> | 144:ef7eb2e8f9f7 | 1285 | @if STM32F303xC |
<> | 144:ef7eb2e8f9f7 | 1286 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1287 | @endif |
<> | 144:ef7eb2e8f9f7 | 1288 | @if STM32F358xx |
<> | 144:ef7eb2e8f9f7 | 1289 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1290 | @endif |
<> | 144:ef7eb2e8f9f7 | 1291 | @if STM32F302xE |
<> | 144:ef7eb2e8f9f7 | 1292 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1293 | @endif |
<> | 144:ef7eb2e8f9f7 | 1294 | @if STM32F303xE |
<> | 144:ef7eb2e8f9f7 | 1295 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1296 | @endif |
<> | 144:ef7eb2e8f9f7 | 1297 | @if STM32F398xx |
<> | 144:ef7eb2e8f9f7 | 1298 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1299 | @endif |
<> | 144:ef7eb2e8f9f7 | 1300 | @if STM32F373xC |
<> | 144:ef7eb2e8f9f7 | 1301 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1302 | @endif |
<> | 144:ef7eb2e8f9f7 | 1303 | @if STM32F378xx |
<> | 144:ef7eb2e8f9f7 | 1304 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1305 | @endif |
<> | 144:ef7eb2e8f9f7 | 1306 | @if STM32F301x8 |
<> | 144:ef7eb2e8f9f7 | 1307 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1308 | @endif |
<> | 144:ef7eb2e8f9f7 | 1309 | @if STM32F302x8 |
<> | 144:ef7eb2e8f9f7 | 1310 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1311 | @endif |
<> | 144:ef7eb2e8f9f7 | 1312 | @if STM32F318xx |
<> | 144:ef7eb2e8f9f7 | 1313 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1314 | @endif |
<> | 144:ef7eb2e8f9f7 | 1315 | @if STM32F303x8 |
<> | 144:ef7eb2e8f9f7 | 1316 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1317 | @endif |
<> | 144:ef7eb2e8f9f7 | 1318 | @if STM32F334x8 |
<> | 144:ef7eb2e8f9f7 | 1319 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1320 | @endif |
<> | 144:ef7eb2e8f9f7 | 1321 | @if STM32F328xx |
<> | 144:ef7eb2e8f9f7 | 1322 | * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1323 | @endif |
<> | 144:ef7eb2e8f9f7 | 1324 | * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1325 | * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1326 | * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock |
<> | 144:ef7eb2e8f9f7 | 1327 | */ |
<> | 144:ef7eb2e8f9f7 | 1328 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) |
<> | 144:ef7eb2e8f9f7 | 1329 | |
<> | 144:ef7eb2e8f9f7 | 1330 | #if defined(RCC_CFGR3_USART2SW) |
<> | 144:ef7eb2e8f9f7 | 1331 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
<> | 144:ef7eb2e8f9f7 | 1332 | * @param __USART2CLKSOURCE__ specifies the USART2 clock source. |
<> | 144:ef7eb2e8f9f7 | 1333 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1334 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1335 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1336 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1337 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1338 | */ |
<> | 144:ef7eb2e8f9f7 | 1339 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 1340 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1341 | |
<> | 144:ef7eb2e8f9f7 | 1342 | /** @brief Macro to get the USART2 clock source. |
<> | 144:ef7eb2e8f9f7 | 1343 | * @retval The clock source can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1344 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1345 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1346 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1347 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
<> | 144:ef7eb2e8f9f7 | 1348 | */ |
<> | 144:ef7eb2e8f9f7 | 1349 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) |
<> | 144:ef7eb2e8f9f7 | 1350 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 144:ef7eb2e8f9f7 | 1351 | |
<> | 144:ef7eb2e8f9f7 | 1352 | #if defined(RCC_CFGR3_USART3SW) |
<> | 144:ef7eb2e8f9f7 | 1353 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
<> | 144:ef7eb2e8f9f7 | 1354 | * @param __USART3CLKSOURCE__ specifies the USART3 clock source. |
<> | 144:ef7eb2e8f9f7 | 1355 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1356 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1357 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1358 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1359 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1360 | */ |
<> | 144:ef7eb2e8f9f7 | 1361 | #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 1362 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1363 | |
<> | 144:ef7eb2e8f9f7 | 1364 | /** @brief Macro to get the USART3 clock source. |
<> | 144:ef7eb2e8f9f7 | 1365 | * @retval The clock source can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1366 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1367 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1368 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1369 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
<> | 144:ef7eb2e8f9f7 | 1370 | */ |
<> | 144:ef7eb2e8f9f7 | 1371 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) |
<> | 144:ef7eb2e8f9f7 | 1372 | #endif /* RCC_CFGR3_USART2SW */ |
<> | 144:ef7eb2e8f9f7 | 1373 | /** |
<> | 144:ef7eb2e8f9f7 | 1374 | * @} |
<> | 144:ef7eb2e8f9f7 | 1375 | */ |
<> | 144:ef7eb2e8f9f7 | 1376 | |
<> | 144:ef7eb2e8f9f7 | 1377 | /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config |
<> | 144:ef7eb2e8f9f7 | 1378 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1379 | */ |
<> | 144:ef7eb2e8f9f7 | 1380 | |
<> | 144:ef7eb2e8f9f7 | 1381 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
<> | 144:ef7eb2e8f9f7 | 1382 | * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. |
<> | 144:ef7eb2e8f9f7 | 1383 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1384 | * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock |
<> | 144:ef7eb2e8f9f7 | 1385 | * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock |
<> | 144:ef7eb2e8f9f7 | 1386 | */ |
<> | 144:ef7eb2e8f9f7 | 1387 | #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 1388 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1389 | |
<> | 144:ef7eb2e8f9f7 | 1390 | /** @brief Macro to get the I2C1 clock source. |
<> | 144:ef7eb2e8f9f7 | 1391 | * @retval The clock source can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1392 | * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock |
<> | 144:ef7eb2e8f9f7 | 1393 | * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock |
<> | 144:ef7eb2e8f9f7 | 1394 | */ |
<> | 144:ef7eb2e8f9f7 | 1395 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) |
<> | 144:ef7eb2e8f9f7 | 1396 | /** |
<> | 144:ef7eb2e8f9f7 | 1397 | * @} |
<> | 144:ef7eb2e8f9f7 | 1398 | */ |
<> | 144:ef7eb2e8f9f7 | 1399 | |
<> | 144:ef7eb2e8f9f7 | 1400 | /** @defgroup RCC_PLL_Configuration PLL Configuration |
<> | 144:ef7eb2e8f9f7 | 1401 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1402 | */ |
<> | 144:ef7eb2e8f9f7 | 1403 | |
<> | 144:ef7eb2e8f9f7 | 1404 | /** @brief Macro to enable the main PLL. |
<> | 144:ef7eb2e8f9f7 | 1405 | * @note After enabling the main PLL, the application software should wait on |
<> | 144:ef7eb2e8f9f7 | 1406 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
<> | 144:ef7eb2e8f9f7 | 1407 | * be used as system clock source. |
<> | 144:ef7eb2e8f9f7 | 1408 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
<> | 144:ef7eb2e8f9f7 | 1409 | */ |
<> | 144:ef7eb2e8f9f7 | 1410 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1411 | |
<> | 144:ef7eb2e8f9f7 | 1412 | /** @brief Macro to disable the main PLL. |
<> | 144:ef7eb2e8f9f7 | 1413 | * @note The main PLL can not be disabled if it is used as system clock source |
<> | 144:ef7eb2e8f9f7 | 1414 | */ |
<> | 144:ef7eb2e8f9f7 | 1415 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 1416 | |
<> | 144:ef7eb2e8f9f7 | 1417 | |
<> | 144:ef7eb2e8f9f7 | 1418 | /** @brief Get oscillator clock selected as PLL input clock |
<> | 144:ef7eb2e8f9f7 | 1419 | * @retval The clock source used for PLL entry. The returned value can be one |
<> | 144:ef7eb2e8f9f7 | 1420 | * of the following: |
<> | 144:ef7eb2e8f9f7 | 1421 | * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock |
<> | 144:ef7eb2e8f9f7 | 1422 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock |
<> | 144:ef7eb2e8f9f7 | 1423 | */ |
<> | 144:ef7eb2e8f9f7 | 1424 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
<> | 144:ef7eb2e8f9f7 | 1425 | |
<> | 144:ef7eb2e8f9f7 | 1426 | /** |
<> | 144:ef7eb2e8f9f7 | 1427 | * @} |
<> | 144:ef7eb2e8f9f7 | 1428 | */ |
<> | 144:ef7eb2e8f9f7 | 1429 | |
<> | 144:ef7eb2e8f9f7 | 1430 | /** @defgroup RCC_Get_Clock_source Get Clock source |
<> | 144:ef7eb2e8f9f7 | 1431 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1432 | */ |
<> | 144:ef7eb2e8f9f7 | 1433 | |
<> | 144:ef7eb2e8f9f7 | 1434 | /** |
<> | 144:ef7eb2e8f9f7 | 1435 | * @brief Macro to configure the system clock source. |
<> | 144:ef7eb2e8f9f7 | 1436 | * @param __SYSCLKSOURCE__ specifies the system clock source. |
<> | 144:ef7eb2e8f9f7 | 1437 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1438 | * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. |
<> | 144:ef7eb2e8f9f7 | 1439 | * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. |
<> | 144:ef7eb2e8f9f7 | 1440 | * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. |
<> | 144:ef7eb2e8f9f7 | 1441 | */ |
<> | 144:ef7eb2e8f9f7 | 1442 | #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ |
<> | 144:ef7eb2e8f9f7 | 1443 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1444 | |
<> | 144:ef7eb2e8f9f7 | 1445 | /** @brief Macro to get the clock source used as system clock. |
<> | 144:ef7eb2e8f9f7 | 1446 | * @retval The clock source used as system clock. The returned value can be one |
<> | 144:ef7eb2e8f9f7 | 1447 | * of the following: |
<> | 144:ef7eb2e8f9f7 | 1448 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock |
<> | 144:ef7eb2e8f9f7 | 1449 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock |
<> | 144:ef7eb2e8f9f7 | 1450 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock |
<> | 144:ef7eb2e8f9f7 | 1451 | */ |
<> | 144:ef7eb2e8f9f7 | 1452 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) |
<> | 144:ef7eb2e8f9f7 | 1453 | |
<> | 144:ef7eb2e8f9f7 | 1454 | /** |
<> | 144:ef7eb2e8f9f7 | 1455 | * @} |
<> | 144:ef7eb2e8f9f7 | 1456 | */ |
<> | 144:ef7eb2e8f9f7 | 1457 | |
<> | 144:ef7eb2e8f9f7 | 1458 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
<> | 144:ef7eb2e8f9f7 | 1459 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1460 | */ |
<> | 144:ef7eb2e8f9f7 | 1461 | |
<> | 144:ef7eb2e8f9f7 | 1462 | #if defined(RCC_CFGR_MCOPRE) |
<> | 144:ef7eb2e8f9f7 | 1463 | /** @brief Macro to configure the MCO clock. |
<> | 144:ef7eb2e8f9f7 | 1464 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
<> | 144:ef7eb2e8f9f7 | 1465 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1466 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1467 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1468 | * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1469 | * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1470 | * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1471 | * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1472 | * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1473 | * @param __MCODIV__ specifies the MCO clock prescaler. |
<> | 144:ef7eb2e8f9f7 | 1474 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1475 | * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 |
<> | 144:ef7eb2e8f9f7 | 1476 | * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 |
<> | 144:ef7eb2e8f9f7 | 1477 | * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 |
<> | 144:ef7eb2e8f9f7 | 1478 | * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 |
<> | 144:ef7eb2e8f9f7 | 1479 | * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 |
<> | 144:ef7eb2e8f9f7 | 1480 | * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 |
<> | 144:ef7eb2e8f9f7 | 1481 | * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 |
<> | 144:ef7eb2e8f9f7 | 1482 | * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 |
<> | 144:ef7eb2e8f9f7 | 1483 | */ |
<> | 144:ef7eb2e8f9f7 | 1484 | #else |
<> | 144:ef7eb2e8f9f7 | 1485 | /** @brief Macro to configure the MCO clock. |
<> | 144:ef7eb2e8f9f7 | 1486 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
<> | 144:ef7eb2e8f9f7 | 1487 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1488 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1489 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1490 | * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1491 | * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1492 | * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1493 | * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1494 | * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock |
<> | 144:ef7eb2e8f9f7 | 1495 | * @param __MCODIV__ specifies the MCO clock prescaler. |
<> | 144:ef7eb2e8f9f7 | 1496 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1497 | * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source |
<> | 144:ef7eb2e8f9f7 | 1498 | */ |
<> | 144:ef7eb2e8f9f7 | 1499 | #endif |
<> | 144:ef7eb2e8f9f7 | 1500 | #if defined(RCC_CFGR_MCOPRE) |
<> | 144:ef7eb2e8f9f7 | 1501 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
<> | 144:ef7eb2e8f9f7 | 1502 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) |
<> | 144:ef7eb2e8f9f7 | 1503 | #else |
<> | 144:ef7eb2e8f9f7 | 1504 | |
<> | 144:ef7eb2e8f9f7 | 1505 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
<> | 144:ef7eb2e8f9f7 | 1506 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1507 | |
<> | 144:ef7eb2e8f9f7 | 1508 | #endif |
<> | 144:ef7eb2e8f9f7 | 1509 | |
<> | 144:ef7eb2e8f9f7 | 1510 | /** |
<> | 144:ef7eb2e8f9f7 | 1511 | * @} |
<> | 144:ef7eb2e8f9f7 | 1512 | */ |
<> | 144:ef7eb2e8f9f7 | 1513 | |
<> | 144:ef7eb2e8f9f7 | 1514 | /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration |
<> | 144:ef7eb2e8f9f7 | 1515 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1516 | */ |
<> | 144:ef7eb2e8f9f7 | 1517 | |
<> | 144:ef7eb2e8f9f7 | 1518 | /** @brief Macro to configure the RTC clock (RTCCLK). |
<> | 144:ef7eb2e8f9f7 | 1519 | * @note As the RTC clock configuration bits are in the Backup domain and write |
<> | 144:ef7eb2e8f9f7 | 1520 | * access is denied to this domain after reset, you have to enable write |
<> | 144:ef7eb2e8f9f7 | 1521 | * access using the Power Backup Access macro before to configure |
<> | 144:ef7eb2e8f9f7 | 1522 | * the RTC clock source (to be done once after reset). |
<> | 144:ef7eb2e8f9f7 | 1523 | * @note Once the RTC clock is configured it cannot be changed unless the |
<> | 144:ef7eb2e8f9f7 | 1524 | * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by |
<> | 144:ef7eb2e8f9f7 | 1525 | * a Power On Reset (POR). |
<> | 144:ef7eb2e8f9f7 | 1526 | * |
<> | 144:ef7eb2e8f9f7 | 1527 | * @param __RTC_CLKSOURCE__ specifies the RTC clock source. |
<> | 144:ef7eb2e8f9f7 | 1528 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1529 | * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
<> | 144:ef7eb2e8f9f7 | 1530 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
<> | 144:ef7eb2e8f9f7 | 1531 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
<> | 144:ef7eb2e8f9f7 | 1532 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 |
<> | 144:ef7eb2e8f9f7 | 1533 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
<> | 144:ef7eb2e8f9f7 | 1534 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
<> | 144:ef7eb2e8f9f7 | 1535 | * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, |
<> | 144:ef7eb2e8f9f7 | 1536 | * the RTC cannot be used in STOP and STANDBY modes. |
<> | 144:ef7eb2e8f9f7 | 1537 | * @note The system must always be configured so as to get a PCLK frequency greater than or |
<> | 144:ef7eb2e8f9f7 | 1538 | * equal to the RTCCLK frequency for a proper operation of the RTC. |
<> | 144:ef7eb2e8f9f7 | 1539 | */ |
<> | 144:ef7eb2e8f9f7 | 1540 | #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) |
<> | 144:ef7eb2e8f9f7 | 1541 | |
<> | 144:ef7eb2e8f9f7 | 1542 | /** @brief Macro to get the RTC clock source. |
<> | 144:ef7eb2e8f9f7 | 1543 | * @retval The clock source can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1544 | * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
<> | 144:ef7eb2e8f9f7 | 1545 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
<> | 144:ef7eb2e8f9f7 | 1546 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
<> | 144:ef7eb2e8f9f7 | 1547 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 |
<> | 144:ef7eb2e8f9f7 | 1548 | */ |
<> | 144:ef7eb2e8f9f7 | 1549 | #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) |
<> | 144:ef7eb2e8f9f7 | 1550 | |
<> | 144:ef7eb2e8f9f7 | 1551 | /** @brief Macro to enable the the RTC clock. |
<> | 144:ef7eb2e8f9f7 | 1552 | * @note These macros must be used only after the RTC clock source was selected. |
<> | 144:ef7eb2e8f9f7 | 1553 | */ |
<> | 144:ef7eb2e8f9f7 | 1554 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1555 | |
<> | 144:ef7eb2e8f9f7 | 1556 | /** @brief Macro to disable the the RTC clock. |
<> | 144:ef7eb2e8f9f7 | 1557 | * @note These macros must be used only after the RTC clock source was selected. |
<> | 144:ef7eb2e8f9f7 | 1558 | */ |
<> | 144:ef7eb2e8f9f7 | 1559 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 1560 | |
<> | 144:ef7eb2e8f9f7 | 1561 | /** @brief Macro to force the Backup domain reset. |
<> | 144:ef7eb2e8f9f7 | 1562 | * @note This function resets the RTC peripheral (including the backup registers) |
<> | 144:ef7eb2e8f9f7 | 1563 | * and the RTC clock source selection in RCC_BDCR register. |
<> | 144:ef7eb2e8f9f7 | 1564 | */ |
<> | 144:ef7eb2e8f9f7 | 1565 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1566 | |
<> | 144:ef7eb2e8f9f7 | 1567 | /** @brief Macros to release the Backup domain reset. |
<> | 144:ef7eb2e8f9f7 | 1568 | */ |
<> | 144:ef7eb2e8f9f7 | 1569 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) |
<> | 144:ef7eb2e8f9f7 | 1570 | |
<> | 144:ef7eb2e8f9f7 | 1571 | /** |
<> | 144:ef7eb2e8f9f7 | 1572 | * @} |
<> | 144:ef7eb2e8f9f7 | 1573 | */ |
<> | 144:ef7eb2e8f9f7 | 1574 | |
<> | 144:ef7eb2e8f9f7 | 1575 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
<> | 144:ef7eb2e8f9f7 | 1576 | * @brief macros to manage the specified RCC Flags and interrupts. |
<> | 144:ef7eb2e8f9f7 | 1577 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1578 | */ |
<> | 144:ef7eb2e8f9f7 | 1579 | |
<> | 144:ef7eb2e8f9f7 | 1580 | /** @brief Enable RCC interrupt. |
<> | 144:ef7eb2e8f9f7 | 1581 | * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. |
<> | 144:ef7eb2e8f9f7 | 1582 | * This parameter can be any combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 1583 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1584 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1585 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1586 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1587 | * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1588 | */ |
<> | 144:ef7eb2e8f9f7 | 1589 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 1590 | |
<> | 144:ef7eb2e8f9f7 | 1591 | /** @brief Disable RCC interrupt. |
<> | 144:ef7eb2e8f9f7 | 1592 | * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. |
<> | 144:ef7eb2e8f9f7 | 1593 | * This parameter can be any combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 1594 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1595 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1596 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1597 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1598 | * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt |
<> | 144:ef7eb2e8f9f7 | 1599 | */ |
<> | 144:ef7eb2e8f9f7 | 1600 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
<> | 144:ef7eb2e8f9f7 | 1601 | |
<> | 144:ef7eb2e8f9f7 | 1602 | /** @brief Clear the RCC's interrupt pending bits. |
<> | 144:ef7eb2e8f9f7 | 1603 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
<> | 144:ef7eb2e8f9f7 | 1604 | * This parameter can be any combination of the following values: |
<> | 144:ef7eb2e8f9f7 | 1605 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1606 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1607 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1608 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1609 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1610 | * @arg @ref RCC_IT_CSS Clock Security System interrupt |
<> | 144:ef7eb2e8f9f7 | 1611 | */ |
<> | 144:ef7eb2e8f9f7 | 1612 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 1613 | |
<> | 144:ef7eb2e8f9f7 | 1614 | /** @brief Check the RCC's interrupt has occurred or not. |
<> | 144:ef7eb2e8f9f7 | 1615 | * @param __INTERRUPT__ specifies the RCC interrupt source to check. |
<> | 144:ef7eb2e8f9f7 | 1616 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1617 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1618 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1619 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1620 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1621 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. |
<> | 144:ef7eb2e8f9f7 | 1622 | * @arg @ref RCC_IT_CSS Clock Security System interrupt |
<> | 144:ef7eb2e8f9f7 | 1623 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 1624 | */ |
<> | 144:ef7eb2e8f9f7 | 1625 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 1626 | |
<> | 144:ef7eb2e8f9f7 | 1627 | /** @brief Set RMVF bit to clear the reset flags. |
<> | 144:ef7eb2e8f9f7 | 1628 | * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
<> | 144:ef7eb2e8f9f7 | 1629 | * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
<> | 144:ef7eb2e8f9f7 | 1630 | */ |
<> | 144:ef7eb2e8f9f7 | 1631 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1632 | |
<> | 144:ef7eb2e8f9f7 | 1633 | /** @brief Check RCC flag is set or not. |
<> | 144:ef7eb2e8f9f7 | 1634 | * @param __FLAG__ specifies the flag to check. |
<> | 144:ef7eb2e8f9f7 | 1635 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1636 | * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. |
<> | 144:ef7eb2e8f9f7 | 1637 | * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. |
<> | 144:ef7eb2e8f9f7 | 1638 | * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. |
<> | 144:ef7eb2e8f9f7 | 1639 | * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. |
<> | 144:ef7eb2e8f9f7 | 1640 | * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. |
<> | 144:ef7eb2e8f9f7 | 1641 | * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset |
<> | 144:ef7eb2e8f9f7 | 1642 | * @arg @ref RCC_FLAG_PINRST Pin reset. |
<> | 144:ef7eb2e8f9f7 | 1643 | * @arg @ref RCC_FLAG_PORRST POR/PDR reset. |
<> | 144:ef7eb2e8f9f7 | 1644 | * @arg @ref RCC_FLAG_SFTRST Software reset. |
<> | 144:ef7eb2e8f9f7 | 1645 | * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. |
<> | 144:ef7eb2e8f9f7 | 1646 | * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. |
<> | 144:ef7eb2e8f9f7 | 1647 | * @arg @ref RCC_FLAG_LPWRRST Low Power reset. |
<> | 144:ef7eb2e8f9f7 | 1648 | @if defined(STM32F301x8) |
<> | 144:ef7eb2e8f9f7 | 1649 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1650 | @endif |
<> | 144:ef7eb2e8f9f7 | 1651 | @if defined(STM32F302x8) |
<> | 144:ef7eb2e8f9f7 | 1652 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1653 | @endif |
<> | 144:ef7eb2e8f9f7 | 1654 | @if defined(STM32F302xC) |
<> | 144:ef7eb2e8f9f7 | 1655 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1656 | * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output |
<> | 144:ef7eb2e8f9f7 | 1657 | @endif |
<> | 144:ef7eb2e8f9f7 | 1658 | @if defined(STM32F302xE) |
<> | 144:ef7eb2e8f9f7 | 1659 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1660 | @endif |
<> | 144:ef7eb2e8f9f7 | 1661 | @if defined(STM32F303x8) |
<> | 144:ef7eb2e8f9f7 | 1662 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1663 | @endif |
<> | 144:ef7eb2e8f9f7 | 1664 | @if defined(STM32F303xC) |
<> | 144:ef7eb2e8f9f7 | 1665 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1666 | * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output |
<> | 144:ef7eb2e8f9f7 | 1667 | @endif |
<> | 144:ef7eb2e8f9f7 | 1668 | @if defined(STM32F303xE) |
<> | 144:ef7eb2e8f9f7 | 1669 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1670 | @endif |
<> | 144:ef7eb2e8f9f7 | 1671 | @if defined(STM32F334x8) |
<> | 144:ef7eb2e8f9f7 | 1672 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1673 | @endif |
<> | 144:ef7eb2e8f9f7 | 1674 | @if defined(STM32F358xx) |
<> | 144:ef7eb2e8f9f7 | 1675 | * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output |
<> | 144:ef7eb2e8f9f7 | 1676 | @endif |
<> | 144:ef7eb2e8f9f7 | 1677 | @if defined(STM32F373xC) |
<> | 144:ef7eb2e8f9f7 | 1678 | * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain |
<> | 144:ef7eb2e8f9f7 | 1679 | @endif |
<> | 144:ef7eb2e8f9f7 | 1680 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 1681 | */ |
<> | 144:ef7eb2e8f9f7 | 1682 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX) ? RCC->CR : \ |
<> | 144:ef7eb2e8f9f7 | 1683 | (((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \ |
<> | 144:ef7eb2e8f9f7 | 1684 | (((__FLAG__) >> 5) == CFGR_REG_INDEX)? RCC->CFGR : \ |
<> | 144:ef7eb2e8f9f7 | 1685 | RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) |
<> | 144:ef7eb2e8f9f7 | 1686 | |
<> | 144:ef7eb2e8f9f7 | 1687 | /** |
<> | 144:ef7eb2e8f9f7 | 1688 | * @} |
<> | 144:ef7eb2e8f9f7 | 1689 | */ |
<> | 144:ef7eb2e8f9f7 | 1690 | |
<> | 144:ef7eb2e8f9f7 | 1691 | /** |
<> | 144:ef7eb2e8f9f7 | 1692 | * @} |
<> | 144:ef7eb2e8f9f7 | 1693 | */ |
<> | 144:ef7eb2e8f9f7 | 1694 | |
<> | 144:ef7eb2e8f9f7 | 1695 | /* Include RCC HAL Extension module */ |
<> | 144:ef7eb2e8f9f7 | 1696 | #include "stm32f3xx_hal_rcc_ex.h" |
<> | 144:ef7eb2e8f9f7 | 1697 | |
<> | 144:ef7eb2e8f9f7 | 1698 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1699 | /** @addtogroup RCC_Exported_Functions |
<> | 144:ef7eb2e8f9f7 | 1700 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1701 | */ |
<> | 144:ef7eb2e8f9f7 | 1702 | |
<> | 144:ef7eb2e8f9f7 | 1703 | /** @addtogroup RCC_Exported_Functions_Group1 |
<> | 144:ef7eb2e8f9f7 | 1704 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1705 | */ |
<> | 144:ef7eb2e8f9f7 | 1706 | |
<> | 144:ef7eb2e8f9f7 | 1707 | /* Initialization and de-initialization functions ******************************/ |
<> | 144:ef7eb2e8f9f7 | 1708 | void HAL_RCC_DeInit(void); |
<> | 144:ef7eb2e8f9f7 | 1709 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
<> | 144:ef7eb2e8f9f7 | 1710 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
<> | 144:ef7eb2e8f9f7 | 1711 | |
<> | 144:ef7eb2e8f9f7 | 1712 | /** |
<> | 144:ef7eb2e8f9f7 | 1713 | * @} |
<> | 144:ef7eb2e8f9f7 | 1714 | */ |
<> | 144:ef7eb2e8f9f7 | 1715 | |
<> | 144:ef7eb2e8f9f7 | 1716 | /** @addtogroup RCC_Exported_Functions_Group2 |
<> | 144:ef7eb2e8f9f7 | 1717 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1718 | */ |
<> | 144:ef7eb2e8f9f7 | 1719 | |
<> | 144:ef7eb2e8f9f7 | 1720 | /* Peripheral Control functions ************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1721 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
<> | 144:ef7eb2e8f9f7 | 1722 | void HAL_RCC_EnableCSS(void); |
<> | 144:ef7eb2e8f9f7 | 1723 | void HAL_RCC_DisableCSS(void); |
<> | 144:ef7eb2e8f9f7 | 1724 | uint32_t HAL_RCC_GetSysClockFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1725 | uint32_t HAL_RCC_GetHCLKFreq(void); |
<> | 144:ef7eb2e8f9f7 | 1726 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
<> | 144:ef7eb2e8f9f7 | 1727 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
<> | 144:ef7eb2e8f9f7 | 1728 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
<> | 144:ef7eb2e8f9f7 | 1729 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
<> | 144:ef7eb2e8f9f7 | 1730 | |
<> | 144:ef7eb2e8f9f7 | 1731 | /* CSS NMI IRQ handler */ |
<> | 144:ef7eb2e8f9f7 | 1732 | void HAL_RCC_NMI_IRQHandler(void); |
<> | 144:ef7eb2e8f9f7 | 1733 | |
<> | 144:ef7eb2e8f9f7 | 1734 | /* User Callbacks in non blocking mode (IT mode) */ |
<> | 144:ef7eb2e8f9f7 | 1735 | void HAL_RCC_CSSCallback(void); |
<> | 144:ef7eb2e8f9f7 | 1736 | |
<> | 144:ef7eb2e8f9f7 | 1737 | /** |
<> | 144:ef7eb2e8f9f7 | 1738 | * @} |
<> | 144:ef7eb2e8f9f7 | 1739 | */ |
<> | 144:ef7eb2e8f9f7 | 1740 | |
<> | 144:ef7eb2e8f9f7 | 1741 | /** |
<> | 144:ef7eb2e8f9f7 | 1742 | * @} |
<> | 144:ef7eb2e8f9f7 | 1743 | */ |
<> | 144:ef7eb2e8f9f7 | 1744 | |
<> | 144:ef7eb2e8f9f7 | 1745 | /** |
<> | 144:ef7eb2e8f9f7 | 1746 | * @} |
<> | 144:ef7eb2e8f9f7 | 1747 | */ |
<> | 144:ef7eb2e8f9f7 | 1748 | |
<> | 144:ef7eb2e8f9f7 | 1749 | /** |
<> | 144:ef7eb2e8f9f7 | 1750 | * @} |
<> | 144:ef7eb2e8f9f7 | 1751 | */ |
<> | 144:ef7eb2e8f9f7 | 1752 | |
<> | 144:ef7eb2e8f9f7 | 1753 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 1754 | } |
<> | 144:ef7eb2e8f9f7 | 1755 | #endif |
<> | 144:ef7eb2e8f9f7 | 1756 | |
<> | 144:ef7eb2e8f9f7 | 1757 | #endif /* __STM32F3xx_HAL_RCC_H */ |
<> | 144:ef7eb2e8f9f7 | 1758 | |
<> | 144:ef7eb2e8f9f7 | 1759 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
<> | 144:ef7eb2e8f9f7 | 1760 |