pravin sarode / Mymbed-dev

MBED-DEV only fro Nucleo STM32F303K8T6

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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr_ex.h@151:acf04f8e7d03, 2016-11-19 (annotated)

Committer:
pravinautosys
Date:
Sat Nov 19 10:38:54 2016 +0000
Revision:
151:acf04f8e7d03
Parent:
149:156823d33999 
MyMBED-DEVWithSTM32F303K8T6;

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<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_pwr_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of PWR HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F3xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F3xx_HAL_PWR_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f3xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup PWREx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #if defined(STM32F302xE) || defined(STM32F303xE) || \
<> 144:ef7eb2e8f9f7 63 defined(STM32F302xC) || defined(STM32F303xC) || \
<> 144:ef7eb2e8f9f7 64 defined(STM32F303x8) || defined(STM32F334x8) || \
<> 144:ef7eb2e8f9f7 65 defined(STM32F301x8) || defined(STM32F302x8) || \
<> 144:ef7eb2e8f9f7 66 defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief PWR PVD configuration structure definition
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 typedef struct
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref PWREx_PVD_detection_level */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref PWREx_PVD_Mode */
<> 144:ef7eb2e8f9f7 77 }PWR_PVDTypeDef;
<> 144:ef7eb2e8f9f7 78 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 79 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 80 /* STM32F303x8 || STM32F334x8 || */
<> 144:ef7eb2e8f9f7 81 /* STM32F301x8 || STM32F302x8 || */
<> 144:ef7eb2e8f9f7 82 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /**
<> 144:ef7eb2e8f9f7 85 * @}
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 89 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #if defined(STM32F302xE) || defined(STM32F303xE) || \
<> 144:ef7eb2e8f9f7 94 defined(STM32F302xC) || defined(STM32F303xC) || \
<> 144:ef7eb2e8f9f7 95 defined(STM32F303x8) || defined(STM32F334x8) || \
<> 144:ef7eb2e8f9f7 96 defined(STM32F301x8) || defined(STM32F302x8) || \
<> 144:ef7eb2e8f9f7 97 defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */
<> 144:ef7eb2e8f9f7 103 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */
<> 144:ef7eb2e8f9f7 104 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */
<> 144:ef7eb2e8f9f7 105 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */
<> 144:ef7eb2e8f9f7 106 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */
<> 144:ef7eb2e8f9f7 107 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */
<> 144:ef7eb2e8f9f7 108 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */
<> 144:ef7eb2e8f9f7 109 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
<> 144:ef7eb2e8f9f7 115 * @{
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
<> 144:ef7eb2e8f9f7 118 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 119 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 120 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 121 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
<> 144:ef7eb2e8f9f7 122 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 123 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 131 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 132 /* STM32F303x8 || STM32F334x8 || */
<> 144:ef7eb2e8f9f7 133 /* STM32F301x8 || STM32F302x8 || */
<> 144:ef7eb2e8f9f7 134 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 137 /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_SDADC1EN) /*!< Enable SDADC1 */
<> 144:ef7eb2e8f9f7 141 #define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_SDADC2EN) /*!< Enable SDADC2 */
<> 144:ef7eb2e8f9f7 142 #define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_SDADC3EN) /*!< Enable SDADC3 */
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @}
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 153 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #if defined(STM32F302xE) || defined(STM32F303xE) || \
<> 144:ef7eb2e8f9f7 158 defined(STM32F302xC) || defined(STM32F303xC) || \
<> 144:ef7eb2e8f9f7 159 defined(STM32F303x8) || defined(STM32F334x8) || \
<> 144:ef7eb2e8f9f7 160 defined(STM32F301x8) || defined(STM32F302x8) || \
<> 144:ef7eb2e8f9f7 161 defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Enable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 165 * @retval None.
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @brief Disable interrupt on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 171 * @retval None.
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 177 * @retval None.
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief Enable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 183 * @retval None.
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @brief Disable event on PVD Exti Line 16.
<> 144:ef7eb2e8f9f7 189 * @retval None.
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @brief Disable the PVD Extended Interrupt Rising Trigger.
<> 144:ef7eb2e8f9f7 195 * @retval None.
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @brief Disable the PVD Extended Interrupt Falling Trigger.
<> 144:ef7eb2e8f9f7 201 * @retval None.
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 207 * @retval None
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @brief PVD EXTI line configuration: set falling edge trigger.
<> 144:ef7eb2e8f9f7 213 * @retval None.
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief PVD EXTI line configuration: set rising edge trigger.
<> 144:ef7eb2e8f9f7 219 * @retval None.
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
<> 144:ef7eb2e8f9f7 225 * @retval None
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /**
<> 144:ef7eb2e8f9f7 230 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
<> 144:ef7eb2e8f9f7 231 * @retval EXTI PVD Line Status.
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Clear the PVD EXTI flag.
<> 144:ef7eb2e8f9f7 237 * @retval None.
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 242 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 243 /* STM32F303x8 || STM32F334x8 || */
<> 144:ef7eb2e8f9f7 244 /* STM32F301x8 || STM32F302x8 || */
<> 144:ef7eb2e8f9f7 245 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 252 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #if defined(STM32F302xE) || defined(STM32F303xE) || \
<> 144:ef7eb2e8f9f7 257 defined(STM32F302xC) || defined(STM32F303xC) || \
<> 144:ef7eb2e8f9f7 258 defined(STM32F303x8) || defined(STM32F334x8) || \
<> 144:ef7eb2e8f9f7 259 defined(STM32F301x8) || defined(STM32F302x8) || \
<> 144:ef7eb2e8f9f7 260 defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 261 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
<> 144:ef7eb2e8f9f7 262 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
<> 144:ef7eb2e8f9f7 263 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
<> 144:ef7eb2e8f9f7 264 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
<> 144:ef7eb2e8f9f7 267 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
<> 144:ef7eb2e8f9f7 268 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
<> 144:ef7eb2e8f9f7 269 ((MODE) == PWR_PVD_MODE_NORMAL))
<> 144:ef7eb2e8f9f7 270 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 271 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 272 /* STM32F303x8 || STM32F334x8 || */
<> 144:ef7eb2e8f9f7 273 /* STM32F301x8 || STM32F302x8 || */
<> 144:ef7eb2e8f9f7 274 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 277 #define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
<> 144:ef7eb2e8f9f7 278 ((SDADC) == PWR_SDADC_ANALOG2) || \
<> 144:ef7eb2e8f9f7 279 ((SDADC) == PWR_SDADC_ANALOG3))
<> 144:ef7eb2e8f9f7 280 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 /* Peripheral Extended control functions **************************************/
<> 144:ef7eb2e8f9f7 297 #if defined(STM32F302xE) || defined(STM32F303xE) || \
<> 144:ef7eb2e8f9f7 298 defined(STM32F302xC) || defined(STM32F303xC) || \
<> 144:ef7eb2e8f9f7 299 defined(STM32F303x8) || defined(STM32F334x8) || \
<> 144:ef7eb2e8f9f7 300 defined(STM32F301x8) || defined(STM32F302x8) || \
<> 144:ef7eb2e8f9f7 301 defined(STM32F373xC)
<> 144:ef7eb2e8f9f7 302 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
<> 144:ef7eb2e8f9f7 303 void HAL_PWR_EnablePVD(void);
<> 144:ef7eb2e8f9f7 304 void HAL_PWR_DisablePVD(void);
<> 144:ef7eb2e8f9f7 305 void HAL_PWR_PVD_IRQHandler(void);
<> 144:ef7eb2e8f9f7 306 void HAL_PWR_PVDCallback(void);
<> 144:ef7eb2e8f9f7 307 #endif /* STM32F302xE || STM32F303xE || */
<> 144:ef7eb2e8f9f7 308 /* STM32F302xC || STM32F303xC || */
<> 144:ef7eb2e8f9f7 309 /* STM32F303x8 || STM32F334x8 || */
<> 144:ef7eb2e8f9f7 310 /* STM32F301x8 || STM32F302x8 || */
<> 144:ef7eb2e8f9f7 311 /* STM32F373xC */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #if defined(STM32F373xC) || defined(STM32F378xx)
<> 144:ef7eb2e8f9f7 314 void HAL_PWREx_EnableSDADC(uint32_t Analogx);
<> 144:ef7eb2e8f9f7 315 void HAL_PWREx_DisableSDADC(uint32_t Analogx);
<> 144:ef7eb2e8f9f7 316 #endif /* STM32F373xC || STM32F378xx */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @}
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @}
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 #endif
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #endif /* __STM32F3xx_HAL_PWR_EX_H */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/