MBED-DEV only fro Nucleo STM32F303K8T6
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.c@151:acf04f8e7d03, 2016-11-19 (annotated)
- Committer:
- pravinautosys
- Date:
- Sat Nov 19 10:38:54 2016 +0000
- Revision:
- 151:acf04f8e7d03
- Parent:
- 149:156823d33999
MyMBED-DEVWithSTM32F303K8T6;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f3xx_hal_nor.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.3.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 01-July-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief NOR HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides a generic firmware to drive NOR memories mounted |
<> | 144:ef7eb2e8f9f7 | 9 | * as external device. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 12 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 13 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 14 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | [..] |
<> | 144:ef7eb2e8f9f7 | 16 | This driver is a generic layered driver which contains a set of APIs used to |
<> | 144:ef7eb2e8f9f7 | 17 | control NOR flash memories. It uses the FMC layer functions to interface |
<> | 144:ef7eb2e8f9f7 | 18 | with NOR devices. This driver is used as follows: |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() |
<> | 144:ef7eb2e8f9f7 | 21 | with control and timing parameters for both normal and extended mode. |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | (+) Read NOR flash memory manufacturer code and device IDs using the function |
<> | 144:ef7eb2e8f9f7 | 24 | HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef |
<> | 144:ef7eb2e8f9f7 | 25 | structure declared by the function caller. |
<> | 144:ef7eb2e8f9f7 | 26 | |
<> | 144:ef7eb2e8f9f7 | 27 | (+) Access NOR flash memory by read/write data unit operations using the functions |
<> | 144:ef7eb2e8f9f7 | 28 | HAL_NOR_Read(), HAL_NOR_Program(). |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | (+) Perform NOR flash erase block/chip operations using the functions |
<> | 144:ef7eb2e8f9f7 | 31 | HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | (+) Read the NOR flash CFI (common flash interface) IDs using the function |
<> | 144:ef7eb2e8f9f7 | 34 | HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef |
<> | 144:ef7eb2e8f9f7 | 35 | structure declared by the function caller. |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ |
<> | 144:ef7eb2e8f9f7 | 38 | HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | (+) You can monitor the NOR device HAL state by calling the function |
<> | 144:ef7eb2e8f9f7 | 41 | HAL_NOR_GetState() |
<> | 144:ef7eb2e8f9f7 | 42 | [..] |
<> | 144:ef7eb2e8f9f7 | 43 | (@) This driver is a set of generic APIs which handle standard NOR flash operations. |
<> | 144:ef7eb2e8f9f7 | 44 | If a NOR flash device contains different operations and/or implementations, |
<> | 144:ef7eb2e8f9f7 | 45 | it should be implemented separately. |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | *** NOR HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 48 | ============================================= |
<> | 144:ef7eb2e8f9f7 | 49 | [..] |
<> | 144:ef7eb2e8f9f7 | 50 | Below the list of most used macros in NOR HAL driver. |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | (+) NOR_WRITE: NOR memory write data to specified address |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 55 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 56 | * @attention |
<> | 144:ef7eb2e8f9f7 | 57 | * |
<> | 144:ef7eb2e8f9f7 | 58 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 59 | * |
<> | 144:ef7eb2e8f9f7 | 60 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 61 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 62 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 63 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 65 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 66 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 68 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 69 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 70 | * |
<> | 144:ef7eb2e8f9f7 | 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 81 | * |
<> | 144:ef7eb2e8f9f7 | 82 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 83 | */ |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 86 | #include "stm32f3xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /** @addtogroup STM32F3xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 91 | * @{ |
<> | 144:ef7eb2e8f9f7 | 92 | */ |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | #ifdef HAL_NOR_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 95 | /** @defgroup NOR NOR |
<> | 144:ef7eb2e8f9f7 | 96 | * @brief NOR HAL module driver |
<> | 144:ef7eb2e8f9f7 | 97 | * @{ |
<> | 144:ef7eb2e8f9f7 | 98 | */ |
<> | 144:ef7eb2e8f9f7 | 99 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 100 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 101 | /** @defgroup NOR_Private_Constants NOR Private Constants |
<> | 144:ef7eb2e8f9f7 | 102 | * @{ |
<> | 144:ef7eb2e8f9f7 | 103 | */ |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | /* Constants to define address to set to write a command */ |
<> | 144:ef7eb2e8f9f7 | 106 | #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 |
<> | 144:ef7eb2e8f9f7 | 107 | #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 |
<> | 144:ef7eb2e8f9f7 | 108 | #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA |
<> | 144:ef7eb2e8f9f7 | 109 | #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 |
<> | 144:ef7eb2e8f9f7 | 110 | #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 |
<> | 144:ef7eb2e8f9f7 | 111 | #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA |
<> | 144:ef7eb2e8f9f7 | 112 | #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 144:ef7eb2e8f9f7 | 114 | /* Constants to define data to program a command */ |
<> | 144:ef7eb2e8f9f7 | 115 | #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 |
<> | 144:ef7eb2e8f9f7 | 116 | #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA |
<> | 144:ef7eb2e8f9f7 | 117 | #define NOR_CMD_DATA_SECOND (uint16_t)0x0055 |
<> | 144:ef7eb2e8f9f7 | 118 | #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 |
<> | 144:ef7eb2e8f9f7 | 119 | #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 |
<> | 144:ef7eb2e8f9f7 | 120 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 |
<> | 144:ef7eb2e8f9f7 | 121 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA |
<> | 144:ef7eb2e8f9f7 | 122 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 |
<> | 144:ef7eb2e8f9f7 | 123 | #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 |
<> | 144:ef7eb2e8f9f7 | 124 | #define NOR_CMD_DATA_CFI (uint16_t)0x0098 |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 |
<> | 144:ef7eb2e8f9f7 | 127 | #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 |
<> | 144:ef7eb2e8f9f7 | 128 | #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | /* Mask on NOR STATUS REGISTER */ |
<> | 144:ef7eb2e8f9f7 | 131 | #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 |
<> | 144:ef7eb2e8f9f7 | 132 | #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | /** |
<> | 144:ef7eb2e8f9f7 | 135 | * @} |
<> | 144:ef7eb2e8f9f7 | 136 | */ |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 139 | /** @defgroup NOR_Private_Macros NOR Private Macros |
<> | 144:ef7eb2e8f9f7 | 140 | * @{ |
<> | 144:ef7eb2e8f9f7 | 141 | */ |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | /** |
<> | 144:ef7eb2e8f9f7 | 144 | * @} |
<> | 144:ef7eb2e8f9f7 | 145 | */ |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | /** @defgroup NOR_Private_Variables NOR Private Variables |
<> | 144:ef7eb2e8f9f7 | 150 | * @{ |
<> | 144:ef7eb2e8f9f7 | 151 | */ |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | /** |
<> | 144:ef7eb2e8f9f7 | 156 | * @} |
<> | 144:ef7eb2e8f9f7 | 157 | */ |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | /** @defgroup NOR_Exported_Functions NOR Exported Functions |
<> | 144:ef7eb2e8f9f7 | 162 | * @{ |
<> | 144:ef7eb2e8f9f7 | 163 | */ |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 166 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 167 | * |
<> | 144:ef7eb2e8f9f7 | 168 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 169 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 170 | ##### NOR Initialization and de_initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 171 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 172 | [..] |
<> | 144:ef7eb2e8f9f7 | 173 | This section provides functions allowing to initialize/de-initialize |
<> | 144:ef7eb2e8f9f7 | 174 | the NOR memory |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 177 | * @{ |
<> | 144:ef7eb2e8f9f7 | 178 | */ |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | /** |
<> | 144:ef7eb2e8f9f7 | 181 | * @brief Perform the NOR memory Initialization sequence |
<> | 144:ef7eb2e8f9f7 | 182 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 183 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 184 | * @param Timing: pointer to NOR control timing structure |
<> | 144:ef7eb2e8f9f7 | 185 | * @param ExtTiming: pointer to NOR extended mode timing structure |
<> | 144:ef7eb2e8f9f7 | 186 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 187 | */ |
<> | 144:ef7eb2e8f9f7 | 188 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) |
<> | 144:ef7eb2e8f9f7 | 189 | { |
<> | 144:ef7eb2e8f9f7 | 190 | /* Check the NOR handle parameter */ |
<> | 144:ef7eb2e8f9f7 | 191 | if(hnor == NULL) |
<> | 144:ef7eb2e8f9f7 | 192 | { |
<> | 144:ef7eb2e8f9f7 | 193 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 194 | } |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | if(hnor->State == HAL_NOR_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 197 | { |
<> | 144:ef7eb2e8f9f7 | 198 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 199 | hnor->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 200 | |
<> | 144:ef7eb2e8f9f7 | 201 | /* Initialize the low level hardware (MSP) */ |
<> | 144:ef7eb2e8f9f7 | 202 | HAL_NOR_MspInit(hnor); |
<> | 144:ef7eb2e8f9f7 | 203 | } |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | /* Initialize NOR control Interface */ |
<> | 144:ef7eb2e8f9f7 | 206 | FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | /* Initialize NOR timing Interface */ |
<> | 144:ef7eb2e8f9f7 | 209 | FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | /* Initialize NOR extended mode timing Interface */ |
<> | 144:ef7eb2e8f9f7 | 212 | FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); |
<> | 144:ef7eb2e8f9f7 | 213 | |
<> | 144:ef7eb2e8f9f7 | 214 | /* Enable the NORSRAM device */ |
<> | 144:ef7eb2e8f9f7 | 215 | __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | /* Initialize NOR Memory Data Width*/ |
<> | 144:ef7eb2e8f9f7 | 218 | if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) |
<> | 144:ef7eb2e8f9f7 | 219 | { |
<> | 144:ef7eb2e8f9f7 | 220 | uwNORMemoryDataWidth = NOR_MEMORY_8B; |
<> | 144:ef7eb2e8f9f7 | 221 | } |
<> | 144:ef7eb2e8f9f7 | 222 | else |
<> | 144:ef7eb2e8f9f7 | 223 | { |
<> | 144:ef7eb2e8f9f7 | 224 | uwNORMemoryDataWidth = NOR_MEMORY_16B; |
<> | 144:ef7eb2e8f9f7 | 225 | } |
<> | 144:ef7eb2e8f9f7 | 226 | |
<> | 144:ef7eb2e8f9f7 | 227 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 228 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 229 | |
<> | 144:ef7eb2e8f9f7 | 230 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | /** |
<> | 144:ef7eb2e8f9f7 | 234 | * @brief Perform NOR memory De-Initialization sequence |
<> | 144:ef7eb2e8f9f7 | 235 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 236 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 237 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 238 | */ |
<> | 144:ef7eb2e8f9f7 | 239 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 240 | { |
<> | 144:ef7eb2e8f9f7 | 241 | /* De-Initialize the low level hardware (MSP) */ |
<> | 144:ef7eb2e8f9f7 | 242 | HAL_NOR_MspDeInit(hnor); |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | /* Configure the NOR registers with their reset values */ |
<> | 144:ef7eb2e8f9f7 | 245 | FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 248 | hnor->State = HAL_NOR_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 251 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 254 | } |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | /** |
<> | 144:ef7eb2e8f9f7 | 257 | * @brief NOR MSP Init |
<> | 144:ef7eb2e8f9f7 | 258 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 259 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 260 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 261 | */ |
<> | 144:ef7eb2e8f9f7 | 262 | __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 263 | { |
<> | 144:ef7eb2e8f9f7 | 264 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 265 | UNUSED(hnor); |
<> | 144:ef7eb2e8f9f7 | 266 | |
<> | 144:ef7eb2e8f9f7 | 267 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 268 | the HAL_NOR_MspInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 269 | */ |
<> | 144:ef7eb2e8f9f7 | 270 | } |
<> | 144:ef7eb2e8f9f7 | 271 | |
<> | 144:ef7eb2e8f9f7 | 272 | /** |
<> | 144:ef7eb2e8f9f7 | 273 | * @brief NOR MSP DeInit |
<> | 144:ef7eb2e8f9f7 | 274 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 275 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 276 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 277 | */ |
<> | 144:ef7eb2e8f9f7 | 278 | __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 279 | { |
<> | 144:ef7eb2e8f9f7 | 280 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 281 | UNUSED(hnor); |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 284 | the HAL_NOR_MspDeInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 285 | */ |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | /** |
<> | 144:ef7eb2e8f9f7 | 289 | * @brief NOR MSP Wait fro Ready/Busy signal |
<> | 144:ef7eb2e8f9f7 | 290 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 291 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 292 | * @param Timeout: Maximum timeout value |
<> | 144:ef7eb2e8f9f7 | 293 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 294 | */ |
<> | 144:ef7eb2e8f9f7 | 295 | __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 296 | { |
<> | 144:ef7eb2e8f9f7 | 297 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 298 | UNUSED(hnor); |
<> | 144:ef7eb2e8f9f7 | 299 | UNUSED(Timeout); |
<> | 144:ef7eb2e8f9f7 | 300 | |
<> | 144:ef7eb2e8f9f7 | 301 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 302 | the HAL_NOR_MspWait could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 303 | */ |
<> | 144:ef7eb2e8f9f7 | 304 | } |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | /** |
<> | 144:ef7eb2e8f9f7 | 307 | * @} |
<> | 144:ef7eb2e8f9f7 | 308 | */ |
<> | 144:ef7eb2e8f9f7 | 309 | |
<> | 144:ef7eb2e8f9f7 | 310 | /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions |
<> | 144:ef7eb2e8f9f7 | 311 | * @brief Input Output and memory control functions |
<> | 144:ef7eb2e8f9f7 | 312 | * |
<> | 144:ef7eb2e8f9f7 | 313 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 314 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 315 | ##### NOR Input and Output functions ##### |
<> | 144:ef7eb2e8f9f7 | 316 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 317 | [..] |
<> | 144:ef7eb2e8f9f7 | 318 | This section provides functions allowing to use and control the NOR memory |
<> | 144:ef7eb2e8f9f7 | 319 | |
<> | 144:ef7eb2e8f9f7 | 320 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 321 | * @{ |
<> | 144:ef7eb2e8f9f7 | 322 | */ |
<> | 144:ef7eb2e8f9f7 | 323 | |
<> | 144:ef7eb2e8f9f7 | 324 | /** |
<> | 144:ef7eb2e8f9f7 | 325 | * @brief Read NOR flash IDs |
<> | 144:ef7eb2e8f9f7 | 326 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 327 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 328 | * @param pNOR_ID: pointer to NOR ID structure |
<> | 144:ef7eb2e8f9f7 | 329 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 330 | */ |
<> | 144:ef7eb2e8f9f7 | 331 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) |
<> | 144:ef7eb2e8f9f7 | 332 | { |
<> | 144:ef7eb2e8f9f7 | 333 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 336 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 337 | |
<> | 144:ef7eb2e8f9f7 | 338 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 339 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 340 | { |
<> | 144:ef7eb2e8f9f7 | 341 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 342 | } |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 345 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 346 | { |
<> | 144:ef7eb2e8f9f7 | 347 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 348 | } |
<> | 144:ef7eb2e8f9f7 | 349 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 350 | { |
<> | 144:ef7eb2e8f9f7 | 351 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 352 | } |
<> | 144:ef7eb2e8f9f7 | 353 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 354 | { |
<> | 144:ef7eb2e8f9f7 | 355 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 356 | } |
<> | 144:ef7eb2e8f9f7 | 357 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 358 | { |
<> | 144:ef7eb2e8f9f7 | 359 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 360 | } |
<> | 144:ef7eb2e8f9f7 | 361 | |
<> | 144:ef7eb2e8f9f7 | 362 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 363 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | /* Send read ID command */ |
<> | 144:ef7eb2e8f9f7 | 366 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 367 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 368 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | /* Read the NOR IDs */ |
<> | 144:ef7eb2e8f9f7 | 371 | pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); |
<> | 144:ef7eb2e8f9f7 | 372 | pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); |
<> | 144:ef7eb2e8f9f7 | 373 | pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); |
<> | 144:ef7eb2e8f9f7 | 374 | pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); |
<> | 144:ef7eb2e8f9f7 | 375 | |
<> | 144:ef7eb2e8f9f7 | 376 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 377 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 380 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 383 | } |
<> | 144:ef7eb2e8f9f7 | 384 | |
<> | 144:ef7eb2e8f9f7 | 385 | /** |
<> | 144:ef7eb2e8f9f7 | 386 | * @brief Returns the NOR memory to Read mode. |
<> | 144:ef7eb2e8f9f7 | 387 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 388 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 389 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 390 | */ |
<> | 144:ef7eb2e8f9f7 | 391 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 392 | { |
<> | 144:ef7eb2e8f9f7 | 393 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 394 | |
<> | 144:ef7eb2e8f9f7 | 395 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 396 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 399 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 400 | { |
<> | 144:ef7eb2e8f9f7 | 401 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 402 | } |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 405 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 406 | { |
<> | 144:ef7eb2e8f9f7 | 407 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 408 | } |
<> | 144:ef7eb2e8f9f7 | 409 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 410 | { |
<> | 144:ef7eb2e8f9f7 | 411 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 412 | } |
<> | 144:ef7eb2e8f9f7 | 413 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 414 | { |
<> | 144:ef7eb2e8f9f7 | 415 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 416 | } |
<> | 144:ef7eb2e8f9f7 | 417 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 418 | { |
<> | 144:ef7eb2e8f9f7 | 419 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 420 | } |
<> | 144:ef7eb2e8f9f7 | 421 | |
<> | 144:ef7eb2e8f9f7 | 422 | NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); |
<> | 144:ef7eb2e8f9f7 | 423 | |
<> | 144:ef7eb2e8f9f7 | 424 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 425 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 428 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 431 | } |
<> | 144:ef7eb2e8f9f7 | 432 | |
<> | 144:ef7eb2e8f9f7 | 433 | /** |
<> | 144:ef7eb2e8f9f7 | 434 | * @brief Read data from NOR memory |
<> | 144:ef7eb2e8f9f7 | 435 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 436 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 437 | * @param pAddress: pointer to Device address |
<> | 144:ef7eb2e8f9f7 | 438 | * @param pData: pointer to read data |
<> | 144:ef7eb2e8f9f7 | 439 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 440 | */ |
<> | 144:ef7eb2e8f9f7 | 441 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
<> | 144:ef7eb2e8f9f7 | 442 | { |
<> | 144:ef7eb2e8f9f7 | 443 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 446 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 447 | |
<> | 144:ef7eb2e8f9f7 | 448 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 449 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 450 | { |
<> | 144:ef7eb2e8f9f7 | 451 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 452 | } |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 455 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 456 | { |
<> | 144:ef7eb2e8f9f7 | 457 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 458 | } |
<> | 144:ef7eb2e8f9f7 | 459 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 460 | { |
<> | 144:ef7eb2e8f9f7 | 461 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 464 | { |
<> | 144:ef7eb2e8f9f7 | 465 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 466 | } |
<> | 144:ef7eb2e8f9f7 | 467 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 468 | { |
<> | 144:ef7eb2e8f9f7 | 469 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 470 | } |
<> | 144:ef7eb2e8f9f7 | 471 | |
<> | 144:ef7eb2e8f9f7 | 472 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 473 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 474 | |
<> | 144:ef7eb2e8f9f7 | 475 | /* Send read data command */ |
<> | 144:ef7eb2e8f9f7 | 476 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 477 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 478 | NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET); |
<> | 144:ef7eb2e8f9f7 | 479 | |
<> | 144:ef7eb2e8f9f7 | 480 | /* Read the data */ |
<> | 144:ef7eb2e8f9f7 | 481 | *pData = *(__IO uint32_t *)(uint32_t)pAddress; |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 484 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 485 | |
<> | 144:ef7eb2e8f9f7 | 486 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 487 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 488 | |
<> | 144:ef7eb2e8f9f7 | 489 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 490 | } |
<> | 144:ef7eb2e8f9f7 | 491 | |
<> | 144:ef7eb2e8f9f7 | 492 | /** |
<> | 144:ef7eb2e8f9f7 | 493 | * @brief Program data to NOR memory |
<> | 144:ef7eb2e8f9f7 | 494 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 495 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 496 | * @param pAddress: Device address |
<> | 144:ef7eb2e8f9f7 | 497 | * @param pData: pointer to the data to write |
<> | 144:ef7eb2e8f9f7 | 498 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 499 | */ |
<> | 144:ef7eb2e8f9f7 | 500 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
<> | 144:ef7eb2e8f9f7 | 501 | { |
<> | 144:ef7eb2e8f9f7 | 502 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 503 | |
<> | 144:ef7eb2e8f9f7 | 504 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 505 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 506 | |
<> | 144:ef7eb2e8f9f7 | 507 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 508 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 509 | { |
<> | 144:ef7eb2e8f9f7 | 510 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 511 | } |
<> | 144:ef7eb2e8f9f7 | 512 | |
<> | 144:ef7eb2e8f9f7 | 513 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 514 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 515 | { |
<> | 144:ef7eb2e8f9f7 | 516 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 517 | } |
<> | 144:ef7eb2e8f9f7 | 518 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 519 | { |
<> | 144:ef7eb2e8f9f7 | 520 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 521 | } |
<> | 144:ef7eb2e8f9f7 | 522 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 523 | { |
<> | 144:ef7eb2e8f9f7 | 524 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 525 | } |
<> | 144:ef7eb2e8f9f7 | 526 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 527 | { |
<> | 144:ef7eb2e8f9f7 | 528 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 529 | } |
<> | 144:ef7eb2e8f9f7 | 530 | |
<> | 144:ef7eb2e8f9f7 | 531 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 532 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | /* Send program data command */ |
<> | 144:ef7eb2e8f9f7 | 535 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 536 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 537 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); |
<> | 144:ef7eb2e8f9f7 | 538 | |
<> | 144:ef7eb2e8f9f7 | 539 | /* Write the data */ |
<> | 144:ef7eb2e8f9f7 | 540 | NOR_WRITE(pAddress, *pData); |
<> | 144:ef7eb2e8f9f7 | 541 | |
<> | 144:ef7eb2e8f9f7 | 542 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 543 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 544 | |
<> | 144:ef7eb2e8f9f7 | 545 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 546 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 547 | |
<> | 144:ef7eb2e8f9f7 | 548 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 549 | } |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /** |
<> | 144:ef7eb2e8f9f7 | 552 | * @brief Reads a block of data from the FMC NOR memory. |
<> | 144:ef7eb2e8f9f7 | 553 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 554 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 555 | * @param uwAddress: NOR memory internal address to read from. |
<> | 144:ef7eb2e8f9f7 | 556 | * @param pData: pointer to the buffer that receives the data read from the |
<> | 144:ef7eb2e8f9f7 | 557 | * NOR memory. |
<> | 144:ef7eb2e8f9f7 | 558 | * @param uwBufferSize: number of Half word to read. |
<> | 144:ef7eb2e8f9f7 | 559 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 560 | */ |
<> | 144:ef7eb2e8f9f7 | 561 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
<> | 144:ef7eb2e8f9f7 | 562 | { |
<> | 144:ef7eb2e8f9f7 | 563 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 566 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 567 | |
<> | 144:ef7eb2e8f9f7 | 568 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 569 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 570 | { |
<> | 144:ef7eb2e8f9f7 | 571 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 572 | } |
<> | 144:ef7eb2e8f9f7 | 573 | |
<> | 144:ef7eb2e8f9f7 | 574 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 575 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 576 | { |
<> | 144:ef7eb2e8f9f7 | 577 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 578 | } |
<> | 144:ef7eb2e8f9f7 | 579 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 580 | { |
<> | 144:ef7eb2e8f9f7 | 581 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 582 | } |
<> | 144:ef7eb2e8f9f7 | 583 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 584 | { |
<> | 144:ef7eb2e8f9f7 | 585 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 586 | } |
<> | 144:ef7eb2e8f9f7 | 587 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 588 | { |
<> | 144:ef7eb2e8f9f7 | 589 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 590 | } |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 593 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 594 | |
<> | 144:ef7eb2e8f9f7 | 595 | /* Send read data command */ |
<> | 144:ef7eb2e8f9f7 | 596 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 597 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 598 | NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | /* Read buffer */ |
<> | 144:ef7eb2e8f9f7 | 601 | while( uwBufferSize > 0) |
<> | 144:ef7eb2e8f9f7 | 602 | { |
<> | 144:ef7eb2e8f9f7 | 603 | *pData++ = *(__IO uint16_t *)uwAddress; |
<> | 144:ef7eb2e8f9f7 | 604 | uwAddress += 2; |
<> | 144:ef7eb2e8f9f7 | 605 | uwBufferSize--; |
<> | 144:ef7eb2e8f9f7 | 606 | } |
<> | 144:ef7eb2e8f9f7 | 607 | |
<> | 144:ef7eb2e8f9f7 | 608 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 609 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 612 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 613 | |
<> | 144:ef7eb2e8f9f7 | 614 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 615 | } |
<> | 144:ef7eb2e8f9f7 | 616 | |
<> | 144:ef7eb2e8f9f7 | 617 | /** |
<> | 144:ef7eb2e8f9f7 | 618 | * @brief Writes a half-word buffer to the FMC NOR memory. This function |
<> | 144:ef7eb2e8f9f7 | 619 | * must be used only with S29GL128P NOR memory. |
<> | 144:ef7eb2e8f9f7 | 620 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 621 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 622 | * @param uwAddress: NOR memory internal address from which the data |
<> | 144:ef7eb2e8f9f7 | 623 | * @note Some NOR memory need Address aligned to xx bytes (can be aligned to |
<> | 144:ef7eb2e8f9f7 | 624 | * 64 bytes boundary for example). |
<> | 144:ef7eb2e8f9f7 | 625 | * @param pData: pointer to source data buffer. |
<> | 144:ef7eb2e8f9f7 | 626 | * @param uwBufferSize: number of Half words to write. |
<> | 144:ef7eb2e8f9f7 | 627 | * @note The maximum buffer size allowed is NOR memory dependent |
<> | 144:ef7eb2e8f9f7 | 628 | * (can be 64 Bytes max for example). |
<> | 144:ef7eb2e8f9f7 | 629 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 630 | */ |
<> | 144:ef7eb2e8f9f7 | 631 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
<> | 144:ef7eb2e8f9f7 | 632 | { |
<> | 144:ef7eb2e8f9f7 | 633 | uint16_t * p_currentaddress = (uint16_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 634 | uint16_t * p_endaddress = (uint16_t *)NULL; |
<> | 144:ef7eb2e8f9f7 | 635 | uint32_t lastloadedaddress = 0, deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 638 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 639 | |
<> | 144:ef7eb2e8f9f7 | 640 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 641 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 642 | { |
<> | 144:ef7eb2e8f9f7 | 643 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 644 | } |
<> | 144:ef7eb2e8f9f7 | 645 | |
<> | 144:ef7eb2e8f9f7 | 646 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 647 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 648 | { |
<> | 144:ef7eb2e8f9f7 | 649 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 650 | } |
<> | 144:ef7eb2e8f9f7 | 651 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 652 | { |
<> | 144:ef7eb2e8f9f7 | 653 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 654 | } |
<> | 144:ef7eb2e8f9f7 | 655 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 656 | { |
<> | 144:ef7eb2e8f9f7 | 657 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 658 | } |
<> | 144:ef7eb2e8f9f7 | 659 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 660 | { |
<> | 144:ef7eb2e8f9f7 | 661 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 662 | } |
<> | 144:ef7eb2e8f9f7 | 663 | |
<> | 144:ef7eb2e8f9f7 | 664 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 665 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | /* Initialize variables */ |
<> | 144:ef7eb2e8f9f7 | 668 | p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); |
<> | 144:ef7eb2e8f9f7 | 669 | p_endaddress = p_currentaddress + (uwBufferSize-1); |
<> | 144:ef7eb2e8f9f7 | 670 | lastloadedaddress = (uint32_t)(uwAddress); |
<> | 144:ef7eb2e8f9f7 | 671 | |
<> | 144:ef7eb2e8f9f7 | 672 | /* Issue unlock command sequence */ |
<> | 144:ef7eb2e8f9f7 | 673 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 674 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 675 | |
<> | 144:ef7eb2e8f9f7 | 676 | /* Write Buffer Load Command */ |
<> | 144:ef7eb2e8f9f7 | 677 | NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); |
<> | 144:ef7eb2e8f9f7 | 678 | NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); |
<> | 144:ef7eb2e8f9f7 | 679 | |
<> | 144:ef7eb2e8f9f7 | 680 | /* Load Data into NOR Buffer */ |
<> | 144:ef7eb2e8f9f7 | 681 | while(p_currentaddress <= p_endaddress) |
<> | 144:ef7eb2e8f9f7 | 682 | { |
<> | 144:ef7eb2e8f9f7 | 683 | /* Store last loaded address & data value (for polling) */ |
<> | 144:ef7eb2e8f9f7 | 684 | lastloadedaddress = (uint32_t)p_currentaddress; |
<> | 144:ef7eb2e8f9f7 | 685 | |
<> | 144:ef7eb2e8f9f7 | 686 | NOR_WRITE(p_currentaddress, *pData++); |
<> | 144:ef7eb2e8f9f7 | 687 | |
<> | 144:ef7eb2e8f9f7 | 688 | p_currentaddress++; |
<> | 144:ef7eb2e8f9f7 | 689 | } |
<> | 144:ef7eb2e8f9f7 | 690 | |
<> | 144:ef7eb2e8f9f7 | 691 | NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); |
<> | 144:ef7eb2e8f9f7 | 692 | |
<> | 144:ef7eb2e8f9f7 | 693 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 694 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 697 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 698 | |
<> | 144:ef7eb2e8f9f7 | 699 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 700 | |
<> | 144:ef7eb2e8f9f7 | 701 | } |
<> | 144:ef7eb2e8f9f7 | 702 | |
<> | 144:ef7eb2e8f9f7 | 703 | /** |
<> | 144:ef7eb2e8f9f7 | 704 | * @brief Erase the specified block of the NOR memory |
<> | 144:ef7eb2e8f9f7 | 705 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 706 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 707 | * @param BlockAddress: Block to erase address |
<> | 144:ef7eb2e8f9f7 | 708 | * @param Address: Device address |
<> | 144:ef7eb2e8f9f7 | 709 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 710 | */ |
<> | 144:ef7eb2e8f9f7 | 711 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) |
<> | 144:ef7eb2e8f9f7 | 712 | { |
<> | 144:ef7eb2e8f9f7 | 713 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 714 | |
<> | 144:ef7eb2e8f9f7 | 715 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 716 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 717 | |
<> | 144:ef7eb2e8f9f7 | 718 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 719 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 720 | { |
<> | 144:ef7eb2e8f9f7 | 721 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 722 | } |
<> | 144:ef7eb2e8f9f7 | 723 | |
<> | 144:ef7eb2e8f9f7 | 724 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 725 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 726 | { |
<> | 144:ef7eb2e8f9f7 | 727 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 730 | { |
<> | 144:ef7eb2e8f9f7 | 731 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 732 | } |
<> | 144:ef7eb2e8f9f7 | 733 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 734 | { |
<> | 144:ef7eb2e8f9f7 | 735 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 736 | } |
<> | 144:ef7eb2e8f9f7 | 737 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 738 | { |
<> | 144:ef7eb2e8f9f7 | 739 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 740 | } |
<> | 144:ef7eb2e8f9f7 | 741 | |
<> | 144:ef7eb2e8f9f7 | 742 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 743 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 744 | |
<> | 144:ef7eb2e8f9f7 | 745 | /* Send block erase command sequence */ |
<> | 144:ef7eb2e8f9f7 | 746 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 747 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 748 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
<> | 144:ef7eb2e8f9f7 | 749 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
<> | 144:ef7eb2e8f9f7 | 750 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
<> | 144:ef7eb2e8f9f7 | 751 | NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | /* Check the NOR memory status and update the controller state */ |
<> | 144:ef7eb2e8f9f7 | 754 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 757 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 760 | |
<> | 144:ef7eb2e8f9f7 | 761 | } |
<> | 144:ef7eb2e8f9f7 | 762 | |
<> | 144:ef7eb2e8f9f7 | 763 | /** |
<> | 144:ef7eb2e8f9f7 | 764 | * @brief Erase the entire NOR chip. |
<> | 144:ef7eb2e8f9f7 | 765 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 766 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 767 | * @param Address: Device address |
<> | 144:ef7eb2e8f9f7 | 768 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 769 | */ |
<> | 144:ef7eb2e8f9f7 | 770 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) |
<> | 144:ef7eb2e8f9f7 | 771 | { |
<> | 144:ef7eb2e8f9f7 | 772 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 773 | |
<> | 144:ef7eb2e8f9f7 | 774 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 775 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 776 | |
<> | 144:ef7eb2e8f9f7 | 777 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 778 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 779 | { |
<> | 144:ef7eb2e8f9f7 | 780 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 781 | } |
<> | 144:ef7eb2e8f9f7 | 782 | |
<> | 144:ef7eb2e8f9f7 | 783 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 784 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 785 | { |
<> | 144:ef7eb2e8f9f7 | 786 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 787 | } |
<> | 144:ef7eb2e8f9f7 | 788 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 789 | { |
<> | 144:ef7eb2e8f9f7 | 790 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 791 | } |
<> | 144:ef7eb2e8f9f7 | 792 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 793 | { |
<> | 144:ef7eb2e8f9f7 | 794 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 795 | } |
<> | 144:ef7eb2e8f9f7 | 796 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 797 | { |
<> | 144:ef7eb2e8f9f7 | 798 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 799 | } |
<> | 144:ef7eb2e8f9f7 | 800 | |
<> | 144:ef7eb2e8f9f7 | 801 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 802 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 803 | |
<> | 144:ef7eb2e8f9f7 | 804 | /* Send NOR chip erase command sequence */ |
<> | 144:ef7eb2e8f9f7 | 805 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
<> | 144:ef7eb2e8f9f7 | 806 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
<> | 144:ef7eb2e8f9f7 | 807 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
<> | 144:ef7eb2e8f9f7 | 808 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
<> | 144:ef7eb2e8f9f7 | 809 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
<> | 144:ef7eb2e8f9f7 | 810 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); |
<> | 144:ef7eb2e8f9f7 | 811 | |
<> | 144:ef7eb2e8f9f7 | 812 | /* Check the NOR memory status and update the controller state */ |
<> | 144:ef7eb2e8f9f7 | 813 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 814 | |
<> | 144:ef7eb2e8f9f7 | 815 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 816 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 819 | } |
<> | 144:ef7eb2e8f9f7 | 820 | |
<> | 144:ef7eb2e8f9f7 | 821 | /** |
<> | 144:ef7eb2e8f9f7 | 822 | * @brief Read NOR flash CFI IDs |
<> | 144:ef7eb2e8f9f7 | 823 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 824 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 825 | * @param pNOR_CFI: pointer to NOR CFI IDs structure |
<> | 144:ef7eb2e8f9f7 | 826 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 827 | */ |
<> | 144:ef7eb2e8f9f7 | 828 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) |
<> | 144:ef7eb2e8f9f7 | 829 | { |
<> | 144:ef7eb2e8f9f7 | 830 | uint32_t deviceaddress = 0; |
<> | 144:ef7eb2e8f9f7 | 831 | |
<> | 144:ef7eb2e8f9f7 | 832 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 833 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 834 | |
<> | 144:ef7eb2e8f9f7 | 835 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 836 | if(hnor->State == HAL_NOR_STATE_BUSY) |
<> | 144:ef7eb2e8f9f7 | 837 | { |
<> | 144:ef7eb2e8f9f7 | 838 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 839 | } |
<> | 144:ef7eb2e8f9f7 | 840 | |
<> | 144:ef7eb2e8f9f7 | 841 | /* Select the NOR device address */ |
<> | 144:ef7eb2e8f9f7 | 842 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 843 | { |
<> | 144:ef7eb2e8f9f7 | 844 | deviceaddress = NOR_MEMORY_ADRESS1; |
<> | 144:ef7eb2e8f9f7 | 845 | } |
<> | 144:ef7eb2e8f9f7 | 846 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
<> | 144:ef7eb2e8f9f7 | 847 | { |
<> | 144:ef7eb2e8f9f7 | 848 | deviceaddress = NOR_MEMORY_ADRESS2; |
<> | 144:ef7eb2e8f9f7 | 849 | } |
<> | 144:ef7eb2e8f9f7 | 850 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
<> | 144:ef7eb2e8f9f7 | 851 | { |
<> | 144:ef7eb2e8f9f7 | 852 | deviceaddress = NOR_MEMORY_ADRESS3; |
<> | 144:ef7eb2e8f9f7 | 853 | } |
<> | 144:ef7eb2e8f9f7 | 854 | else /* FMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 855 | { |
<> | 144:ef7eb2e8f9f7 | 856 | deviceaddress = NOR_MEMORY_ADRESS4; |
<> | 144:ef7eb2e8f9f7 | 857 | } |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 860 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 861 | |
<> | 144:ef7eb2e8f9f7 | 862 | /* Send read CFI query command */ |
<> | 144:ef7eb2e8f9f7 | 863 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); |
<> | 144:ef7eb2e8f9f7 | 864 | |
<> | 144:ef7eb2e8f9f7 | 865 | /* read the NOR CFI information */ |
<> | 144:ef7eb2e8f9f7 | 866 | pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); |
<> | 144:ef7eb2e8f9f7 | 867 | pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); |
<> | 144:ef7eb2e8f9f7 | 868 | pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); |
<> | 144:ef7eb2e8f9f7 | 869 | pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); |
<> | 144:ef7eb2e8f9f7 | 870 | |
<> | 144:ef7eb2e8f9f7 | 871 | /* Check the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 872 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 873 | |
<> | 144:ef7eb2e8f9f7 | 874 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 875 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 876 | |
<> | 144:ef7eb2e8f9f7 | 877 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 878 | } |
<> | 144:ef7eb2e8f9f7 | 879 | |
<> | 144:ef7eb2e8f9f7 | 880 | /** |
<> | 144:ef7eb2e8f9f7 | 881 | * @} |
<> | 144:ef7eb2e8f9f7 | 882 | */ |
<> | 144:ef7eb2e8f9f7 | 883 | |
<> | 144:ef7eb2e8f9f7 | 884 | /** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 885 | * @brief management functions |
<> | 144:ef7eb2e8f9f7 | 886 | * |
<> | 144:ef7eb2e8f9f7 | 887 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 888 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 889 | ##### NOR Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 890 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 891 | [..] |
<> | 144:ef7eb2e8f9f7 | 892 | This subsection provides a set of functions allowing to control dynamically |
<> | 144:ef7eb2e8f9f7 | 893 | the NOR interface. |
<> | 144:ef7eb2e8f9f7 | 894 | |
<> | 144:ef7eb2e8f9f7 | 895 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 896 | * @{ |
<> | 144:ef7eb2e8f9f7 | 897 | */ |
<> | 144:ef7eb2e8f9f7 | 898 | |
<> | 144:ef7eb2e8f9f7 | 899 | /** |
<> | 144:ef7eb2e8f9f7 | 900 | * @brief Enables dynamically NOR write operation. |
<> | 144:ef7eb2e8f9f7 | 901 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 902 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 903 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 904 | */ |
<> | 144:ef7eb2e8f9f7 | 905 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 906 | { |
<> | 144:ef7eb2e8f9f7 | 907 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 908 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | /* Enable write operation */ |
<> | 144:ef7eb2e8f9f7 | 911 | FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); |
<> | 144:ef7eb2e8f9f7 | 912 | |
<> | 144:ef7eb2e8f9f7 | 913 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 914 | hnor->State = HAL_NOR_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 915 | |
<> | 144:ef7eb2e8f9f7 | 916 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 917 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 918 | |
<> | 144:ef7eb2e8f9f7 | 919 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 920 | } |
<> | 144:ef7eb2e8f9f7 | 921 | |
<> | 144:ef7eb2e8f9f7 | 922 | /** |
<> | 144:ef7eb2e8f9f7 | 923 | * @brief Disables dynamically NOR write operation. |
<> | 144:ef7eb2e8f9f7 | 924 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 925 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 926 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 927 | */ |
<> | 144:ef7eb2e8f9f7 | 928 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 929 | { |
<> | 144:ef7eb2e8f9f7 | 930 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 931 | __HAL_LOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 932 | |
<> | 144:ef7eb2e8f9f7 | 933 | /* Update the SRAM controller state */ |
<> | 144:ef7eb2e8f9f7 | 934 | hnor->State = HAL_NOR_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 935 | |
<> | 144:ef7eb2e8f9f7 | 936 | /* Disable write operation */ |
<> | 144:ef7eb2e8f9f7 | 937 | FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); |
<> | 144:ef7eb2e8f9f7 | 938 | |
<> | 144:ef7eb2e8f9f7 | 939 | /* Update the NOR controller state */ |
<> | 144:ef7eb2e8f9f7 | 940 | hnor->State = HAL_NOR_STATE_PROTECTED; |
<> | 144:ef7eb2e8f9f7 | 941 | |
<> | 144:ef7eb2e8f9f7 | 942 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 943 | __HAL_UNLOCK(hnor); |
<> | 144:ef7eb2e8f9f7 | 944 | |
<> | 144:ef7eb2e8f9f7 | 945 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 946 | } |
<> | 144:ef7eb2e8f9f7 | 947 | |
<> | 144:ef7eb2e8f9f7 | 948 | /** |
<> | 144:ef7eb2e8f9f7 | 949 | * @} |
<> | 144:ef7eb2e8f9f7 | 950 | */ |
<> | 144:ef7eb2e8f9f7 | 951 | |
<> | 144:ef7eb2e8f9f7 | 952 | /** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 953 | * @brief Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 954 | * |
<> | 144:ef7eb2e8f9f7 | 955 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 956 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 957 | ##### NOR State functions ##### |
<> | 144:ef7eb2e8f9f7 | 958 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 959 | [..] |
<> | 144:ef7eb2e8f9f7 | 960 | This subsection permits to get in run-time the status of the NOR controller |
<> | 144:ef7eb2e8f9f7 | 961 | and the data flow. |
<> | 144:ef7eb2e8f9f7 | 962 | |
<> | 144:ef7eb2e8f9f7 | 963 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 964 | * @{ |
<> | 144:ef7eb2e8f9f7 | 965 | */ |
<> | 144:ef7eb2e8f9f7 | 966 | |
<> | 144:ef7eb2e8f9f7 | 967 | /** |
<> | 144:ef7eb2e8f9f7 | 968 | * @brief return the NOR controller state |
<> | 144:ef7eb2e8f9f7 | 969 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 970 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 971 | * @retval NOR controller state |
<> | 144:ef7eb2e8f9f7 | 972 | */ |
<> | 144:ef7eb2e8f9f7 | 973 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) |
<> | 144:ef7eb2e8f9f7 | 974 | { |
<> | 144:ef7eb2e8f9f7 | 975 | return hnor->State; |
<> | 144:ef7eb2e8f9f7 | 976 | } |
<> | 144:ef7eb2e8f9f7 | 977 | |
<> | 144:ef7eb2e8f9f7 | 978 | /** |
<> | 144:ef7eb2e8f9f7 | 979 | * @brief Returns the NOR operation status. |
<> | 144:ef7eb2e8f9f7 | 980 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 981 | * the configuration information for NOR module. |
<> | 144:ef7eb2e8f9f7 | 982 | * @param Address: Device address |
<> | 144:ef7eb2e8f9f7 | 983 | * @param Timeout: NOR progamming Timeout |
<> | 144:ef7eb2e8f9f7 | 984 | * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR |
<> | 144:ef7eb2e8f9f7 | 985 | * or HAL_NOR_STATUS_TIMEOUT |
<> | 144:ef7eb2e8f9f7 | 986 | */ |
<> | 144:ef7eb2e8f9f7 | 987 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 988 | { |
<> | 144:ef7eb2e8f9f7 | 989 | HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; |
<> | 144:ef7eb2e8f9f7 | 990 | uint16_t tmp_sr1 = 0, tmp_sr2 = 0; |
<> | 144:ef7eb2e8f9f7 | 991 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 992 | |
<> | 144:ef7eb2e8f9f7 | 993 | /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 994 | HAL_NOR_MspWait(hnor, Timeout); |
<> | 144:ef7eb2e8f9f7 | 995 | |
<> | 144:ef7eb2e8f9f7 | 996 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 997 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 998 | while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) |
<> | 144:ef7eb2e8f9f7 | 999 | { |
<> | 144:ef7eb2e8f9f7 | 1000 | /* Check for the Timeout */ |
<> | 144:ef7eb2e8f9f7 | 1001 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1002 | { |
<> | 144:ef7eb2e8f9f7 | 1003 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1004 | { |
<> | 144:ef7eb2e8f9f7 | 1005 | status = HAL_NOR_STATUS_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1006 | } |
<> | 144:ef7eb2e8f9f7 | 1007 | } |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | /* Read NOR status register (DQ6 and DQ5) */ |
<> | 144:ef7eb2e8f9f7 | 1010 | tmp_sr1 = *(__IO uint16_t *)Address; |
<> | 144:ef7eb2e8f9f7 | 1011 | tmp_sr2 = *(__IO uint16_t *)Address; |
<> | 144:ef7eb2e8f9f7 | 1012 | |
<> | 144:ef7eb2e8f9f7 | 1013 | /* If DQ6 did not toggle between the two reads then return NOR_Success */ |
<> | 144:ef7eb2e8f9f7 | 1014 | if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) |
<> | 144:ef7eb2e8f9f7 | 1015 | { |
<> | 144:ef7eb2e8f9f7 | 1016 | return HAL_NOR_STATUS_SUCCESS; |
<> | 144:ef7eb2e8f9f7 | 1017 | } |
<> | 144:ef7eb2e8f9f7 | 1018 | |
<> | 144:ef7eb2e8f9f7 | 1019 | if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) |
<> | 144:ef7eb2e8f9f7 | 1020 | { |
<> | 144:ef7eb2e8f9f7 | 1021 | status = HAL_NOR_STATUS_ONGOING; |
<> | 144:ef7eb2e8f9f7 | 1022 | } |
<> | 144:ef7eb2e8f9f7 | 1023 | |
<> | 144:ef7eb2e8f9f7 | 1024 | tmp_sr1 = *(__IO uint16_t *)Address; |
<> | 144:ef7eb2e8f9f7 | 1025 | tmp_sr2 = *(__IO uint16_t *)Address; |
<> | 144:ef7eb2e8f9f7 | 1026 | |
<> | 144:ef7eb2e8f9f7 | 1027 | /* If DQ6 did not toggle between the two reads then return NOR_Success */ |
<> | 144:ef7eb2e8f9f7 | 1028 | if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) |
<> | 144:ef7eb2e8f9f7 | 1029 | { |
<> | 144:ef7eb2e8f9f7 | 1030 | return HAL_NOR_STATUS_SUCCESS; |
<> | 144:ef7eb2e8f9f7 | 1031 | } |
<> | 144:ef7eb2e8f9f7 | 1032 | else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) |
<> | 144:ef7eb2e8f9f7 | 1033 | { |
<> | 144:ef7eb2e8f9f7 | 1034 | return HAL_NOR_STATUS_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1035 | } |
<> | 144:ef7eb2e8f9f7 | 1036 | } |
<> | 144:ef7eb2e8f9f7 | 1037 | |
<> | 144:ef7eb2e8f9f7 | 1038 | /* Return the operation status */ |
<> | 144:ef7eb2e8f9f7 | 1039 | return status; |
<> | 144:ef7eb2e8f9f7 | 1040 | } |
<> | 144:ef7eb2e8f9f7 | 1041 | |
<> | 144:ef7eb2e8f9f7 | 1042 | /** |
<> | 144:ef7eb2e8f9f7 | 1043 | * @} |
<> | 144:ef7eb2e8f9f7 | 1044 | */ |
<> | 144:ef7eb2e8f9f7 | 1045 | |
<> | 144:ef7eb2e8f9f7 | 1046 | /** |
<> | 144:ef7eb2e8f9f7 | 1047 | * @} |
<> | 144:ef7eb2e8f9f7 | 1048 | */ |
<> | 144:ef7eb2e8f9f7 | 1049 | /** |
<> | 144:ef7eb2e8f9f7 | 1050 | * @} |
<> | 144:ef7eb2e8f9f7 | 1051 | */ |
<> | 144:ef7eb2e8f9f7 | 1052 | #endif /* HAL_NOR_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1053 | |
<> | 144:ef7eb2e8f9f7 | 1054 | /** |
<> | 144:ef7eb2e8f9f7 | 1055 | * @} |
<> | 144:ef7eb2e8f9f7 | 1056 | */ |
<> | 144:ef7eb2e8f9f7 | 1057 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
<> | 144:ef7eb2e8f9f7 | 1058 | |
<> | 144:ef7eb2e8f9f7 | 1059 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |